JP2008108856A - Compound semiconductor element, and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a compound semiconductor element capable of inhibiting degradation in element characteristics. <P>SOLUTION: A p-type clad layer 106 with impurities doped and an active layer 104 without impurities doped are vertically adjacently provided on a substrate 101. A semiconductor layer 105 having distortion is provided between the layers 106 and 104. A crystal of the semiconductor layer 105 having the distortion has higher internal energy of the crystal than a distortionless crystal as distortion works on its interstitial bonding. Therefore, a dopant is hard to pass between these distorted grates. This prevents the dopant from diffusing from the p-type clad layer 106 to the active layer 104. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates generally to compound semiconductor devices, and more specifically, compound semiconductors such as semiconductor lasers and light-emitting diodes, high electron mobility transistors, and heterojunction bipolar transistors that are preferably used in optical disk devices, optical communication systems, and the like. It relates to an element. The present invention also relates to a method of manufacturing a compound semiconductor device improved so as to prevent the diffusion of dopants.

  Compound semiconductor elements are broadly classified into electronic devices such as high electron mobility transistors and heterojunction bipolar transistors, and optical devices such as semiconductor lasers and light emitting diodes. In these elements, a technique for mixing impurities is important in order to impart polarity to the semiconductor. This technique is generally called doping, and the impurity is called a dopant. In the compound semiconductor device, desired device characteristics are realized by appropriately controlling the impurity concentration by doping.

  For example, a high electron mobility transistor includes a layer to which an impurity for supplying electrons is added and a high purity channel layer. Since the channel layer contains almost no impurities, electrons passing through the channel layer hardly collide with the impurities, and as a result, the electron mobility increases.

  Further, for example, a semiconductor laser has a sandwich structure in which a non-doped semiconductor layer is sandwiched between p-type semiconductor and n-type semiconductor that are polarized by doping, and is joined at the center. These p-type semiconductor and n-type semiconductor The semiconductor layer sandwiched between the layers corresponds to the light emitting layer. This light emitting layer is called an active layer, and the layers on both sides of the active layer are called clad layers. The clad layer and the active layer are made of semiconductor materials having different band gaps, and form a double heterojunction. In this double heterojunction, electrons and holes are combined and converted into light efficiently, and the light is confined in the cladding layer and laser oscillation occurs.

  As described above, compound semiconductor elements include electronic devices and optical devices. Here, semiconductor lasers will be described as examples from optical devices.

  As a conventional semiconductor laser, for example, there is a ridge embedded semiconductor laser disclosed in Patent Document 1. The main manufacturing process and the element structure of this conventional semiconductor laser are shown in FIGS. 7A to 7D and will be described.

First, as shown in FIG. 7A, an n-type AlGaAs buffer layer 302 is formed on an n-type GaAs substrate 301, and an n-type Al _x Ga _1-x As (0.3 <X <1) first clad layer 303, Al _y Ga _1-y As (0 <Y <0.2) active layer 304, p-type Al _x Ga _1-x As second clad layer 305, and p-type GaAs The contact layer 306 is sequentially laminated by using a MOCVD (metal organic chemical vapor deposition) method, and then a SiO ₂ mask 307 is formed on a necessary portion on the laminated body.

  Next, as shown in FIGS. 7A and 7B, the second cladding layer 305 is etched using an etchant that is a mixed aqueous solution of sulfuric acid and hydrogen peroxide solution, and the second cladding layer is etched. Side surfaces of the mesa portion 308 including the 305 and the p-type GaAs contact layer 306 are formed.

Further, as shown in FIG. 7C, a current composed of n-type GaAs, which is regrowth using the MOCVD method and selectively grown using the SiO ₂ mask 307 so as to be in contact with the side surface of the mesa portion 308. A blocking layer 309 is embedded.

Finally, as shown in FIGS. 7C and 7D, the SiO ₂ mask 7 is removed, and a p-type electrode 310 and an n-type electrode 311 are formed on the top and bottom of this laminate, and then cleaved to form a chip. By dividing, a ridge embedded semiconductor laser can be manufactured.
Japanese Patent Laid-Open No. 7-50446

  By the way, in such a compound semiconductor device, the dopant diffuses from the doped layer to the active layer 304 due to a thermal history or the like, and a crystal defect serving as a non-radiative recombination center of the carrier is formed, and the device characteristics are deteriorated. In addition, the dopant is easily diffused during the operation of the device due to the influence of the injection current and heat generation during operation, resulting in a problem that the device life is shortened.

  Furthermore, the p-type contact layer 306 is highly doped to reduce the resistance. However, the dopant is affected by the thermal history in crystal growth or subsequent manufacturing processes, the influence of injection current or heat generation during device operation, and the like. Diffusion from the contact layer 306 results in a problem that the carrier concentration of the contact layer 306 decreases, the resistance increases, and current does not flow easily.

  Although a semiconductor laser, which is an optical device, has been described as an example here, the same applies to an electronic device. For example, in the case of a high electron mobility transistor, if impurities enter the channel layer from the layer to which impurities are added by diffusion, the impurities prevent the movement of electrons, so that high mobility cannot be obtained and the characteristics of the device are deteriorated. There was a problem.

  As described above, the compound semiconductor device has a problem that the characteristics of the device are deteriorated when impurities are diffused.

  The present invention has been made to solve the above problems, and an object of the present invention is to provide an improved compound semiconductor device that can suppress deterioration of device characteristics.

  Another object of the present invention is to provide a method of manufacturing a compound semiconductor device which is improved so that diffusion of impurities can be suppressed, a doping profile as designed can be formed, and original device characteristics can be realized.

  The compound semiconductor device according to the present invention includes a first semiconductor layer doped with impurities and provided adjacent to each other on a substrate, and an impurity doped or lower than the first semiconductor layer. And a second semiconductor layer doped in concentration. A strained third semiconductor layer is provided between the first semiconductor layer and the second semiconductor layer.

  According to the present invention, by providing the strained third semiconductor layer, the internal energy of the crystal is changed to a high state so that the dopant cannot pass between the lattices or cannot be replaced with atoms at the lattice positions. It is what you want to do.

  According to a preferred embodiment of the present invention, the absolute value of the strain amount of the third semiconductor layer is not less than 0.5% and not more than 10%.

  By setting the absolute value of the strain amount of the semiconductor layer having strain in this way to a strain amount of 0.5% or more and 10% or less, the internal energy of the crystal is changed to a high state, and the dopant cannot pass between the lattices. Or to prevent substitution with atoms at lattice positions. If it is less than 0.5%, the effect of preventing impurity diffusion becomes insufficient, and crystallinity is deteriorated by impurity diffusion. On the other hand, if it exceeds 10%, it becomes difficult to form a flat crystal or more monolayer without causing misfit dislocations. Therefore, by setting the strain amount of the semiconductor layer having strain to 0.5% or more and 10% or less, diffusion of impurities can be prevented and deterioration of crystallinity can be prevented. Can be realized.

  According to a further preferred embodiment of the present invention, the thickness of the third semiconductor layer having strain is not less than a monomolecular layer thickness and not more than 10 nm.

  When the thickness of the strained third semiconductor layer becomes thinner than the monomolecular layer thickness, it becomes insufficient to prevent the diffusion of impurities, the device characteristics and reliability deteriorate, and when the thickness becomes thicker than 10 nm, the critical film If the thickness is exceeded, the crystallinity is lowered and the characteristics of the device are deteriorated. Therefore, the thickness of the semiconductor layer having strain needs to be not less than a monomolecular layer thickness and not more than 10 nm.

According to a more preferred embodiment, the substrate is GaAs and the third semiconductor layer is In _1-x Ga _x As _1-y P _y “0 ≦ x, y ≦ 1”.

When In _1-x Ga _x As _1-y P _y (0 ≦ x, y ≦ 1) is used, there is an advantage that the band gap can be selected in a wide range and the band gap between adjacent semiconductor layers can be easily adjusted. In other words, there is an advantage that a desired strain amount can be adjusted by adjusting the composition while maintaining a certain band gap.

  Further, the substrate is GaAs, and the strained third semiconductor layer is made of a binary compound containing a group III element having an atomic radius larger than Ga or a group V element having an atomic radius larger than As. The layer thickness is preferably a monomolecular layer or more. Even a monomolecular layer has a high strain amount, and thus has a high effect of preventing impurity diffusion.

  Moreover, it is preferable that the substrate to be used is GaAs and the binary compound is InAs. The InAs monomolecular layer has a strain amount of about 7%, and a sufficient diffusion suppressing effect can be obtained.

  In addition, it is preferable that an impurity is not doped in a part of the thickness of the first semiconductor layer on the side in contact with the third semiconductor layer.

  According to another aspect of the present invention, there is provided a method for manufacturing a compound semiconductor device comprising: a first semiconductor layer doped with impurities; and a lower concentration than the first semiconductor layer that is not doped with impurities. In the method of manufacturing a group III-V compound semiconductor device in which a doped second semiconductor layer is formed adjacent to each other in the vertical direction, a strain is generated between the first semiconductor layer and the second semiconductor layer. The method includes a step of forming a third semiconductor layer.

  Since the diffusion of impurities is suppressed by this manufacturing method and high-quality crystallinity can be secured, a compound semiconductor element having good characteristics and high reliability can be obtained.

  In the step of forming the first semiconductor layer, it is preferable to form a part of the thickness of the first semiconductor layer without doping impurities on the side in contact with the third semiconductor layer. .

  When impurities are diffused due to thermal history during crystal growth, a semiconductor layer having a strain for preventing diffusion of impurities is formed in the second semiconductor layer in advance. There is an advantage that impurities diffusing into the semiconductor layer during growth can be prevented by using a semiconductor layer having strain.

  According to the above-described compound semiconductor device according to the present invention, diffusion of impurities is suppressed, a doping profile as designed can be formed, and original device characteristics can be realized. Therefore, since deterioration of crystallinity can be prevented, a compound semiconductor element having a long element lifetime is obtained in the case of a semiconductor laser, and a compound semiconductor element having a high mobility is obtained in the case of a high electron mobility transistor. And a compound semiconductor element connected with a low resistance.

  In a compound semiconductor device having a first semiconductor layer doped with impurities on a substrate and a second semiconductor layer not doped with impurities formed vertically adjacent to the first semiconductor layer, as designed A third semiconductor layer having a strain is formed between the first semiconductor layer and the second semiconductor layer for the purpose of forming a doping profile and realizing the original device characteristics. This is realized by preventing diffusion of impurities from the semiconductor layer to the second semiconductor layer.

  Here, the strain includes a compressive strain and a tensile strain. When the strain amount is expressed as “e”, when e> 0, it is called compression strain, and when e <0, it is called tensile strain (extension strain).

The amount of strain was calculated as follows. That is, as a general method, an X-ray diffractometer is used to measure the crystal lattice spacing of a strained thin film, determine the difference from the normal crystal lattice spacing without strain, and calculate the amount of strain. First, as a procedure, the value of the crystal lattice spacing of the strained thin film is set to “a (with strain)”. Next, a normal crystal lattice spacing without distortion is assumed to be “a (no distortion)”. In the present embodiment, the lattice spacing of the GaAs substrate, which is the substrate, corresponds to “a normal crystal lattice spacing without distortion”. Next, the distortion amount e is calculated using “a (with distortion)” and “a (without distortion)”
e = (a (with distortion) -a (without distortion)) / a (without distortion)
It is defined as Since it is a numerical value without a unit as it is, in order to display%, e was multiplied by 100% again to calculate e = e × 100%.

  Embodiments of the present invention will be described below with reference to the drawings.

  1 is a cross-sectional view of an element of a ridge embedded semiconductor laser, which is a III-V group compound semiconductor element according to Example 1. FIG.

Referring to FIG. 1, an n-type Al _0.5 Ga _0.5 As buffer layer 102 (thickness 0.5 μm, Si carrier concentration 1) is formed on an n-type GaAs substrate 101 (Si carrier concentration 2 × 10 ¹⁸ cm ⁻³ ). 5 × 10 ¹⁸ cm ⁻³ ), and n-type Al _0.4 Ga _0.6 As first cladding layer 103 (thickness 0.9 μm, Si carrier concentration 8 × 10 ¹⁷ cm ⁻³ ), Al _0.1 Ga _0.9 As (thickness 0.2 μm) active layer 104, tensile strained In _0.1 Ga _0.9 As _0.47 P _0.53 semiconductor layer 105 (thickness 5 nm, strain amount—1.17%), p-type Al _0.4 Ga _{A 0.6} As second cladding layer 106 (thickness 0.6 μm, Zn carrier concentration 2 × 10 ¹⁸ cm ⁻³ ) is provided.

  When the second cladding layer 106 is grown, the doping timing of the second cladding layer 106 in contact with the active layer 104 is slightly delayed. That is, while the first 0.1 μm is stacked, Zn is not allowed to flow into the reaction furnace, and the growth layer is grown so as not to be doped with Zn. After 0.1 μm, normal growth is performed, DEZn is supplied, and doping is performed.

A p-type GaAs contact layer 107 (thickness 0.3 μm, Zn carrier concentration 5 × 10 ¹⁸ cm ⁻³ ) is stacked on the second cladding layer 106.

The second cladding layer 106 and the p-type GaAs contact layer 107 are etched to form a side surface of the mesa portion 109 including the second cladding layer 106 and the p-type GaAs contact layer 107. A current blocking layer 110 (thickness 0.3 μm, carrier concentration 1.5 × 10 ¹⁸ cm ⁻³ ) made of n-type GaAs is embedded so as to be in contact with the side surface of the mesa portion 109. On this laminated body, titanium (Ti) having a thickness of about 100 nm, platinum (Pt) having a thickness of about 50 nm, and gold (Au) having a thickness of about 400 nm are sequentially deposited. A mold electrode 111 is formed. On the other hand, a gold-germanium alloy (Au—Ge) having a thickness of about 100 nm, nickel (Ni) having a thickness of about 15 nm, and gold (Au) having a thickness of about 300 nm are sequentially deposited on the back side of the GaAs substrate. An n-type electrode 112 made of Au—Ge / Ni / Au is formed.

In _0.1 Ga _0.9 As _0.47 P _0.53 was used for the semiconductor layer 105 having strain in the above. The band gap of the semiconductor layer 105 is preferably larger than the band gap of the active layer so as not to absorb light emitted from the active layer. Here, the band gap of the strained semiconductor layer 105 is about 1.92 eV, which is the same as the band gap 1.92 eV of the second cladding layer 106 and larger than the band gap of the active layer. The present invention is not limited to this band gap of 1.92 eV. InGaAsP mixed crystals have a range of selection from a lower limit of about 0.36 eV to an upper limit of about 2 eV in consideration of the band gap satisfying the direct transition. As described above, when the InGaAsP material is used, there is an advantage that the selection range of the band gap is wide and the band gap between the adjacent semiconductor layers can be easily adjusted. The strain amount here is −1.17%. If the Ga composition is x and the P composition is y (x> 0.9, y> 0.53), the strain is The absolute value of the amount can be increased to -2% (the amount of strain at a thickness of 5 nm) including the sign, and the effect of suppressing diffusion can be further enhanced.

  FIG. 2 is a conceptual diagram for explaining an operational effect that dopant diffusion is prevented by providing a strained semiconductor layer. In general, a crystal of a semiconductor layer having strain has a higher internal energy of the crystal than in the case of no strain due to strain applied to the interstitial bond. For this reason, as shown in FIG. 2B, impurity atoms between lattices trying to move between the strained lattices by diffusion feel high internal energy (the mountain to be crossed is high). Compared to the case of no distortion shown in A) (when the mountain to be crossed is low), it is impossible to pass between the lattices unless the energy is larger. Thus, dopant diffusion from the p-type cladding layer 106 to the active layer 104 is suppressed. This is not only when the strain is tensile strain. The same applies to the case of compression distortion described later.

  When a current is passed between the p-type electrode 111 and the n-type electrode 112, light is output as shown by an arrow with reference to FIG.

Next, a method for manufacturing the ridge embedded semiconductor laser of the present invention will be described. Note that the crystal growth is performed using the MOCVD method, and the growth conditions are a growth temperature of 750 ° C., a growth pressure of 76 Torr, and V / III (ratio of supply amount of Group V element to Group III element) = 120. . Also, TMG (trimethylgallium) and TMA (trimethylaluminum) were used as group III materials, AsH ₃ (arsine) was used as group V materials, SiH ₄ (silane) and DEZn (diethyl zinc) were used as n-type and p-type dopant materials. . Hydrogen (H ₂ ) was used as the carrier gas.

First, as shown in FIG. 4A, an n-type Al _0.5 Ga _0.5 As buffer layer 102 (thickness 0.5 μm, Si) is formed on an n-type GaAs substrate 101 (Si carrier concentration 2 × 10 ¹⁸ cm ⁻³ ). Carrier density 1.5 × 10 ¹⁸ cm ⁻³ ) and n-type Al _0.4 Ga _0.6 As first cladding layer 103 (thickness 0.9 μm, Si carrier concentration 8 × 10 ¹⁷ cm ⁻³⁾ ), Al _0.1 Ga _0.9 As (thickness 0.2 μm) active layer 104, tensile strained In _0.1 Ga _0.9 As _0.47 P _0.53 semiconductor layer 105 (thickness 5 nm, strain amount—1.17%), p-type A second clad layer 106 (thickness 0.6 μm, Zn carrier concentration 2 × 10 ¹⁸ cm ⁻³ ) of Al _0.4 Ga _0.6 As is stacked. At this time, when the second clad layer 106 is grown, the active layer 104 side Doping of the second cladding layer 106 in contact with Do a little delay the timing. That is, while the first 0.1 μm is stacked, Zn is not allowed to flow into the reaction furnace, and the growth layer is grown so as not to be doped with Zn. When the thickness exceeds 0.1 μm, normal growth is performed, DEZn is supplied, and doping is performed. Then, after p-type GaAs contact layer 107 (thickness 0.3 μm, Zn carrier concentration 5 × 10 ¹⁸ cm ⁻³ ) is laminated in order, SiO ₂ mask 108 (thickness 0) is formed on a necessary portion on the laminated body. .3 μm).

  Next, as shown in FIG. 4B, etching is performed using an etching solution which is a mixed aqueous solution of sulfuric acid and hydrogen peroxide so as to leave a portion having a thickness h of the second cladding layer 106 of 0.3 μm. The side surfaces of the mesa portion 109 including the second cladding layer 106 and the p-type GaAs contact layer 107 are formed.

Further, as shown in FIG. 4C, n-type GaAs is grown by selective growth using the SiO ₂ mask 108 so as to be in contact with the side surface of the mesa portion 109 by performing regrowth using a metal organic chemical vapor deposition method. Embedded in a current blocking layer 110 (thickness 0.3 μm, carrier concentration 1.5 × 10 ¹⁸ cm ⁻³ ).

Finally, as shown in FIG. 4D, the SiO ₂ mask 108 is removed, and titanium (Ti) having a thickness of about 100 nm, platinum (Pt) having a thickness of about 50 nm, and a thickness of 400 nm are formed on the stacked body. About gold (Au) is sequentially deposited by vapor deposition, and is patterned by photolithography and etching to form a p-type electrode 111 made of Ti / Pt / Au. On the other hand, a gold-germanium alloy (Au—Ge) having a thickness of about 100 nm, nickel (Ni) having a thickness of about 15 nm, and gold (Au) having a thickness of about 300 nm are sequentially deposited on the back side of the GaAs substrate. An n-type electrode 112 made of -Ge / Ni / Au is formed. Then, by cleaving the stacked body, it can be divided into chips and a ridge embedded semiconductor laser can be manufactured.

In the present invention, the non-doped active layer 104, the strained In _0.1 Ga _0.9 As _0.47 P _0.53 semiconductor layer 105 (thickness 5 nm, strain amount—1.17%), and the second cladding layer 106 of p-type Al _0.4 Ga _0.6 As. When the layers were sequentially stacked (thickness 0.6 μm, Zn carrier concentration 2 × 10 ¹⁸ cm ⁻³ ), the timing of doping the second cladding layer 106 in contact with the semiconductor layer 105 side was slightly delayed. That is, during the initial stacking of 0.1 μm, growth was performed without supplying DEZn so that the second cladding layer 106 in contact with the semiconductor layer 105 side was not doped with Zn. Thus, a layer not doped with Zn by 0.1 μm is formed in the second cladding layer 106 in contact with the semiconductor layer 105 side during the growth, and the doped first layer is formed by the thermal history during the growth. The non-doped region of the second cladding layer 106 was doped by diffusion of Zn generated from the second cladding layer 106. However, the presence of the semiconductor layer 105 formed between the second cladding layer 106 and the non-doped active layer 104 prevented Zn diffusion.

  In this way, if a semiconductor layer having strain is formed in a non-doped region in advance, when the dopant diffuses due to the thermal history during growth, the dopant is prevented by the strained semiconductor layer and a desired region is doped. be able to. Here, considering the case where a semiconductor layer having a strain is formed at the interface between the doped layer and the non-doped layer, the semiconductor layer having a strain has an effect of preventing a dopant that diffuses from the doped layer to the non-doped layer. However, as described above, it is understood that when a semiconductor layer having a strain in a non-doped region is formed in advance, there is an effect of further preventing a diffusing dopant.

  Thus, the above-described configuration and manufacturing method of the semiconductor laser have an advantage that the strained semiconductor layer 105 can prevent diffusion of the dopant from the p-type cladding layer 106 to the active layer 104 and suppress degradation of the active layer due to the dopant. Original element characteristics can be realized.

In this embodiment, the case where the strained In _0.1 Ga _0.9 As _0.47 P _0.53 semiconductor layer 105 is provided between the active layer and the clad layer is illustrated, but the present invention is not limited to this. A non-doped light guide layer may be further provided between the active layer and the clad layer, and a strained semiconductor layer may be provided between the light guide layer and the clad layer. As a result, when the dopant diffuses into the guide layer, the defect formed by the dopant becomes an effect of preventing the deterioration of the characteristics of the element by becoming the recombination center of the light distributed in the guide layer.

  FIG. 5 is a cross-sectional view of a ridge embedded semiconductor laser which is a III-V group compound semiconductor device according to Example 3.

Referring to FIG. 5, n-type Al _0.5 Ga _0.5 As buffer layer 202 (thickness 0.5 μm, Si carrier concentration 1... On n-type GaAs substrate 201 (Si carrier concentration 2 × 10 ¹⁸ cm ⁻³ ). 5 × 10 ¹⁸ cm ⁻³ ), and n-type Al _0.4 Ga _0.6 As first cladding layer 203 (thickness 0.9 μm, Si carrier concentration 8 × 10 ¹⁷ cm ⁻³ ), Al _0.1 The active layer 204 of Ga _0.9 As (thickness 0.2 μm), the second cladding layer 205 (thickness 0.6 μm, Zn carrier concentration 2 × 10 ¹⁸ cm ⁻³ ) of p-type Al _0.4 Ga _0.6 As and compressive strain In _0.08 Ga _0.92 As semiconductor layer 206 (thickness 5 nm, strain amount + 0.5%) and p-type GaAs contact layer 207 (thickness 0.3 μm, Zn carrier concentration 5 × 10 ¹⁸ cm ⁻³ ) are sequentially stacked. Has been.
By etching, a mesa portion 209 including the second cladding layer 205, the semiconductor layer 206 having strain, and the p-type GaAs contact layer 207 is formed.

A current blocking layer 210 (thickness 0.3 μm, carrier concentration 1.5 × 10 ¹⁸ cm ⁻³ ) made of n-type GaAs is embedded so as to be in contact with the side surface of the mesa portion 209. On this laminate, titanium (Ti) having a thickness of about 100 nm, platinum (Pt) having a thickness of about 50 nm and gold (Au) having a thickness of about 400 nm were sequentially deposited by vapor deposition. A p-type electrode 211 made of Au is formed. On the other hand, under this laminate, that is, on the back side of the GaAs substrate 201, a gold-germanium alloy (Au—Ge) having a thickness of about 100 nm, nickel (Ni) having a thickness of about 15 nm, and gold having a thickness of about 300 nm ( An n-type electrode 212 made of Au—Ge / Ni / Au is provided by sequentially depositing Au).

  The strained semiconductor layer 206 does not pass Zn diffused from the p-type contact layer 207 to the cladding layer 205, and does not reduce the carrier concentration of the p-type contact layer 207. Therefore, a doping profile as designed can be formed, the resistance of the p-type contact layer 207 can be kept low, and the original threshold current of the device can be realized.

With reference to FIG. 6, a method of manufacturing the ridge embedded semiconductor laser shown in FIG. 5 will be described. Note that the crystal growth is performed using the MOCVD method, and the growth conditions are a growth temperature of 750 ° C., a growth pressure of 76 Torr, and V / III (ratio of supply amount of Group V element to Group III element) = 120. . Also, TMG (trimethylgallium) and TMA (trimethylaluminum) were used as group III materials, AsH ₃ (arsine) was used as group V materials, SiH ₄ (silane) and DEZn (diethyl zinc) were used as n-type and p-type dopant materials. . Hydrogen (H ₂ ) was used as the carrier gas.

First, as shown in FIG. 6A, on an n-type GaAs substrate 201 (Si carrier concentration 2 × 10 ¹⁸ cm ⁻³ ), an n-type Al _0.5 Ga _0.5 As buffer layer 202 (thickness 0.5 μm, A Si carrier concentration of 1.5 × 10 ¹⁸ cm ⁻³ ), and a first cladding layer 203 of n-type Al _0.4 Ga _0.6 As (thickness 0.9 μm, Si carrier concentration of 8 × 10 ¹⁷ cm ^{−). 3} ), Al _0.1 Ga _0.9 As (thickness 0.2 μm) active layer 204, p-type Al _0.4 Ga _0.6 As second cladding layer 205 (thickness 0.6 μm, Zn carrier concentration 2 × 10 ¹⁸ cm ^−3). ) And a compressive strained In _0.08 Ga _0.92 As semiconductor layer 206 (thickness 5 nm, strain amount + 0.5%) and p-type GaAs contact layer 207 (thickness 0.3 μm, Zn carrier concentration 5 × 10 ¹⁸ cm ^−3). ) In order, then the necessary parts on this laminate Forming a SiO ₂ mask 208.

  Next, as shown in FIGS. 6A and 6B, an etching solution that is a mixed aqueous solution of sulfuric acid and hydrogen peroxide solution is used to reduce the thickness h of the second cladding layer 205 by 0.3 μm. Etching is performed so as to leave a side surface of the mesa portion 209 including the second clad layer 205, the semiconductor layer 206 having strain, and the p-type GaAs contact layer 207.

Further, as shown in FIG. 6C, regrowth is performed using a metal organic chemical vapor deposition method, and an SiO ₂ mask 208 (thickness 0.3 μm) is used so as to contact the side surface of the mesa portion 209. Then, a current blocking layer 210 (thickness 0.3 μm, carrier concentration 1.5 × 10 ¹⁸ cm ⁻³ ) made of n-type GaAs, which has been selectively grown, is buried.

Finally, as shown in FIGS. 6C and 6D, the SiO ₂ mask 208 is removed, and titanium (Ti) with a thickness of about 100 nm and platinum (Pt with a thickness of about 50 nm) are formed on the stacked body. ) And gold (Au) having a thickness of about 400 nm are sequentially deposited by vapor deposition and patterned by photolithography and etching to form a p-type electrode 211 made of Ti / Pt / Au. On the other hand, under this laminate, that is, on the back side of the GaAs substrate 201, a gold-germanium alloy (Au—Ge) having a thickness of about 100 nm, nickel (Ni) having a thickness of about 15 nm, and gold having a thickness of about 300 nm ( Au) is sequentially deposited to form an n-type electrode 212 made of Au-Ge / Ni / Au. Then, by cleaving the stacked body, it can be divided into chips and a ridge embedded semiconductor laser can be manufactured.

By the way, the strained semiconductor layer 206 is made of InGaAs, and with this material, by adding a little In, strain is generated while maintaining the same band gap as that of the GaAs contact layer, thereby preventing diffusion of impurities from the contact layer. be able to. In order to further enhance the effect of preventing diffusion, since the layer thickness is 5 nm, the amount of strain can be increased to about 2%. The composition at this time is In _0.3 Ga _0.7 As. If the crystal growth exceeds 5 nm, misfit dislocations occur, resulting in a crystal that cannot be used as a device.

Further, although the case where an InGaAs material is used for the strained semiconductor layer 206 is illustrated here, an In _0.1 Ga _0.9 As _0.47 P _0.53 material may be used.

  Further, InAs may be used for the semiconductor layer 206 having strain. When an InAs monoatomic layer is used, InAs has a high strain (about 7%), dopant diffusion can be effectively prevented even in the monoatomic layer.

  Further, the InAs monoatomic layer may be combined with a plurality of unstrained layers. In this case, since the diffusion preventing layer of the dopant can be formed exceeding the critical film thickness, the effect of preventing diffusion is further enhanced. In other words, since the binary compound InAs is formed as a monomolecular layer, an atomic layer made of In having a high local strain is formed in the crystal. Therefore, when the dopant atoms pass through the InAs layer, Be sure to be affected by the high local strain caused by this In atom. Therefore, for example, a strained layer is formed by a mixed crystal such as InGaAs, and the diffusion of dopant can be suppressed more effectively with a thinner film thickness than when local strain is discretely formed in the crystal. It becomes. Although an example of InAs is shown here, the same effect can be obtained by using InSb, GaSb, AlSb, or the like.

  Thus, in the above-described configuration and manufacturing method of the semiconductor laser, the semiconductor layer 206 having strain does not pass Zn diffused from the p-type contact layer 207 to the cladding layer 205, and the carrier concentration of the p-type contact layer 207 Does not decrease. Therefore, a doping profile as designed can be formed, the resistance of the p-type contact layer 207 can be kept low, and the original threshold current of the device can be realized.

  In the above embodiment, the ridge buried type semiconductor laser element is exemplified as the compound semiconductor element. However, the present invention is not limited to this, and other semiconductor lasers, optical devices such as light emitting diodes, and high electron mobility transistors. And can be applied to electronic devices such as heterojunction bipolar transistors.

  Moreover, in the said Example, although illustrated about the III-V group compound semiconductor element, the problem of the spreading | diffusion of a dopant is seen also in another compound semiconductor element. The present invention is not limited to the case where GaAs is used as the substrate, and can be applied to a compound semiconductor device using a substrate other than the group III-V, such as an InP substrate or a GaN substrate.

  It should be understood that the embodiments disclosed herein are illustrative and non-restrictive in every respect. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  According to the compound semiconductor device of the present invention, a compound semiconductor device having a long device life and connected to an electrode with low resistance can be obtained.

1 is a cross-sectional view of an element of a ridge embedded semiconductor laser according to Example 1. FIG. It is a conceptual diagram for demonstrating the effect by which dopant diffusion is prevented by providing the semiconductor layer which has a distortion. (A) When a strained semiconductor layer is not formed (B) When a strained semiconductor layer is formed FIG. 3 is a conceptual diagram showing a state of light output of a ridge embedded semiconductor laser according to Example 1; FIG. 10 is a cross-sectional view in each step of the sequence of main manufacturing steps of the ridge embedded semiconductor laser according to Example 2; (A) It is a schematic cross section showing the state which laminated | stacked each semiconductor layer and attached the resist mask. (B) It is a schematic cross section showing the state in which the ridge stripe is formed. (C) It is a schematic cross section showing the state in which the current blocking layer was formed. (D) It is a schematic cross section showing the state which laminated | stacked the cap layer. 7 is a cross-sectional view of a ridge embedded semiconductor laser device according to Example 3. FIG. FIG. 10 is a cross-sectional view in each step of the sequence of main manufacturing steps of a ridge embedded semiconductor laser according to Example 4. (A) It is a schematic cross section showing the state which laminated | stacked each semiconductor layer and attached the resist mask. (B) It is a schematic cross section showing the state in which the ridge stripe is formed. (C) It is a schematic cross section showing the state in which the current blocking layer was formed. (D) It is a schematic cross section showing the state which laminated | stacked the cap layer. It is sectional drawing in each process of the order of the main manufacturing process of the element of the conventional ridge embedding type | mold semiconductor laser. (A) It is a schematic cross section showing the state which laminated | stacked each semiconductor layer and attached the resist mask. (B) It is a schematic cross section showing the state in which the ridge stripe is formed. (C) It is a schematic cross section showing the state in which the current blocking layer was formed. (D) It is a schematic cross section showing the state which laminated | stacked the cap layer.

Explanation of symbols

102 n-type Al _0.5 Ga _0.5 As buffer layer 103 n-type Al _0.4 Ga _0.6 As first cladding layer 104 Al _0.1 Ga _0.9 As active layer 105 In _0.1 Ga _0.9 As _0.47 P _0.53 semiconductor layer (strain layer)
106 p-type Al _0.4 Ga _0.6 As second clad layer 107 p-type GaAs contact layer 108 SiO ₂ mask 109 mesa 110 n-type GaAs current blocking layer 111 p-type electrode 112 n-type electrode 201 n-type GaAs substrate 202 n-type Al _0.5 Ga _0.5 As buffer layer 203 n-type Al _0.4 Ga _0.6 As first cladding layer 204 Al _0.1 Ga _0.9 As active layer 205 p-type Al _0.4 Ga _0.6 As second cladding layer 206 In _0.08 Ga _0.92 As semiconductor layer (Strain layer)
207 p-type GaAs contact layer 208 SiO ₂ mask 209 mesa portion 210 n-type GaAs current blocking layer 211 p-type electrode 212 n-type electrode 301 n-type GaAs substrate 302 buffer layer 303 first cladding layer 304 active layer 305 second cladding layer 306 p-type GaAs contact layer 307 SiO ₂ mask 308 mesa 309 n-type GaAs current blocking layer 310 p-type electrode 311 n-type electrode

Claims (9)

A first semiconductor layer doped with an impurity provided adjacent to the upper and lower sides on the substrate; and a second semiconductor layer not doped with the impurity or doped at a lower concentration than the first semiconductor layer. A semiconductor layer,
A compound semiconductor element in which a strained third semiconductor layer is provided between the first semiconductor layer and the second semiconductor layer.   2. The compound semiconductor device according to claim 1, wherein an absolute value of a strain amount of the third semiconductor layer is not less than 0.5% and not more than 10%.   2. The compound semiconductor device according to claim 1, wherein a thickness of the third semiconductor layer is not less than a monomolecular layer thickness and not more than 10 nm. 2. The compound according to claim 1, wherein the substrate is GaAs and the third semiconductor layer is In _1−x Ga _x As _1−y P _y “0 ≦ x, y ≦ 1”. Semiconductor element. The substrate is GaAs;
The strained third semiconductor layer is made of a binary compound containing a group III element having an atomic radius larger than Ga or a group V element having an atomic radius larger than As, and the layer thickness is not less than a monomolecular layer. The compound semiconductor device according to claim 1, wherein the compound semiconductor device is provided.   The compound semiconductor device according to claim 1, wherein the binary compound is InAs.   6. The compound semiconductor device according to claim 1, wherein an impurity is not doped in a part of the thickness of the first semiconductor layer on a side in contact with the third semiconductor layer. On the substrate, a first semiconductor layer doped with impurities and a second semiconductor layer not doped with impurities or doped at a lower concentration than the first semiconductor layer are vertically adjacent to each other. In the method for producing a III-V compound semiconductor device to be formed,
A method of manufacturing a compound semiconductor device, comprising: forming a strained third semiconductor layer between the first semiconductor layer and the second semiconductor layer.   In the step of forming the first semiconductor layer, on the side in contact with the third semiconductor layer, a part of the thickness of the first semiconductor layer is formed without doping impurities. The manufacturing method of the compound semiconductor element of Claim 6.

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