JP2015162605A - Substrate for device fabrication, manufacturing method thereof, and near infrared light-emitting device - Google Patents

Substrate for device fabrication, manufacturing method thereof, and near infrared light-emitting device Download PDF

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JP2015162605A
JP2015162605A JP2014037437A JP2014037437A JP2015162605A JP 2015162605 A JP2015162605 A JP 2015162605A JP 2014037437 A JP2014037437 A JP 2014037437A JP 2014037437 A JP2014037437 A JP 2014037437A JP 2015162605 A JP2015162605 A JP 2015162605A
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substrate
gaas
device fabrication
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lattice
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JP6241939B2 (en
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高明 間野
Takaaki Mano
高明 間野
和貴 三石
Kazuki Mitsuishi
和貴 三石
野田　武司
Takeshi Noda
武司 野田
晃浩 大竹
Akihiro Otake
晃浩 大竹
ヌル ハ
Neul Ha
ヌル ハ
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National Institute for Materials Science
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Abstract

PROBLEM TO BE SOLVED: To provide: a substrate for device fabrication which has no lattice strain and a flat surface; a simple and convenient manufacturing method of such a substrate; and a near infrared light-emitting device with the structure as described above.SOLUTION: A substrate 31 for device fabrication has a lattice relaxation layer 13 and a lattice-relaxed layer 14 which are stacked in this order on (111)A plane 12a of a GaAs substrate or GaAs buffer layer 12 formed on the GaAs substrate 11. The lattice relaxation layer 13 is an InAs thin film having a thickness of 0.7-1.8 nm. The lattice-relaxed layer 14 is an InMAs thin film (where Mrepresents a metal atom of Group III). Using the substrate 31 for device fabrication, the above objects can be achieved.

Description

本発明は、デバイス作製用基板、その製造方法及び近赤外線発光デバイスに関する。特に、格子歪みがなく、平坦な一面を有するデバイス作製用基板、その製造方法及び近赤外線発光デバイスに関する。   The present invention relates to a device manufacturing substrate, a manufacturing method thereof, and a near-infrared light emitting device. In particular, the present invention relates to a device manufacturing substrate having no flat lattice distortion and a flat surface, a manufacturing method thereof, and a near infrared light emitting device.

格子歪みがなく、平坦な一面を有するＩｎＧａＡｓ（砒化インジウムガリウム）薄膜は、その上に、バンドギャップ及び格子定数を広い範囲で自由に制御可能なデバイスを構築できる基板として検討されている。特に、高移動度電子半導体デバイスや近赤外発光デバイス等への応用が期待されている。   An InGaAs (indium gallium arsenide) thin film having a flat surface without lattice distortion has been studied as a substrate on which a device capable of freely controlling a band gap and a lattice constant in a wide range can be constructed. In particular, application to high mobility electronic semiconductor devices, near-infrared light emitting devices, and the like is expected.

通常、前記ＩｎＧａＡｓ薄膜は、市販されているＧａＡｓ（砒化ガリウム）半導体基板上にエピタキシャル成長させて作製される。
しかし、エピタキシャル成長の際、前記ＩｎＧａＡｓ薄膜の格子定数とＧａＡｓ基板の格子定数の相違により、ＩｎＧａＡｓ薄膜にＧａＡｓ基板との格子不整合に起因する歪みが生じ、更に、貫通転位などの欠陥が伝搬するという問題があった。 Usually, the InGaAs thin film is produced by epitaxial growth on a commercially available GaAs (gallium arsenide) semiconductor substrate.
However, during epitaxial growth, due to the difference between the lattice constant of the InGaAs thin film and the lattice constant of the GaAs substrate, distortion is caused in the InGaAs thin film due to lattice mismatch with the GaAs substrate, and defects such as threading dislocations propagate. There was a problem.

この問題を解決するために様々な対策が取られてきた。
例えば、特許文献１では、欠損型化合物層である（Ｇａ２Ｓｅ３）を界面に導入する事により歪みを緩和し、転位の発生伝搬を抑制している。しかし、Ｓｅを含む化合物の導入は、蒸気圧が高いためにＧａＡｓの品質を大幅に低下させた。 Various measures have been taken to solve this problem.
For example, in Patent Document 1, distortion is mitigated by introducing (Ga 2 Se 3 ), which is a defect type compound layer, into the interface, and dislocation propagation is suppressed. However, the introduction of a compound containing Se significantly reduced the quality of GaAs due to the high vapor pressure.

特許文献２では、多孔質化したＧａＡｓを界面に導入する事により、転位の抑制を試みている。しかし、多孔質化したＧａＡｓ形成では、複雑なプロセスの導入が必要となり、歩留まりが悪化し、コストを高めた。   In Patent Document 2, an attempt is made to suppress dislocation by introducing porous GaAs into the interface. However, the formation of porous GaAs requires the introduction of a complicated process, which deteriorates the yield and increases the cost.

非特許文献１では、有機気相成長（ＭＯＣＶＤ）法を用い、ＧａＡｓ（１００）基板上に１ミクロン以上の格子緩和層と呼ばれるＩｎＧａＡｓ中間層を導入して、歪みに起因する転位がＩｎ０．３Ｇａ０．７Ａｓ疑似基板に伝搬するのを防いでいる。しかし、５００ｎｍ以上という非常に厚い格子緩和層を導入する事により、製造コストを増大させるという問題を発生させた。 In Non-Patent Document 1, an organic vapor phase epitaxy (MOCVD) method is used to introduce an InGaAs intermediate layer called a lattice relaxation layer of 1 micron or more on a GaAs (100) substrate . thereby preventing 3 Ga 0.7 propagating to As pseudo substrate. However, the introduction of a very thick lattice relaxation layer of 500 nm or more has caused a problem of increasing the manufacturing cost.

非特許文献２には、分子線エピタキシー（ＭＢＥ）法を用い、ＧａＡｓ（１００）基板上に組成の異なるＩｎＧａＡｓを３層積層することにより、同様に転位がＩｎ０．２３Ｇａ０．７７Ａｓ疑似基板に伝搬するのを防いでいる。しかし、３層導入により、製造コストを増大させるという問題を発生させた。また、実用の際には結晶成長に必要なコストと作製の手間を大幅に悪化させた。 Non-Patent Document 2, using a molecular beam epitaxy (MBE) method, GaAs (100) by three-layer different InGaAs compositions on the substrate, similarly dislocations In 0.23 Ga 0.77 As pseudo Propagation to the substrate is prevented. However, the introduction of three layers caused a problem of increasing manufacturing costs. In practical use, the cost required for crystal growth and the time and effort of production were greatly deteriorated.

特開平７−６６３６６号公報JP-A-7-66366 特開２００３−８６６０７号公報JP 2003-86607 A

Ｈ．-Ｑ．Ｎｇｕｙｅｎ ｅｔ ａｌ．，Ａｐｐｌｉｅｄ Ｐｈｙｓｉｃｓ Ｅｘｐｒｅｓｓ ５，（２０１２）０５５５０３．H. -Q. Nguyen et al. , Applied Physics Express 5, (2012) 0555503. Ｚ．Ｍｉ ｅｔ ａｌ．，Ｊｏｕｒｎａｌ ｏｆ Ｖａｃｕｕｍ Ｓｃｉｅｎｃｅ ＆ Ｔｅｃｈｎｏｌｏｇｙ Ｂ２６，（２００８）１１５３．Z. Mi et al. , Journal of Vacuum Science & Technology B26, (2008) 1153. Ａ．Ｏｈｔａｋｅ ｅｔ ａｌ．，Ｐｈｙｓｉｃａｌ Ｒｅｖｉｅｗ Ｌｅｔｔｅｒｓ ８４，（２０００）４６６５．A. Ohtake et al. , Physical Review Letters 84, (2000) 4665.

本発明は、格子歪みがなく、平坦な一面を有するデバイス作製用基板、その簡便な製造方法、上記構造を用いた近赤外線発光デバイスを提供することを課題とする。   It is an object of the present invention to provide a device manufacturing substrate having no flat lattice distortion and having a flat surface, a simple manufacturing method thereof, and a near infrared light emitting device using the above structure.

本発明者は、上記事情を鑑みて、分子線エピタキシー（ＭＢＥ）法を用いてＧａＡｓ（１１１）Ａ基板上に高品質の単結晶ＩｎＡｓ薄膜を結晶成長により形成する研究を行ってきた（非特許文献３）。この研究では、分子線エピタキシー法をもちいて、ＧａＡｓ（１１１）Ａ基板表面上にＩｎＡｓを成長させた場合、成長初期に転位が導入されて急峻に歪みが緩和することにより、高品質で平坦なＩｎＡｓ層を成長可能であることを報告した。そしてその成長の初期において、ＩｎＡｓ表面の面内の格子定数がＧａＡｓからＩｎＡｓへと変化することを報告した。これらの知見に基づいて、試行錯誤を行った結果、ＧａＡｓの（１１１）Ａ面上に、０．７ｎｍ以上１．８ｎｍ未満の厚さのＩｎＡｓ薄膜（格子緩和層）を導入するだけで、格子歪みがなく、平坦な一面を有するＩｎｘＧａ１−ｘＡｓ薄膜（０．２３≦ｘ≦０．７５）（被格子緩和層）を形成することができ、本研究を完成した。また、被格子緩和層の上に量子井戸構造を形成することにより、近赤外域で発光するデバイスを作製できた。
本発明は、以下の構成を有する。 In view of the above circumstances, the present inventor has conducted research to form a high-quality single-crystal InAs thin film on a GaAs (111) A substrate by crystal growth using a molecular beam epitaxy (MBE) method (non-patented). Reference 3). In this study, when InAs is grown on the surface of a GaAs (111) A substrate by using molecular beam epitaxy, dislocations are introduced at the initial stage of growth and the strain is relieved sharply, so that high quality and flatness is achieved. It has been reported that an InAs layer can be grown. It was reported that the in-plane lattice constant of the InAs surface changed from GaAs to InAs at the beginning of the growth. As a result of trial and error based on these findings, it is possible to obtain a lattice by simply introducing an InAs thin film (lattice relaxation layer) having a thickness of 0.7 nm to less than 1.8 nm on the (111) A surface of GaAs. An In x Ga 1-x As thin film (0.23 ≦ x ≦ 0.75) (lattice relaxation layer) having no strain and having a flat surface can be formed, and this study was completed. In addition, by forming a quantum well structure on the lattice relaxation layer, a device that emits light in the near-infrared region could be fabricated.
The present invention has the following configuration.

（１） ＧａＡｓ基板又はＧａＡｓ基板に形成したＧａＡｓバッファ層の（１１１）Ａ面に格子緩和層と被格子緩和層をこの順序で積層したデバイス作製用基板であって、前記格子緩和層が膜厚０．７ｎｍ以上１．８ｎｍ以下のＩｎＡｓ薄膜であり、前記被格子緩和層がＩｎＭ（ＩＩＩ）Ａｓ薄膜（ここで、Ｍ（ＩＩＩ）がＩＩＩ族の金属原子である。）であることを特徴とするデバイス作製用基板。 (1) A device manufacturing substrate in which a lattice relaxation layer and a lattice relaxation layer are laminated in this order on a (111) A surface of a GaAs substrate or a GaAs buffer layer formed on a GaAs substrate, and the lattice relaxation layer has a film thickness It is an InAs thin film of 0.7 nm or more and 1.8 nm or less, and the lattice relaxation layer is an InM (III) As thin film (where M (III) is a group III metal atom). A device manufacturing substrate.

（２） 前記Ｍ（ＩＩＩ）がＧａ又はＡｌであることを特徴とするデバイス作製用基板。
（３） 前記Ｍ（ＩＩＩ）がＧａであり、前記被格子緩和層がＩｎｘＧａ１−ｘＡｓ膜（０．２３≦ｘ≦０．７５）であることを特徴とするデバイス作製用基板。
（４） 前記ＩｎｘＧａ１−ｘＡｓ膜（０．２３≦ｘ≦０．７５）の膜厚が５０ｎｍ以上１５０ｎｍ以下であることを特徴とするデバイス作製用基板。 (2) The device fabrication substrate, wherein M (III) is Ga or Al.
(3) The device manufacturing substrate, wherein the M (III) is Ga, and the lattice relaxation layer is an In x Ga 1-x As film (0.23 ≦ x ≦ 0.75).
(4) The device manufacturing substrate, wherein the In x Ga 1-x As film (0.23 ≦ x ≦ 0.75) has a thickness of 50 nm to 150 nm.

（５） ＧａＡｓ基板又はＧａＡｓ基板に形成したＧａＡｓバッファ層の（１１１）Ａ面上に、膜厚０．７ｎｍ以上１．８ｎｍ以下のＩｎＡｓ薄膜からなる格子緩和層を形成する工程と、前記格子緩和層上にＩｎＭ（ＩＩＩ）Ａｓ薄膜（ここで、Ｍ（ＩＩＩ）がＩＩＩ族の金属原子である。）からなる被格子緩和層を形成する工程と、を有することを特徴とするデバイス作製用基板の製造方法。 (5) A step of forming a lattice relaxation layer made of an InAs thin film having a film thickness of 0.7 nm or more and 1.8 nm or less on a (111) A surface of a GaAs substrate or a GaAs buffer layer formed on the GaAs substrate, and the lattice relaxation Forming a lattice relaxation layer made of an InM (III) As thin film (wherein M (III) is a group III metal atom) on the layer. Manufacturing method.

（６） （１）〜（４）のいずれかに記載のデバイス作製用基板のＩｎＧａＡｓ薄膜のデバイス作製面上に、薄膜を積層して、量子井戸構造を形成したことを特徴とする近赤外線発光デバイス。 (6) Near infrared emission characterized in that a quantum well structure is formed by laminating a thin film on the device fabrication surface of the InGaAs thin film of the device fabrication substrate according to any one of (1) to (4). device.

本発明のデバイス作製用基板は、ＧａＡｓ基板又はＧａＡｓ基板に形成したＧａＡｓバッファ層の（１１１）Ａ面に格子緩和層と被格子緩和層をこの順序で積層したデバイス作製用基板であって、前記格子緩和層が膜厚０．７ｎｍ以上１．８ｎｍ以下のＩｎＡｓ薄膜であり、前記被格子緩和層がＩｎＭ（ＩＩＩ）Ａｓ薄膜（ここで、Ｍ（ＩＩＩ）がＩＩＩ族の金属原子である。）である構成なので、格子緩和層が被格子緩和層の格子定数の歪みを無くし、被格子緩和層の露出面を二乗平均粗さ０．６５ｎｍ以下で、格子定数の歪みの無い面とすることができ、膜厚を精密に限定して積層膜を形成することができ、所望の量子井戸構造を形成できる。これにより、優れた近赤外線発光デバイスを構築できる。 The device fabrication substrate of the present invention is a device fabrication substrate in which a lattice relaxation layer and a lattice relaxation layer are laminated in this order on the (111) A surface of a GaAs substrate or a GaAs buffer layer formed on the GaAs substrate, The lattice relaxation layer is an InAs thin film having a thickness of 0.7 nm to 1.8 nm, and the lattice relaxation layer is an InM (III) As thin film (where M (III) is a group III metal atom). Therefore, the lattice relaxation layer can eliminate the lattice constant distortion of the lattice relaxation layer, and the exposed surface of the lattice relaxation layer can be a surface having a root mean square roughness of 0.65 nm or less and no lattice constant distortion. In addition, a laminated film can be formed by precisely limiting the film thickness, and a desired quantum well structure can be formed. Thereby, an excellent near-infrared light emitting device can be constructed.

本発明のデバイス作製用基板の製造方法は、ＧａＡｓ基板又はＧａＡｓ基板に形成したＧａＡｓバッファ層の（１１１）Ａ面上に、膜厚０．７ｎｍ以上１．８ｎｍ以下のＩｎＡｓ薄膜からなる格子緩和層を形成する工程と、前記格子緩和層上にＩｎＭ（ＩＩＩ）Ａｓ薄膜（ここで、Ｍ（ＩＩＩ）がＩＩＩ族の金属原子である。）からなる被格子緩和層を形成する工程と、を有する構成なので、二乗平均粗さ０．６５ｎｍ以下で、格子定数の歪みの無い面を有する被格子緩和層を、非常に薄い格子緩和層を導入するだけで簡単に形成でき、二乗平均粗さ０．６５ｎｍ以下で、格子定数の歪みの無い面を有するデバイス作製用基板を簡便に製造できる。 The method for manufacturing a device manufacturing substrate according to the present invention includes a lattice relaxation layer comprising an InAs thin film having a thickness of 0.7 nm to 1.8 nm on a (111) A surface of a GaAs substrate or a GaAs buffer layer formed on the GaAs substrate. And a step of forming a lattice relaxation layer made of an InM (III) As thin film (wherein M (III) is a Group III metal atom) on the lattice relaxation layer. Because of this configuration, a lattice relaxation layer having a surface having a square average roughness of 0.65 nm or less and having no lattice constant distortion can be easily formed by simply introducing a very thin lattice relaxation layer. A device fabrication substrate having a surface with a lattice constant of 65 nm or less and no distortion can be easily produced.

本発明の近赤外線発光デバイスは、先に記載のデバイス作製用基板のＩｎＧａＡｓ薄膜のデバイス作製面上に、薄膜を積層して、量子井戸構造を形成した構成なので、発光波長を近赤外に限定した発光デバイスとすることができる。   The near-infrared light-emitting device of the present invention has a structure in which a quantum well structure is formed by laminating a thin film on the device fabrication surface of the InGaAs thin film of the device fabrication substrate described above, so the emission wavelength is limited to the near infrared Light emitting device.

本発明の実施形態であるデバイス作製用基板の一例を示す側面図である。It is a side view showing an example of a device fabrication substrate which is an embodiment of the present invention. 本発明の実施形態であるデバイス作製用基板の製造方法の一例を示すフローチャート図である。It is a flowchart figure which shows an example of the manufacturing method of the board | substrate for device preparation which is embodiment of this invention. 本発明の実施形態である近赤外線発光デバイスの一例を示す側面図である。It is a side view which shows an example of the near-infrared light-emitting device which is embodiment of this invention. ＧａＡｓ（１１１）A基板をインジウムハンダでモリブデン製基板ホルダに貼り付けてから加熱する様子を説明する図である。It is a figure explaining a mode that it heats, after affixing a GaAs (111) A board | substrate to a molybdenum substrate holder with an indium solder. 実施例１のデバイス作製用基板のＩｎ０．２３Ｇａ０．７７Ａｓ表面の５μｍ×５μｍの領域の原子間力顕微鏡（ＡＦＭ）像である。2 is an atomic force microscope (AFM) image of a 5 μm × 5 μm region of the In 0.23 Ga 0.77 As surface of the device fabrication substrate of Example 1. FIG. 実施例２のデバイス作製用基板のＩｎ０．２３Ｇａ０．７７Ａｓ表面の５μｍ×５μｍの領域の原子間力顕微鏡（ＡＦＭ）像である。4 is an atomic force microscope (AFM) image of a 5 μm × 5 μm region of the In 0.23 Ga 0.77 As surface of the device fabrication substrate of Example 2. FIG. 実施例２のデバイス作製用基板のデバイス作製用基板のＸ線回折（１１５）入射逆格子マッピングの結果である。It is a result of the X-ray diffraction (115) incident reciprocal lattice mapping of the device manufacturing substrate of the device manufacturing substrate of Example 2. 実施例２のデバイス作製用基板を用いて作製した近赤外線発光デバイスの擬略側面図である。It is a quasi-schematic side view of the near-infrared light-emitting device produced using the device production board | substrate of Example 2. FIG. 実施例２のデバイス作製用基板を用いて作製した近赤外線発光デバイスの発光スペクトルである。2 is an emission spectrum of a near infrared light emitting device manufactured using the device manufacturing substrate of Example 2. 実施例３のデバイス作製用基板のＩｎ０．２３Ｇａ０．７７Ａｓ表面の５μｍ×５μｍの領域の原子間力顕微鏡（ＡＦＭ）像である。4 is an atomic force microscope (AFM) image of a 5 μm × 5 μm region of the In 0.23 Ga 0.77 As surface of the device fabrication substrate of Example 3. FIG. 比較例１のデバイス作製用基板のＩｎ０．２３Ｇａ０．７７Ａｓ表面の５μｍ×５μｍの領域の原子間力顕微鏡（ＡＦＭ）像である。4 is an atomic force microscope (AFM) image of a 5 μm × 5 μm region of the In 0.23 Ga 0.77 As surface of the device fabrication substrate of Comparative Example 1. FIG. 比較例１のデバイス作製用基板のデバイス作製用基板のＸ線回折（１１５）入射逆格子マッピングの結果である。It is a result of the X-ray diffraction (115) incident reciprocal lattice mapping of the device manufacturing substrate of the device manufacturing substrate of Comparative Example 1. 比較例２のデバイス作製用基板のＩｎ０．２３Ｇａ０．７７Ａｓ表面の５μｍ×５μｍの領域の原子間力顕微鏡（ＡＦＭ）像である。4 is an atomic force microscope (AFM) image of a 5 μm × 5 μm region on the In 0.23 Ga 0.77 As surface of a device fabrication substrate of Comparative Example 2. FIG. 比較例１、２の一例を示す断面模式図である。It is a cross-sectional schematic diagram which shows an example of the comparative examples 1 and 2. FIG. 比較例３のデバイス作製用基板のＩｎ０．２３Ｇａ０．７７Ａｓ表面の５μｍ×５μｍの領域の原子間力顕微鏡（ＡＦＭ）像である。4 is an atomic force microscope (AFM) image of a 5 μm × 5 μm region of the In 0.23 Ga 0.77 As surface of a device fabrication substrate of Comparative Example 3. 比較例４のデバイス作製用基板のＩｎ０．２３Ｇａ０．７７Ａｓ表面の５μｍ×５μｍの領域の原子間力顕微鏡（ＡＦＭ）像である。6 is an atomic force microscope (AFM) image of a 5 μm × 5 μm region of the In 0.23 Ga 0.77 As surface of a device fabrication substrate of Comparative Example 4. 比較例３、４の一例を示す断面模式図である。It is a cross-sectional schematic diagram which shows an example of the comparative examples 3 and 4. FIG. 比較例５のデバイス作製用基板のＩｎ０．２３Ｇａ０．７７Ａｓ表面の５μｍ×５μｍの領域の原子間力顕微鏡（ＡＦＭ）像である。6 is an atomic force microscope (AFM) image of a 5 μm × 5 μm region of the In 0.23 Ga 0.77 As surface of a device fabrication substrate of Comparative Example 5. FIG. 比較例５のデバイス作製用基板のデバイス作製用基板のＸ線回折（１１５）入射逆格子マッピングの結果である。It is a result of the X-ray diffraction (115) incident reciprocal lattice mapping of the device manufacturing substrate of the device manufacturing substrate of Comparative Example 5. 実施例４のデバイス作製用基板のＩｎ０．５１Ｇａ０．４９Ａｓ表面の５μｍ×５μｍの領域の原子間力顕微鏡（ＡＦＭ）像である。4 is an atomic force microscope (AFM) image of a 5 μm × 5 μm region of the In 0.51 Ga 0.49 As surface of the device fabrication substrate of Example 4. 実施例４のデバイス作製用基板のデバイス作製用基板のＸ線回折（１１５）入射逆格子マッピングの結果である。It is a result of the X-ray diffraction (115) incident reciprocal lattice mapping of the device manufacturing substrate of the device manufacturing substrate of Example 4. 実施例５のデバイス作製用基板のＩｎ０．７５Ｇａ０．２５Ａｓ表面の５μｍ×５μｍの領域の原子間力顕微鏡（ＡＦＭ）像である。6 is an atomic force microscope (AFM) image of a 5 μm × 5 μm region of the In 0.75 Ga 0.25 As surface of the device fabrication substrate of Example 5. FIG. 実施例５のデバイス作製用基板のデバイス作製用基板のＸ線回折（１１５）入射逆格子マッピングの結果である。It is a result of X-ray diffraction (115) incidence reciprocal lattice mapping of the device manufacturing substrate of the device manufacturing substrate of Example 5. 実施例６のデバイス作製用基板のＩｎ０．５２Ａｌ０．４８Ａｓ表面の５μｍ×５μｍの領域の原子間力顕微鏡（ＡＦＭ）像である。7 is an atomic force microscope (AFM) image of a 5 μm × 5 μm region of the In 0.52 Al 0.48 As surface of the device fabrication substrate of Example 6. 実施例６のデバイス作製用基板のデバイス作製用基板のＸ線回折（１１５）入射逆格子マッピングの結果である。It is a result of the X-ray diffraction (115) incident reciprocal lattice mapping of the device manufacturing substrate of the device manufacturing substrate of Example 6. 実施例６のデバイス作製用基板を用いて作製した別の近赤外線発光デバイスの擬略側面図である。It is a quasi-schematic side view of another near-infrared light-emitting device produced using the device production substrate of Example 6. 実施例６のデバイス作製用基板を用いて作製した別の近赤外線発光デバイスの発光スペクトルである。7 is an emission spectrum of another near-infrared light emitting device manufactured using the device manufacturing substrate of Example 6. 実施例７のデバイス作製用基板の（ａ）はＩｎ０．２３Ｇａ０．７７Ａｓを５０ｎｍ、（ｂ）はＩｎ０．２３Ｇａ０．７７Ａｓを１００ｎｍ、（ｃ）はＩｎ０．２３Ｇａ０．７７Ａｓを１５０ｎｍ成長した表面のＲＨＥＥＤパターンを示す図である。(A) of the device fabrication substrate of Example 7 is 50 nm of In 0.23 Ga 0.77 As, (b) is 100 nm of In 0.23 Ga 0.77 As, and (c) is In 0.23 Ga. It is a figure which shows the RHEED pattern of the surface which grew 0.77As 150nm. 実施例８のデバイス作製用基板の（ａ）はＩｎ０．５２Ａｌ０．４８Ａｓを５０ｎｍ、（ｂ）はＩｎ０．５２Ａｌ０．４８Ａｓを１００ｎｍ、（ｃ）はＩｎ０．５２Ａｌ０．４８Ａｓを１５０ｎｍ成長した表面のＲＨＥＥＤパターンを示す図である。(A) of the device manufacturing substrate of Example 8 is 50 nm of In 0.52 Al 0.48 As, (b) is 100 nm of In 0.52 Al 0.48 As, and (c) is In 0.52 Al. It is a figure which shows the RHEED pattern of the surface which grew 0.48 As 150 nm.

（本発明の実施形態）
＜デバイス作製用基板＞
まず、本発明の実施形態であるデバイス作製用基板について説明する。
図１は、本発明の実施形態であるデバイス作製用基板の一例を示す側面図である。
図１に示すように、本発明の実施形態であるデバイス作製用基板３１は、ＧａＡｓ基板１１と、ＧａＡｓバッファ層１２と、ＩｎＡｓ薄膜１３と、ＩｎＭ（ＩＩＩ）Ａｓ膜１４とをこの順序で積層してなる。 (Embodiment of the present invention)
<Device fabrication substrate>
First, a device manufacturing substrate according to an embodiment of the present invention will be described.
FIG. 1 is a side view showing an example of a device fabrication substrate according to an embodiment of the present invention.
As shown in FIG. 1, a device manufacturing substrate 31 according to an embodiment of the present invention includes a GaAs substrate 11, a GaAs buffer layer 12, an InAs thin film 13, and an InM (III) As film 14 stacked in this order. Do it.

ＩｎＡｓ薄膜１３の膜厚は０．７ｎｍ以上１．８ｎｍ以下とされている。ＩｎＡｓ薄膜１３を導入することにより、ＩｎＡｓ薄膜１３がその上に積層されるＩｎＭ（ＩＩＩ）Ａｓ膜１４を格子緩和して、格子歪みがなく、平坦な一面を有するＩｎＭ（ＩＩＩ）Ａｓ膜１４を形成できる。
０．７ｎｍ未満では、ＩｎＡｓを格子緩和できず、その上に形成するＩｎＭ（ＩＩＩ）Ａｓ膜１４も格子緩和できない。そのため、格子歪みがなく、平坦な一面を有するＩｎＭ（ＩＩＩ）Ａｓ膜１４を形成できない。例えば、ＩｎｘＧａ１−ｘＡｓ は、一定の値まで格子緩和せず（ＧａＡｓの格子定数に合わせたまま）に成長し、その後、格子不整合転位が形成されることにより、表面が著しく荒れる。 The thickness of the InAs thin film 13 is 0.7 nm or more and 1.8 nm or less. By introducing the InAs thin film 13, the InM (III) As film 14 on which the InAs thin film 13 is laminated is lattice-relaxed, and the InM (III) As film 14 having no flat lattice distortion and having a flat surface is obtained. Can be formed.
If the thickness is less than 0.7 nm, InAs cannot be lattice-relaxed, and the InM (III) As film 14 formed thereon cannot be lattice-relaxed. Therefore, the InM (III) As film 14 having no lattice distortion and having a flat surface cannot be formed. For example, In x Ga 1-x As grows without lattice relaxation to a certain value (while maintaining the lattice constant of GaAs), and then a lattice mismatch dislocation is formed, so that the surface becomes extremely rough. .

また、１．８ｎｍ超でも、ＩｎＡｓ薄膜がＩｎＡｓ本来の特性を持ち始め、ＩｎＡｓとＩｎｘＧａ１−ｘＡｓの間の格子不整合により、ＩｎｘＧａ１−ｘＡｓ層の平坦性を悪化させる。格子歪みがなく、平坦な一面を有するＩｎＭ（ＩＩＩ）Ａｓ膜１４を形成できない。 In addition, even if it exceeds 1.8 nm, the InAs thin film starts to have InAs inherent characteristics, and the flatness of the In x Ga 1-x As layer is deteriorated due to lattice mismatch between InAs and In x Ga 1-x As. . There is no lattice distortion and the InM (III) As film 14 having a flat surface cannot be formed.

ＩｎＭ（ＩＩＩ）Ａｓ薄膜１４は、ＩｎｘＭ（ＩＩＩ）１−ｘＡｓ薄膜（０．２３≦ｘ≦０．７５）であることが好ましい。これにより、ＩｎＡｓ薄膜の平坦化が実現できる。０．２３未満では格子定数がＧａＡｓと近すぎるために、表面平坦性を悪化させる可能性があり、０．７５超では、格子定数及びバンドギャップがＩｎＡｓバルクと近くなりすぎるため、近赤外域デバイ作製用の基板として適さない。Ｇａの代わりにＡｌを用いた場合においても、同様の効果が期待できる。Ｍ（ＩＩＩ）はＩＩＩ族の金属原子であり、例えば、Ｇａ、Ａｌである。 The InM (III) As thin film 14 is preferably an In x M (III) 1-x As thin film (0.23 ≦ x ≦ 0.75). Thereby, planarization of the InAs thin film can be realized. If it is less than 0.23, the lattice constant is too close to GaAs, which may deteriorate the surface flatness. If it exceeds 0.75, the lattice constant and the band gap are too close to the InAs bulk. It is not suitable as a substrate for manufacturing. A similar effect can be expected when Al is used instead of Ga. M (III) is a Group III metal atom, for example, Ga or Al.

ＧａＡｓ基板の（１１１）Ａ面上にＩｎＡｓ薄膜１３を形成してもよいが、ＧａＡｓ基板の（１１１）Ａ面上に成膜されたＧａＡｓバッファ層の（１１１）Ａ面上にＩｎＡｓ薄膜１３を形成することが好ましい。ＧａＡｓ基板上にＩｎＡｓ薄膜１３を成膜する場合に比べて、より清浄化された面にＩｎＡｓ薄膜１３を成膜でき、不純物欠陥等を少なくできるためである。   Although the InAs thin film 13 may be formed on the (111) A surface of the GaAs substrate, the InAs thin film 13 is formed on the (111) A surface of the GaAs buffer layer formed on the (111) A surface of the GaAs substrate. It is preferable to form. This is because the InAs thin film 13 can be formed on a cleaner surface and the impurity defects and the like can be reduced as compared with the case where the InAs thin film 13 is formed on the GaAs substrate.

＜デバイス作製用基板の製造方法＞
次に、本発明の実施形態であるデバイス作製用基板の製造方法について説明する。
図２は、本発明の実施形態であるデバイス作製用基板の製造方法の一例を示すフローチャート図である。
図２に示すように、本発明の実施形態であるデバイス作製用基板の製造方法は、ＩｎＡｓ薄膜形成工程Ｓ１と、ＩｎＧａＡｓ薄膜成膜工程Ｓ２と、を有する。 <Method for manufacturing substrate for device fabrication>
Next, a method for manufacturing a device manufacturing substrate according to an embodiment of the present invention will be described.
FIG. 2 is a flowchart showing an example of a method for manufacturing a device manufacturing substrate according to an embodiment of the present invention.
As shown in FIG. 2, the device manufacturing substrate manufacturing method according to the embodiment of the present invention includes an InAs thin film forming step S1 and an InGaAs thin film forming step S2.

（ＩｎＡｓ薄膜形成工程Ｓ１）
まず、ＧａＡｓ基板の（１１１）Ａ面を清浄化する。
次に、分子線エピタキシー（ＭＢＥ）法で、ＧａＡｓ基板の（１１１）Ａ面上に、ＩｎＡｓ薄膜を膜厚０．７ｎｍ以上１．８ｎｍ以下で形成する。 (InAs thin film forming step S1)
First, the (111) A surface of the GaAs substrate is cleaned.
Next, an InAs thin film having a film thickness of 0.7 nm to 1.8 nm is formed on the (111) A surface of the GaAs substrate by molecular beam epitaxy (MBE).

（ＩｎＧａＡｓ薄膜成膜工程Ｓ２）
分子線エピタキシー（ＭＢＥ）法で、ＩｎＡｓ薄膜上にＩｎＧａＡｓ薄膜を成膜する。 (InGaAs thin film forming step S2)
An InGaAs thin film is formed on the InAs thin film by molecular beam epitaxy (MBE).

なお、ＩｎＡｓ薄膜形成工程Ｓ１の前工程として、ＧａＡｓ基板の（１１１）Ａ面を熱処理により酸化膜除去を行う事により清浄化してから、ＧａＡｓ基板の（１１１）Ａ面上にＧａＡｓバッファ層を成膜するＧａＡｓバッファ層成膜工程を設けてもよい。   As a pre-process of the InAs thin film forming step S1, the (111) A surface of the GaAs substrate is cleaned by removing the oxide film by heat treatment, and then a GaAs buffer layer is formed on the (111) A surface of the GaAs substrate. A step of forming a GaAs buffer layer may be provided.

＜近赤外線発光デバイス＞
次に、本発明の実施形態である近赤外線発光デバイスについて説明する。
図３は、本発明の実施形態である近赤外線発光デバイスの一例を示す側面図である。
図３に示すように、本発明の実施形態である近赤外線発光デバイス６１は、デバイス作製用基板３１のＩｎＭ（ＩＩＩ）Ａｓ膜１４の一面１４ａ上に、薄膜４１〜５０を積層して、量子井戸構造５１を形成してなる。 <Near infrared light emitting device>
Next, a near infrared light emitting device according to an embodiment of the present invention will be described.
FIG. 3 is a side view showing an example of a near infrared light emitting device according to an embodiment of the present invention.
As shown in FIG. 3, the near-infrared light emitting device 61 according to the embodiment of the present invention includes a thin film 41 to 50 stacked on one surface 14 a of the InM (III) As film 14 of the device manufacturing substrate 31. A well structure 51 is formed.

量子井戸構造５１としては、例えば、ＩｎｘＧａ１−ｘＡｓ量子井戸／ＩｎｘＡｌ１−ｘＡｓ構造や、ＩｎＡｓ量子ドット／ＩｎＡｌＧａＡｓ構造を挙げることができる。
所定の波長の発光が可能な材料を選択し、量子井戸での閉じ込め効果を勘案することにより、所望の近赤外域領域で発光させることができる。 Examples of the quantum well structure 51 include an In x Ga 1-x As quantum well / In x Al 1-x As structure and an InAs quantum dot / InAlGaAs structure.
By selecting a material that can emit light of a predetermined wavelength and considering the confinement effect in the quantum well, light can be emitted in a desired near-infrared region.

本発明の実施形態であるデバイス作製用基板は、ＧａＡｓ基板又はＧａＡｓ基板に形成したＧａＡｓバッファ層の（１１１）Ａ面に格子緩和層と被格子緩和層をこの順序で積層したデバイス作製用基板であって、前記格子緩和層が膜厚０．７ｎｍ以上１．８ｎｍ以下のＩｎＡｓ薄膜であり、前記被格子緩和層がＩｎＭ（ＩＩＩ）Ａｓ薄膜（ここで、Ｍ（ＩＩＩ）がＩＩＩ族の金属原子である。）である構成なので、格子緩和層が被格子緩和層の格子定数の歪みを無くし、被格子緩和層の露出面を二乗平均粗さ０．６５ｎｍ以下で、格子定数の歪みの無い面とすることができ、膜厚を精密に限定して積層膜を形成することができ、所望の量子井戸構造を形成できる。これにより、優れた近赤外線発光デバイスを構築できる。 A device fabrication substrate according to an embodiment of the present invention is a device fabrication substrate in which a lattice relaxation layer and a lattice relaxation layer are laminated in this order on the (111) A surface of a GaAs substrate or a GaAs buffer layer formed on the GaAs substrate. The lattice relaxation layer is an InAs thin film having a thickness of 0.7 nm to 1.8 nm, and the lattice relaxation layer is an InM (III) As thin film (where M (III) is a group III metal atom. Therefore, the lattice relaxation layer eliminates the lattice constant distortion of the lattice relaxation layer, the exposed surface of the lattice relaxation layer has a root mean square roughness of 0.65 nm or less, and has no lattice constant distortion. The film thickness can be precisely limited to form a laminated film, and a desired quantum well structure can be formed. Thereby, an excellent near-infrared light emitting device can be constructed.

本発明の実施形態であるデバイス作製用基板は、前記Ｍ（ＩＩＩ）がＧａ又はＡｌである構成なので、ＧａとＡｌの比率を変える事により禁制帯幅を制御できる。 Since the device manufacturing substrate according to the embodiment of the present invention has a configuration in which the M (III) is Ga or Al, the forbidden bandwidth can be controlled by changing the ratio of Ga and Al.

本発明の実施形態であるデバイス作製用基板は、前記Ｍ（ＩＩＩ）がＧａであり、前記被格子緩和層がＩｎｘＧａ１−ｘＡｓ膜（０．２３≦ｘ≦０．７５）である構成なので、平坦な面であって、格子定数の歪みの無い面を形成することができる。 In the device fabrication substrate according to an embodiment of the present invention, the M (III) is Ga, and the lattice relaxation layer is an In x Ga 1-x As film (0.23 ≦ x ≦ 0.75). Since the structure is used, a flat surface having no lattice constant distortion can be formed.

本発明の実施形態であるデバイス作製用基板は、前記ＩｎｘＧａ１−ｘＡｓ膜（０．２３≦ｘ≦０．７５）の膜厚が５０ｎｍ以上１５０ｎｍ以下である構成なので、平坦な面であって、格子定数の歪みの無い面を形成することができる。 The device fabrication substrate according to an embodiment of the present invention has a flat surface because the In x Ga 1-x As film (0.23 ≦ x ≦ 0.75) has a thickness of 50 nm to 150 nm. Thus, it is possible to form a surface free from lattice constant distortion.

本発明のデバイス作製用基板の製造方法は、ＧａＡｓ基板又はＧａＡｓ基板上に形成したＧａＡｓバッファ層の（１１１）Ａ面上に、膜厚０．７ｎｍ以上１．８ｎｍ以下のＩｎＡｓ薄膜からなる格子緩和層を形成する工程Ｓ１と、前記格子緩和層上にＩｎＭ（ＩＩＩ）Ａｓ薄膜（ここで、Ｍ（ＩＩＩ）がＩＩＩ族の金属原子である。）からなる被格子緩和層を形成する工程Ｓ２と、を有する構成なので、二乗平均粗さ０．６５ｎｍ以下で、格子定数の歪みの無い面を有する被格子緩和層を、非常に薄い格子緩和層を導入するだけで簡単に形成でき、二乗平均粗さ０．６５ｎｍ以下で、格子定数の歪みの無い面を有するデバイス作製用基板を簡便に製造できる。 The method for manufacturing a device manufacturing substrate according to the present invention includes a lattice relaxation comprising an InAs thin film having a thickness of 0.7 nm or more and 1.8 nm or less on a (111) A surface of a GaAs substrate or a GaAs buffer layer formed on the GaAs substrate. Step S1 for forming a layer, Step S2 for forming a lattice relaxation layer made of an InM (III) As thin film (wherein M (III) is a group III metal atom) on the lattice relaxation layer, and Therefore, it is possible to easily form a lattice relaxation layer having a square mean roughness of 0.65 nm or less and having a lattice constant distortion-free surface by simply introducing a very thin lattice relaxation layer. A device fabrication substrate having a thickness of 0.65 nm or less and having no lattice constant distortion can be easily produced.

本発明の近赤外線発光デバイスは、先に記載のデバイス作製用基板のＩｎＧａＡｓ薄膜のデバイス作製面上に、薄膜を積層して、量子井戸構造を形成した構成なので、発光波長を近赤外に限定した発光デバイスとすることができる。   The near-infrared light-emitting device of the present invention has a structure in which a quantum well structure is formed by laminating a thin film on the device fabrication surface of the InGaAs thin film of the device fabrication substrate described above, so the emission wavelength is limited to the near infrared Light emitting device.

本発明の実施形態であるデバイス作製用基板、その製造方法及び近赤外線発光デバイスは、上記実施形態に限定されるものではなく、本発明の技術的思想の範囲内で、種々変更して実施することができる。本実施形態の具体例を以下の実施例で示す。しかし、本発明はこれらの実施例に限定されるものではない。   The device manufacturing substrate, the manufacturing method thereof, and the near-infrared light emitting device which are the embodiments of the present invention are not limited to the above-described embodiments, and various modifications are made within the scope of the technical idea of the present invention. be able to. Specific examples of this embodiment are shown in the following examples. However, the present invention is not limited to these examples.

（実施例１）
図４は、ＧａＡｓ（１１１）A基板をインジウムハンダでモリブデン製基板ホルダに貼り付けてから加熱する様子を説明する図である。
まず、図４に示すようにＧａＡｓの（１１１）Ａ面基板（市販）をインジウムハンダにより、モリブデン製基板ホルダに貼り付けた。
次に、結晶成長装置の超高真空チャンバー内にこれを配置した。
次に、砒素雰囲気下、裏面のヒーターによりＧａＡｓ基板を約６００℃に加熱して、自然酸化膜を蒸発させた。
次に、砒素雰囲気下、裏面のヒーターによりＧａＡｓ基板を５００℃に加熱して、ガリウムを供給して、（１１１）Ａ面上にＧａＡｓをホモエピタキシャル成長させて、ＧａＡｓバッファ層を形成した。これによりＧａＡｓ（１１１）Ａの清浄表面を得た。 Example 1
FIG. 4 is a diagram for explaining a state in which a GaAs (111) A substrate is heated after being attached to a molybdenum substrate holder with indium solder.
First, as shown in FIG. 4, a GaAs (111) A-plane substrate (commercially available) was attached to a molybdenum substrate holder by indium solder.
Next, this was placed in an ultra-high vacuum chamber of a crystal growth apparatus.
Next, in a arsenic atmosphere, the GaAs substrate was heated to about 600 ° C. by the heater on the back surface, and the natural oxide film was evaporated.
Next, the GaAs substrate was heated to 500 ° C. with a backside heater in an arsenic atmosphere, gallium was supplied, and GaAs was homoepitaxially grown on the (111) A plane to form a GaAs buffer layer. This gave a clean surface of GaAs (111) A.

次に、分子線エピタキシー（ＭＢＥ）法により、砒素雰囲気下でインジウムを照射して、厚さが０．７ｎｍのＩｎＡｓ層を形成した。
成長条件としては、基板温度４００〜５００℃、砒素分子線強度１〜１０×１０−５Ｔｏｒｒ程度、Ｉｎ成長速度はＩｎＡｓに換算して０．０６ｎｍ／ｓｅｃ程度とした。 Next, indium was irradiated in an arsenic atmosphere by molecular beam epitaxy (MBE) method to form an InAs layer having a thickness of 0.7 nm.
As growth conditions, the substrate temperature was 400 to 500 ° C., the arsenic molecular beam intensity was about 1 to 10 × 10 −5 Torr, and the In growth rate was about 0.06 nm / sec in terms of InAs.

次に、分子線エピタキシー（ＭＢＥ）法により、表面の平坦性に優れ、且つ、低欠陥密度であるＩｎ０．２３Ｇａ０．７７Ａｓエピタキシャル薄膜を１５０ｎｍの厚さで形成した。
以上により、実施例１のデバイス作製用基板「Ｉｎ０．２３Ｇａ０．７７Ａｓ／ＩｎＡｓ（０．６４ｎｍ）／ＧａＡｓ（１１１）Ａ」を作製した。
図５は、実施例１のデバイス作製用基板のＩｎ０．２３Ｇａ０．７７Ａｓ表面の５μｍ×５μｍの領域の原子間力顕微鏡（ＡＦＭ）像である。 Next, an In 0.23 Ga 0.77 As epitaxial thin film having excellent surface flatness and low defect density was formed to a thickness of 150 nm by molecular beam epitaxy (MBE).
In this manner, the device fabrication substrate “In 0.23 Ga 0.77 As / InAs (0.64 nm) / GaAs (111) A” of Example 1 was fabricated.
FIG. 5 is an atomic force microscope (AFM) image of a 5 μm × 5 μm region of the In 0.23 Ga 0.77 As surface of the device fabrication substrate of Example 1.

（実施例２）
ＩｎＡｓ層の膜厚を１ｎｍとした他は実施例１と同様にして、実施例２のデバイス作製用基板「Ｉｎ０．２３Ｇａ０．７７Ａｓ（１５０ｎｍ）／ＩｎＡｓ（１．０ｎｍ）／ＧａＡｓ（１１１）Ａ」を作製した。
図６は、実施例２のデバイス作製用基板のＩｎ０．２３Ｇａ０．７７Ａｓ表面の５μｍ×５μｍの領域の原子間力顕微鏡（ＡＦＭ）像である。
図７は、実施例２のデバイス作製用基板のＸ線回折（１１５）入射逆格子マッピングの結果である。Ｉｎ０．２３Ｇａ０．７７Ａｓに起因する単峰ピークがｘ＝−５．６４４１、ｙ＝７．０２９２に観察される。この２つの数値から面内（11-2）と成長方向（111）の格子定数の比（ｄ１１１／ｄ１１−２）が、１．４０５１６３と求まる。無歪みのＩｎ０．２３Ｇａ０．７７Ａｓではこの値は、１．４１４であることから、９９％以上の格子緩和が実現されている。 (Example 2)
The device fabrication substrate “In 0.23 Ga 0.77 As (150 nm) / InAs (1.0 nm) / GaAs (Example 2) was obtained in the same manner as in Example 1 except that the thickness of the InAs layer was changed to 1 nm. 111) A "was produced.
6 is an atomic force microscope (AFM) image of a 5 μm × 5 μm region of the In 0.23 Ga 0.77 As surface of the device fabrication substrate of Example 2. FIG.
FIG. 7 shows the result of X-ray diffraction (115) incident reciprocal mapping of the device fabrication substrate of Example 2. A single peak due to In 0.23 Ga 0.77 As is observed at x = −5.6441 and y = 7.0292. From these two numerical values, the ratio (d 111 / d 11-2 ) of the lattice constant between the in-plane (11-2) and the growth direction (111) is obtained as 1.405163. In the unstrained In 0.23 Ga 0.77 As, this value is 1.414, and hence 99% or more of lattice relaxation is realized.

次に、実施例２のデバイス作製用基板のＩｎＧａＡｓ薄膜の一面上に、薄膜を積層して、量子井戸構造を形成して、近赤外線発光デバイスを作製した。
図８は、実施例２のデバイス作製用基板を用いて作製した近赤外線発光デバイスの擬略側面図である。
図９は、実施例２のデバイス作製用基板を用いて作製した近赤外線発光デバイスの発光スペクトルである。 Next, a near-infrared light-emitting device was fabricated by stacking a thin film on one surface of an InGaAs thin film of the device fabrication substrate of Example 2 to form a quantum well structure.
FIG. 8 is a quasi-schematic side view of a near-infrared light emitting device manufactured using the device manufacturing substrate of Example 2.
FIG. 9 is an emission spectrum of a near-infrared light emitting device manufactured using the device manufacturing substrate of Example 2.

（実施例３）
ＩｎＡｓ層の膜厚を１．８ｎｍとした他は実施例１と同様にして、実施例３のデバイス作製用基板「Ｉｎ０．２３Ｇａ０．７７Ａｓ（１５０ｎｍ）／ＩｎＡｓ（１．８ｎｍ）／ＧａＡｓ（１１１）Ａ」を作製した。
図１０は、実施例３のデバイス作製用基板のＩｎ０．２３Ｇａ０．７７Ａｓ表面の５μｍ×５μｍの領域の原子間力顕微鏡（ＡＦＭ）像である。 (Example 3)
The device fabrication substrate “In 0.23 Ga 0.77 As (150 nm) / InAs (1.8 nm) / of Example 3 was used in the same manner as in Example 1 except that the thickness of the InAs layer was 1.8 nm. GaAs (111) A ”was produced.
FIG. 10 is an atomic force microscope (AFM) image of a 5 μm × 5 μm region of the In 0.23 Ga 0.77 As surface of the device fabrication substrate of Example 3.

（比較例１）
ＩｎＡｓ層を形成しなかった他は実施例１と同様にして、比較例１のデバイス作製用基板「Ｉｎ０．２３Ｇａ０．７７Ａｓ（１５０ｎｍ）／ＧａＡｓ（１１１）Ａ」を作製した。
図１１は、比較例１のデバイス作製用基板のＩｎ０．２３Ｇａ０．７７Ａｓ表面の５μｍ×５μｍの領域の原子間力顕微鏡（ＡＦＭ）像である。
図１２は、比較例１のデバイスス作製用基板のＸ線回折（１１５）入射逆格子マッピングの結果である。Ｉｎ０．２３Ｇａ０．７７Ａｓに起因するピークがｘ＝―５．７２１３、ｙ＝７．００４６にピークが観察される。また、ピークが面内の格子定数がＧａＡｓと一致する方向にも広がっている。このことから、初めに格子緩和していない層が成長した後に一部格子緩和した層が成長されている事が分かる。 (Comparative Example 1)
A device fabrication substrate “In 0.23 Ga 0.77 As (150 nm) / GaAs (111) A” of Comparative Example 1 was fabricated in the same manner as in Example 1 except that the InAs layer was not formed.
11 is an atomic force microscope (AFM) image of a 5 μm × 5 μm region of the In 0.23 Ga 0.77 As surface of the device fabrication substrate of Comparative Example 1. FIG.
12 shows the result of X-ray diffraction (115) incident reciprocal mapping of the device fabrication substrate of Comparative Example 1. FIG. Peaks attributable to In 0.23 Ga 0.77 As are observed at x = −5.7213 and y = 7.70046. The peak also extends in the direction in which the in-plane lattice constant coincides with GaAs. From this, it can be seen that a layer partially relaxed in lattice is grown after a layer not initially lattice-relaxed grows.

（比較例２）
ＩｎＡｓ層の膜厚を０．３８ｎｍとした他は実施例１と同様にして、比較例２のデバイス作製用基板「Ｉｎ０．２３Ｇａ０．７７Ａｓ／ＩｎＡｓ（０．４ｎｍ）／ＧａＡｓ（１１１）Ａ」を作製した。
図１３は、比較例２のデバイス作製用基板のＩｎ０．２３Ｇａ０．７７Ａｓ表面の５μｍ×５μｍの領域の原子間力顕微鏡（ＡＦＭ）像である。
図１４は、比較例１、２の一例を示す断面模式図である。 (Comparative Example 2)
The device fabrication substrate “In 0.23 Ga 0.77 As / InAs (0.4 nm) / GaAs (111) of Comparative Example 2 was obtained in the same manner as in Example 1 except that the thickness of the InAs layer was set to 0.38 nm. ) A ".
FIG. 13 is an atomic force microscope (AFM) image of a 5 μm × 5 μm region of the In 0.23 Ga 0.77 As surface of the device fabrication substrate of Comparative Example 2.
FIG. 14 is a schematic cross-sectional view showing an example of Comparative Examples 1 and 2.

（比較例３）
ＩｎＡｓ層の膜厚を３．５ｎｍとした他は実施例１と同様にして、比較例３のデバイス作製用基板「Ｉｎ０．２３Ｇａ０．７７Ａｓ／ＩｎＡｓ（３．５ｎｍ）／ＧａＡｓ（１１１）Ａ」を作製した。
図１５は、比較例３のデバイス作製用基板のＩｎ０．２３Ｇａ０．７７Ａｓ表面の５μｍ×５μｍの領域の原子間力顕微鏡（ＡＦＭ）像である。 (Comparative Example 3)
The device fabrication substrate “In 0.23 Ga 0.77 As / InAs (3.5 nm) / GaAs (111) of Comparative Example 3 was used in the same manner as in Example 1 except that the thickness of the InAs layer was 3.5 nm. ) A ".
FIG. 15 is an atomic force microscope (AFM) image of a 5 μm × 5 μm region of the In 0.23 Ga 0.77 As surface of the device fabrication substrate of Comparative Example 3.

（比較例４）
ＩｎＡｓ層の膜厚を２０．８ｎｍとした他は実施例１と同様にして、比較例４のデバイス作製用基板「Ｉｎ０．２３Ｇａ０．７７Ａｓ／ＩｎＡｓ（２０．８ｎｍ）／ＧａＡｓ（１１１）Ａ」を作製した。
図１６は、比較例４のデバイス作製用基板のＩｎ０．２３Ｇａ０．７７Ａｓ表面の５μｍ×５μｍの領域の原子間力顕微鏡（ＡＦＭ）像である。
図１７は、比較例３、４の一例を示す断面模式図である。 (Comparative Example 4)
The device fabrication substrate “In 0.23 Ga 0.77 As / InAs (20.8 nm) / GaAs (111) of Comparative Example 4 was used in the same manner as in Example 1 except that the thickness of the InAs layer was 20.8 nm. ) A ".
FIG. 16 is an atomic force microscope (AFM) image of a 5 μm × 5 μm region of the In 0.23 Ga 0.77 As surface of the device fabrication substrate of Comparative Example 4.
FIG. 17 is a schematic cross-sectional view showing an example of Comparative Examples 3 and 4. As shown in FIG.

（比較例５）
Ｉｎ０．２３Ｇａ０．７７Ａｓ層の膜厚を８０ｎｍとした他は比較例２と同様にして、比較例５のデバイス作製用基板「Ｉｎ０．２３Ｇａ０．７７Ａｓ（８０ｎｍ）／ＧａＡｓ（１１１）Ａ」を作製した。
図１８は、比較例５のデバイス作製用基板のＩｎ０．２３Ｇａ０．７７Ａｓ表面の５μｍ×５μｍの領域の原子間力顕微鏡（ＡＦＭ）像である。
図１９は、比較例５のデバイス作製用基板のＸ線回折（１１５）入射逆格子マッピングの結果である。Ｉｎ０．２３Ｇａ０．７７Ａｓ（８０ｎｍ）に起因するピークが観測されるが。面内の格子定数はＧａＡｓ基板と一致しており、全く格子緩和していない層が成長している事が分かる。 (Comparative Example 5)
The device fabrication substrate “In 0.23 Ga 0.77 As (80 nm) / GaAs in Comparative Example 5 was used in the same manner as in Comparative Example 2 except that the thickness of the In 0.23 Ga 0.77 As layer was 80 nm. (111) A ”was prepared.
FIG. 18 is an atomic force microscope (AFM) image of a 5 μm × 5 μm region of the In 0.23 Ga 0.77 As surface of the device fabrication substrate of Comparative Example 5.
FIG. 19 shows the result of X-ray diffraction (115) incident reciprocal lattice mapping of the device fabrication substrate of Comparative Example 5. A peak due to In 0.23 Ga 0.77 As (80 nm) is observed. The in-plane lattice constant coincides with that of the GaAs substrate, and it can be seen that a layer having no lattice relaxation has grown.

（実施例４）
ＩｎＧａＡｓ層のＩｎ組成をＩｎ０．５１Ｇａ０．４９Ａｓとした他は実施例２と同様にして、実施例４のデバイス作製用基板「Ｉｎ０．５１Ｇａ０．４９Ａｓ（１５０ｎｍ）／ＩｎＡｓ（１．０ｎｍ）／ＧａＡｓ（１１１）Ａ」を作製した。
図２０は、実施例４のデバイス作製用基板のＩｎ０．２３Ｇａ０．７７Ａｓ表面の５μｍ×５μｍの領域の原子間力顕微鏡（ＡＦＭ）像である。
図２１は、実施例４のデバイス作製用基板のＸ線回折（１１５）入射逆格子マッピングの結果である。Ｉｎ０．５１Ｇａ０．４９Ａｓに起因する単峰ピークがｘ＝―５．５６０９、ｙ＝６．８７９６に観察される。この２つの数値から成長方向と面内方向の格子定数の比（ｄ１１１／ｄ１１−２）が、１．４１４５５５と求まる。無歪みのＩｎ０．５１Ｇａ０．４９Ａｓではこの値は、１．４１４であることから、９９％以上の格子緩和が実現されている。 Example 4
Except that the In composition of the InGaAs layer was In 0.51 Ga 0.49 As in the same manner as in Example 2, a device substrate for manufacturing "In 0.51 Ga 0.49 As (150nm) Example 4 / InAs (1.0 nm) / GaAs (111) A ”was produced.
FIG. 20 is an atomic force microscope (AFM) image of a 5 μm × 5 μm region of the In 0.23 Ga 0.77 As surface of the device fabrication substrate of Example 4.
FIG. 21 shows the result of X-ray diffraction (115) incident reciprocal mapping of the device fabrication substrate of Example 4. A single peak due to In 0.51 Ga 0.49 As is observed at x = −5.5609 and y = 6.8796. From these two values, the ratio (d 111 / d 11-2 ) of the lattice constant between the growth direction and the in-plane direction is found to be 1.414555. In unstrained In 0.51 Ga 0.49 As, this value is 1.414, so that 99% or more of lattice relaxation is realized.

（実施例５）
ＩｎＧａＡｓ層のＩｎ組成をＩｎ０．７５Ｇａ０．２５Ａｓとした他は実施例２と同様にして、実施例４のデバイス作製用基板「Ｉｎ０．７５Ｇａ０．２５Ａｓ（１５０ｎｍ）／ＩｎＡｓ（１．０ｎｍ）／ＧａＡｓ（１１１）Ａ」を作製した。
図２２は、実施例５のデバイス作製用基板のＩｎ０．７５Ｇａ０．２５Ａｓ表面の５μｍ×５μｍの領域の原子間力顕微鏡（ＡＦＭ）像である。
図２３は、実施例５のデバイス作製用基板のＸ線回折（１１５）入射逆格子マッピングの結果である。Ｉｎ０．７５Ｇａ０．２５Ａｓに起因する単峰ピークがｘ＝―５．４８８、ｙ＝６．７７１４に観察される。この２つの数値から成長方向と面内方向の格子定数の比（ｄ１１１／ｄ１１−２）が、１．４１８３１８と求まる。無歪みのＩｎ０．７５Ｇａ０．２５Ａｓではこの値は、１．４１４であることから、９９％以上の格子緩和が実現されている。 (Example 5)
Except that the In composition of the InGaAs layer was In 0.75 Ga 0.25 As in the same manner as in Example 2, Example 4 of a device substrate for manufacturing "In 0.75 Ga 0.25 As (150nm) / InAs (1.0 nm) / GaAs (111) A ”was produced.
FIG. 22 is an atomic force microscope (AFM) image of a 5 μm × 5 μm region of the In 0.75 Ga 0.25 As surface of the device fabrication substrate of Example 5.
FIG. 23 shows the result of X-ray diffraction (115) incident reciprocal mapping of the device fabrication substrate of Example 5. A single peak due to In 0.75 Ga 0.25 As is observed at x = −5.488 and y = 6.7714. From these two values, the ratio (d 111 / d 11-2 ) of the lattice constant between the growth direction and the in-plane direction is obtained as 1.418318. In unstrained In 0.75 Ga 0.25 As, this value is 1.414, so that 99% or more of lattice relaxation is realized.

（実施例６）
被格子緩和層をＩｎ０．５２Ａｌ０．４８Ａｓとした他は、実施例２と同様にして、実施例６のデバイス作製用基板「Ｉｎ０．５２Ａｌ０．４８Ａｓ（１５０ｎｍ）／ＩｎＡｓ（１．０ｎｍ）／ＧａＡｓ（１１１）Ａ」を作製した。
図２４は、実施例６のデバイス作製用基板のＩｎ０．５２Ａｌ０．４８Ａｓ表面の５μｍ×５μｍの領域の原子間力顕微鏡（ＡＦＭ）像である。
図２５は、実施例６のデバイス作製用基板のＸ線回折（１１５）入射逆格子マッピングの結果である。Ｉｎ０．５２Ａｌ０．４８Ａｓに起因する単峰ピークがｘ＝―５．５４１７、ｙ＝６．８９９４に観察される。この２つの数値から成長方向と面内方向の格子定数の比（ｄ１１１／ｄ１１−２）が、１．４０５６２６と求まる。無歪みのＩｎ０．５２Ａｌ０．４８Ａｓではこの値は、１．４１４であることから、９９％以上の格子緩和が実現されている。 (Example 6)
The device fabrication substrate “In 0.52 Al 0.48 As (150 nm) / InAs of Example 6 was used in the same manner as in Example 2 except that the lattice relaxation layer was In 0.52 Al 0.48 As. (1.0 nm) / GaAs (111) A ”was produced.
FIG. 24 is an atomic force microscope (AFM) image of a 5 μm × 5 μm region on the In 0.52 Al 0.48 As surface of the device fabrication substrate of Example 6.
FIG. 25 shows the result of X-ray diffraction (115) incident reciprocal mapping of the device fabrication substrate of Example 6. A single peak due to In 0.52 Al 0.48 As is observed at x = −5.5417, y = 6.8994. From these two values, the ratio (d 111 / d 11-2 ) of the lattice constant between the growth direction and the in-plane direction is obtained as 1.405626. In unstrained In 0.52 Al 0.48 As, this value is 1.414, so that 99% or more of lattice relaxation is realized.

次に、実施例６のデバイス作製用基板のＩｎＡｌＡｓ薄膜の一面上に、薄膜を積層して、量子井戸構造を形成して、近赤外線発光デバイスを作製した。
図２６は、実施例６のデバイス作製用基板を用いて作製した近赤外線発光デバイスの擬略側面図である。
図２７は、実施例６のデバイス作製用基板を用いて作製した近赤外線発光デバイスの発光スペクトルである。 Next, a thin film was laminated on one surface of the InAlAs thin film of the device fabrication substrate of Example 6 to form a quantum well structure, and a near infrared light emitting device was fabricated.
FIG. 26 is a quasi-schematic side view of a near-infrared light-emitting device manufactured using the device manufacturing substrate of Example 6.
FIG. 27 is an emission spectrum of a near-infrared light emitting device manufactured using the device manufacturing substrate of Example 6.

（実施例７）
被格子緩和層であるＩｎ０．２３Ｇａ０．７７Ａｓの厚さ以外は実施例２と同様にして、実施例７のデバイス作製用基板「Ｉｎ０．２３Ｇａ０．７７Ａｓ（５０ｎｍまたは１００ｎｍまたは１５０ｎｍ）／ＩｎＡｓ（１．０ｎｍ）／ＧａＡｓ（１１１）Ａ」を作製した。図２８は、実施例７のデバイス作製用基板の表面のＲＨＥＥＤパターンを示す図である。５０ｎｍ、１００ｎｍ、１５０ｎｍいずれの場合の於いても表面が平坦であることを表すストリークパターンが観察されている。また、図７に示すようにＩｎ０．２３Ｇａ０．７７Ａｓ（１５０ｎｍ）／ＩｎＡｓ（１．０ｎｍ）／ＧａＡｓ（１１１）ＡにおいてすべてのＩｎ０．２３Ｇａ０．７７Ａｓ（１５０ｎｍ）は格子緩和していることから、Ｉｎ０．２３Ｇａ０．７７Ａｓ（５０ｎｍまたは１００ｎｍ）／ＩｎＡｓ（１．０ｎｍ）／ＧａＡｓ（１１１）Ａも格子緩和している事がわかる。 (Example 7)
The device fabrication substrate “In 0.23 Ga 0.77 As (50 nm or 100 nm) of Example 7 was obtained in the same manner as in Example 2 except for the thickness of In 0.23 Ga 0.77 As, which is a lattice relaxation layer. Or 150 nm) / InAs (1.0 nm) / GaAs (111) A ”. FIG. 28 is a diagram showing an RHEED pattern of the surface of the device fabrication substrate of Example 7. In any case of 50 nm, 100 nm, and 150 nm, a streak pattern indicating that the surface is flat is observed. Further, as shown in FIG. 7, in In 0.23 Ga 0.77 As (150 nm) / InAs (1.0 nm) / GaAs (111) A, all In 0.23 Ga 0.77 As (150 nm) are lattices. From the relaxation, it can be seen that In 0.23 Ga 0.77 As (50 nm or 100 nm) / InAs (1.0 nm) / GaAs (111) A also has a lattice relaxation.

（実施例８）
被格子緩和層であるＩｎ０．５２Ａｌ０．４８Ａｓの厚さ以外は、実施例６と同様にして、実施例８のデバイス作製用基板「Ｉｎ０．５２Ａｌ０．４８Ａｓ（５０ｎｍまたは１００ｎｍまたは１００ｎｍ）／ＩｎＡｓ（１．０ｎｍ）／ＧａＡｓ（１１１）Ａ」を作製した。図２９は、実施例８のデバイス作製用基板の表面のＲＨＥＥＤパターンを示す図である。５０ｎｍ、１００ｎｍ、１５０ｎｍいずれの場合の於いても、表面が平坦であることを表すストリークパターンが観察されている。また、図２５に示すようにＩｎ０．５２Ａｌ０．４８Ａｓ（１５０ｎｍ）／ＩｎＡｓ（１．０ｎｍ）／ＧａＡｓ（１１１）ＡにおいてすべてのＩｎ０．５２Ａｌ０．４８Ａｓ（１５０ｎｍ）は格子緩和していることから、Ｉｎ０．５２Ａｌ０．４８Ａｓ（５０ｎｍまたは１００ｎｍ）／ＩｎＡｓ（１．０ｎｍ）／ＧａＡｓ（１１１）Ａも格子緩和している事がわかる。
表１に、各実験条件及び結果をまとめた。 (Example 8)
Except for the thickness of In 0.52 Al 0.48 As, which is a lattice relaxation layer, the device fabrication substrate “In 0.52 Al 0.48 As (50 nm or 50 nm or 50 nm or 100 nm or 100 nm) / InAs (1.0 nm) / GaAs (111) A ”. FIG. 29 is a diagram showing an RHEED pattern of the surface of the device fabrication substrate of Example 8. In any case of 50 nm, 100 nm, and 150 nm, a streak pattern indicating that the surface is flat is observed. Further, as shown in FIG. 25, in In 0.52 Al 0.48 As (150 nm) / InAs (1.0 nm) / GaAs (111) A, all In 0.52 Al 0.48 As (150 nm) are lattices. From the relaxation, it can be seen that In 0.52 Al 0.48 As (50 nm or 100 nm) / InAs (1.0 nm) / GaAs (111) A also has a lattice relaxation.
Table 1 summarizes the experimental conditions and results.


本発明は、デバイス作製用基板、その製造方法及び光ファイバー通信に適合した波長帯の発光を有する近赤外線発光デバイスに関するものであり、情報通信産業、半導体産業等において利用可能性がある。   The present invention relates to a device manufacturing substrate, a manufacturing method thereof, and a near-infrared light emitting device having light emission in a wavelength band suitable for optical fiber communication, and can be used in the information communication industry, the semiconductor industry, and the like.

１１…ＧａＡｓ基板、１１ａ…（１１１）Ａ面、１２…ＧａＡｓバッファ層、１２ａ…（１１１）Ａ清浄化面、１３…格子緩和層（ＩｎＡｓ薄膜）、１４…被格子緩和層（ＩｎＭ（ＩＩＩ）Ａｓ膜）、１４ａ…デバイス作製面、３１…デバイス作製用基板、４１、４２、４３、４４、４５、４６、４７、４８、４９、５０…薄膜、５１…量子井戸構造、６１…近赤外線発光デバイス。
DESCRIPTION OF SYMBOLS 11 ... GaAs substrate, 11a ... (111) A surface, 12 ... GaAs buffer layer, 12a ... (111) A cleaning surface, 13 ... Lattice relaxation layer (InAs thin film), 14 ... Lattice relaxation layer (InM (III) As film), 14a ... device fabrication surface, 31 ... device fabrication substrate, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50 ... thin film, 51 ... quantum well structure, 61 ... near infrared emission device.

Claims (6)

ＧａＡｓ基板又はＧａＡｓ基板に形成したＧａＡｓバッファ層の（１１１）Ａ面に格子緩和層と被格子緩和層をこの順序で積層したデバイス作製用基板であって、
前記格子緩和層が膜厚０．７ｎｍ以上１．８ｎｍ以下のＩｎＡｓ薄膜であり、
前記被格子緩和層がＩｎＭ（ＩＩＩ）Ａｓ薄膜（ここで、Ｍ（ＩＩＩ）がＩＩＩ族の金属原子である。）であることを特徴とするデバイス作製用基板。 A device fabrication substrate in which a lattice relaxation layer and a lattice relaxation layer are laminated in this order on the (111) A surface of a GaAs substrate or a GaAs buffer layer formed on a GaAs substrate,
The lattice relaxation layer is an InAs thin film having a thickness of 0.7 nm to 1.8 nm,
The device fabrication substrate, wherein the lattice relaxation layer is an InM (III) As thin film (wherein M (III) is a group III metal atom). 前記Ｍ（ＩＩＩ）がＧａ又はＡｌであることを特徴とするデバイス作製用基板。 The device fabrication substrate, wherein M (III) is Ga or Al. 前記Ｍ（ＩＩＩ）がＧａであり、前記被格子緩和層がＩｎｘＧａ１−ｘＡｓ膜（０．２３≦ｘ≦０．７５）であることを特徴とするデバイス作製用基板。 The device fabrication substrate, wherein M (III) is Ga, and the lattice relaxation layer is an In x Ga 1-x As film (0.23 ≦ x ≦ 0.75). 前記ＩｎｘＧａ１−ｘＡｓ膜（０．２３≦ｘ≦０．７５）の膜厚が５０ｎｍ以上１５０ｎｍ以下であることを特徴とするデバイス作製用基板。 A device fabrication substrate, wherein the In x Ga 1-x As film (0.23 ≦ x ≦ 0.75) has a thickness of 50 nm to 150 nm. ＧａＡｓ基板又はＧａＡｓ基板に形成したＧａＡｓバッファ層の（１１１）Ａ面上に、膜厚０．７ｎｍ以上１．８ｎｍ以下のＩｎＡｓ薄膜からなる格子緩和層を形成する工程と、
前記格子緩和層上にＩｎＭ（ＩＩＩ）Ａｓ薄膜（ここで、Ｍ（ＩＩＩ）がＩＩＩ族の金属原子である。）からなる被格子緩和層を形成する工程と、を有することを特徴とするデバイス作製用基板の製造方法。 Forming a lattice relaxation layer made of an InAs thin film having a thickness of 0.7 nm or more and 1.8 nm or less on a (111) A surface of a GaAs substrate or a GaAs buffer layer formed on the GaAs substrate;
Forming a lattice relaxation layer made of an InM (III) As thin film (wherein M (III) is a group III metal atom) on the lattice relaxation layer. A method for manufacturing a manufacturing substrate. 請求項１〜４のいずれか１項に記載のデバイス作製用基板のＩｎＧａＡｓ薄膜のデバイス作製面上に、薄膜を積層して、量子井戸構造を形成したことを特徴とする近赤外線発光デバイス。

A near-infrared light-emitting device, wherein a quantum well structure is formed by laminating a thin film on the device fabrication surface of an InGaAs thin film of the device fabrication substrate according to claim 1.

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Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0274600A (en) * 1988-08-03 1990-03-14 Internatl Business Mach Corp <Ibm> Method for forming single crystal hetero- structure and strain free semiconductor layer
JPH0445519A (en) * 1990-06-13 1992-02-14 Nec Corp Growing method for semiconductor crystal
JPH07326582A (en) * 1994-05-30 1995-12-12 Fujitsu Ltd Manufacture of compound semiconductor crystal device
JPH0845844A (en) * 1994-07-29 1996-02-16 Nippon Telegr & Teleph Corp <Ntt> Production of compound semiconductor film
JPH10107045A (en) * 1996-09-26 1998-04-24 Nec Corp Ii-vi compound semiconductor and its manufacturing method
US5877519A (en) * 1997-03-26 1999-03-02 Picolight Incoporated Extended wavelength opto-electronic devices
JP2006278850A (en) * 2005-03-30 2006-10-12 Advanced Telecommunication Research Institute International Semiconductor light-emitting element, manufacturing method thereof, and semiconductor laser gyro using the same
JP2008108856A (en) * 2006-10-25 2008-05-08 Sharp Corp Compound semiconductor element, and its manufacturing method

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0274600A (en) * 1988-08-03 1990-03-14 Internatl Business Mach Corp <Ibm> Method for forming single crystal hetero- structure and strain free semiconductor layer
JPH0445519A (en) * 1990-06-13 1992-02-14 Nec Corp Growing method for semiconductor crystal
JPH07326582A (en) * 1994-05-30 1995-12-12 Fujitsu Ltd Manufacture of compound semiconductor crystal device
JPH0845844A (en) * 1994-07-29 1996-02-16 Nippon Telegr & Teleph Corp <Ntt> Production of compound semiconductor film
JPH10107045A (en) * 1996-09-26 1998-04-24 Nec Corp Ii-vi compound semiconductor and its manufacturing method
US6072202A (en) * 1996-09-26 2000-06-06 Nec Corporation II-VI compound semiconductor device with III-V buffer layer
US5877519A (en) * 1997-03-26 1999-03-02 Picolight Incoporated Extended wavelength opto-electronic devices
JP2006278850A (en) * 2005-03-30 2006-10-12 Advanced Telecommunication Research Institute International Semiconductor light-emitting element, manufacturing method thereof, and semiconductor laser gyro using the same
JP2008108856A (en) * 2006-10-25 2008-05-08 Sharp Corp Compound semiconductor element, and its manufacturing method

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Ｈ． ＭＵＮＥＫＡＴＡ: "Lattice Relaxation Of InAs Heteroepitaxy on GaAs", JOURNAL OF CRYSTAL GROWTH, vol. 81, JPN6017037015, 1987, pages 237-242 *

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