JP2008103479A - Semiconductor device, and manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of narrowly forming a hetero-semiconductor region and capable of reducing a leakage current from the hetero-semiconductor region, and to provide a manufacturing method for the semiconductor device. <P>SOLUTION: The semiconductor device has N+ type polycrystalline silicon 4 formed on the side face of an insulator region 3 formed in the specified region of the surface of an N- type silicon-carbide epitaxial layer 2 in a side wall shape from polycrystalline silicon having a band-gap width different from an N+ type silicon-carbide base body 1 and the N- type silicon-carbide epitaxial layer 2. The semiconductor device further has a gate insulating film 6 formed on the surface of the N- type silicon-carbide epitaxial layer 2 and the side face of N+ type polycrystalline silicon 4 and a gate electrode 7 formed while being brought into contact with the gate insulating film 6. The semiconductor device further has a source electrode 9 connected to N+ type polycrystalline silicon 4 and a drain electrode 10 connected to the N+ type silicon-carbide base body 1. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device having a hetero semiconductor region heterojunction with a semiconductor substrate and a method for manufacturing the semiconductor device.

  As a conventional technique, an N− type polycrystalline silicon region and an N + type polycrystalline silicon region are in contact with one main surface of a semiconductor substrate in which an N− type silicon carbide epitaxial region is formed on an N + type silicon carbide substrate. There is a semiconductor device (see Patent Document 1). In the semiconductor device, the N− type silicon carbide epitaxial region, the N− type polycrystalline silicon region, and the N + type polycrystalline silicon region form a heterojunction. A gate electrode is formed via a gate insulating film adjacent to the heterojunction between the N− type silicon carbide epitaxial region and the N + type polycrystalline silicon region. The N− type polycrystalline silicon region is connected to the source electrode, and a drain electrode is formed on the back surface of the N + type silicon carbide substrate.

The semiconductor device having the above structure functions as a switch by controlling the potential of the gate electrode in a state where the source electrode is grounded and a predetermined positive potential is applied to the drain electrode. That is, in the state where the gate electrode is grounded, a reverse bias is applied to the N− type polycrystalline silicon region and the heterojunction of the N + type polycrystalline silicon region and the N− type silicon carbide epitaxial region, and the drain electrode and the source electrode During this period, no current flows. However, when a predetermined positive voltage is applied to the gate electrode, a gate electric field acts on the heterojunction interface between the N + type polycrystalline silicon region and the N− type silicon carbide epitaxial region. As a result, the thickness of the energy barrier generated at the heterojunction interface between the N + type polycrystalline silicon region and the N− type silicon carbide epitaxial region is reduced, so that a current flows between the drain electrode and the source electrode. In the semiconductor device described above, since the heterojunction is used as a current cutoff / conduction control channel, the channel length functions at the thickness of the heterobarrier, so that low resistance conduction characteristics can be obtained.
JP 2003-318398 A

  However, in the above semiconductor device, the N− type polycrystalline silicon region is heterojunctioned to one main surface of the semiconductor substrate, and a positive voltage is applied to the semiconductor substrate side. There are cases where electrons slightly tunnel through the energy barrier at the heterojunction interface and move to the semiconductor substrate side. In some cases, the electrons in the N-type polycrystalline silicon region excited in energy move to the semiconductor substrate side over the energy barrier. As described above, electrons in the N − -type polycrystalline silicon region move to the semiconductor substrate, which causes a problem of leakage current. Furthermore, in order to reduce the leakage current from the N + type polycrystalline silicon region serving as the drive unit, it is important to form the N + type polycrystalline silicon region as narrow as possible. However, when the N− type polycrystalline silicon region is adjacent to the N + type polycrystalline silicon region serving as a driving part as in the prior art, it is difficult to narrow the N + type polycrystalline silicon region by impurity diffusion. . As a result, there is a problem that the leakage current cannot be reduced.

  The present invention has been made in view of these problems, and an object of the present invention is to provide a semiconductor device capable of forming a hetero semiconductor region narrowly and reducing a leakage current from the hetero semiconductor region, and a method for manufacturing the semiconductor device. And

  In order to achieve the above object, the semiconductor device according to the present invention is formed in a sidewall shape on the side surface of an insulator region formed in a predetermined region on the surface of the semiconductor substrate from a semiconductor material having a band cap width different from that of the semiconductor substrate. A gate insulating film formed on a surface of the semiconductor substrate and on a side surface of the hetero semiconductor region, a gate electrode formed in contact with the gate insulating film, and the hetero semiconductor region. And a drain electrode connected to the semiconductor substrate.

  According to the present invention, by forming the insulator region instead of the N-type polycrystalline silicon region, the leakage current flowing from the semiconductor substrate to the insulator region can be reduced to a negligible level. In addition, since there is almost no interdiffusion of impurities between the hetero semiconductor region and the insulator region, the hetero semiconductor region can be formed narrowly. Furthermore, by forming the hetero semiconductor region in a sidewall shape on the side surface of the insulator region, it can be formed in a self-aligned manner with good controllability, and leakage current from the hetero semiconductor region can be reduced.

  Hereinafter, semiconductor devices according to first to third embodiments of the present invention will be described with reference to FIGS.

(First embodiment)
The semiconductor device according to the first embodiment will be described with reference to FIG. FIG. 1 is a cross-sectional view showing a configuration of a semiconductor device according to the first embodiment of the present invention. The semiconductor device according to the first embodiment shown in FIG. 1 has a structure in which two unit cells of a field effect transistor are arranged to face each other. In practice, a plurality of unit cells of the field effect transistor are arranged and connected in parallel to form one transistor.

  The semiconductor device shown in FIG. 1 includes an N + type silicon carbide substrate 1 and an N− type silicon carbide epitaxial layer 2 which are semiconductor substrates. N + type silicon carbide substrate 1 is formed of N type high concentration (N +) silicon carbide. On the surface of N + type silicon carbide substrate 1, an N− type silicon carbide epitaxial layer 2 made of N type low concentration (N−) silicon carbide is formed. Further, silicon carbide has a plurality of polytypes (crystal polymorphs). In the first embodiment, representative 4H is used. In FIG. 1, the concept of the thicknesses of the N + type silicon carbide substrate 1 and the N− type silicon carbide epitaxial layer 2 is omitted. Actually, the N + type silicon carbide substrate 1 has a thickness of about several hundred μm, and the N− type silicon carbide epitaxial layer 2 has a thickness of about several μm to several tens of μm.

  The semiconductor device shown in FIG. 1 further includes an insulator region 3 formed in a predetermined region on the surface of the N-type silicon carbide epitaxial layer 2, that is, the surface of the semiconductor substrate, corresponding to each cell of the field effect transistor. N + type polycrystalline silicon 4 which is a hetero semiconductor region which forms a heterojunction with N− type silicon carbide epitaxial layer 2 and is formed in a sidewall shape on the side surface of insulator region 3, and N− type silicon carbide epitaxial Gate insulating film 6 formed on the surface of layer 2 and the side surface of N + type polycrystalline silicon 4, gate electrode 7 formed in contact with gate insulating film 6, and source connected directly to N + type polycrystalline silicon 4 An electrode 9, a drain electrode 10 ohmically connected with low resistance on the back surface of the N + type silicon carbide substrate 1, and an interlayer insulating film 8 that insulates the source electrode 9 and the gate electrode 7. It is equipped with a. Here, N + type polycrystalline silicon 4 is formed from polycrystalline silicon which is a semiconductor material having a band gap width and electron affinity different from that of silicon carbide forming N + type silicon carbide substrate 1 and N− type silicon carbide epitaxial layer 2. Has been. Further, the heterojunction interface between the N− type silicon carbide epitaxial layer 2 and the N + type polycrystalline silicon 4 is formed very narrow as shown in FIG.

  Next, basic operation of the semiconductor device illustrated in FIG. 1 will be described. In the semiconductor device of FIG. 1, a predetermined positive potential is applied to the drain electrode 10, the source electrode 9 is grounded, and then the potential of the gate electrode 7 is controlled to function as a switch. More specifically, the N + type polycrystalline silicon 4 and the N− type silicon carbide epitaxial layer 2 have different band gap widths and electron affinity, so that the N + type polycrystalline silicon 4 and the N− type silicon carbide epitaxial layer 2 are different from each other. An energy barrier ΔEc is generated at the heterojunction interface. Even when a predetermined positive potential is applied to the drain electrode 10 and the source electrode 9 is grounded in a state where the gate electrode 7 is grounded, the positive potential applied between the drain electrode 10 and the source electrode 9 is Since a reverse bias is applied to the heterojunction between N + type polycrystalline silicon 4 and N− type silicon carbide epitaxial layer 2, no current flows between drain electrode 10 and source electrode 9. On the other hand, when a predetermined positive potential is applied to the drain electrode 10 and a predetermined positive voltage is applied to the gate electrode 7 with the source electrode 9 grounded, the N + type polycrystalline silicon 4 and the N− type silicon carbide epitaxial are applied. A gate electric field acts on the heterojunction interface with the layer 2, and the thickness of the energy barrier ΔEc is reduced. When the thickness of the energy barrier ΔEc becomes sufficiently thin, electrons of the N + type polycrystalline silicon 4 pass through the energy barrier ΔEc due to a tunnel phenomenon. As a result, a current flows between the drain electrode 10 and the source electrode 9.

  As described above, in the semiconductor device according to the first embodiment, the insulator region 3 is formed in a predetermined region on the surface of the N− type silicon carbide epitaxial layer 2 instead of the N− type polycrystalline silicon region. Compared to the conventional example, the leakage current flowing from N-type silicon carbide epitaxial layer 2 to insulator region 3 can be reduced to a negligible level. Further, since there is almost no interdiffusion of impurities between the N + type polycrystalline silicon 4 and the insulator region 3, the N + type polycrystalline silicon 4 can be formed extremely narrow. Further, by forming the N + type polycrystalline silicon 4 in the shape of a sidewall on the side surface of the insulator region 3, it becomes possible to form a self-aligned and good controllability, and the leakage current from the N + type polycrystalline silicon 4 is reduced. Can be reduced. The semiconductor device manufacturing method according to the first embodiment is substantially the same as the second embodiment described later. The semiconductor device manufacturing method of the first embodiment is different from the second embodiment only in that there is no step of forming the conductor region 5 on the insulator region 3.

(Second Embodiment)
Next, a semiconductor device according to the second embodiment will be described with reference to FIGS. 2 to 6 focusing on differences from the semiconductor device according to the first embodiment. Also, in the semiconductor device according to the second embodiment, the same reference numerals are given to the same structures as those of the semiconductor device according to the first embodiment, and description thereof is omitted. The structure of the semiconductor device according to the second embodiment is basically the same as the structure of the semiconductor device according to the first embodiment. The semiconductor device of the second embodiment is different from the first embodiment only in that the conductor region 5 is formed in order to connect the N + type polycrystalline silicon 4 and the source electrode 9. . Therefore, the same effect as that of the semiconductor device of the first embodiment can be obtained.

  FIG. 2 is a cross-sectional view showing a configuration of a semiconductor device according to the second embodiment of the present invention. As in the first embodiment, the semiconductor device shown in FIG. 2 includes an N + type silicon carbide substrate 1, an N− type silicon carbide epitaxial layer 2 formed on the surface of the N + type silicon carbide substrate 1, and an N− type. Insulator region 3 formed in a predetermined region on the surface of silicon carbide epitaxial layer 2 and heterojunction with N-type silicon carbide epitaxial layer 2 were formed in a sidewall shape on the side surface of insulator region 3 N + type polycrystalline silicon 4, gate insulating film 6 formed on the surface of N− type silicon carbide epitaxial layer 2 and the side surface of N + type polycrystalline silicon 4, and gate electrode 7 formed in contact with gate insulating film 6 A source electrode 9 formed on the insulator region 3, a drain electrode 10 ohmically connected on the back surface of the N + type silicon carbide substrate 1, and an interlayer insulating film 8 that insulates the source electrode 9 and the gate electrode 7. Eteiru. Furthermore, in order to connect the N + type polycrystalline silicon 4 and the source electrode 9, a conductor region 5 formed between the insulator region 3 and the source electrode 9 is provided. Here, the conductive region 5 can be made of polycrystalline silicon doped at a high concentration, metal, or the like.

Next, a method for manufacturing a semiconductor device according to the second embodiment will be described with reference to FIGS. 3 to 6 are diagrams for explaining a manufacturing process of the semiconductor device shown in FIG. First, in the process of FIG. 3A, an N− type silicon carbide epitaxial layer 2 having an impurity concentration of 10 ¹⁴ to 10 ¹⁸ cm ⁻³ and a thickness of 1 to 100 μm, for example, is formed on the N + type silicon carbide substrate 1. Has been. On the N− type silicon carbide epitaxial layer 2, an insulator is formed to a thickness of, for example, 0.1 to 10 μm to form the insulator region 3. As the insulator, SiO ₂ , SiN, or the like can be used. As a film formation method, thermal CVD, plasma CVD, thermal oxidation, or the like can be used. Next, the conductor region 5 is formed on the insulator region 3. Note that polycrystalline silicon doped with impurities at a high concentration, metal, or the like can be used as the conductor. Next, in the step (b), a resist 11 is applied on the conductor region 5, the resist 11 is patterned using photolithography, and the conductor region 5 and the insulator region are used using the resist 11 as a mask. 3 is etched to expose the N-type silicon carbide epitaxial layer 2, and then the resist 11 is removed.

  Next, in the step of FIG. 4C, polycrystalline silicon isotropically formed on the N − -type silicon carbide epitaxial layer 2, the conductor region 5, and on the side surfaces of the insulator region 3 and the conductor region 5. To do. As a film forming method, low pressure CVD or the like is used. As a method for introducing impurities, a method of introducing impurities during film formation, a method of thermally diffusing impurities after forming polycrystalline silicon, a method of ion implantation of impurities, or the like can be used. Next, in the step (d), the N + type polycrystalline silicon 4 is etched using anisotropic etching. By using anisotropic etching, N + type polycrystalline silicon 4 can be formed on the side surfaces of insulator region 3 and conductor region 5 in a self-aligning manner. Next, in the step of FIG. 5E, gate insulating film 6 is formed on N − type silicon carbide epitaxial layer 2, N + type polycrystalline silicon 4 and conductor region 5. Further, a gate electrode 7 is formed on the gate insulating film 6. Next, in the step (f), a resist 11 is applied on the gate electrode 7, the resist 11 is patterned by photolithography, and the gate electrode 7 is etched using the resist 11 as a mask. Thereafter, the resist 11 is removed. Next, in the process of FIG. 6G, an interlayer insulating film 8 is formed and a contact hole is opened. Thereafter, the source electrode 9 and the drain electrode 10 are formed as shown in FIG.

  As described above, in the semiconductor device according to the second embodiment, since the N + type polycrystalline silicon 4 and the source electrode 9 are connected via the conductor region 5, the contact hole for the source electrode 9 is opened. In addition, a margin for alignment with the gate electrode 7 can be increased, manufacturing is facilitated, and a highly reliable semiconductor device can be obtained.

(Third embodiment)
Next, a semiconductor device according to the third embodiment will be described with reference to FIG. 7 focusing on differences from the semiconductor device according to the second embodiment. Further, in the semiconductor device according to the third embodiment, the same reference numerals are given to the same structures as those of the semiconductor device according to the second embodiment, and the description thereof is omitted. Note that the structure of the semiconductor device according to the third embodiment is basically the same as the structure of the semiconductor device of the second embodiment. The semiconductor device of the third embodiment is different from the second embodiment in that it is in contact with the surface of the N− type silicon carbide epitaxial layer 2 and the N− type silicon carbide epitaxial layer 2 and the N + type polycrystalline silicon 4. It is only that the electric field relaxation region 12 is formed in the vicinity of the heterojunction interface. Therefore, the same effect as the semiconductor device of the second embodiment can be obtained.

  FIG. 7 is a cross-sectional view showing a configuration of a semiconductor device according to the third embodiment of the present invention. Similar to the second embodiment, the semiconductor device shown in FIG. 3 includes an N + type silicon carbide substrate 1, an N− type silicon carbide epitaxial layer 2 formed on the surface of the N + type silicon carbide substrate 1, and an N− type. Insulator region 3 formed in a predetermined region on silicon carbide epitaxial layer 2, N− type silicon carbide epitaxial layer 2 and a heterojunction are formed, and N + formed in a sidewall shape on the side surface of insulator region 3 Type polycrystalline silicon 4, gate insulating film 6 formed on N− type silicon carbide epitaxial layer 2 and on the side surface of N + type polycrystalline silicon 4, gate electrode 7 formed in contact with gate insulating film 6, In order to connect N + type polycrystalline silicon 4 and source electrode 9, conductor region 5 formed on insulator region 3, source electrode 9 formed on conductor region 5, and N + type silicon carbide On the back side of the base 1 Mick connected the drain electrode 10, and an interlayer insulating film 8 insulates the source electrode 9 and the gate electrode 7. Further, an electric field relaxation region 12 is formed in contact with the surface of N− type silicon carbide epitaxial layer 2 and in the vicinity of the heterojunction interface between N− type silicon carbide epitaxial layer 2 and N + type polycrystalline silicon 4. Specifically, electric field relaxation region 12 is formed between insulator region 3 and N − type silicon carbide epitaxial layer 2 and between gate insulating film 6 and N − type silicon carbide epitaxial layer 2. Here, P-type silicon carbide, a high resistance layer, or the like is used as the electric field relaxation region 12.

  As described above, in the semiconductor device according to the third embodiment, an electric field is generated between the insulator region 3 and the N− type silicon carbide epitaxial layer 2 and between the gate insulating film 6 and the N− type silicon carbide epitaxial layer 2. Since the relaxation region 12 is formed, a high electric field due to a positive potential applied to the drain electrode 10 can be relaxed even when the gate electrode 7 is grounded. In other words, even when the gate electrode 7 is grounded, the electric field applied to the heterojunction interface is relaxed, so that the leakage current can be further reduced. The semiconductor device manufacturing method according to the third embodiment is substantially the same as that of the second embodiment. The manufacturing method of the semiconductor device of the third embodiment is different from that of the second embodiment in that it is in contact with the surface of the N− type silicon carbide epitaxial layer 2 and the N− type silicon carbide epitaxial layer 2 and the N + type polycrystal. Only the step of forming the electric field relaxation region 12 in the vicinity of the heterojunction interface with the silicon 4 is included.

  The embodiment described above is an example of the implementation of the present invention, and the scope of the present invention is not limited thereto, and other various embodiments are within the scope described in the claims. It is applicable to. For example, in the first to third embodiments, silicon carbide is used as the material of the semiconductor substrate (N + type silicon carbide substrate 1 and N− type silicon carbide epitaxial layer 2). However, the present invention is not particularly limited to this. Gallium nitride or diamond can also be used.

  In the first to third embodiments, the N + type is used as the conductivity type of the hetero semiconductor region. However, the present invention is not limited to this, and an N− type, a non-doped type, a P− type, or the like is used. You can also. When the non-doped type or the P− type is used, an inversion layer is generated in the vicinity of the interface between the hetero semiconductor and the gate insulating film 6 when a gate voltage is applied, and a current flows between the drain electrode 10 and the source electrode 9. Similarly, an N− type can also be used, but the N + type can reduce the diffusion potential VD and allow a current to flow with a lower gate voltage.

  In the first to third embodiments, the N + type polycrystalline silicon 4 is used as the hetero semiconductor. However, the present invention is not limited to this, and silicon germanium, germanium, gallium arsenide, or the like can also be used. . Furthermore, although N + type polycrystalline silicon 4 is used, it may be single crystal or amorphous.

  In addition, although not adopted in the first to third embodiments, a high withstand voltage is reduced at the outermost peripheral portion of a chip in which a plurality of unit cells are connected in parallel to reduce electric field concentration in the periphery when the field effect transistor is off. A termination structure such as a guard ring for realizing the above may be employed. A general termination structure used in the power device field is applicable.

  In the first to third embodiments, the drain electrode 10 is formed on the back surface of the N + type silicon carbide substrate 1, the source electrode 9 is disposed on the surface facing the drain electrode 10, and current flows vertically in the semiconductor device. However, the present invention is not particularly limited to this, and a structure in which the drain electrode 10 is arranged on the same surface as the source electrode 9 and current flows laterally may be employed.

Sectional drawing which shows the structure of the semiconductor device which concerns on the 1st Embodiment of this invention. Sectional drawing which shows the structure of the semiconductor device which concerns on the 2nd Embodiment of this invention. The figure explaining the manufacturing process of the semiconductor device shown in FIG. The figure explaining the manufacturing process following FIG. The figure explaining the manufacturing process following FIG. The figure explaining the manufacturing process following FIG. Sectional drawing which shows the structure of the semiconductor device which concerns on the 3rd Embodiment of this invention.

Explanation of symbols

1 N + type silicon carbide substrate, 2 N− type silicon carbide epitaxial layer,
3 Insulator region, 4 N + type polycrystalline silicon, 5 Conductor region,
6 gate insulating film, 7 gate electrode, 8 interlayer insulating film, 9 source electrode,
10 drain electrode, 11 resist, 12 electric field relaxation region

Claims (7)

A semiconductor substrate, and an insulator region formed in a predetermined region on the surface of the semiconductor substrate;
A hetero semiconductor region formed of a semiconductor material having a band cap width different from that of the semiconductor substrate, forming a heterojunction with the semiconductor substrate, and formed in a sidewall shape on a side surface of the insulator region;
A gate insulating film formed on a surface of the semiconductor substrate and a side surface of the hetero semiconductor region;
A gate electrode formed in contact with the gate insulating film;
A source electrode connected to the hetero semiconductor region;
A semiconductor device comprising a drain electrode connected to the semiconductor substrate.   The semiconductor device according to claim 1, wherein the hetero semiconductor region and the source electrode are connected via a conductor region formed on the insulator region.   3. The semiconductor device according to claim 1, further comprising an electric field relaxation region in contact with the surface of the semiconductor substrate and in the vicinity of the heterojunction interface.   The semiconductor device according to claim 1, wherein the semiconductor substrate is made of any one of silicon carbide, gallium nitride, and diamond.   5. The semiconductor device according to claim 1, wherein the hetero semiconductor region is any one of silicon, silicon germanium, germanium, and gallium arsenide. The method of manufacturing a semiconductor device according to claim 1, wherein the insulator region is formed on a surface of the semiconductor substrate.
Patterning the insulator region using a mask layer;
Forming the hetero semiconductor isotropically on the insulator region, the insulator region side surface, and the semiconductor substrate;
A method of manufacturing a semiconductor device, comprising: etching the hetero semiconductor by anisotropic etching to form the hetero semiconductor region in a self-aligned manner on a side surface of the insulator region. The method for manufacturing a semiconductor device according to claim 2, wherein the insulator region is formed on a surface of the semiconductor substrate.
Forming the conductor region on the insulator region;
Patterning the conductor region and the insulator region using a mask layer;
Forming the hetero semiconductor isotropically on the conductor region, the conductor region side surface, the insulator region side surface, and the semiconductor substrate;
Etching the hetero semiconductor by anisotropic etching, and forming the hetero semiconductor region in a self-aligned manner on the conductor region side surface and the insulator region side surface. .

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