JP2013157577A - Silicon carbide semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a silicon carbide semiconductor device having low on-resistance and to provide a method of manufacturing the same.SOLUTION: A first layer 10 of a silicon carbide substrate SC has a first conductivity type and forms a second surface P2. A second layer 21 is provided on the first layer 10 and has a second conductivity type. A third layer 22 is provided on the second layer 21, has the first conductivity type, and forms a first surface P1. A trench TR provided on the first surface P1 has a side wall surface SL. The trench TR penetrates through the third layer 22 and the second layer 21, and reaches the first layer 10. A channel layer 31 is provided on the side wall surface SL and has the first conductivity type. A gate layer 32 sandwiches the channel layer 31 with the side wall surface SL and has the second conductivity type.

Description

  The present invention relates to a silicon carbide semiconductor device and a manufacturing method thereof, and more particularly to a silicon carbide semiconductor device having a gate electrode and a manufacturing method thereof.

  As a power semiconductor device using a silicon substrate, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) having a trench gate has been widely used. On the other hand, the use of silicon carbide instead of silicon has been actively studied. It is expected that the on-resistance of the semiconductor device can be further reduced by using silicon carbide. However, so far, a MOSFET having a low on-resistance as theoretically expected has not been obtained. This is presumably because the channel mobility that greatly affects the on-resistance is significantly smaller than the theoretical value predicted from the physical properties of silicon carbide.

  According to Japanese Patent Laid-Open No. 2011-23675 (Patent Document 1), it is pointed out that the decrease in channel mobility of a trench MOSFET using silicon carbide is caused by the fact that the trench side wall surface is not smooth. Further, the impurity concentration and structure of the p body region intended to solve this problem are disclosed.

JP 2011-23675 A

  The optimization of the impurity concentration and structure as described in the above publication cannot sufficiently improve the channel mobility, and thus it is considered difficult to obtain a silicon carbide semiconductor device having a sufficiently small on-resistance. .

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a silicon carbide semiconductor device having a low on-resistance and a method for manufacturing the same.

  The silicon carbide semiconductor device of the present invention includes a silicon carbide substrate, a channel layer, a gate layer, a gate electrode, a first main electrode, and a second main electrode. The silicon carbide substrate has a first surface and a second surface opposite to the first surface. The silicon carbide substrate has a first layer, a second layer, and a third layer. The first layer has the first conductivity type. The first layer forms the second surface. The second layer is provided on the first layer so as to be separated from the second surface by the first layer. The second layer has a second conductivity type different from the first conductivity type. The third layer is provided on the second layer. The third layer has the first conductivity type. The third layer forms the first surface. A trench is provided in the first surface of the silicon carbide substrate. The trench has a sidewall surface. The trench penetrates the third layer and the second layer to reach the first layer. The channel layer is provided on the side wall surface of the silicon carbide substrate. The channel layer has a first conductivity type. The gate layer sandwiches the channel layer between the side walls of the silicon carbide substrate. The gate layer has the second conductivity type. The gate electrode is in contact with the gate layer. The first main electrode is separated from the gate layer and is in contact with at least one of the channel layer and the third layer. The second main electrode is provided on the second surface of the silicon carbide substrate.

  According to the silicon carbide semiconductor device described above, the channel layer having a channel thickness controlled by being sandwiched by the depletion layer extending from each of the second layer and the gate layer is provided on the sidewall surface of the trench. Unlike the channel layer formed at the interface between the semiconductor layer and the insulating film in the MOSFET, the channel layer includes a current path in the bulk crystal. As a result, the carrier mobility in the channel layer becomes closer to the intrinsic carrier mobility of the crystal. That is, channel mobility increases. Therefore, the on-resistance of the silicon carbide semiconductor device can be reduced.

  Preferably, the inclination of the sidewall surface of the trench of the silicon carbide substrate with respect to the first surface of the silicon carbide substrate is smaller than a right angle. Thereby, the channel layer and the gate layer can be easily formed on the sidewall surface of the trench in the manufacture of the silicon carbide semiconductor device.

  Preferably the first main electrode is in contact with the second layer. Thereby, the potential of the second layer can be stabilized.

  The method for manufacturing a silicon carbide semiconductor device of the present invention includes the following steps. A silicon carbide substrate is prepared. The silicon carbide substrate has a first surface and a second surface opposite to the first surface. The silicon carbide substrate has a first layer, a second layer, and a third layer. The first layer has the first conductivity type. The first layer forms the second surface. The second layer is provided on the first layer so as to be separated from the second surface by the first layer. The second layer has a second conductivity type different from the first conductivity type. The third layer is provided on the second layer. The third layer has the first conductivity type. The third layer forms the first surface. Next, a trench having a side wall surface and penetrating through the third layer and the second layer and reaching the first layer is formed on the first surface of the silicon carbide substrate. A channel layer having the first conductivity type is formed on the side wall surface of the silicon carbide substrate. A gate layer having the second conductivity type is formed with the channel layer sandwiched between the side walls of the silicon carbide substrate. A gate electrode in contact with the gate layer is formed. A first main electrode in contact with at least one of the channel layer and the third layer is formed. A second main electrode provided on the second surface of the silicon carbide substrate is formed.

  According to the above method for manufacturing a silicon carbide semiconductor device, a channel layer having a channel thickness controlled by being sandwiched between depletion layers extending from the second layer and the gate layer is provided on the sidewall surface of the trench. . Unlike the channel layer formed at the interface between the semiconductor layer and the insulating film in the MOSFET, the channel layer includes a current path in the bulk crystal. As a result, the carrier mobility in the channel layer becomes closer to the intrinsic carrier mobility of the crystal. That is, channel mobility increases. Therefore, the on-resistance of the silicon carbide semiconductor device can be reduced.

  Preferably, in the above method for manufacturing a silicon carbide semiconductor device, the step of forming the trench is performed by thermal etching. Thereby, the manufacturing dispersion | variation in the inclination angle of the side wall surface of a trench can be suppressed. Therefore, a silicon carbide semiconductor device with small characteristic variations can be obtained.

  As described above, according to the present invention, the on-resistance of the silicon carbide semiconductor device can be lowered.

FIG. 4 schematically shows a configuration of the silicon carbide semiconductor device in the first embodiment of the present invention, and is a cross-sectional view taken along a line II in FIG. 2 and FIG. 3. FIG. 2 is a plan view schematically showing a structure of the silicon carbide semiconductor device of FIG. 1. FIG. 2 is a plan view schematically showing a structure of a silicon carbide substrate included in the silicon carbide semiconductor device of FIG. 1. It is sectional drawing which shows schematically the 1st process of the manufacturing method of the silicon carbide semiconductor device in Embodiment 1 of this invention. It is sectional drawing which shows schematically the 2nd process of the manufacturing method of the silicon carbide semiconductor device in Embodiment 1 of this invention. It is sectional drawing which shows schematically the 3rd process of the manufacturing method of the silicon carbide semiconductor device in Embodiment 1 of this invention. It is sectional drawing which shows schematically the 4th process of the manufacturing method of the silicon carbide semiconductor device in Embodiment 1 of this invention. It is sectional drawing which shows schematically the 5th process of the manufacturing method of the silicon carbide semiconductor device in Embodiment 1 of this invention. It is sectional drawing which shows schematically the structure of the silicon carbide semiconductor device in Embodiment 2 of this invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

(Embodiment 1)
As shown in FIGS. 1 and 2, silicon carbide semiconductor device 90 of the present embodiment includes epitaxial substrate SC (silicon carbide substrate), channel layer 31, gate layer 32, gate electrode 40, and source electrode 41. (First main electrode) and a drain electrode 42 (second main electrode).

  As shown in FIGS. 1 and 3, the epitaxial substrate SC has an upper surface P1 (first surface) and a back surface P2 (second surface opposite to the first surface). Epitaxial substrate SC is made of silicon carbide. Epitaxial substrate SC has a first layer 10, a second layer 21, and a third layer 22. The first layer 10 has n-type (first conductivity type). The first layer 10 forms the back surface P2. The second layer 21 is provided on the first layer 10 so as to be separated from the back surface P <b> 2 by the first layer 10. The second layer 21 has a p-type (second conductivity type different from the first conductivity type). The third layer 22 is provided on the second layer 21. The third layer 22 has n-type (first conductivity type). The third layer 22 forms the upper surface P1.

  In the present embodiment, first layer 10 has single crystal substrate 11 and epitaxial layer 12 provided on single crystal substrate 11 and facing second layer 21. Preferably, the impurity concentration of second layer 21 is lower than the impurity concentration of single crystal substrate 11. Preferably, epitaxial substrate SC has a hexagonal crystal structure.

  A trench TR is provided on the upper surface P1 of the epitaxial substrate SC. Trench TR has side wall surface SL and bottom surface BS. The trench TR passes through the third layer 22 and the second layer 21 and reaches the first layer 10. Preferably, the inclination of side wall surface SL of trench TR of epitaxial substrate SC with respect to upper surface P1 of epitaxial substrate SC is greater than 0 ° and smaller than a right angle. Preferably, the inclination of the side wall surface SL with respect to the upper surface P1 is 10 ° or more. Preferably, the inclination of the side wall surface SL with respect to the upper surface P1 is 90 ° or less.

  Channel layer 31 is provided on at least side wall surface SL, and is further provided on top surface P1 and bottom surface BS in the present embodiment. The channel layer 31 has n-type (first conductivity type). Preferably, the thickness of channel layer 31 on side wall surface SL is 50 nm or more. Preferably, the thickness of the channel layer 31 on the side wall surface SL is 500 nm or less.

  Gate layer 32 sandwiches channel layer 31 between sidewall surface SL of epitaxial substrate SC. Gate layer 32 has p-type (second conductivity type).

  The gate electrode 40 is in contact with the gate layer 32. Preferably, gate electrode 40 includes a portion arranged in trench TR. The source electrode 41 is separated from the gate layer 32 and is in ohmic contact with the channel layer 31. In the present embodiment, the source electrode 41 is in contact with the channel layer 31. The drain electrode 42 is provided on the back surface P2 of the epitaxial substrate SC, and is in ohmic contact with the back surface P2.

  Next, a method for using silicon carbide semiconductor device 90 will be described. Silicon carbide semiconductor device 90 is a kind of junction field effect transistor, and is used as a switching element that controls electrical conduction between source electrode 41 and drain electrode 42. The channel controlled for the purpose of the on / off operation of the switching element is a portion of the channel layer 31 sandwiched between the gate layer 32 and the portion of the side wall surface SL made of the second layer 21. . When a depletion layer is sufficiently formed in the channel by applying an electric field to the channel, the switching element is turned off. For this purpose, a potential at which carriers in the channel are sufficiently eliminated is applied to the gate layer 32 via the gate electrode 40. In this embodiment, a negative potential having a sufficiently large absolute value is applied. Conversely, when such a potential is not applied, carriers exist in the channel, and thus the switching element is in the on state. As described above, silicon carbide semiconductor device 90 can be used as a switching element by changing the potential applied to gate electrode 40.

Next, a method for manufacturing silicon carbide semiconductor device 90 will be described below.
As shown in FIG. 4, first, an epitaxial substrate SC is prepared. At this time, the trench TR (FIG. 1) has not been formed yet.

  As shown in FIG. 5, a mask layer 60 having an opening is formed. The position of the opening corresponds to the position where the trench TR (FIG. 1) is to be formed. The material of mask layer 60 is, for example, silicon oxide.

  Next, etching is performed using the mask layer 60 as a mask. Preferably, this etching is performed by thermal etching (details will be described later).

  As shown in FIG. 6, trench TR is formed by the etching. Next, the mask layer 60 is removed. As a result, an epitaxial substrate SC having a trench TR is obtained as shown in FIG.

  As shown in FIG. 7, channel layer 31 is formed on upper surface P1, side wall surface SL, and bottom surface BS. Next, by forming a film on the channel layer 31, a gate layer 32 sandwiching the channel layer 31 with the side wall surface SL of the epitaxial substrate SC is formed. The channel layer 31 and the gate layer 32 can be formed by, for example, chemical vapor deposition.

  As shown in FIG. 8, the channel layer 31 is exposed by patterning the gate layer 32. Referring to FIG. 1 again, gate electrode 40 in contact with gate layer 32 is formed. Further, a source electrode 41 that is separated from the gate layer 32 and is in contact with the channel layer 31 is formed. In addition, drain electrode 42 provided on back surface P2 of epitaxial substrate SC is formed. Thus, silicon carbide semiconductor device 90 is obtained.

  According to the present embodiment, channel layer 31 having a channel thickness controlled by being sandwiched by a depletion layer extending from each of second layer 21 and gate layer 32 is provided on sidewall surface SL of trench TR. It is done. Unlike the channel layer formed at the interface between the semiconductor layer and the insulating film in the MOSFET, the channel layer 31 includes a current path in the bulk crystal. As a result, the carrier mobility in the channel layer 31 becomes closer to the original carrier mobility of the crystal. That is, channel mobility increases. Therefore, the on-resistance of silicon carbide semiconductor device 90 can be reduced.

  In addition, by adjusting the thickness of the channel layer, the absolute value of the voltage (the absolute value of the voltage threshold value) required to turn off silicon carbide semiconductor device 90 can be adjusted. For example, if the thickness is not excessively large, the absolute value of the voltage threshold can be made sufficiently small.

  According to the present embodiment, the inclination of sidewall surface SL of trench TR of epitaxial substrate SC with respect to upper surface P1 of epitaxial substrate SC is smaller than a right angle. Thereby, channel layer 31 and gate layer 32 can be easily formed on side wall surface SL of trench TR in the manufacture of silicon carbide semiconductor device 90.

  The process for forming the trench TR is performed by thermal etching. Thereby, the manufacturing dispersion | variation in the inclination angle of side wall surface SL of trench TR can be suppressed. Therefore, silicon carbide semiconductor device 90 with small characteristic variation is obtained.

  In addition, since the conductivity type (first conductivity type) of channel layer 31 is n-type, electrons can be used as carriers in the silicon carbide semiconductor device. Thereby, carrier mobility becomes high compared with the case where a hole is used as a carrier. Therefore, the on-resistance of silicon carbide semiconductor device 90 can be further reduced.

  In this embodiment, the source electrode 41 is in contact with the channel layer 31, but the source electrode 41 is in contact with the channel layer 31 instead of or in contact with the third layer 22. It may be in contact. In order to obtain such a configuration, for example, the channel layer 31 is also patterned in the patterning of the gate layer 32 shown in FIG. 8, and the source electrode 41 is provided on the third layer 22 exposed by this patterning. . Note that a mode in which the source electrode is in contact with the second layer 21 will be described in Embodiment Mode 2.

  Instead of trench TR (FIG. 1) having bottom surface BS, a trench having no bottom surface, for example, a V-shaped trench may be provided. As a result, the semiconductor device can be made smaller.

  The formation of the gate electrode 40 is not necessarily performed after the patterning of the gate layer 32 (FIG. 8), and may be performed before the patterning of the gate layer 32 (FIG. 7).

Further, “thermal etching” is performed by exposing an object to be etched to an etching gas at a high temperature, and has substantially no physical etching action. By using thermal etching, a crystallographically specific side wall surface SL can be self-formed. The thermal etching process gas preferably contains a halogen atom, and more preferably the halogen atom is a chlorine atom. Specifically, the process gas may be Cl ₂ gas. Preferably, the process gas further includes a gas containing oxygen atoms in addition to the gas containing a halogen element. Specifically, the gas containing oxygen atoms may be O ₂ gas. The process gas may contain a carrier gas. As the carrier gas, for example, N ₂ gas, Ar gas, or He gas can be used. The heat treatment temperature for thermal etching is preferably 700 ° C. or higher and 1200 ° C. or lower. The lower limit of this temperature is more preferably 800 ° C, and still more preferably 900 ° C. Further, the upper limit of this temperature is more preferably 1100 ° C., still more preferably 1000 ° C. In this case, the etching rate can be set to a sufficiently practical value. When the heat treatment temperature is set to 700 ° C. or higher and 1000 ° C. or lower, the etching rate of silicon carbide is about 70 μm / hr, for example.

  Etching for forming the trench TR is not limited to thermal etching, and other dry etching methods may be used. For example, dry etching such as reactive ion etching or ion beam etching may be used. Further, wet etching may be used instead of dry etching.

(Embodiment 2)
As shown in FIG. 9, silicon carbide semiconductor device 90V of the present embodiment has source electrode 41V instead of source electrode 41 of the first embodiment. The source electrode 41 </ b> V penetrates the third layer 22 and is in contact with the second layer 21.

  According to the present embodiment, since the source electrode 41V is in contact with the second layer 21, the potential of the second layer 21 corresponds to the potential of the source electrode 41V. Thereby, the potential of the second layer 21 can be stabilized.

  In the above description, the first conductivity type is n-type and the second conductivity type is p-type, but the first conductivity type is p-type and the second conductivity type is n-type. Also good.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the embodiments and examples described above but by the scope of claims for patent, and is intended to include all modifications within the meaning and scope equivalent to the scope of claims for patent.

  10 first layer, 11 single crystal substrate, 12 epitaxial layer, 21 second layer, 22 third layer, 31 channel layer, 32 gate layer, 40 gate electrode, 41, 41 V source electrode (first main electrode) ), 42 Drain electrode (second main electrode), 60 mask layer, 90, 90 V silicon carbide semiconductor device, BS bottom surface, P1 top surface, P2 back surface, SC epitaxial substrate (silicon carbide substrate), SL side wall surface, TR trench.

Claims (5)

A silicon carbide substrate having a first surface and a second surface opposite to the first surface, wherein the silicon carbide substrate has a first conductivity type and forms the second surface. And a second layer having a second conductivity type different from the first conductivity type provided on the first layer so as to be separated from the second surface by the first layer. A third layer provided on the second layer and having the first conductivity type and forming the first surface, wherein the first surface of the silicon carbide substrate has a side wall surface. And a trench extending through the third layer and the second layer to reach the first layer is provided, further provided on the side wall surface of the silicon carbide substrate, A channel layer having one conductivity type;
A gate layer having the second conductivity type, sandwiching the channel layer between the sidewall surfaces of the silicon carbide substrate;
A gate electrode in contact with the gate layer;
A first main electrode separated from the gate layer and in contact with at least one of the channel layer and the third layer;
A silicon carbide semiconductor device comprising: a second main electrode provided on the second surface of the silicon carbide substrate.   The silicon carbide semiconductor device according to claim 1, wherein an inclination of the side wall surface of the trench of the silicon carbide substrate with respect to the first surface of the silicon carbide substrate is smaller than a right angle.   The silicon carbide semiconductor device according to claim 1, wherein the first main electrode is in contact with the second layer. A step of preparing a silicon carbide substrate, wherein the silicon carbide substrate has a first surface and a second surface opposite to the first surface, and the silicon carbide substrate has a first conductivity type. A first layer having the second surface, and provided on the first layer so as to be separated from the second surface by the first layer, and different from the first conductivity type A second layer having a second conductivity type; and a third layer provided on the second layer and having the first conductivity type and forming the first surface. Forming a trench on the first surface of the substrate having a side wall surface and penetrating the third layer and the second layer to reach the first layer;
Forming a channel layer having the first conductivity type on the sidewall surface of the silicon carbide substrate;
Forming the gate layer having the second conductivity type by sandwiching the channel layer with the side wall surface of the silicon carbide substrate;
Forming a gate electrode in contact with the gate layer;
Forming a first main electrode in contact with at least one of the channel layer and the third layer;
Forming a second main electrode provided on the second surface of the silicon carbide substrate. A method for manufacturing a silicon carbide semiconductor device.   The method for manufacturing a silicon carbide semiconductor device according to claim 4, wherein the step of forming the trench is performed by thermal etching.

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