JP2008103369A - Semiconductor device and its manufacturing process - Google Patents

Semiconductor device and its manufacturing process Download PDF

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JP2008103369A
JP2008103369A JP2006282070A JP2006282070A JP2008103369A JP 2008103369 A JP2008103369 A JP 2008103369A JP 2006282070 A JP2006282070 A JP 2006282070A JP 2006282070 A JP2006282070 A JP 2006282070A JP 2008103369 A JP2008103369 A JP 2008103369A
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conductor layer
metal plate
conductor
semiconductor device
semiconductor chip
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Michinari Tetani
道成 手谷
Koichi Nagao
浩一 長尾
Yoshifumi Nakamura
嘉文 中村
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which can assure heat dissipation properties even when a metal plate is made small with reduction of a wiring board or when a face-down structure is employed, and to provide its manufacturing process. <P>SOLUTION: The structure of a semiconductor device includes a wiring board B having a first conductor layer 4 and a second conductor layer 9 formed on the surface and the back of a substrate 3 and a conductive material 11 for connecting the first conductor layer 4 and the second conductor layer 9 provided in a through hole 10, a semiconductor element 1 connected with first conductor wiring 4a patterned on the first conductor layer 4 through a bump electrode 2 from side opposite to the substrate 3, and a metal plate 7 connected with the second conductor layer 9. Although a face-down structure is employed, heat from the semiconductor element 1 is transmitted through the first conductor layer 4 and the conductive material 11 to the second conductor layer 9 and dissipated therefrom, and further transmitted from the second conductor layer 9 to the metal plate 7 and dissipated therefrom. Since the heat is dissipated entirely from the second conductor layer 9 and the metal plate 7 on one side of the wiring board, high heat dissipation efficiency is attained. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は半導体装置およびその製造方法に関し、特に放熱性に優れた半導体装置およびその製造方法に関する。   The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device excellent in heat dissipation and a manufacturing method thereof.

近年、集積回路の高集積化、半導体チップの縮小化が進み、微細ピッチの端子接続に対応可能な実装技術が要求されている。この要求に対応できる実装技術として、TCP(Tape Carrier Package)等に利用されるTAB(Tape Automated Bonding)や、異方性導電膜(ACF:Anisotropic Conductive Film)を利用したCOG(Chip On Glass)あるいはCOF(Chip On Film)といった実装形態が知られている。   In recent years, as integrated circuits have been highly integrated and semiconductor chips have been reduced in size, a mounting technique that can cope with terminal connection at a fine pitch is required. As mounting technology that can meet this requirement, TAB (Tape Automated Bonding) used for TCP (Tape Carrier Package), COG (Chip On Glass) using anisotropic conductive film (ACF) or A mounting form such as COF (Chip On Film) is known.

これらの実装形態の基本構成は、半導体チップの各電極パッド上にバンプと呼ばれる突起電極をAuや半田を用いて形成し、樹脂テープやガラス基板上に形成された金属配線に前記半導体チップのバンプを一括に接合するというものである。集積回路の高集積化に伴い、高電圧、高電流が使用されるようになってきたことから、発熱対策もとられている。   The basic structure of these mounting forms is that bump electrodes called bumps are formed on each electrode pad of a semiconductor chip using Au or solder, and bumps of the semiconductor chip are formed on metal wiring formed on a resin tape or a glass substrate. Are joined together. With the high integration of integrated circuits, high voltage and high current have come to be used.

この種の半導体装置の構成を図6に示す。半導体チップ1は、一方の面(以下、主面という)に突起電極2が形成されており、半導体チップ1と相似形状の開口部(デバイスホール)を持った配線基板に対して、具体的にはデバイスホールを持った絶縁性フィルム3上の導体層4にパターン形成された第一の導体配線4aに対して、絶縁性フィルム3側から前記突起電極2により電気的に接続されている。接続部分及び半導体チップ1の主面は封止樹脂5によって覆われている。   The configuration of this type of semiconductor device is shown in FIG. The semiconductor chip 1 has a protruding electrode 2 formed on one surface (hereinafter referred to as a main surface), and specifically, for a wiring board having an opening (device hole) similar in shape to the semiconductor chip 1. Is electrically connected to the first conductor wiring 4a patterned on the conductor layer 4 on the insulating film 3 having a device hole by the protruding electrode 2 from the insulating film 3 side. The connecting portion and the main surface of the semiconductor chip 1 are covered with a sealing resin 5.

半導体チップ1のもう一方の面(以下、裏面という)はグリース6を介して熱的に金属板7に接続されている(たとえば特許文献1の図4)。図示したように、半導体チップ1の接地端子の突起電極2が接続された導体層4が導通ねじ8を用いて金属板7に電気的に接続されているものもある。   The other surface (hereinafter referred to as the back surface) of the semiconductor chip 1 is thermally connected to the metal plate 7 via the grease 6 (for example, FIG. 4 of Patent Document 1). As shown in the figure, there is a case where the conductor layer 4 to which the protruding electrode 2 of the ground terminal of the semiconductor chip 1 is connected is electrically connected to the metal plate 7 using a conduction screw 8.

このような半導体装置においては、半導体チップ1が駆動する際に発生する熱は、半導体チップ1裏面からグリース6を通じて金属板7に伝わって空気中に放熱されると同時に、突起電極2を通じて導体層4に伝わって空気中に放熱される。一方で、半導体チップ1の接地端子信号は、突起電極2から導体層4と導通ねじ8とを通じて金属板7に流れることになり、接地を充分に取ることが可能であるため、ノイズの低減、EMI対策を行うことが可能となる。   In such a semiconductor device, the heat generated when the semiconductor chip 1 is driven is transferred from the back surface of the semiconductor chip 1 to the metal plate 7 through the grease 6 and dissipated into the air, and at the same time, the conductor layer through the protruding electrode 2. 4 is dissipated in the air. On the other hand, since the ground terminal signal of the semiconductor chip 1 flows from the protruding electrode 2 to the metal plate 7 through the conductor layer 4 and the conduction screw 8, it is possible to sufficiently take the ground, thereby reducing noise. It becomes possible to take measures against EMI.

一方、半導体チップ1を導体配線4aに対して、図6に示したのとは逆に、絶縁性フィルム3に背反する側から接続させたい場合がある(以下、この向きの接続をフェイスダウンという)。またたとえば導体配線4aの幅(リード幅)を細くして端子の配置ピッチを小さくする場合は、導体配線4aを図示したように宙に浮かせるのでなく支持する構造にする必要がある。   On the other hand, there is a case where it is desired to connect the semiconductor chip 1 to the conductor wiring 4a from the side opposite to the insulating film 3 contrary to that shown in FIG. ). For example, when the width (lead width) of the conductor wiring 4a is reduced to reduce the terminal arrangement pitch, it is necessary to support the conductor wiring 4a instead of floating in the air as shown in the figure.

これに適合するものとして、スルーホールを形成した絶縁性フィルムにデバイスホールを開口させることなく導体層を形成し、その導体配線上に半導体チップをフェイスダウンで接続した構造であって、導体層を形成していない絶縁性フィルムのもう一方の面に金属板を配置したものや、絶縁性フィルムの両面に導体層を設けておき、半導体チップを接続させた導体層上に金属板を配置したものがある(特許文献1の図2、図5)。
特開平10−41428号公報
In conformity with this, a conductor layer is formed in an insulating film in which a through hole is formed without opening a device hole, and a semiconductor chip is connected face-down on the conductor wiring. A metal plate placed on the other side of the insulating film that has not been formed, or a conductor layer provided on both sides of the insulating film, and a metal plate placed on the conductor layer to which the semiconductor chip was connected (FIGS. 2 and 5 of Patent Document 1).
Japanese Patent Laid-Open No. 10-41428

しかしながら、図6に示したような従来の半導体装置では、装置小型化のために配線基板を縮小化する場合は同時に金属板7も小さくするので、放熱性が低下するという問題がある。   However, the conventional semiconductor device as shown in FIG. 6 has a problem that heat dissipation is reduced because the metal plate 7 is also made smaller at the same time when the wiring board is reduced in order to reduce the size of the device.

また上記したフェイスダウン構造の半導体装置の内、前者は、半導体チップを接続した導体層をスルーホールを通じて金属板に接続しているものの、半導体チップと金属板とを熱的に直接接続するものではなく、金属板に直接に熱伝導するのはスルーホール部分のみである。後者は、スルーホールで接続された一方の導体層の上に半導体チップと金属板とを配置したものであることから、金属板の設置面積が限られる。そのためいずれも半導体装置も所望の放熱性が得られないことがある。   Of the face-down semiconductor devices described above, the former connects the semiconductor layer to the metal plate through the through hole, but does not directly connect the semiconductor chip and the metal plate thermally. Instead, only the through hole portion conducts heat directly to the metal plate. In the latter, a semiconductor chip and a metal plate are arranged on one conductor layer connected by a through hole, so that the installation area of the metal plate is limited. Therefore, none of the semiconductor devices can obtain the desired heat dissipation.

仮に、図6に示した配線基板に対するフェイスダウン構造を考えてみても、半導体チップ1と金属板7とを熱的に直接接続することはできず、金属板7に直接に熱伝導するのは導通ねじ8部分のみである。絶縁性フィルム3にスルーホールを設けた場合も同様である。このため、上述したように半導体チップ1の裏面をグリース6を介して金属板7に接続させる構造をとっているのが現状である。   Even if the face-down structure for the wiring board shown in FIG. 6 is considered, the semiconductor chip 1 and the metal plate 7 cannot be directly thermally connected, and the heat conduction directly to the metal plate 7 is not possible. There are only 8 conductive screws. The same applies when a through hole is provided in the insulating film 3. For this reason, as described above, the current situation is that the back surface of the semiconductor chip 1 is connected to the metal plate 7 via the grease 6.

本発明は上記問題を解決するもので、配線基板の縮小化に伴い金属板を小さくする場合も、フェイスダウン構造の場合も、放熱性を確保できる半導体装置およびその製造方法を提供することを目的とする。   SUMMARY OF THE INVENTION The present invention solves the above problems, and an object of the present invention is to provide a semiconductor device that can ensure heat dissipation and a method of manufacturing the same, both in the case of reducing the size of a metal plate as the wiring board is reduced and in the case of a face-down structure. And

上記課題を解決するために、本発明の半導体装置は、第一の導体層と第二の導体層とが基板の表裏面に形成され、前記第一の導体層と第二の導体層とを接続する導電性材料がスルーホール内に設けられた配線基板と、前記第一の導体層にパターン形成された第一の導体配線に前記基板に背反する側から突起電極を介して接続された半導体素子と、前記第二の導体層に接続された金属板とを有することを特徴とする。   In order to solve the above-described problems, a semiconductor device of the present invention includes a first conductor layer and a second conductor layer formed on the front and back surfaces of a substrate, and the first conductor layer and the second conductor layer. A semiconductor in which a conductive material to be connected is provided in a through hole, and a semiconductor connected to a first conductor wiring patterned on the first conductor layer via a protruding electrode from the side opposite to the substrate It has an element and the metal plate connected to said 2nd conductor layer, It is characterized by the above-mentioned.

この半導体装置は、半導体素子を突起電極を介して第一の導体層に対してフェイスダウンで接続した構造であるが、半導体素子の熱は、第一の導体層とスルーホールとを通じて第二の導体層に伝わり、この第二の導体層から放熱されるとともに、第二の導体層から金属板に伝わってそこから放熱される。配線基板の片面にある第二の導体層と金属板の全体から放熱されるため、放熱効率は高い。   This semiconductor device has a structure in which a semiconductor element is connected face-down to a first conductor layer via a protruding electrode. The heat of the semiconductor element is transmitted through a first conductor layer and a through hole to the second conductor layer. It is transmitted to the conductor layer and is radiated from the second conductor layer, and is also transmitted from the second conductor layer to the metal plate and radiated from there. Since heat is radiated from the entire second conductive layer and metal plate on one side of the wiring board, the heat dissipation efficiency is high.

また、前記半導体素子の接地端子と前記第二の導体層とが電気的に接続されていることを特徴とする。これによれば、半導体素子の接地端子は第二の導体層を介して金属板と電気的に接続されることになり、ノイズの低減、EMI対策を行うことができる。   The ground terminal of the semiconductor element and the second conductor layer are electrically connected. According to this, the ground terminal of the semiconductor element is electrically connected to the metal plate via the second conductor layer, and noise can be reduced and EMI countermeasures can be taken.

また、前記配線基板は前記半導体素子の搭載領域に開口部を有し、前記金属板は前記開口部内に配置される突起部を有することを特徴とする。これによれば、半導体素子の近傍に伝熱性の高い金属板の突起部が配置されることになり、熱伝導性、放熱性が向上する。よって、配線基板の縮小化に伴い金属板を小さくする場合も放熱性を確保できる。   The wiring board may have an opening in the mounting region of the semiconductor element, and the metal plate may have a protrusion disposed in the opening. According to this, the protrusion part of a highly heat conductive metal plate will be arrange | positioned in the vicinity of a semiconductor element, and thermal conductivity and heat dissipation will improve. Therefore, heat dissipation can be ensured even when the metal plate is made smaller as the wiring board is reduced.

本発明の半導体装置の製造方法は、第一および第二の導体層を基板の表裏面に有し、両導体層を接続する導電性材料をスルーホール内に有した配線基板に対して、前記第一の導体層にパターン形成された第一の導体配線に接続される突起電極を有した半導体素子を前記基板に背反する側から位置合わせする工程と、前記第一の導体配線と前記突起電極とを熱圧着もしくは超音波接合する工程と、前記第二の導体層上に導電導熱性材料を配置する工程と、前記第二の導体層に前記導電導熱性材料を介して金属板を接続させる工程とを有することを特徴とする。位置合わせは当然ながら相対的に行えばよい。   The method for manufacturing a semiconductor device of the present invention has the first and second conductor layers on the front and back surfaces of the substrate, and the wiring substrate having a conductive material in the through hole for connecting both conductor layers. A step of aligning a semiconductor element having a protruding electrode connected to the first conductor wiring patterned on the first conductor layer from a side opposite to the substrate; the first conductor wiring and the protruding electrode; A step of thermocompression bonding or ultrasonic bonding, a step of disposing a conductive heat conductive material on the second conductor layer, and a metal plate connected to the second conductor layer via the conductive heat conductive material And a process. Naturally, alignment may be performed relatively.

本発明によれば、表裏の第一および第二の導体層をスルーホール内の導電性材料で接続した配線基板を用い、第一の導体層に半導体素子を接続し、第二の導体層に金属板を接続するようにしたことにより、従来のフェイスダウン構造よりも高い放熱性を確保できる。   According to the present invention, using the wiring board in which the first and second conductor layers on the front and back sides are connected by the conductive material in the through hole, the semiconductor element is connected to the first conductor layer, and the second conductor layer is connected to the second conductor layer. By connecting the metal plates, it is possible to ensure higher heat dissipation than the conventional face-down structure.

また、半導体素子の接地端子を、金属板に接続している第二の導体配線に電気的に接続させるようにしたことにより、ノイズの低減、EMI対策を行うことができる。
また、突起部を有する金属板を用いることにより、突起部が半導体素子に近づくこととなり、熱伝導距離が短くなり、熱抵抗を下げることができ、配線基板の縮小化に伴って金属板の面積を小さくせざるをえない場合も、効率よく放熱することが可能である。
Further, since the ground terminal of the semiconductor element is electrically connected to the second conductor wiring connected to the metal plate, noise can be reduced and EMI countermeasures can be taken.
In addition, by using a metal plate having a protrusion, the protrusion approaches the semiconductor element, the heat conduction distance is shortened, the thermal resistance can be reduced, and the area of the metal plate is reduced as the wiring board is reduced. Even if it is unavoidable to reduce the size, it is possible to dissipate heat efficiently.

以下、本発明の実施の形態を、図面を参照しながら説明する。
図1は本発明の実施の形態1における半導体装置の構成を示す。半導体チップ(半導体素子)1は、主面(回路形成面)に突起電極2が形成されており、この突起電極2を介して、半導体チップ1と相似形状の開口部(デバイスホール)を持った配線基板Bに電気的に接続されている。
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 shows a configuration of a semiconductor device according to the first embodiment of the present invention. The semiconductor chip (semiconductor element) 1 has a projecting electrode 2 formed on the main surface (circuit formation surface), and has an opening (device hole) similar to the semiconductor chip 1 through the projecting electrode 2. It is electrically connected to the wiring board B.

詳細には、配線基板Bは、半導体チップ1よりも大きい開口部3aを持った絶縁性フィルム3の一方の面に蒸着などで形成された第一の導体層4に第一の導体配線4aがパターン形成され、もう一方の面に蒸着などで形成された第二の導体層9に第二の導体配線(図示せず)がパターン形成されたものであり、第一の導体配線4aのみが開口部3a内まで延びている。第一の導体層4と第二の導体層3とは、絶縁性フィルム3を貫通するスルーホール10内に充填された導電性材料11によって電気的かつ熱的に接続されている。   Specifically, the wiring board B has a first conductor wiring 4a on a first conductor layer 4 formed by vapor deposition or the like on one surface of an insulating film 3 having an opening 3a larger than the semiconductor chip 1. A second conductor wiring (not shown) is formed in a pattern on the second conductor layer 9 formed by vapor deposition or the like on the other surface, and only the first conductor wiring 4a is opened. It extends into the portion 3a. The first conductor layer 4 and the second conductor layer 3 are electrically and thermally connected by a conductive material 11 filled in a through hole 10 penetrating the insulating film 3.

そしてこの配線基板Bの第一の導体配線4aに対して、上述した半導体チップ1がその突起電極2により絶縁性フィルム3に背反する側から電気的に接続されている。つまりフェイスダウン構造である。第一の導体配線4aと突起電極2との接続部分及び半導体チップ1の主面は封止樹脂5によって覆われている。   The semiconductor chip 1 described above is electrically connected to the first conductor wiring 4 a of the wiring board B from the side opposite to the insulating film 3 by the protruding electrode 2. In other words, it is a face-down structure. The connecting portion between the first conductor wiring 4 a and the protruding electrode 2 and the main surface of the semiconductor chip 1 are covered with a sealing resin 5.

絶縁性フィルム3の第二の導体層9側には金属板7が配置されている。この金属板7は、開口部3aを覆い得るサイズであり、一方の面の中央部に突起部7aを有していて、この突起部7aを半導体チップ1の方向へ向けて、つまり突起部7aを開口部3a内に侵入させた状態で、第二の導体層9上であって開口部3a近傍部分にグリース6によって電気的かつ熱的に接続されている。上記の封止樹脂5は、図示したように金属板7まで充填されている。   A metal plate 7 is disposed on the second conductive layer 9 side of the insulating film 3. The metal plate 7 has a size that can cover the opening 3a. The metal plate 7 has a protrusion 7a at the center of one surface, and the protrusion 7a is directed toward the semiconductor chip 1, that is, the protrusion 7a. Is electrically and thermally connected to the portion near the opening 3a by the grease 6 on the second conductor layer 9 in a state in which is inserted into the opening 3a. The sealing resin 5 is filled up to the metal plate 7 as shown.

なお、突起電極2は例えばAu、又はNi上にAu被覆を施したものである。絶縁性フィルム3は例えばポリイミドを主体としたものであり、第一の導体層4と第二の導体層9はともに例えばCuにSnあるいはAu被覆を施したものである。導電性材料11は例えばエポキシ樹脂やシリコーン樹脂などの絶縁性樹脂の中に銅粒子、銀粒子、ニッケル粒子などの導電性フィラーを添加した導電性樹脂や半田等の金属である。封止樹脂5は例えばエポキシ系樹脂である。   The protruding electrode 2 is, for example, Au or Ni coated with Au. The insulating film 3 is mainly made of polyimide, for example, and the first conductor layer 4 and the second conductor layer 9 are both Cu, for example, coated with Sn or Au. The conductive material 11 is, for example, a conductive resin or a metal such as solder obtained by adding a conductive filler such as copper particles, silver particles, or nickel particles to an insulating resin such as an epoxy resin or a silicone resin. The sealing resin 5 is, for example, an epoxy resin.

上記構成により、半導体チップ1が駆動する際に発生する熱は、半導体チップ1表面から封止樹脂5を通じて突起部7aへ伝わり、金属板7全体から空気中に放熱される。また半導体チップ1の突起電極2から第一の導体層4と導電性材料11とを通じて第二の導体層9へ伝わり、この第二の導体層9からグリース6を通じて金属板7に伝わり、金属板7から空気中に放熱されると同時に、第二の導体層9自体も放熱性を有しているためそこから空気中に放熱される。絶縁性フィルム3の片面にある第二の導体層9と金属板7の全体から放熱されるため、放熱効率は高い。   With the above configuration, the heat generated when the semiconductor chip 1 is driven is transmitted from the surface of the semiconductor chip 1 to the protrusion 7a through the sealing resin 5 and is radiated from the entire metal plate 7 into the air. Further, it is transmitted from the protruding electrode 2 of the semiconductor chip 1 to the second conductor layer 9 through the first conductor layer 4 and the conductive material 11, and is transmitted from the second conductor layer 9 to the metal plate 7 through the grease 6. At the same time as heat is radiated from the air 7 to the air, the second conductor layer 9 itself is also radiating heat so that it is radiated from the air to the air. Since heat is radiated from the entire second conductor layer 9 and the metal plate 7 on one side of the insulating film 3, the heat radiation efficiency is high.

一方で、半導体チップ1の突起電極2の中には接地端子上に形成されているものもあるので、半導体チップ1の接地端子信号は該当する突起電極2から第一の導体層4と導電性材料11とを通じて第二の導体層9へ伝わり、次いでグリース6を通じて金属板7に伝わることとなり、接地を充分に取ることが可能であるため、ノイズの低減、EMI対策を行うことが可能となる。   On the other hand, since some of the protruding electrodes 2 of the semiconductor chip 1 are formed on the ground terminal, the ground terminal signal of the semiconductor chip 1 is transmitted from the corresponding protruding electrode 2 to the first conductor layer 4 and conductive. It is transmitted to the second conductor layer 9 through the material 11 and then transmitted to the metal plate 7 through the grease 6 and can be sufficiently grounded, so that it is possible to reduce noise and take measures against EMI. .

この半導体装置を実装するときは、図2に示すように、配線基板Bを、ガラスパネル基板12などの実装基板に第一の導体層4を接合させるように、またガラスパネル基板12を囲うように配置する。半導体チップ1はその突起電極2が形成された面(回路形成面)が基板面と同じ向きとなり、背面において基板面に支持されることとなり、半導体チップ1よりも外周側に(基板面を基準にして)、第一の導体層4と絶縁フィルム3と第二の導体層4と金属板7とが順に配置される。放熱の役割を持った金属板7が最外周に配置されることになる。   When mounting this semiconductor device, as shown in FIG. 2, the wiring board B is so formed that the first conductor layer 4 is bonded to a mounting board such as the glass panel board 12, and the glass panel board 12 is surrounded. To place. The semiconductor chip 1 has a surface (circuit forming surface) on which the protruding electrode 2 is formed in the same direction as the substrate surface, and is supported by the substrate surface on the back surface. The first conductor layer 4, the insulating film 3, the second conductor layer 4, and the metal plate 7 are arranged in this order. The metal plate 7 having a heat radiating role is arranged on the outermost periphery.

この半導体装置のように、第一の導体層4に対して絶縁性フィルム3に背反する側から半導体チップ1を接続させるフェイスダウン構造の場合には、半導体チップ1に直接に金属板7を接続させることができないため、上述の構造が必要となるのである。金属板7が外気に曝されない配置では熱交換ができない。なお、先に図6を用いて説明した従来の半導体装置は、フェイスダウン構造でないため、半導体チップ1の裏面に直接に接続した金属板7を最外周に配置することが可能である。   In the case of a face-down structure in which the semiconductor chip 1 is connected to the first conductor layer 4 from the side opposite to the insulating film 3 as in this semiconductor device, the metal plate 7 is directly connected to the semiconductor chip 1. The above-described structure is necessary because it cannot be made. Heat exchange cannot be performed in an arrangement where the metal plate 7 is not exposed to the outside air. Since the conventional semiconductor device described above with reference to FIG. 6 does not have a face-down structure, the metal plate 7 directly connected to the back surface of the semiconductor chip 1 can be disposed on the outermost periphery.

上記の本発明の半導体装置の製造方法について図3および図4を用いて説明する。
図3(a)に示すように、ボンディングステージ21上に、突起電極2を有する半導体チップ1を配置する。半導体チップ1の上方に、第一の導体層4と第二の導体層9と導電性材料11とを有する絶縁性フィルム3を配置し、突起電極2と第一の導体配線4aとを位置合わせする。
The method for manufacturing the semiconductor device of the present invention will be described with reference to FIGS.
As shown in FIG. 3A, the semiconductor chip 1 having the protruding electrode 2 is disposed on the bonding stage 21. An insulating film 3 having a first conductor layer 4, a second conductor layer 9, and a conductive material 11 is disposed above the semiconductor chip 1, and the protruding electrode 2 and the first conductor wiring 4a are aligned. To do.

次に、図3(b)に示すように、ボンディングツール22を半導体チップ1上に配置することで、ボンディングツール22と突起電極2との間に第一の導体配線4aを挟み込み、接合に必要な温度加熱、荷重印可または超音波振動を与える。このことにより、突起電極2の表面のAuと第一の導体配線4aの表面のAuもしくはSnが共晶または金属間結合にて接合される。なおボンディングステージ21およびボンディングツール22は鋼材もしくはセラミック材で形成されている。   Next, as shown in FIG. 3B, the bonding tool 22 is disposed on the semiconductor chip 1 so that the first conductor wiring 4a is sandwiched between the bonding tool 22 and the protruding electrode 2 and is necessary for bonding. Apply appropriate temperature heating, load application or ultrasonic vibration. As a result, Au on the surface of the protruding electrode 2 and Au or Sn on the surface of the first conductor wiring 4a are joined together by eutectic or intermetallic bonding. The bonding stage 21 and the bonding tool 22 are made of steel or ceramic material.

次に、図3(c)に示すように、半導体チップ1上に封止樹脂5を滴下して図示したように第二の導体層9の開口近傍部分までを覆う。
次に、図4(a)に示すように、第二の導体層9上であって封止樹脂5の周囲にグリース6を塗布し、その後に、図4(b)(c)に示すように、金属板7を封止樹脂5上に配置して突起部7aを封止樹脂5に埋入させ、金属板7の周縁部分をグリース6上に載せる。この状態で、封止樹脂5を硬化させる熱処理を加える。
Next, as shown in FIG. 3C, the sealing resin 5 is dropped on the semiconductor chip 1 to cover the portion near the opening of the second conductor layer 9 as shown.
Next, as shown in FIG. 4 (a), grease 6 is applied on the second conductor layer 9 and around the sealing resin 5, and thereafter, as shown in FIGS. 4 (b) and 4 (c). Then, the metal plate 7 is placed on the sealing resin 5, the protrusion 7 a is embedded in the sealing resin 5, and the peripheral portion of the metal plate 7 is placed on the grease 6. In this state, heat treatment for curing the sealing resin 5 is applied.

図5は本発明の実施の形態2における半導体装置の構成を示す。この実施の形態2の半導体装置が上記した実施の形態1の半導体装置と相違するのは、絶縁性フィルム3には開口部3a(図1参照)は形成されておらず、金属板7は平板状であってその一面全体が第二の導体層9の上にグリース6により電気的かつ熱的に接続されている点である。   FIG. 5 shows the configuration of the semiconductor device according to the second embodiment of the present invention. The difference between the semiconductor device of the second embodiment and the semiconductor device of the first embodiment is that the opening 3a (see FIG. 1) is not formed in the insulating film 3, and the metal plate 7 is a flat plate. The entire surface is electrically and thermally connected to the second conductor layer 9 by the grease 6.

詳細には、第一の導体層4の複数の第一の導体配線4aは、絶縁性フィルム3に密着した状態で半導体チップ1のダイボンド領域内まで、つまり突起電極2が接続可能な位置まで、延びていて、互いの間に間隙を有している。封止樹脂5は、第一の導体配線4aと突起電極2との接続部分を覆い、半導体チップ1の主面と第一の導体配線4aおよび絶縁性フィルム3の露出部との間に充填されている。第二の導体層5は第一の導体配線4aどうしの間隙に対応する位置に、つまり半導体チップ1の中央に対応する位置に、間隙(あるいは開口)を有しており、この間隙内にもグリース6が充填されている。   Specifically, the plurality of first conductor wirings 4a of the first conductor layer 4 are in close contact with the insulating film 3 up to the die bond region of the semiconductor chip 1, that is, to the position where the protruding electrode 2 can be connected. It extends and has a gap between each other. The sealing resin 5 covers a connection portion between the first conductor wiring 4 a and the protruding electrode 2 and is filled between the main surface of the semiconductor chip 1 and the exposed portions of the first conductor wiring 4 a and the insulating film 3. ing. The second conductor layer 5 has a gap (or an opening) at a position corresponding to the gap between the first conductor wirings 4a, that is, at a position corresponding to the center of the semiconductor chip 1, and also in this gap. Grease 6 is filled.

この実施の形態2の半導体装置では、半導体チップ1が駆動する際に発生する熱は、半導体チップ1表面から封止樹脂5を介して第一の導体層4へ、また半導体チップ1の突起電極2から第一の導体層4へと伝わり、そこからスルーホール10内の導電性材料11を通じて第二の導体層9へ伝わる。そしてこの第二の導体層9からグリース6を通じて金属板7に伝わり、空気中に放熱されると同時に、第二の導体層9自体も放熱性を有しているためそこから空気中に放熱される。実施の形態1の半導体装置に比べて、絶縁性フィルム3に開口部を設けることなく、高放熱性を実現するものである。   In the semiconductor device according to the second embodiment, heat generated when the semiconductor chip 1 is driven is transferred from the surface of the semiconductor chip 1 to the first conductor layer 4 via the sealing resin 5 and the protruding electrode of the semiconductor chip 1. 2 to the first conductor layer 4, and from there to the second conductor layer 9 through the conductive material 11 in the through hole 10. Then, it is transmitted from the second conductor layer 9 to the metal plate 7 through the grease 6 and radiated into the air. At the same time, the second conductor layer 9 itself has a heat radiating property, so that the heat is radiated from there into the air. The Compared to the semiconductor device of the first embodiment, high heat dissipation is realized without providing an opening in the insulating film 3.

一方で、半導体チップ1の接地端子信号は、突起電極2から第一の導体層4と導電性材料11とを通じて第二の導体層9へ伝わり、さらにグリース6を通じて金属板7に流れることになり、接地を充分に取ることが可能であるため、また導体層9で被覆した構造であるため、ノイズの低減、EMI対策を行うことが可能となる。   On the other hand, the ground terminal signal of the semiconductor chip 1 is transmitted from the protruding electrode 2 to the second conductor layer 9 through the first conductor layer 4 and the conductive material 11, and further flows to the metal plate 7 through the grease 6. Since the grounding can be sufficiently taken and the structure is covered with the conductor layer 9, it is possible to reduce noise and take measures against EMI.

以上説明したように、本発明に係る半導体装置は、半導体チップの発熱を容易に外部へ逃がすことができ、また基板を被覆した導体層によりシールド性が向上するので、ガラスパネル基板等への実装後に他のシールド板などを用いる必要もない。   As described above, the semiconductor device according to the present invention can easily release the heat generated by the semiconductor chip to the outside, and the shielding performance is improved by the conductor layer covering the substrate. There is no need to use another shield plate or the like later.

なお、第一の導体層4および第二の導体層9を絶縁性フィルム3の両面に形成するものとして説明したが、これに限られず、絶縁性フィルム3に代えてガラス基板などの絶縁性基板を用いてもよい。第二の導体層9と金属板7とをグリース6によって電気的かつ熱的に接続するものとして説明したが、同様の性能を有する放熱シートを用いてもよい。   In addition, although demonstrated as what forms the 1st conductor layer 4 and the 2nd conductor layer 9 on both surfaces of the insulating film 3, it is not restricted to this, It replaces with the insulating film 3, and insulating substrates, such as a glass substrate May be used. Although the second conductor layer 9 and the metal plate 7 have been described as being electrically and thermally connected by the grease 6, a heat dissipation sheet having the same performance may be used.

本発明に係る半導体装置は、半導体チップ(半導体素子)の放熱性およびシールド性に優れるので、集積回路の高集積化、半導体チップの縮小化に対応するものとして有用である。   Since the semiconductor device according to the present invention is excellent in heat dissipation and shielding properties of a semiconductor chip (semiconductor element), it is useful as a device corresponding to high integration of an integrated circuit and downsizing of a semiconductor chip.

本発明の実施の形態1における半導体装置の構成を示す断面図Sectional drawing which shows the structure of the semiconductor device in Embodiment 1 of this invention 図1の半導体装置をガラスパネル基板へ実装した状態を示す断面図Sectional drawing which shows the state which mounted the semiconductor device of FIG. 1 on the glass panel board | substrate. 図1の半導体装置を製造する前半工程を説明する工程断面図Process sectional drawing explaining the first half process of manufacturing the semiconductor device of FIG. 図1の半導体装置を製造する後半工程を説明する工程断面図Process sectional drawing explaining the latter half process of manufacturing the semiconductor device of FIG. 本発明の実施の形態2における半導体装置の構成を示す断面図Sectional drawing which shows the structure of the semiconductor device in Embodiment 2 of this invention. 従来の半導体装置の構成を示す断面図Sectional drawing which shows the structure of the conventional semiconductor device

符号の説明Explanation of symbols

1 半導体チップ
2 突起電極
3 絶縁性フィルム
4 (第一の)導体層
5 封止樹脂
6 グリース
7 金属板
7a 突起部
8 導通ねじ
9 第二の導体層
10 スルーホール
11 導電性材料
12 ガラスパネル基板
21 ボンディングステージ
22 ボンディングツール
DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 Protruding electrode 3 Insulating film 4 (1st) conductor layer 5 Sealing resin 6 Grease 7 Metal plate
7a Protrusion 8 Conductive screw 9 Second conductor layer
10 Through hole
11 Conductive material
12 Glass panel substrate
21 Bonding stage
22 Bonding tool

Claims (4)

第一の導体層と第二の導体層とが基板の表裏面に形成され、前記第一の導体層と第二の導体層とを接続する導電性材料がスルーホール内に設けられた配線基板と、前記第一の導体層にパターン形成された第一の導体配線に前記基板に背反する側から突起電極により接続された半導体素子と、前記第二の導体層に接続された金属板とを有する半導体装置。   A wiring board in which a first conductor layer and a second conductor layer are formed on the front and back surfaces of the board, and a conductive material for connecting the first conductor layer and the second conductor layer is provided in the through hole. A semiconductor element connected to the first conductor wiring patterned on the first conductor layer by a protruding electrode from the side opposite to the substrate, and a metal plate connected to the second conductor layer. A semiconductor device having the same. 前記半導体素子の接地端子と前記第二の導体層とが電気的に接続されている請求項1記載の半導体装置。   The semiconductor device according to claim 1, wherein a ground terminal of the semiconductor element and the second conductor layer are electrically connected. 前記配線基板は前記半導体素子の搭載領域に開口部を有し、前記金属板は前記開口部内に配置される突起部を有する請求項1記載の半導体装置。   2. The semiconductor device according to claim 1, wherein the wiring board has an opening in a mounting region of the semiconductor element, and the metal plate has a protrusion disposed in the opening. 第一および第二の導体層を基板の表裏面に有し、両導体層を接続する導電性材料をスルーホール内に有した配線基板に対して、前記第一の導体層にパターン形成された第一の導体配線に接続される突起電極を有した半導体素子を前記基板に背反する側から位置合わせする工程と、前記第一の導体配線と前記突起電極とを熱圧着もしくは超音波接合する工程と、前記第二の導体層上に導電導熱性材料を配置する工程と、前記第二の導体層に前記導電導熱性材料を介して金属板を接続させる工程とを有する、半導体装置の製造方法。   A pattern is formed on the first conductor layer with respect to the wiring board having the first and second conductor layers on the front and back surfaces of the substrate and having a conductive material connecting the two conductor layers in the through hole. A step of aligning a semiconductor element having a protruding electrode connected to the first conductor wiring from the side opposite to the substrate; and a step of thermocompression bonding or ultrasonic bonding of the first conductor wiring and the protruding electrode A method of manufacturing a semiconductor device, comprising: disposing a conductive heat conductive material on the second conductor layer; and connecting a metal plate to the second conductor layer via the conductive heat conductive material. .
JP2006282070A 2006-10-17 2006-10-17 Semiconductor device and its manufacturing process Pending JP2008103369A (en)

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