JP2008098464A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that when a thin-film transistor (TFT) having a high current driving capability and large crystal grains is formed in a channel region, an electric operation becomes unstable due to a parasitic bipolar effect and when fine crystal capable of suppressing the parasitic bipolar effect is used, the current driving capability is deteriorated, because it is difficult to form a structure having different crystal sizes in a channel region inside the TFT in a process of forming the TFT using a polysilicon semiconductor as one embodiment of a manufacturing method of a semiconductor device. <P>SOLUTION: A pattern using a semi-transparent mask is formed on a channel portion to control distribution of crystal grains after annealing near the channel in executing laser annealing. For example, high-intensity laser annealing is executed on a channel center region and low-intensity laser annealing is executed on a gate end. Thus, a manufacturing method of a TFT as a semiconductor device capable of preventing the generation of a parasitic bipolar operation and having high current driving capability can be obtained. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  Laser annealing is employed to improve the crystallinity of a semiconductor film typified by a Si film. As a laser annealing method, there is a general method for laser annealing a Si film formed on the entire surface of a substrate. In addition, as shown in Patent Document 1, a plurality of stripe-shaped translucent insulating films formed in parallel on a semiconductor film are used as an antireflection layer, and a region covered with the translucent insulating film ( There is a method for manufacturing a crystalline semiconductor film in which a region (bare region) covered with the light-transmitting insulating film is converted into a crystalline semiconductor film using a cap region) as a seed crystal. Further, as in Patent Document 2, a semiconductor film is formed on an insulating substrate, a reflective film made of an insulating film is formed on a part of the semiconductor film, and laser light is irradiated using the reflective film as a mask. A method for manufacturing a semiconductor device is known in which a temperature gradient is formed in a direction parallel to the semiconductor film by crystallization so that the semiconductor film is crystallized with high controllability.

JP 2005-12030 A JP 2006-32924 A

  However, in the manufacturing method of Patent Document 1 described above, a semiconductor film with high crystallinity can be formed. However, when the semiconductor film is viewed in a plan view, the semiconductor film is composed of a film having a homogeneous property, There is a problem that it is difficult to control and form semiconductor films having different properties. Further, in the manufacturing method of Patent Document 2 described above, the crystal grains in the region where the semiconductor film is exposed can be enlarged, but it is difficult to change the characteristics of the region of the semiconductor film covered with the reflective film. Also, there is a problem that it is difficult to control and form semiconductor films having different properties. Further, both Patent Documents 1 and 2 have a problem that it is difficult to accurately form a channel region of a transistor in correspondence with a region in which crystal is grown in a lateral direction.

  Therefore, the present invention solves such a problem, and a laser annealing method for irradiating laser light with uniform intensity as uniform energy light when the substrate is viewed in plan on a semiconductor film formed on the substrate. An object of the present invention is to provide a method for manufacturing a semiconductor device including two or more levels different from the semiconductor film before laser annealing using (a method of irradiating uniform energy light).

  In this specification, “upper” is defined to indicate a direction away from the substrate active surface side.

  In order to solve the above problems, a method for manufacturing a semiconductor device of the present invention includes a step of forming a semiconductor film on a substrate, a step of forming a light-transmitting mask on a part of the semiconductor film, The semiconductor film is irradiated with light from a side opposite to the substrate to the first part that does not overlap the first part that overlaps the mask, and the bonding state of the substance constituting the first part and the second part And a step of changing the binding state of the substance constituting the material.

  According to this manufacturing method, control of the coupling state of the first part and the coupling state of the second part by light irradiation can be realized by controlling the light transmittance of the mask. A plurality of regions having different bonding states can be obtained through a process of irradiating light having a uniform intensity distribution. Further, since the mask is formed after patterning the semiconductor film, the patterned semiconductor film can be used as an alignment pattern for alignment. Therefore, it is possible to accurately define the region for modulating the coupling state.

  The method for manufacturing a semiconductor device according to the present invention includes a step of forming a semiconductor film on a substrate, a step of forming a light-transmitting mask on a part of the semiconductor film, and the semiconductor film out of the semiconductor film. Irradiating light from the opposite side of the substrate to the first part that overlaps the mask and the second part that does not overlap, and changing the crystal state between the first part and the second part. It is characterized by.

  According to this manufacturing method, the crystal state of the first part and the crystal state of the second part can be controlled by controlling the light transmittance of the mask. By irradiating with light having a uniform intensity distribution, a plurality of regions having different crystal states can be obtained only by the mask formation and light irradiation processes. Further, since the mask can be formed after patterning the semiconductor film, the patterned semiconductor film can be used as an alignment pattern for alignment, and a region in which the crystal state is modulated can be accurately defined.

  According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising: a step of removing the mask after irradiating the light; and a gate insulating film on the semiconductor film after removing the mask. And a step of forming a gate electrode overlying the second portion on the gate insulating film.

  According to this manufacturing method, the channel portion of the transistor including the gate electrode includes the second portion that was under the light-transmitting mask. The second portion located under the mask is housed under the channel, and a method for manufacturing a semiconductor device reflecting the change in the bonding (crystal) state of the region located under the mask can be provided.

  In the method for manufacturing a semiconductor device according to the present invention, it is preferable that the gate electrode is formed so as to have a portion that does not overlap the gate electrode in the second portion.

  According to this manufacturing method, the second portion has a portion that does not overlap the gate electrode, and a portion of the second portion is formed so as to protrude from the gate electrode. Therefore, it is possible to provide a manufacturing method for obtaining a transistor governed by the electrical characteristics of the second portion.

  In the method for manufacturing a semiconductor device according to the present invention, the gate electrode is preferably formed so as to have a portion overlapping the gate electrode in the first portion.

  According to this manufacturing method, the first portion has a portion overlapping with the gate electrode, and the first portion is arranged avoiding the gate electrode end where the electric field is concentrated. Therefore, it is possible to provide a manufacturing method for obtaining a transistor having a gate electrode that operates in a state reflecting the electrical characteristics of the first portion located under the gate electrode of the second portion.

  According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising: a step of removing the mask after irradiating the light; and a gate insulating film on the semiconductor film after removing the mask. And forming a first gate electrode overlying the first portion and a second gate electrode overlying the second portion on the gate insulating film, and the first gate. The electrode constitutes a first transistor, the second gate electrode constitutes a second transistor, and the characteristics of the first transistor and the second transistor are different.

  According to this manufacturing method, the first transistor and the second transistor having different characteristics can be formed by using a step of performing uniform light irradiation in the same plane.

  The semiconductor device manufacturing method according to the present invention is the semiconductor device manufacturing method, wherein the semiconductor film formed in the step of forming the semiconductor film is first polysilicon, and the first after the light irradiation. Preferably, one portion is a second polysilicon having a particle size larger than that of the first polysilicon, and the second portion is a microcrystal silicon.

  According to this manufacturing method, since the crystallinity of the semiconductor film can be controlled in a wide range from the microcrystal state to the polycrystalline state having a large grain size, it is possible to provide semiconductor films having more various performances. .

  The semiconductor device manufacturing method according to the present invention is the semiconductor device manufacturing method, wherein the semiconductor film formed in the step of forming the semiconductor film is amorphous silicon, and the first portion after the light irradiation is performed. Is a first polysilicon, and the second portion is preferably a second polysilicon having a particle size larger than that of the first polysilicon.

  According to this manufacturing method, the crystallinity of the first polysilicon and the second polysilicon semiconductor film having different particle diameters can be controlled by performing light irradiation once on the amorphous silicon film. Therefore, semiconductor films having more various performances can be provided.

  In the method for manufacturing a semiconductor device according to the present invention, the mask is preferably formed of any one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and a multilayer film thereof.

  According to this manufacturing method, since the silicon oxide film, the silicon nitride film, and the silicon oxynitride film are stable materials even at high temperatures, energy light can be applied without parasitically affecting the characteristics of the semiconductor film. .

  In the semiconductor device manufacturing method according to the present invention, it is preferable that the semiconductor film is patterned before the mask forming step.

  According to this manufacturing method, since the photolithography process can be performed using the patterned semiconductor film as an alignment mark, the arrangement of the mask can be controlled more accurately.

(First embodiment)
The first embodiment will be described below with reference to the drawings. In the present embodiment, a case where a laser annealing process is performed through a mask and one is subjected to a laser annealing process directly through a mask will be described. Here, FIG. 1A to FIG. 8A are schematic plan views for explaining the first embodiment, and FIG. 1B to FIG. 8B are AA lines in the schematic plan views. It is a schematic cross section.
First, as step 1, a silicon oxide film 12 is formed as a buffer film on a glass substrate 11 as shown in FIG. The silicon oxide film 12 is formed to a thickness of 100 to 500 nm by using, for example, a plasma chemical vapor deposition method (plasma CVD method). As a source gas for forming the silicon oxide film 12 by plasma enhanced chemical vapor deposition, for example, a mixed gas of monosilane and laughter or oxygen, TEOS (tetraethoxysilane, Si (OC ₂ H ₅ ) ₄ ) and A mixed gas with oxygen can be used.

  Here, instead of silicon oxide, silicon nitride may be used as the material of the buffer film. In this case, for example, a mixed gas of silane and ammonia can be used as the source gas. Further, silicon oxynitride may be used as the material of the buffer film. Further, a multilayer structure in which silicon oxide, silicon nitride, or silicon oxynitride is combined may be used. Further, the manufacturing method of the buffer film is not limited to the plasma chemical vapor deposition method, and for example, a thermal chemical vapor deposition method, a vapor deposition method, or a sputtering method may be used. Further, when the glass substrate 11 is made of a material such as fused quartz that has a small amount of impurities that affect the semiconductor element formed on the glass substrate 11, the buffer film forming step can be omitted.

  Next, as step 2, a polysilicon film 13 is formed as a semiconductor film as shown in FIG. In this embodiment, a polysilicon film is used as the semiconductor film, but an amorphous silicon film may be used. When an amorphous silicon film is used, since the crystallinity of the silicon film can be controlled in a wide range from an amorphous state to a polycrystalline state, semiconductor films having more various performances can be provided.

  As a method for forming the polysilicon film 13, a method is used in which the temperature of the glass substrate 11 is heated to about 580 ° C. and the polysilicon film 13 is directly formed on the silicon oxide film 12 by using a vapor phase growth method. In order to use the glass substrate 11 having low heat resistance, the temperature of the glass substrate 11 is suppressed to about 300 ° C. and an amorphous silicon film is once formed on the silicon oxide film 12 by plasma chemical vapor deposition. A method of converting to the polysilicon film 13 by a laser annealing method or a heat treatment method can be used. In particular, when the laser annealing method is used, the temperature applied to the glass substrate 11 can be suppressed to about 300 ° C., and therefore, a low-priced glass substrate 11 with a low softening point can be used. It becomes a membrane method.

  When the temperature of the glass substrate 11 is suppressed to about 580 ° C. as the temperature for directly forming the polysilicon film 13 on the silicon oxide film 12, the polysilicon film 13 has a small particle size. Therefore, there is room for further enlargement of the particle size by further processing by a laser annealing method in a later step, and the state where various thin film transistors can be formed is maintained.

Further, as a source gas for forming the polysilicon film 13 and the amorphous silicon film, disilane or monosilane can be suitably used. Here, in the laser annealing method for modifying amorphous silicon into polysilicon by the laser annealing method, for example, XeCl excimer laser (oscillation wavelength 308 nm) is used as an energy light source and is processed at about 200 to 400 mJ / cm ^2. Turn into.

  When polycrystallized under these conditions, the polysilicon film 13 having an appropriate grain size can be obtained by combining the initial film thickness of the amorphous silicon film and the energy of the excimer laser beam. Therefore, it is possible to further enlarge the particle size by further processing in the later process by laser annealing, and as described later, a combination of a partially formed mask and laser annealing allows partial non-melting part As a seed region for crystallization, a region with better crystallinity can be formed by lateral crystal growth in the adjacent region, and a crystalline state capable of forming a thin film transistor having various electrical characteristics can be formed. Can be created. The polysilicon film 13 is formed to a thickness of about 50 nm to 100 nm, which provides good electrical characteristics when forming a thin film transistor. Note that when the required electrical characteristics are different, the thickness can be changed without being limited to this film thickness.

Further, III-V group compound semiconductors represented by GaAs, AlAs, InSb, GaP, GaN, etc., II-VI group compound semiconductors represented by ZnSe, CdTe, ZnS, etc., IV groups represented by SiGe, SiGeC, etc. A compound semiconductor may be used. In particular, SiGe and SiGeC are preferable because they can be formed by utilizing silicon device technology. When SiGe is formed as the semiconductor film, silane, monosilane, or the like is used as the Si source, germane (GeH ₄ ) is used as the source gas, and the temperature of the glass substrate 11 is heated to about 500 to 600 ° C. Thus, a vapor deposition method can be used. In this case, the polycrystalline SiGe film can be formed by heating the temperature of the glass substrate 11 to about 580 ° C. as in the process of forming the polysilicon film 13.

When a compound semiconductor film is used, a metal organic chemical vapor deposition method (MOCVD method), a molecular beam epitaxial method (MBE method), or the like can be used. For example, in order to form a GaAs film by metal organic chemical vapor deposition, it can be formed using trimethylaluminum and arsine (arsenic hydride, AsH ₃ ).

Next, as step 3, as shown in FIG. 3, the polysilicon film 13 is etched using a normal photolithographic method to form a polysilicon film 13a and a polysilicon film 13b. As a film forming method, for example, a chemical vapor deposition method is used. The silicon oxide film used for the mask 15 can be formed by, for example, a plasma chemical vapor deposition method. As a source gas, for example, a mixed gas of monosilane and laughter or oxygen, TEOS (tetraethoxysilane, Si (OC ₂₎ A mixed gas of H ₅ ) ₄ ) and oxygen can be used. Further, the film forming method is not limited to the chemical vapor deposition method, and for example, a vapor deposition method or a sputtering method may be used.

  Next, as step 4, a mask 15 is formed so as to cover the polysilicon film 13b as shown in FIG. Since the polysilicon film 13a and the polysilicon film 13b have independent rectangular shapes in plan view, the mask 15 can be accurately aligned by using these as an alignment pattern in the photolithography process. .

Here, as a material of the mask 15, for example, a silicon oxide film can be used. The silicon oxide film used for the mask 15 can be formed by, for example, a plasma chemical vapor deposition method. As a source gas, for example, a mixed gas of monosilane and laughter or oxygen, TEOS (tetraethoxysilane, Si (OC ₂₎ A mixed gas of H ₅ ) ₄ ) and oxygen can be used. Further, the film forming method is not limited to the chemical vapor deposition method, and for example, a vapor deposition method or a sputtering method may be used.

  When a silicon oxide film is used for the mask 15, a thickness of, for example, about 200 nm is used. As a basis for selecting about 200 nm as the thickness of the silicon oxide film, FIG. 9 shows the relationship between the energy light intensity (using XeCl excimer laser) at which the polysilicon film starts recrystallization (melting) and the silicon oxide film thickness. As shown in FIG. 9, the amount of energy that causes recrystallization increases with a positive correlation with the thickness of the silicon oxide film formed by the silicon oxide film. That is, as the silicon oxide film is thicker, a mask having a lower light transmittance is formed. That is, a greater change can be generated with or without the silicon oxide film.

Further, FIG. 9 shows that when laser irradiation is performed on the silicon film with energy of about 250 mJ / cm ² to 300 mJ / cm ² , the silicon oxide film is not formed on the portion where the silicon oxide film is formed. This indicates that a portion with better crystallinity can be obtained because it is irradiated with a strong laser beam. Furthermore, in FIG. 9, in a portion where the silicon oxide film is not formed, when the laser beam irradiation is performed with such a high energy that the silicon film becomes microcrystal silicon (for example, 350 mJ / cm ² ), a silicon oxide film is formed. It is also shown that the crystal grain size of the portion of the polysilicon film can be made larger than that of the portion without the silicon oxide film.
On the other hand, the intensity of energy light that causes recrystallization even when the thickness of the silicon oxide film is increased to 500 nm is not significantly different from that when the thickness is 200 nm. The effect of changing the transmission intensity of energy light at about 200 nm is as follows. It is considered saturated. Therefore, by selecting the thickness of the mask 15 using the silicon oxide film to about 200 nm, the transmission intensity of energy light is sufficiently changed, and the mask is formed while suppressing the film formation time and the amount of gas used for film formation. It becomes possible.

  Here, a silicon oxide film is used as the mask 15, but as a material of the mask 15, silicon nitride, silicon oxynitride, and a stacked film thereof may be used instead of silicon oxide. In particular, when silicon nitride is used as the material for the mask 15, silicon nitride is an extremely hard material, and therefore, silicon oxide or silicon oxynitride having a high oxygen ratio is interposed between the polysilicon film 13 and the mask made of silicon nitride. This is preferable because the stress received by the polysilicon film 13 received from silicon nitride can be relaxed.

  Further, after the mask 15 is formed or before the mask 15 is formed, a different mask having a different optical film thickness is formed using a chemical vapor deposition method, a sputtering method, etc. A plurality of masks can be formed, and multilevel films having different characteristics derived from the polysilicon film 13 can be obtained.

  In particular, instead of the polysilicon film 13, a III-V group compound semiconductor represented by GaAs, AlAs, InSb, GaP, GaN or the like, or a II-VI group compound semiconductor represented by ZnSe, CdTe, ZnS or the like is used. In this case, the pattern of the mask 15 is formed by dry etching as the first step. Subsequently, for example, by forming a silicon oxide film of about 4 nm using chemical vapor deposition or the like, it is possible to suppress the volatilization of elements due to the difference in vapor pressure of the elements constituting each compound semiconductor. The metrics can be maintained.

Next, as shown in FIG. 5, as step 5, XeCl excimer laser is irradiated as energy light to modify the polysilicon films 13a and 13b. The energy of the XeCl excimer laser is about 270 mJ / cm ² under the current conditions. In this case, in the region where the polysilicon film 13 is exposed (polysilicon film 13a), the particle size is increased and the region is modified to have high mobility. The region covered with the mask 15 (polysilicon film 13b) is also recrystallized, but leaves more recombination centers and has a smaller grain size than the region where the polysilicon film 13 is exposed. Therefore, the flatness of the polysilicon film 13 is kept high compared to the region where the polysilicon film 13 is exposed.

Next, as shown in FIG. 6, as a step 6, the mask 15 is removed by etching, and then the polysilicon film 13 is patterned, and subsequently, a gate oxide film 16 made of silicon oxide is formed by chemical vapor deposition. To do. The gate oxide film 16 is formed to a thickness of about 50 to 150 nm using, for example, plasma chemical vapor deposition. Examples of the source gas for forming the gate oxide film 16 by plasma enhanced chemical vapor deposition include a mixed gas of monosilane and laughter gas or oxygen, TEOS (tetraethoxysilane, Si (OC ₂ H ₅ ) ₄ ), and the like. A mixed gas with oxygen can be used. In the region where the mask 15 is left, since the grain size of the polysilicon film 13 is kept small, the flatness of the gate oxide film 16 can be kept high.

  Next, as step 7, gate electrodes 17a and 17b are formed as shown in FIG. For the gate electrode 17a and the gate electrode 17b, a metal tantalum film is formed on the entire active surface side of the glass substrate 11 by using, for example, a sputtering method, leaving a portion used as the gate electrode 17a, the gate electrode 17b, or the wiring material. For example, it is formed by removing using a photolithography process. The gate electrode 17a is formed on the portion irradiated with the XeCl excimer laser for modification through the mask 15, and the gate electrode 17b is formed on the portion irradiated with the XeCl excimer laser for direct modification.

Next, in step 8, as shown in FIG. 8, ion implantation is performed using the gate electrode 17a and the gate electrode 17b as a self-alignment mask to form the source / drain regions 18b of the thin film transistors 19a and 19b. As ion implantation conditions, for example, phosphorus is used as an ion species, and a dose amount of about 1 × 10 ^{15 to} 5 × 10 ¹⁵ cm ⁻² can be used.

  As described in Step 6, the thin film transistor 19b has higher flatness of the gate oxide film 16 than the thin film transistor 19a. Therefore, the phenomenon that the electric field in the gate oxide film 16 generated with respect to the voltage applied to the gate electrode 17a is partially concentrated can be prevented, and the breakdown voltage of the gate oxide film 16 can be kept high. Therefore, a highly reliable circuit can be formed by using the thin film transistor 19b where a high voltage is applied, such as a booster circuit. In addition, since the thin film transistor 19a has a large crystal grain size and high mobility, a logic element circuit capable of high-speed calculation can be formed by using, for example, a logic element that requires high speed.

Here, the energy of the XeCl excimer laser is used in Step 5, is raised from 270mJ / cm ² to 350 mJ / cm ^2, the particle size of the polysilicon of the portion covered with the mask 15 is increased, high mobility Have a degree. On the other hand, since the portion of the polysilicon not covered with the mask 15 is once melted, including the seed crystal, the polysilicon having a fine grain size is generated due to sudden and high-density crystal nucleation associated with the supercooled state. (Microcrystal silicon). In this case, the thin film transistor 19b has high mobility and is a transistor suitable for high-speed operation. Further, the thin film transistor is formed using polysilicon having a fine grain size, and 19a has a highly flat gate oxide film 16, so that a transistor suitable for a place where a high voltage is applied, such as a booster circuit, Become. That is, it is possible to realize a state in which the advantages of the thin film transistor 19b and the thin film transistor 19a are interchanged.

(Second Embodiment)
The second embodiment will be described below with reference to the drawings. In this embodiment, a semiconductor film is disposed only in a region where a thin film transistor is formed, a source / drain region is subjected to a laser annealing step through a mask, and a channel region is directly subjected to a laser annealing step. Here, FIGS. 10A to 13A are schematic plan views for explaining the second embodiment, and FIGS. 10B to 13B are schematic views taken along line AA of the schematic plan view. It is sectional drawing.

  First, the process 1a similar to the process 1 of 1st Embodiment is performed.

  Next, as step 2a, a polysilicon island 21 is formed as a semiconductor island having an island shape as shown in FIG. The polysilicon island 21 can be manufactured, for example, by performing the step 2 according to the first embodiment and then etching and removing the polysilicon island 21 by a photolithographic method.

  Further, a solution containing a liquid silicon material typified by cyclopentasilane is placed in a liquid state on the silicon oxide film 12 as a buffer film by an ink jet method, and drying / annealing (laser annealing may be used) is performed. It is also possible to directly form a silicon film in an island shape. In this case, more accurate shape reproducibility can be achieved by introducing a bank structure and controlling the spread of the liquid silicon material using a liquid repellent self-assembled monolayer and / or a lyophilic self-assembled monolayer. It is also possible to form a polysilicon island 21 having

  Further, a contact printing method represented by a contact printing method, a relief printing method, an intaglio printing method, a screen printing method, and a flat plate printing method is used instead of the ink jet method, and a similar process such as annealing is performed later to perform polysilicon island 21. Can be formed.

  Further, here, the polysilicon island 21 using polysilicon is used as the semiconductor material. However, the semiconductor material exemplified in the step 2 according to the first embodiment can be used.

  Next, the same process 3a as the process 3 of 1st Embodiment is performed.

  Next, the same process 4a as the process 4 of 1st Embodiment is performed. Here, as shown in FIG. 11, it is formed so as to cover both ends of the polysilicon island 21. The size of the gap of the mask 22 provided on the polysilicon island 21 occurs when the gate length of the thin film transistor 23 formed in step 8a (see FIG. 13), the pattern of the mask 22, and the gate electrode 27 are formed. A dimension obtained by adding an alignment error is used. For example, when the misalignment is 0.25 μm in both positive and negative directions, the dimension of the mask 22 is designed in consideration of 0.5 μm. Therefore, the gate electrode 27 of the thin film transistor 23 is disposed so as to overlap with the region where the mask 22 is not present. If the alignment error is sufficiently small, the gate length of the thin film transistor 23 may be the dimension of the gap of the mask 22.

Next, the same process 5a as the process 5 of 1st Embodiment is performed. As shown in FIG. 12, XeCl excimer laser is irradiated as energy light to modify the polysilicon island 21. The energy of the XeCl excimer laser is about 270 mJ / cm ² under the current conditions. In the region of the polysilicon island 21a where the polysilicon island 21 is exposed by this irradiation, the particle size is increased and the region is modified to have high mobility. In addition, although the particle size of both the portion covered with the mask 22 and the polysilicon island 21b is large, more recombination centers are left and the particle size is kept small than the region where the polysilicon island 21 is exposed. In addition, the flatness of the polysilicon island 21 is kept high compared to the region where the polysilicon island 21 is exposed.

  Next, steps 6a, 7a, and 8a similar to steps 6, 7, and 8 of the first embodiment are performed to form the thin film transistor 23 shown in FIG. The channel region 24 and the channel adjacent source / drain region 28 of the thin film transistor 23 are subjected to strong XeCl excimer laser annealing to increase the particle size and be modified to have high mobility. For this reason, when used in a logic circuit or the like, a high switching speed is obtained, which is preferable. On the other hand, since most of the source / drain regions 28 have a small particle size and good flatness, when a contact hole is opened in the source / drain region in a later step (not shown), Since the damage of the source / drain region can be reduced, the effect of forming a good electrical connection between the source / drain region and the electrode is obtained.

Further, when the energy of the XeCl excimer laser used in step 5a is increased from 270 mJ / cm ² to 350 mJ / cm ² , the energy is used for the channel region 24 not covered with the mask 22 and the channel adjacent source / drain region 28. All the polysilicon including the seed crystal melts once. After that, when solidifying through a supercooled state, the source / drain portions covered with adjacent masks act as crystal nuclei, so that lateral crystal growth occurs and a silicon film with a large grain size is formed. That is, the channel region has crystal grains larger than those obtained by normal laser irradiation, and a thin film transistor with high mobility and low leakage current between the source and drain can be obtained.

  After laser annealing, the mask is removed and the process of forming the gate insulating film and forming the gate electrode proceeds.However, since the mask pattern is formed based on the silicon pattern, the same silicon pattern is used as a reference. The gate electrode to be patterned can be formed by aligning the pattern with high accuracy. That is, since the gate electrode can be formed in alignment with the silicon region having a large grain size, a high-performance thin film transistor can be formed.

(Third embodiment)
Hereinafter, a third embodiment will be described with reference to the drawings. In the present embodiment, a semiconductor film is disposed only in a region where a thin film transistor is formed, as in the second embodiment, and the central portion of the channel region is subjected to a direct laser annealing process, and the source / drain region and the source / drain region of the channel region are closer to the source / drain. A manufacturing method in which the region is subjected to a laser annealing process through a mask will be described. Here, FIGS. 14A and 15A are schematic plan views for explaining the third embodiment, and FIGS. 14B and 15B are schematic views taken along line AA of the schematic plan view. It is sectional drawing.

  First, steps 1b to 3b similar to the steps 1a to 3a of the second embodiment are performed.

  Next, the same process 4b as the process 4a of 2nd Embodiment is performed. Here, the mask 32 is formed so as to cover both ends of the polysilicon island 31 as shown in FIG. The size of the gap of the mask 32 provided on the polysilicon island 31 is obtained by subtracting the alignment error generated when the gate electrode 37 is formed from the gate length of the thin film transistor 33 formed in step 8b (see FIG. 15). In consideration of the size, it is set as a size smaller than the gate electrode size. Therefore, the gate electrode 37 of the thin film transistor 33 is disposed so as to overlap the region where the mask 32 is present. For example, when the misalignment is 0.25 μm in both positive and negative directions, the dimension of the mask 32 is designed in consideration of 0.5 μm. For example, when the gate electrode width (channel length) is 5 μm and the misalignment is 0.25 μm in both positive and negative directions, the dimension of the gap is set to 3.6 μm, for example. In this case, the dimension of the portion where the gate electrode and the mask finally overlap is in the range of 0.1 μm to 0.6 μm on one side. This dimension is important in this embodiment as will be described later.

  Next, steps 5b to 8b similar to the steps 5a to 8a of the second embodiment are performed to form the thin film transistor 33 shown in FIG. The central portion of the channel region 34 of the thin film transistor 33 is modified so as to have a large particle size and high mobility by XeCl excimer laser annealing. Further, since the particle size is kept small in the channel adjacent source / drain region 38 close to the source / drain region 35 of the channel region 34, the gate insulating film 36 also has high flatness so as to take over the flatness of the channel region 34. .

  That is, the reliability of the gate insulating film 36 can be increased when a voltage is applied between the end of the channel region 34 to which the highest voltage is applied and the gate electrode 37. Further, since the central portion of the channel region 34 has a large particle size and high mobility, the thin film transistor 33 having a good balance with high reliability of the gate insulating film 36 and high operation speed can be obtained.

Further, the energy of the XeCl excimer laser is used to step 5b, is raised from 270mJ / cm ² to 350 mJ / cm ^2, the adjacent channels are covered with the mask 32 source and drain regions 38 and the source and drain regions 35 The grain size of the polysilicon becomes large and has high mobility. On the other hand, the polysilicon in the central portion of the channel region 34 not covered with the mask 32 is once melted once including the seed crystal. After that, when solidifying through a supercooled state, the source / drain portions covered with adjacent masks act as crystal nuclei, so that lateral crystal growth occurs and a silicon film with a large grain size is formed. That is, the channel region has crystal grains larger than those obtained by normal laser irradiation, and a thin film transistor with high mobility and low leakage current between the source and drain can be obtained. Further, as described above, in this embodiment, the crystallinity at the center of the channel is good, and the crystallinity in the region near the source / drain is slightly inferior to that. This region with poor crystallinity is a region where the gate electrode and the mask overlap. When the thin film transistor operates in such a manner that the electric field in the vicinity of the drain is strong and impact ionization occurs, the overlapping region functions as a recombination region of minority carriers generated by impact ionization, and thus has an effect of suppressing the kink effect and the bipolar operation. .

(Fourth embodiment)
Hereinafter, the fourth embodiment will be described with reference to the drawings. In this embodiment, a semiconductor film is disposed only in a region where a thin film transistor is formed as in the second embodiment, and a channel annealing region and a part of the channel side of the source / drain region are subjected to a laser annealing process through a mask. A manufacturing method in which a region of the source / drain region away from the channel is directly subjected to laser annealing will be described. Here, FIGS. 16A and 17A are schematic plan views for explaining the fourth embodiment, and FIGS. 16B and 17B are schematic views taken along line AA of the schematic plan view. It is sectional drawing.

  First, steps 1c to 3c similar to the steps 1a to 3a of the second embodiment are performed.

  Next, the same process 4c as the process 4a of 2nd Embodiment is performed. Here, the mask 42 is formed so as to cover the central portion of the polysilicon island 41 as shown in FIG. The dimension of the mask 42 provided on the polysilicon island 41 is a dimension obtained by adding an alignment error generated when the gate electrode 47 is formed from the gate length of the thin film transistor 43 formed in the step 8c (see FIG. 17). Used. For example, when the misalignment is 0.25 μm in both positive and negative directions, the dimension of the mask 42 is designed in consideration of 0.5 μm. Therefore, the gate electrode 47 (see FIG. 17) of the thin film transistor 43 (see FIG. 17) is disposed so as to overlap with the region where the mask 42 is present. When the alignment error is sufficiently small, the gate length of the thin film transistor 43 (see FIG. 17) may be used as the dimension of the mask 42.

  Next, steps 5c to 8c similar to the steps 5a to 8a of the second embodiment are performed to form the thin film transistor 43 shown in FIG.

  Since the channel region 44 and the channel adjacent source / drain region 48 are subjected to a laser annealing process through the mask 42, the crystal grain size can be kept small. Therefore, a lot of recombination centers remain. Therefore, since the photocarrier generated when irradiated with light is rapidly recombined through the recombination center and generation of photocurrent is suppressed, it is suitable for use in a place where light is irradiated, such as a liquid crystal device. Thus, a thin film transistor 43 can be obtained.

  Further, since parasitic bipolar operation is unlikely to occur for the same reason, kinks in electrical characteristics and abnormal drop in breakdown voltage due to snapback are suppressed. Furthermore, since the resistance value can be lowered because the grain size of polysilicon is increased in the source / drain region 45, ohmic contact can be easily obtained. Further, since the channel region 44 and the channel adjacent source / drain region 48 have a small grain size, the flatness at the upper portion of the polysilicon island 41 can be improved. The gate insulating film 46 formed on the channel region 44 and the channel adjacent source / drain region 48 also has high flatness so as to inherit the flatness of the channel region 44 and channel adjacent source / drain region 48. Therefore, electric field concentration is suppressed, and the reliability of the gate insulating film 46 can be improved when a voltage is applied between the channel adjacent source / drain regions 48 and the gate electrode 47 to which the highest voltage is applied.

Further, the energy of the XeCl excimer laser is used to step 5c, 270mJ / when the cm ² increased to 350 mJ / cm ^2, and has a channel region 44 and the channel adjacent the source and drain regions 48 in polysilicon covered with the mask 42 The particle size of the material becomes large and has a high mobility. For this reason, when used in a logic circuit or the like, a high switching speed is obtained, which is preferable.

(Fifth embodiment)
Hereinafter, a fifth embodiment will be described with reference to the drawings. In the present embodiment, as in the second embodiment, the semiconductor film is disposed only in the region where the thin film transistor is formed. A mask is arranged so that the central portion of the channel region is subjected to a laser annealing process through a mask, and the source / drain regions and the regions near the source / drain of the channel region are directly subjected to a laser annealing process. Here, FIGS. 18A and 19A are schematic plan views for explaining the fifth embodiment, and FIGS. 18B and 19B are schematic views taken along line AA of the schematic plan view. It is sectional drawing.

  First, steps 1d to 3d similar to the steps 1a to 3a of the second embodiment are performed.

  Next, the same process 4d as the process 4a of the second embodiment is performed. Here, the mask 52 is formed so as to cover a part of the channel region 54 (see FIG. 19) of the polysilicon island 51 as shown in FIG. The dimension of the mask 52 provided on the polysilicon island 51 is a dimension obtained by subtracting an alignment error generated when the gate electrode 57 is formed from the gate length of the thin film transistor 53 formed in step 8d (see FIG. 19). Is used. Therefore, the gate electrode 57 of the thin film transistor 53 is disposed so as to cover the region where the mask 52 is present. For example, when the misalignment is 0.25 μm in both positive and negative directions, the dimension of the mask 52 is designed in consideration of 0.5 μm. If the alignment error is sufficiently small, the gate length of the thin film transistor 53 may be the dimension of the mask 52.

  Next, steps 5d to 8d similar to the steps 5a to 8a of the second embodiment are performed to form the thin film transistor 53 shown in FIG. The channel region 54 and the channel adjacent source / drain region 58 of the thin film transistor 53 are modified so as to have a large particle size and high mobility by XeCl excimer laser annealing. In addition, the particle size is kept small at the center of the channel region 54, and a recombination center remains. Therefore, the minority carriers that have been generated or flown into the channel region 54 are quickly recombined and disappear, so that the parasitic bipolar operation that occurs in the presence of the minority carriers is suppressed. Abnormal drop in breakdown voltage is suppressed. Furthermore, since the grain size of the polysilicon is increased in the source / drain region 55, an ohmic contact can be easily obtained.

Further, when the energy of the XeCl excimer laser used in the step 5d is increased from 270 mJ / cm ² to 350 mJ / cm ² , the polysilicon covered region is covered with the mask 52 located in the center of the channel region 54. The particle size increases and has a high mobility. On the other hand, the channel adjacent source / drain regions 58 and the source / drain regions 55 that are not covered with the mask 52 are once melted, including the seed crystal. Thereafter, when solidifying through a supercooled state, the channel region 54 covered with the adjacent mask functions as a crystal nucleus, so that lateral crystal growth occurs and a silicon film with a large grain size is formed. That is, the source / drain region 55 has larger crystal grains than those obtained by normal laser irradiation.
In this case, the resistance value can be lowered because the grain size of the polysilicon is increased in the source / drain region 55, so that an ohmic contact can be easily obtained.

(A) is a schematic plan view for demonstrating 1st Embodiment, (b) is a schematic cross section in the AA line of a schematic plan view. (A) is a schematic plan view for demonstrating 1st Embodiment, (b) is a schematic cross section in the AA line of a schematic plan view. (A) is a schematic plan view for demonstrating 1st Embodiment, (b) is a schematic cross section in the AA line of a schematic plan view. (A) is a schematic plan view for demonstrating 1st Embodiment, (b) is a schematic cross section in the AA line of a schematic plan view. (A) is a schematic plan view for demonstrating 1st Embodiment, (b) is a schematic cross section in the AA line of a schematic plan view. (A) is a schematic plan view for demonstrating 1st Embodiment, (b) is a schematic cross section in the AA line of a schematic plan view. (A) is a schematic plan view for demonstrating 1st Embodiment, (b) is a schematic cross section in the AA line of a schematic plan view. (A) is a schematic plan view for demonstrating 1st Embodiment, (b) is a schematic cross section in the AA line of a schematic plan view. FIG. 3 is a graph showing the relationship between the energy light intensity at which the polysilicon film starts recrystallization (melting) and the silicon oxide film thickness. (A) is a schematic plan view for demonstrating 2nd Embodiment, (b) is a schematic cross section in the AA line of a schematic plan view. (A) is a schematic plan view for demonstrating 2nd Embodiment, (b) is a schematic cross section in the AA line of a schematic plan view. (A) is a schematic plan view for demonstrating 2nd Embodiment, (b) is a schematic cross section in the AA line of a schematic plan view. (A) is a schematic plan view for demonstrating 2nd Embodiment, (b) is a schematic cross section in the AA line of a schematic plan view. (A) is a schematic plan view for demonstrating 3rd Embodiment, (b) is a schematic cross section in the AA line of a schematic plan view. (A) is a schematic plan view for demonstrating 3rd Embodiment, (b) is a schematic cross section in the AA line of a schematic plan view. (A) is a schematic plan view for demonstrating 4th Embodiment, (b) is a schematic cross section in AA of a schematic plan view. (A) is a schematic plan view for demonstrating 4th Embodiment, (b) is a schematic cross section in AA of a schematic plan view. (A) is a schematic plan view for demonstrating 5th Embodiment, (b) is a schematic cross section in AA of a schematic plan view. (A) is a schematic plan view for demonstrating 5th Embodiment, (b) is a schematic cross section in AA of a schematic plan view.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11 ... Glass substrate, 12 ... Silicon oxide film, 13 ... Polysilicon film, 13a ... Polysilicon film, 13b ... Polysilicon film, 15 ... Mask, 16 ... Gate oxide film, 17a ... Gate electrode, 17b ... Gate electrode, 19a Thin film transistor 19b Thin film transistor 21 Polysilicon island 21a Polysilicon island 21b Polysilicon island 22 Mask 23 Thin film transistor 24 Channel region 25 Source / drain region 26 Gate insulating film , 27 ... Gate electrode, 28 ... Source / drain region adjacent to channel, 32 ... Mask, 33 ... Thin film transistor, 34 ... Channel region, 35 ... Source / drain region, 36 ... Gate insulating film, 37 ... Gate electrode, 38 ... Adjacent to channel Source / drain region, 41 ... polysilicon island, 42 ... mass 43 ... Thin film transistor, 44 ... Channel region, 45 ... Source / drain region, 46 ... Gate insulating film, 47 ... Gate electrode, 48 ... Channel adjacent source / drain region, 51 ... Polysilicon island, 52 ... Mask, 53 ... Thin film transistor 54 ... channel region, 55 ... source / drain region, 57 ... gate electrode, 58 ... channel adjacent source / drain region.

Claims (10)

Forming a semiconductor film on the substrate;
Forming a light-transmitting mask on a portion of the semiconductor film;
The semiconductor film is irradiated with light from a side opposite to the substrate to the first part that does not overlap the first part that overlaps the mask, and the bonding state of the substance constituting the first part and the second part And a step of changing a bonding state of substances constituting the semiconductor device. Forming a semiconductor film on the substrate;
Forming a light-transmitting mask on a portion of the semiconductor film;
The semiconductor film is irradiated with light from the opposite side of the substrate to the second part that does not overlap the first part that overlaps the mask, and the crystalline state differs between the first part and the second part. And a method of manufacturing a semiconductor device. In the manufacturing method of the semiconductor device according to claim 1 or 2,
Removing the mask after irradiating the light;
Forming a gate insulating film on the semiconductor film after removing the mask;
Forming a gate electrode on the gate insulating film so as to overlap the second portion. A method for manufacturing a semiconductor device, comprising: In the manufacturing method of the semiconductor device according to claim 3,
The method of manufacturing a semiconductor device, wherein the gate electrode is formed so as to have a portion of the second portion that does not overlap the gate electrode. In the manufacturing method of the semiconductor device according to claim 3,
The method of manufacturing a semiconductor device, wherein the gate electrode is formed so as to have a portion overlapping the gate electrode in the first portion. In the manufacturing method of the semiconductor device according to claim 1 or 2,
Removing the mask after irradiating the light;
Forming a gate insulating film on the semiconductor film after removing the mask;
Forming a first gate electrode overlapping the first portion and a second gate electrode overlapping the second portion on the gate insulating film, wherein the first gate electrode includes the first transistor; A method of manufacturing a semiconductor device, wherein the second gate electrode constitutes a second transistor, and the characteristics of the first transistor and the second transistor are different. In the manufacturing method of the semiconductor device according to claim 1,
The semiconductor film formed in the step of forming the semiconductor film is first polysilicon, and the first portion after the light irradiation is second polysilicon having a particle size larger than that of the first polysilicon. The method for manufacturing a semiconductor device, wherein the second portion is microcrystalline silicon. In the manufacturing method of the semiconductor device according to claim 1,
The semiconductor film formed in the step of forming the semiconductor film is amorphous silicon, the first portion after the light irradiation is the first polysilicon, and the second portion is more than the first polysilicon. A method of manufacturing a semiconductor device, wherein the second polysilicon has a large particle size. In the manufacturing method of the semiconductor device according to claim 1,
A method of manufacturing a semiconductor device, wherein the mask is made of any one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and a multilayer film thereof.   10. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor film is patterned before the mask forming step.

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