JP2010182716A - Thin-film transistor, method of manufacturing the same, and display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a thin-film transistor that decreases an off-state current while keeping a large on-state current, and also has an LDD region easy to manufacture. <P>SOLUTION: In the planar view, a drain electrode 171 is formed with a predetermined distance away from a gate electrode 121, whereby an ohmic contact layer 161 to be used as an LDD region 165 is formed in a horizontal direction. In such a case, the LDD region 165 becomes less influenced by the electric field based on the electric potential of the gate electrode 121, and so, in effect alleviates only electric field concentration by the electric field based on the voltage potential of the drain electrode 171. Accordingly, a TFT 100 forms a channel region 141c composed of a crystalline silicon film, and thus, it can also keep the large on-state current and can sufficiently reduce the off-state current. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a thin film transistor, a manufacturing method thereof, and a display device, and more particularly to a thin film transistor provided with a lightly doped drain region (hereinafter referred to as “LDD region”), a manufacturing method thereof, and a display device.

  In an active matrix liquid crystal display panel, a thin film transistor (hereinafter referred to as “TFT”) is used as a switching element in a pixel formation portion. The TFT of this pixel formation portion writes the voltage according to the data signal to the pixel capacitor when the gate is on, and turns off the gate until the voltage according to the next data signal is written, Hold. For this reason, the TFT needs to reduce the leakage current as much as possible so that the held voltage does not decrease when the gate is turned off. Therefore, an LDD region is provided between the channel region of the TFT and the high concentration drain region, and the leakage current is reduced by relaxing the electric field concentration generated near the end of the drain.

  A semiconductor layer which is an active layer of a TFT is a TFT composed of a polycrystalline silicon layer or a microcrystalline silicon layer (hereinafter, these silicon layers may be collectively referred to as “crystalline silicon layer”). Si_TFT ”and“ μc-Si_TFT ”have higher mobility, higher reliability, and higher light resistance than TFTs made of an amorphous silicon layer (hereinafter referred to as“ a-Si_TFT ”). It has excellent characteristics. In particular, since the mobility of the crystalline silicon layer is larger than that of the amorphous silicon layer, the on-current of the p-Si_TFT and the μc-Si_TFT can be made larger than the on-current of the a-Si_TFT.

  However, the crystalline silicon layer has problems such as a narrower bandgap, a lower resistance value, and more defects in the film than the amorphous silicon layer, which makes it difficult to reduce off-state current. There is.

  FIG. 19 is a graph showing the relationship between the gate voltage Vg and the drain current Id in a conventional N-channel μc-Si_TFT. In a region surrounded by a dotted line in FIG. 19, a negative voltage is applied to the gate electrode in order to turn off the TFT while a positive voltage is applied to the drain electrode. In this case, there is a problem that an electric field based on the potential of the gate electrode and an electric field based on the drain voltage applied to the drain electrode overlap in the vicinity of the end of the drain region, thereby increasing the off-current. In order to reduce the off-current, an LDD region has been provided in the TFT.

  FIG. 20 is a cross-sectional view showing a configuration of a conventional bottom gate TFT 800 provided with an LDD region. As shown in FIG. 20, in the TFT 800, a gate electrode 621 is formed on an insulating substrate 610, and a semiconductor layer 641 serving as an active layer is formed on the gate electrode 621 with a gate insulating film 630 interposed therebetween. The semiconductor layer 641 is located immediately above the gate electrode 621 and is formed of an intrinsic region where impurities are not diffused. The channel region 649 is located on both sides of the channel region 649 so as to diffuse N-type impurities at a low concentration. LDD regions 645 and 646 made of low-concentration impurity regions, and drain regions 647 and sources made of high-concentration impurity regions located outside LDD regions 645 and 646 and diffused so that N-type impurities have a high concentration Region 648 is formed.

  FIG. 21A and FIG. 21B are process cross-sectional views showing a method for manufacturing a conventional TFT 800 having LDD regions 645 and 646 formed by ion implantation. When manufacturing such a TFT 800, first, as shown in FIG. 21A, a resist pattern 710 is formed on a channel region 649, and a dose such that the N-type impurity is reduced in concentration using the resist pattern 710 as a mask. LDD regions 645 and 646 are formed by ion implantation in a quantity. Next, as shown in FIG. 21B, a resist pattern 720 wider than the resist pattern 710 is formed so as to cover a part of the channel region 649 and the LDD regions 645 and 646, and the resist pattern 720 is used as a mask. , N-type impurities are ion-implanted at a dose such that the concentration is high, and a drain region 647 and a source region 648 are formed.

  Patent Document 1 discloses a bottom gate TFT having an LDD region formed without ion implantation. FIG. 22 is a cross-sectional view showing the configuration of the bottom gate TFT 900 disclosed in Patent Document 1. In FIG. Unlike the TFT 800 illustrated in FIG. 20, in the TFT 900, the semiconductor layer 741 includes only an intrinsic region, and low-concentration impurity layers 751 and 752 and high-concentration impurity layers 761 and 762 are provided on the upper surfaces of both ends of the semiconductor layer 741. A drain electrode 771 and a source electrode 772 are formed on the upper surfaces of the high-concentration impurity layers 761 and 762, respectively. In this TFT 900, the low-concentration impurity layer 751 sandwiched between the semiconductor layer 741 and the high-concentration impurity layer 761 functions as an LDD region, and an increase in off current is suppressed.

Japanese Patent Laid-Open No. 7-131030

  However, when the LDD regions 645 and 646 shown in FIG. 20 are formed by ion implantation, as shown in FIG. 21, a resist pattern 710 used when forming a low concentration impurity region and a high concentration impurity region are formed. The resist pattern 720 to be used in the process must be formed. In this case, when the difference between the resist pattern 710 and the resist pattern 720 increases, there is a problem that the LDD region 645 cannot sufficiently relax the electric field based on the drain voltage. In addition, a photolithography process for forming the resist pattern 710 and the resist pattern 720 and a heat treatment process for activating the implanted impurity ions are necessary, and other processes that must be added to the a-Si_TFT manufacturing process. Will increase. For this reason, there is a problem that consistency with the manufacturing process of the a-Si_TFT is lost, and a new capital investment is required.

  Further, the low concentration impurity layer 751 described in Patent Document 1 is sandwiched between the semiconductor layer 741 and the high concentration impurity layer 761. For this reason, in the vicinity of the end of the drain region surrounded by a dotted line shown in FIG. 22, an electric field based on the potential of the gate electrode 621 and an electric field based on the drain voltage applied to the drain electrode 771 are simultaneously received. There is a problem that the off-state current increases and the off-current increases. In the low concentration impurity layer 751 having such an arrangement, the length of the LDD region (hereinafter referred to as “LDD length”) is equal to the length of the low concentration impurity layer 751 in the vertical direction, that is, the film thickness thereof. Therefore, in order to secure the LDD length of 0.1 to 3 μm necessary for relaxing the electric field concentration by the low concentration impurity layer 751, the thickness of the low concentration impurity layer 651 needs to be set to 0.1 to 3 μm. . However, it takes too much time to form or etch a silicon film having a thickness of 0.1 to 3 μm. On the other hand, if the thickness of the silicon film is reduced, a sufficient electric field relaxation effect cannot be obtained. .

  Accordingly, an object of the present invention is to provide a thin film transistor including an LDD region that can be easily manufactured while reducing the off current while maintaining a large on current. Another object of the present invention is to provide a method of manufacturing a thin film transistor having consistency with the manufacturing process of an a-Si_TFT.

A first invention is a bottom gate type thin film transistor formed on an insulating substrate,
A gate electrode formed on the insulating substrate;
A gate insulating film formed on the gate electrode;
A semiconductor layer formed on the gate insulating film and having a channel region facing the gate electrode, and a source region and a drain region formed so as to sandwich the channel region;
A source electrode and a drain electrode formed on the semiconductor layer;
Ohmic contact layers formed between the source electrode and the source region and between the drain electrode and the drain region, respectively.
The semiconductor layer includes one of a microcrystalline semiconductor layer and a polycrystalline semiconductor layer,
The drain electrode overlaps with a part of the ohmic contact layer formed on the drain electrode and is disposed at a predetermined distance from an end of the gate electrode in plan view.

According to a second invention, in the first invention,
The predetermined distance is 0.5 to 3 μm,
The ohmic contact layer is a conductor layer having a sheet resistance of 50 k to 5000 kΩ / □.

According to a third invention, in the first or second invention,
The ohmic contact layer is a semiconductor layer doped with impurities.

According to a fourth invention, in the third invention,
The ohmic contact layer includes a microcrystalline semiconductor layer having a sheet resistance of 50 k to 500 kΩ / □.

A fifth invention is the fourth invention,
The ohmic contact layer further includes an amorphous semiconductor layer.

According to a sixth invention, in the third invention,
The ohmic contact layer includes an amorphous semiconductor layer having a sheet resistance of 500 k to 5000 kΩ / □.

According to a seventh invention, in the first invention,
The semiconductor layer is characterized in that an amorphous semiconductor layer is stacked on an upper surface of the microcrystalline semiconductor layer or the polycrystalline semiconductor layer.

In an eighth aspect based on the first aspect,
A channel stopper layer is formed on the channel region of the semiconductor layer.

  A ninth invention is a display device using the thin film transistor according to any one of the first to eighth inventions as a switching element of a pixel formation portion.

A tenth invention is a method of manufacturing a bottom gate thin film transistor formed on an insulating substrate,
Forming a gate electrode on the insulating substrate; and
Forming a gate insulating film on the gate electrode; and
Forming a semiconductor film having a channel region opposed to the gate electrode and a source region and a drain region formed so as to sandwich the channel region on the gate insulating film;
An impurity film forming step of forming an impurity film doped with impurities on the semiconductor film;
A metal film forming step of forming a metal film on the impurity film;
Using a halftone mask having at least a semi-transmissive portion that transmits light with reduced light intensity and a light-shielding portion that blocks light, the light is left in at least a portion of the metal film corresponding to the channel region. The film thickness of the first resist film is thinner than the film thickness of the second resist film left in the region where the source electrode and the drain electrode are to be formed, and the edge of the second resist film in plan view A first patterning step of forming a first resist pattern in which a portion is arranged at a predetermined distance from an end of the gate electrode;
A selective removal step of removing the first resist film using plasma with oxygen and leaving the second resist film;
An electrode forming step of forming a drain electrode and a source electrode by etching the metal film using the second resist film left in the selective removal step as a mask;
An ohmic contact layer forming step of forming an ohmic contact layer on the upper surface of the source region and the drain region by etching the impurity film either before the selective removing step and after the electrode forming step, It is characterized by providing.

In an eleventh aspect based on the tenth aspect,
The ohmic contact layer forming step includes
A resist film removing step of removing the second resist film left in the selective removing step after forming the drain electrode and the source electrode;
A second patterning step of forming a second resist pattern having an opening at a position corresponding to the gate electrode on the upper surface of the metal film;
And an impurity film etching step of etching the impurity film using the second resist pattern as a mask.

In a twelfth aspect based on the tenth aspect,
The halftone mask has a transmission part in a part of the semi-transmission part,
The first resist pattern has an opening at a position of the first resist film corresponding to the transmission part of the halftone mask,
The ohmic contact layer forming step includes an opening portion etching step which is performed before the selective removal step and sequentially etches the metal film and the impurity film exposed to the opening portion using the first resist pattern as a mask. It is characterized by that.

A thirteenth invention is a method of manufacturing a bottom gate type thin film transistor formed on an insulating substrate,
Forming a gate electrode on the insulating substrate; and
Forming a gate insulating film on the gate electrode; and
Forming a semiconductor film on the gate insulating film; and
An impurity film forming step of forming an impurity film doped with impurities on the semiconductor film;
A metal film forming step of forming a metal film on the impurity film;
Forming a resist pattern having an opening in a region corresponding to the gate electrode on the upper surface of the metal film;
Etching process for etching the metal film and the impurity film using the resist pattern as a mask;
An additional etching step of additionally etching the metal film by wet etching until the end of the metal film is separated from the end of the gate electrode by a predetermined distance in plan view using the resist pattern as a mask. And

In a fourteenth aspect based on the thirteenth aspect,
In the etching process and the additional etching process, wet etching is performed using an etchant containing phosphoric acid, nitric acid, and acetic acid.

In a fifteenth aspect based on the tenth aspect or the thirteenth aspect,
The impurity film forming step is characterized in that the impurity film is formed by plasma CVD using plasma of a gas containing impurities.

In a sixteenth aspect based on the tenth or thirteenth aspect,
The semiconductor film is a microcrystalline semiconductor film;
The semiconductor film forming step includes a microcrystalline semiconductor film forming step of forming the microcrystalline semiconductor film by a plasma CVD method or a high density plasma CVD method.

In a seventeenth aspect based on the tenth or thirteenth aspect,
The semiconductor film is a polycrystalline semiconductor film;
The semiconductor film forming step includes a polycrystalline semiconductor film forming step of generating a polycrystalline semiconductor film from either an amorphous semiconductor film or a microcrystalline semiconductor film by a laser crystallization method.

  According to the first aspect of the invention, since the drain electrode is formed at a predetermined distance from the end of the gate electrode in plan view, the ohmic contact layer that does not overlap the drain electrode, which becomes the LDD region, is formed in the horizontal direction. can do. Such an LDD region is hardly affected by the electric field based on the potential of the gate electrode, and is substantially influenced only by the electric field based on the drain voltage. The current can be reduced. Therefore, the TFT can maintain a large on-current by forming a channel region made of a crystalline silicon film, and at the same time, the off-current can be sufficiently reduced by the LDD region formed in the horizontal direction.

  According to the second invention, the distance from the end of the gate electrode to the drain electrode in plan view, which is the length of the LDD region, is adjusted to 0.5 to 3 μm, and the sheet resistance as the ohmic contact layer is 50 k to 5000 kΩ. If a / □ conductor layer is used, the off-current can be sufficiently reduced.

  According to the third aspect of the invention, the ohmic contact between the semiconductor layer, the drain electrode, and the source electrode can be easily ensured by adjusting the amount of impurities doped in the semiconductor layer.

  According to the fourth invention, the off-current can be sufficiently reduced by using the ohmic contact layer made of the microcrystalline semiconductor layer having a sheet resistance of 50 k to 500 kΩ / □ as the LDD region.

  According to the fifth aspect, since the ohmic contact layer includes not only the microcrystalline semiconductor layer but also the amorphous semiconductor layer, the off-current can be further reduced.

  According to the sixth invention, the off-current can be further reduced by using the ohmic contact layer made of an amorphous semiconductor layer having a sheet resistance of 500 k to 5000 kΩ / □ as the LDD region.

  According to the seventh aspect, by providing the amorphous silicon layer on the upper surface of the crystalline silicon layer, the film thickness at the time of forming the crystalline silicon layer is maintained as it is after the etching. For this reason, it is possible to prevent the on-state current from being reduced by reducing the thickness of the semiconductor layer and increasing the resistance value.

  According to the eighth aspect, by providing the etching stopper film, the film thickness at the time of forming the crystalline silicon layer is maintained as it is without being changed by subsequent processes. Further, the state of the interface between the crystalline silicon layer and the etching stopper film is also maintained as it is. For this reason, the on-current can be prevented from being reduced, and the on-current can be easily controlled.

  According to the ninth aspect, by using the thin film transistor that can sufficiently reduce the off-current as the switching element of the pixel, the voltage corresponding to the data signal given to each pixel formation portion is not lowered, It can be held until the next data signal is applied.

  According to the tenth aspect of the invention, the first resist pattern includes the first resist film having a small thickness and the second resist film having a thickness larger than that of the first resist film. First, etching is performed using the first resist film and the second resist film as a mask. Next, after removing the first resist film using plasma by oxygen gas, etching is performed using the remaining second resist film as a mask. In this case, since the first resist film and the second resist film can be simultaneously formed by using one halftone mask, the number of photomasks can be reduced and the manufacturing cost can be reduced. . In addition, since there are few steps to be added to the manufacturing process of the amorphous thin film transistor, a new capital investment becomes unnecessary by using the amorphous thin film transistor manufacturing line. For this reason, the manufacturing cost of a thin-film transistor can be reduced.

  According to the eleventh aspect, since the second resist pattern is formed after removing the first resist pattern, the number of steps is increased, but the impurity film is etched by a stable manufacturing process to form the ohmic contact layer. Can be formed.

  According to the twelfth aspect, the ohmic contact layer is formed by etching the metal film and the impurity film exposed in the opening formed in the first resist film. Next, after removing the first resist film using plasma by oxygen gas, the metal film is further etched using the remaining second resist film as a mask to form a source electrode and a drain electrode. In this case, the LDD length of the LDD region is determined by the positional relationship between the drain electrode and the ohmic contact layer. However, since the first resist film and the second resist film that form the ohmic contact layer and the drain electrode, respectively, are formed at the same time, the LDD length can be controlled without being affected by the alignment accuracy.

  According to the thirteenth aspect of the invention, not only can the metal film and the high-concentration impurity film be separated using the resist pattern formed in the resist pattern forming step, but also the length of the LDD region can be adjusted. There is no need to add a mask for adjusting the length of the metal layer. Further, since the shift amount of the metal layer can be adjusted by changing the additional etching time, the LDD length of the TFT can be easily adjusted.

  According to the fourteenth aspect, if additional etching is performed using an etchant containing phosphoric acid, nitric acid, and acetic acid, the resist pattern may be peeled off during the additional etching, or the underlying high-concentration impurity film may be etched. Absent.

  According to the fifteenth aspect, since the impurity concentration in the high concentration impurity film can be adjusted by adjusting the gas flow rate during film formation, it is not necessary to perform ion implantation. For this reason, a step of forming a resist pattern serving as a mask for ion implantation, an ion implantation step, and an annealing step for activating doped impurity ions are not required, and an increase in the number of manufacturing steps can be suppressed. By eliminating the need for an ion implantation step that becomes difficult if the substrate is enlarged, a high-concentration impurity film can be easily formed on the enlarged substrate. Further, since a high temperature heat treatment for activating impurities doped by ion implantation is not required, the TFT can be formed by a low temperature process.

  According to the sixteenth aspect, since the microcrystalline semiconductor film can be directly formed on the gate insulating film by the plasma CVD method or the high-density plasma CVD method, the manufacturing process of the thin film transistor having a large on-current can be shortened. Can do.

  According to the seventeenth aspect, since the polycrystalline semiconductor film can be easily formed by irradiating the amorphous semiconductor film or the microcrystalline semiconductor film with the laser, the amorphous thin film transistor manufacturing line is used. This eliminates the need for new capital investment.

(A) is sectional drawing which shows schematic structure of the liquid crystal display device in which the thin-film transistor based on one Embodiment of this invention was formed, (b) is a top view which shows a part of active matrix substrate contained in a liquid crystal display device It is. (A) is a top view which shows the structure of TFT which concerns on one Embodiment of this invention, (b) is sectional drawing which shows the structure of TFT along the AA line shown to (a). 3 is a graph showing a relationship between a gate voltage and a drain current in the N channel type μc-Si_TFT provided with an LDD region shown in FIG. 2. FIG. 6 is a cross-sectional view showing a configuration of a TFT according to a first modification of the TFT shown in FIG. 2. FIG. 6 is a cross-sectional view illustrating a configuration of a TFT according to a second modification of the TFT illustrated in FIG. 2. FIG. 10 is a cross-sectional view showing a configuration of a TFT according to a third modification of the TFT shown in FIG. 2. FIG. 3 is a process cross-sectional view illustrating a manufacturing method of the TFT shown in FIG. 2. FIG. 3 is a process cross-sectional view illustrating a manufacturing method of the TFT shown in FIG. 2. FIG. 3 is a process cross-sectional view illustrating a manufacturing method of the TFT shown in FIG. 2. FIG. 10 is a schematic plan view of a halftone mask used in the manufacturing method shown in FIGS. 7 to 9. It is process sectional drawing which shows the manufacturing method which concerns on the 1st modification of the manufacturing method shown in FIGS. It is process sectional drawing which shows the manufacturing method which concerns on the 1st modification of the manufacturing method shown in FIGS. It is process sectional drawing which shows the manufacturing method which concerns on the 1st modification of the manufacturing method shown in FIGS. It is a typical top view of the halftone mask used for the manufacturing method shown in FIGS. It is process sectional drawing which shows the manufacturing method which concerns on the 2nd modification of the manufacturing method shown in FIGS. It is process sectional drawing which shows the manufacturing method which concerns on the 2nd modification of the manufacturing method shown in FIGS. It is process sectional drawing which shows the manufacturing method which concerns on the 3rd modification of the manufacturing method shown in FIGS. It is process sectional drawing which shows the manufacturing method which concerns on the 3rd modification of the manufacturing method shown in FIGS. It is a graph which shows the relationship between the gate voltage and drain current in the conventional N channel type | mold micro-c_Si_TFT. It is sectional drawing which shows the structure of the conventional bottom gate type TFT provided with the LDD area | region. FIG. 20 is a process cross-sectional view illustrating the manufacturing method of the conventional TFT shown in FIG. 19. It is sectional drawing which shows the structure of the other conventional bottom gate type TFT.

<1. Configuration of liquid crystal display device>
FIG. 1A is a cross-sectional view showing a schematic configuration of a liquid crystal display device 10 in which a bottom-gate TFT according to an embodiment of the present invention is formed, and FIG. 1B is included in the liquid crystal display device 10. 2 is a plan view showing a part of an active matrix substrate 11. FIG. A liquid crystal display device 10 shown in FIG. 1A is arranged with an active matrix substrate 11 on which data signal lines 13, pixel electrodes 15, and the like are formed, and opposed to the active matrix substrate 11, and a color filter 23 and a black matrix 24. And the counter substrate 21 on which the common electrode 25 and the like are formed, and the liquid crystal layer 30 sandwiched between the active matrix substrate 11 and the counter substrate 21.

  A data signal line 13 and a scanning signal line 14 are formed on the active matrix substrate 11 shown in FIG. The data signal line 13 and the scanning signal line 14 are arranged so as to cross each other, and a TFT and a pixel electrode 15 functioning as a switching element are provided at each intersection where they cross each other. A TFT gate electrode 121 is connected to the scanning signal line 14, and a TFT source electrode 172 is connected to the data signal line 13. The pixel electrode 15 is connected to the drain electrode 171 of the TFT through the contact hole 16. When the TFT is turned on, a voltage corresponding to the data signal is applied from the data signal line 13 to the pixel capacitor constituted by the pixel electrode 15 and the common electrode 25 via the TFT. The voltage applied to the pixel capacitor is held in the pixel capacitor while the TFT is in the off state.

<2. Configuration of TFT>
<2.1 Embodiment of TFT Configuration>
2A is a plan view showing the configuration of the bottom gate type TFT 100 according to the embodiment of the present invention, and FIG. 2B is the configuration of the TFT 100 along the line AA shown in FIG. FIG.

  As shown in FIGS. 2A and 2B, the TFT 100 is a bottom gate type, a gate electrode 121 is provided on the insulating substrate 110, and a gate insulating film 130 is formed so as to cover the gate electrode 121. Has been. On the upper surface of the gate insulating film 130, a semiconductor layer 141 made of a microcrystalline silicon film or a polycrystalline silicon film containing no impurities is stacked.

  On the upper surface of the left end portion of the semiconductor layer 141, an ohmic contact layer 162 made of a microcrystalline silicon film having the same size as the left end portion of the semiconductor layer 141 and containing a high concentration N-type impurity overlaps the left end portion. It is formed as follows. A source electrode 172 that partially overlaps the ohmic contact layer 162 and extends to the left is formed on the upper surface of the ohmic contact layer 162.

  Further, on the upper surface of the right end portion of the semiconductor layer 141, an ohmic contact layer 161 having the same size as the right end portion of the semiconductor layer 141 and made of a microcrystalline silicon film containing a high concentration N-type impurity is provided on the right end portion. It is formed to overlap. A drain electrode 171 that partially overlaps the ohmic contact layer 161 and extends to the right is formed on the upper surface of the ohmic contact layer 161. The source electrode 172 and the drain electrode 171 are formed of a metal film. A protective film (passivation film) 180 is formed so as to cover the entire TFT 100.

  Note that the ohmic contact layers 161 and 162 may be formed of an amorphous silicon film containing a high concentration N-type impurity instead of a microcrystalline silicon film containing a high concentration N-type impurity. In this manner, when the ohmic contact layers 161 and 162 are formed of a semiconductor layer, the resistance value can be adjusted by adjusting the amount of impurities to be doped. Therefore, the ohmic contact between the semiconductor layer 141, the drain electrode 171 and the source electrode 172 is achieved. Can be easily formed. The ohmic contact layers 161 and 162 may be formed of a conductor layer such as a metal that does not form a Schottky junction with the semiconductor layer 141.

  Of the semiconductor layer 141, a region not covered by the ohmic contact layers 161 and 162 functions as a channel region 141c, and left and right regions of the channel region 141c function as a source region 141s and a drain region 141d, respectively. The ohmic contact layers 161 and 162 serve to make ohmic contact between the drain electrode 171 and the drain region 141d and between the source electrode 172 and the source region 141s, respectively.

When a positive voltage is applied to the gate electrode 121 of the N-channel TFT 100, the surface of the channel region 141c on the gate electrode 121 side becomes an N ⁺ layer in which a large number of electrons are induced. Therefore, the N-type source electrode 172 and drain electrode 171 are electrically connected by the N ⁺ layer of the channel region 141c, and the TFT 100 is turned on. On the other hand, when a negative voltage is applied to the gate electrode 121, holes are induced on the surface of the channel region 141c to become P-type. Therefore, the N-type source electrode 172 and the drain electrode 171 are separated by the P-type channel region 141c, and the TFT 100 is turned off.

  In such a TFT 100, as shown in FIGS. 2A and 2B, a predetermined distance is provided so that the right end of the gate electrode 121 and the left end of the drain electrode 171 do not overlap in plan view. Are only spaced apart. Therefore, a portion of the ohmic contact layer 161 where the gate electrode 121 and the drain electrode 171 do not overlap in plan view functions as the LDD region 165. In this case, since the LDD region 165 is formed in the horizontal direction, the range that can be used for adjusting the length (LDD length) of the LDD region 165 is widened, and the resistance value of the LDD region 165 can be easily adjusted. . Similarly, the left end portion of the gate electrode 121 and the right end portion of the source electrode 172 are arranged at a predetermined distance so as not to overlap each other.

  Since the LDD region 165 formed in the horizontal direction is hardly affected by the electric field based on the potential of the gate electrode 121, it is only necessary to substantially reduce the electric field concentration due to the electric field based on the drain voltage applied to the drain electrode 171. Such an LDD region 165 can reduce off-current by reducing electric field concentration by adjusting the LDD length and the resistance value of the ohmic contact layer 161. In addition, by adjusting the resistance value by changing the crystallinity of the ohmic contact layer 161, the electric field concentration may be reduced and the off-current may be reduced.

  When the resistance value of the ohmic contact layer 161 is too low, or when the LDD length is too short, electric field relaxation by the LDD region 165 becomes insufficient, and thus there arises a problem that the off current cannot be sufficiently reduced. On the other hand, when the resistance value of the ohmic contact layer 161 is too high, or when the LDD length is too long, the parasitic resistance value of the LDD region 165 increases, which causes a problem that the on-current decreases.

  Therefore, the LDD length is set in the range of 0.5 to 3 μm so that such a problem does not occur. Further, when a microcrystalline silicon film is used as the ohmic contact layer 161, the sheet resistance is set in a range of 50 k to 500 kΩ / □. Further, when an amorphous silicon film is used, the sheet resistance is set in a range of 500 k to 5000 kΩ / □. The sheet resistance is adjusted by changing the amount of impurities to be doped.

  Note that no electric field concentration occurs on the source electrode 172 side because it is not affected by the drain voltage applied to the drain electrode 171. Therefore, it is not necessary to alleviate electric field concentration by the LDD region. Therefore, the LDD length on the source electrode 172 side and the sheet resistance of the ohmic contact layer 162 may be different from the above values.

  FIG. 3 is a graph showing the relationship between the gate voltage Vg and the drain current Id in the N-channel type μc-Si_TFT 100 provided with such an LDD region 165. This graph shows data measured for the TFT 100 in which the sheet resistance of the ohmic contact layers 161 and 162 is 200 kΩ / □ and the LDD length is 2 μm. For comparison, FIG. 3 also shows the relationship between the gate voltage Vg and the drain current Id of a conventional TFT 800 having an LDD region formed by ion implantation.

  As can be seen from FIG. 3, when the TFT 100 is in an on state, that is, when a positive voltage is applied to the gate electrode 121, the drain current Id of the TFT 100, that is, the on current is the case of the conventional TFT 800 with respect to the gate voltage Vg. Changes as well.

  However, when the TFT 100 is in an off state, that is, when a negative voltage is applied to the gate electrode 121, even if the gate voltage Vg increases on the negative voltage side, it is not easily affected by the electric field based on the potential of the gate electrode 121. The increase in off current is moderate. On the other hand, in the conventional TFT 800, as the gate voltage Vg increases on the negative voltage side, the influence of the electric field based on the potential of the gate electrode 121 becomes stronger, so the drain current Id, that is, the off-current also increases rapidly. Thus, it can be seen that by providing the LDD region 165 in which the resistance value and the LDD length of the ohmic contact layer 161 are adjusted, the off current can be reduced while maintaining a large on current.

<2.2 Effect>
As described above, in the TFT 100 of the present embodiment, the drain electrode 171 is formed at a predetermined distance from the gate electrode 121 in plan view. Therefore, the ohmic contact layer 161 formed in the horizontal direction in plan view. A region that does not overlap with either the gate electrode 121 or the drain electrode 171 becomes an LDD region 165. The LDD region 165 is less susceptible to the influence of the electric field based on the potential of the gate electrode 121, and therefore, it is only necessary to alleviate electric field concentration due to the electric field based on the drain voltage applied to the drain electrode 171. Therefore, the TFT 100 can maintain a large on-current with a channel region made of a crystalline silicon film with high mobility, and at the same time sufficiently reduce the off-current with the LDD region 165 formed in the horizontal direction.

Further, the TFT 100 capable of sufficiently reducing the off-current can be formed only by adjusting the resistance value and the LDD length of the ohmic contact layer 161. The resistance value of the ohmic contact layer 161 can be freely selected in the range of 50 k to 5000 kΩ / □ by changing at least one of crystallinity and impurity concentration. The LDD length can be freely selected in the range of 0.5 to 3 μm.
<2.3 First Modification of TFT Configuration>
FIG. 4 is a cross-sectional view showing a configuration of a TFT 300 according to a first modification of the embodiment of the present invention. In the TFT 300 shown in FIG. 4, the same or corresponding components as those of the TFT 100 according to the above-described embodiment are denoted by the same reference numerals, and differences from the TFT 100 will be mainly described.

  As shown in FIG. 4, in the TFT 300, unlike the TFT 100 shown in FIG. 2, the ohmic contact layers 161, 162 are disposed between the semiconductor layer 141 made of crystalline silicon and the ohmic contact layers 161, 162 made of microcrystalline silicon. The amorphous silicon layers 151 and 152 having the same size as those of the ohmic contact layers 161 and 162 are arranged so as to overlap with each other in a plan view. In this manner, by adding the amorphous silicon layers 151 and 152 to the ohmic contact layers 161 and 162, the resistance value of the ohmic contact layers 161 and 162 can be increased, so that the off-current can be further reduced. it can.

<2.4 Second Modification of TFT Configuration>
FIG. 5 is a cross-sectional view showing a configuration of a TFT 400 according to a second modification of the embodiment of the present invention. In the TFT 400 illustrated in FIG. 5, the same or corresponding components as those of the TFT 100 according to the embodiment are denoted by the same reference numerals, and the difference from the TFT 100 will be mainly described.

  As shown in FIG. 5, in the TFT 400, the semiconductor layer 141 includes a crystalline silicon layer 143 and an amorphous silicon layer 145 formed on the upper surface thereof. The amorphous silicon layer 145 is thick on the source region 141s and the drain region 141d and thin on the channel region 141c. This is because when the high concentration impurity film on the channel region 141c is etched, a part of the amorphous silicon layer 145 is removed by overetching.

  If the amorphous silicon layer 145 is formed on the upper surface of the crystalline silicon layer 143 as in the TFT 400, the high-concentration impurity film is etched to form an ohmic contact as in the TFTs 100 and 300 shown in FIGS. When the layers 161 and 162 are formed, a part of the amorphous silicon layer 145 is removed by overetching, and the crystalline silicon layer 143 is not removed. By providing the amorphous silicon layer 145 on the upper surface of the crystalline silicon layer 143 in this manner, the film thickness at the time of forming the crystalline silicon layer 143 is maintained as it is after the etching. It can be prevented that the resistance value increases and the on-current decreases.

<2.5 Third Modification of TFT Configuration>
FIG. 6 is a cross-sectional view showing a configuration of a TFT 500 having an etching stopper layer 155. As shown in FIG. In the TFT 500 illustrated in FIG. 6, the same or corresponding components as those of the TFT 100 according to the embodiment are denoted by the same reference numerals, and differences from the TFT 100 will be mainly described.

  In the TFTs 100 and 300 shown in FIGS. 2 and 4, respectively, the channel region 141c of the semiconductor layer 141 is not protected by the etching stopper layer. Therefore, when the ohmic contact layers 161 and 162 are formed by etching the high concentration impurity film, a part of the semiconductor layer 141 in the channel region 141c is removed by overetching. It is difficult to control the thickness of the semiconductor layer 141 to be removed, and when the thickness of the semiconductor layer 141 in the channel region 141c is reduced, there arises a problem that the resistance value is increased and the on-current is reduced.

  Therefore, if the etching stopper layer 155 is formed on the upper surface of the semiconductor layer 141 so as to cover the channel region 141c, the semiconductor layer 141 in the channel region 141c is over-etched when the high concentration impurity film is removed. There is no. As the etching stopper layer 155, for example, a SiNx film (silicon nitride) having a high etching selectivity with respect to the silicon film is used. In this manner, by providing the etching stopper layer 155, the film thickness when the semiconductor layer 141 is formed is maintained as it is after the etching. For this reason, it becomes easy to control the on-current.

<3 TFT manufacturing method>
<One Embodiment of Manufacturing Method of TFT>
7 to 9 are process cross-sectional views illustrating the manufacturing method of the TFT 100 according to the embodiment. First, as shown in FIG. 7A, a laminated film made of Ti (titanium) / Al (aluminum) / Ti is sputtered on the surface of an insulating substrate 110 made of a transparent insulator such as glass, quartz, or plastic. The film is formed by the method. Next, a resist is applied onto the laminated film, and exposure and development are performed to form a resist pattern (not shown) that serves as a mask when the gate electrode 121 is etched. Using the formed resist pattern as a mask, dry etching is performed in the order of Ti, Al, and Ti, and then the resist pattern is peeled off. As a result, the gate electrode 121 is formed on the substrate 110.

Next, a gate insulating film 130 made of a SiNx film having a film thickness of, for example, about 410 nm is formed so as to cover the gate electrode 121. The SiNx film is formed by a plasma CVD method (Chemical Vapor Deposition) using a mixed gas of SiH ₄ (monosilane), NH ₃ (ammonia) and N ₂ (nitrogen).

A semiconductor film 140 made of a microcrystalline silicon film is formed on the surface of the gate insulating film 130. This semiconductor film 140 is formed using a parallel plate type plasma CVD apparatus so that, for example, the pressure in the chamber is 3 Torr, the flow rate ratio of SiH ₄ and H ₂ is 1: 300, and the RF power is 3 kW / m ^2. The film is formed under the conditions. In place of the CVD method using a parallel plate type plasma apparatus, a high density plasma CVD method (ICP (Inductively coupled Plasma) method, an ECR (Electron Cyclotron Resonance) method, a surface wave plasma CVD method, a helicon wave plasma CVD method). The semiconductor film 140 made of a microcrystalline silicon film may be formed. For example, when the film is formed by the ICP method, the semiconductor film 140 is formed under such conditions that the pressure in the chamber is 10 mTorr, the flow ratio of SiH ₄ and H ₂ is 1: 1, and the RF power is 20 kW / m ^2. Is done.

Further, as the semiconductor film 140, a polycrystalline silicon film may be formed instead of the microcrystalline silicon film. The semiconductor film 140 made of a polycrystalline silicon film is formed by crystallizing an amorphous silicon film. The amorphous silicon film is formed using a parallel plate type plasma apparatus, for example, such that the pressure in the chamber is 1 Torr, the flow rate ratio of SiH ₄ and H ₂ is 1: 1, and the RF power is 1 kW / m ^2. The film is formed under the conditions. The amorphous silicon film thus formed is crystallized by irradiating it with an excimer laser such as XeCl. For example, about 1mm beam width of the laser beam to be irradiated to the amorphous silicon, if the irradiation energy was 250 mJ / cm ^2, the size is polycrystalline silicon film of 0.1 to 0.3 [mu] m. In addition, crystallization is performed by irradiating with another solid-state laser (for example, a second harmonic laser beam emitted by making a YAG laser beam incident on an SHG (Second Harmonic Generation) active substance) instead of an excimer laser. You may let them. In addition, the laser beam irradiated to the amorphous silicon film has a beam width of about 10 μm, the irradiation energy is set to 350 mJ / cm ^2, and the temperature difference generated by moving the solid-liquid interface of the amorphous silicon film in the lateral direction is used. Then, the polycrystalline silicon film may be grown laterally along the film surface (lateral growth). In this case, since the thermal conductivity is high on the gate electrode 121, the polycrystalline silicon film is easily grown on the gate electrode 121.

  The semiconductor film 140 made of a polycrystalline silicon film may be formed by crystallizing a microcrystalline silicon film formed by the above method instead of crystallizing an amorphous silicon film. . Since the crystal grain size of silicon in the polycrystalline silicon film thus formed becomes larger, when used as the semiconductor film 140, the on-current of the TFT 100 can be further increased. Alternatively, the amorphous silicon film or the microcrystalline silicon film may be crystallized by solid phase growth by heating with a heating method other than laser. Examples of such a heating method include an RTA (Rapid Thermal Annealing) method, a flash lamp annealing method, and a heating method using a firing furnace.

  Further, a microcrystalline semiconductor film is formed over the gate insulating film 130 by a plasma CVD method or a high-density plasma CVD method, and the formed microcrystalline semiconductor film is used as the semiconductor film 140 without being crystallized. You can also In this case, a process necessary for crystallization is not necessary, and thus the manufacturing process of the TFT 100 can be shortened.

After the semiconductor film 140 is stacked, a high concentration impurity film 160 made of a microcrystalline silicon film doped with, for example, P (phosphorus) at a high concentration as an N-type impurity is stacked by plasma CVD. Specifically, a mixed gas of SiH ₄ (monosilane), H ₂ (hydrogen) and PH ₃ (phosphine) is supplied to the parallel plate type plasma apparatus, and the gas flow rate of PH ₃ with respect to SiH ₄ is 0.01-2. %, A microcrystalline silicon film having a sheet resistance of 50 k to 500 kΩ / □ is formed.

Note that an amorphous silicon film may be stacked as the high concentration impurity film 160 instead of the microcrystalline silicon film. In this case, an amorphous silicon film having a sheet resistance of 500 k to 5000 kΩ / □ is formed by adjusting the gas flow rates of PH ₃ and SiH ₄ .

  As shown in FIG. 7B, a metal film 170 made of, for example, Mo (molybdenum) or the like is formed on the upper surface of the high concentration impurity film 160 by sputtering. Next, as shown in FIG. 7C, a resist film 210 is formed on the upper surface of the metal film 170 and exposed using a halftone mask 190 (hereinafter referred to as “halftone exposure”).

  In this specification, a plurality of slits are provided at positions on the mask corresponding to the intermediately exposed region, and a mask (also referred to as a gray-tone mask) that reduces the light intensity according to the width of the slit and a semi-transmissive film are covered. The masks that weaken the light intensity by the semi-transmissive portion are collectively referred to as a halftone mask. FIG. 10 is a schematic plan view of a halftone mask used in the manufacturing method according to this embodiment. A halftone mask 190 shown in FIG. 10 includes a light shielding portion 191 that shields light, a transmission portion 193 that transmits light, and a semi-transmission portion 192 that weakens light intensity by a plurality of slits 194.

  As shown in FIG. 7C, the semi-transmissive portion 192 of the halftone mask 190 is aligned with the position where the channel region 141c is to be formed, and the light shielding portion 191 is aligned with the position where the drain electrode and the source electrode are to be formed. And expose. As a result, the resist film 210 in the region to be the channel region 141c is exposed by light having a lower intensity than the light transmitted through the transmission portion 193, and the resist film 210 in the region where the drain electrode and the source electrode are to be formed is not exposed. .

  When development is performed after halftone exposure, a part of the resist film 210 is dissolved in the developer at a position where the channel region 141c corresponding to the semi-transmissive portion 192 of the halftone mask 190 is to be formed, as shown in FIG. Thus, the film thickness of the resist pattern 220 becomes thin. Since the resist film 210 is not dissolved in the developer at the position where the drain electrode and the source electrode corresponding to the light shielding portion 191 are to be formed, the film thickness of the resist pattern 220 remains thick. On the other hand, the resist film 210 is removed at the portion corresponding to the transmission part 193 of the halftone mask 190, and the surface of the metal film 170 is exposed. Using the resist pattern 220 as a mask, the metal film 170 whose surface is exposed, the high-concentration impurity film 160 thereunder, and the semiconductor film 140 are successively etched by dry etching.

Subsequently, as shown in FIG. 8E, a high frequency power is applied to O ₂ (oxygen) gas in order to remove only the region of the resist pattern 220 exposed by the light transmitted through the semi-transmissive portion 192. Ashing (hereinafter referred to as “half ashing”) is performed in which the generated plasma is generated and the resist film is ashed and removed by the plasma. In the region where the channel region is to be formed by half ashing, the thin portion of the resist pattern 220 is completely removed, and the surface of the metal film 170 is exposed. At this time, although the film thickness of the resist pattern 220 corresponding to the light shielding portion 191 of the halftone mask is slightly reduced, the resist pattern 230 having a sufficient film thickness is left as a mask when the metal film 170 is etched.

  As shown in FIG. 8F, the metal film 170 is dry-etched using the resist pattern 230 left after half ashing as a mask to form a drain electrode 171 and a source electrode 172. Thereafter, the resist pattern 230 is peeled off. Next, as shown in FIG. 9G, a resist is applied, and exposure and development are performed to form a resist pattern 240 having an opening on a region to be the channel region 141c.

  As shown in FIG. 9H, the high-concentration impurity film 160 exposed in the opening is dry-etched using the resist pattern 240 as a mask to form a gap etch portion 243. The high-concentration impurity film 160 on the channel region 141c is removed and separated into two high-concentration impurity layers by the gap etch portion 243 formed in this way, and become ohmic contact layers 161 and 162, respectively. Thereafter, the resist pattern 240 is peeled off. Note that the semiconductor layer 141 therebelow is also etched to some extent by over-etching when the high-concentration impurity film 160 is removed.

  As shown in FIG. 9I, a protective film 180 made of SiNx is formed so as to cover the entire TFT 100 by plasma CVD. Thereafter, a contact hole (16 in FIG. 1B) reaching the surface of the drain electrode 171 is opened in the protective film 180. A transparent metal film such as ITO (Indium Tin Oxide) is formed on the protective film 180 by sputtering, and the transparent metal film is patterned to form a pixel electrode (15 in FIG. 1B). . As a result, the pixel electrode 15 connected to the drain electrode 171 through the contact hole 16 is formed.

<3.2 Effects>
As described above, according to the manufacturing method of the present embodiment, the resist pattern for removing the metal film 170 on the channel region 141c and the resist pattern for patterning the drain electrode 171 and the source electrode 172 are each obtained. Instead of using a different photomask, it is only necessary to form the resist pattern 220 using the halftone mask 190, so that the LDD region 165 can be formed without increasing the number of photomasks.

  Further, since the impurity concentration in the high concentration impurity film 160 is adjusted by adjusting the gas flow rate during film formation, it is not necessary to perform ion implantation. For this reason, a step of forming a resist pattern that becomes a mask at the time of ion implantation, an ion implantation step, and an annealing step for activating doped impurity ions become unnecessary, and an increase in the number of manufacturing steps can be suppressed. In addition, since an ion implantation step that becomes difficult when the insulating substrate 110 is enlarged is not necessary, the high-concentration impurity film 160 can be easily formed on the enlarged insulating substrate 110. Further, since heat treatment (about 600 ° C.) for activating the impurities doped by ion implantation is not required, the TFT 100 can be formed by a low temperature process (about 350 ° C. or less).

  Furthermore, since there are few steps to be added to the a-Si_TFT manufacturing process, it is not necessary to provide a new manufacturing line by using the a-Si_TFT manufacturing line. For this reason, the manufacturing cost of TFT100 can be reduced.

<3.3 First Modified Example of TFT Manufacturing Method>
11 to 13 are process cross-sectional views illustrating a manufacturing method according to the first modification of the TFT 100 of the above-described embodiment. 11 to 13, the same or corresponding manufacturing steps as those shown in FIGS. 7 to 9 are denoted by the same reference numerals, and the manufacturing steps shown in FIGS. The difference will be mainly described.

  The manufacturing process until the high-concentration impurity film 160 shown in FIG. 11A is formed is the same as the manufacturing process shown in FIG. Next, as shown in FIG. 11B, a resist is applied on the high-concentration impurity film 160, and a resist pattern (not shown) is formed by performing exposure and development. Using the formed resist pattern as a mask, dry etching is performed in the order of the high-concentration impurity film 160, the semiconductor film 140, and the gate insulating film 130, and then the resist pattern is peeled off. As a result, a stacked film in which the gate insulating film 130, the semiconductor layer 141, and the high-concentration impurity film 160 are stacked in a region where the TFT is to be formed is formed.

  As shown in FIG. 11C, a metal film 170 made of, for example, Mo (molybdenum) or the like is formed on the upper surface of the high concentration impurity film 160 by sputtering. Next, as shown in FIG. 12D, a resist film 210 is formed on the upper surface of the metal film 170, and halftone exposure is performed using a halftone mask 290.

  FIG. 14 is a schematic plan view of a halftone mask 290 used for this halftone exposure. In the halftone mask 290 shown in FIG. 14, a light shielding portion 291 that shields light, a transmission portion 293 that transmits light, and a semi-transmission portion 292 that weakens light intensity by a plurality of slits are formed.

  As shown in FIG. 12D, the translucent portion 292 and the translucent portion 292 sandwiched by the transflective portion 292 of the halftone mask 290 are aligned with the position where the channel region 141c is to be formed, and the drain electrode and the source electrode are aligned. The light shielding portion 291 is positioned at the position to be formed and exposed. In this case, of the resist film 210 on the channel region 141c, the resist film corresponding to the transmissive part 293 is exposed with high intensity light, and the resist film corresponding to the semi-transmissive part 292 is exposed with light with reduced intensity. The resist film in the region where the drain electrode 171 and the source electrode 172 are to be formed is not exposed.

  When development is performed after half-tone exposure, the resist film 210 exposed to a high intensity light in the resist film 210 at a position to become the channel region 141c is dissolved in the developer and exposed to light with a reduced intensity. Since a part of the resist film is dissolved in the developer, the formed resist pattern 280 has a shape as shown in FIG. Specifically, the resist pattern 280 includes a thin resist film having an opening at a position where the channel region 141c is to be formed, and a thick resist film at a position where the drain electrode 171 and the source electrode 172 are to be formed. It becomes the pattern which has. The resist film 210 is removed at a portion corresponding to the transmission part 293 of the halftone mask 290, and the surface of the metal film 170 is exposed. Next, as shown in FIG. 12F, by using the resist pattern 280 as a mask, the metal film 170 whose surface is exposed and the high-concentration impurity film 160 therebelow are continuously etched by dry etching. A gap etch portion 283 is formed. The high-concentration impurity film 160 is separated into right and left by the gap etch portion 283 formed in this way, and ohmic contact layers 161 and 162 are formed. Note that the surface of the semiconductor layer 141 is also etched to some extent by overetching during dry etching.

  Subsequently, as shown in FIG. 13G, half ashing is performed in order to remove the portions of the resist pattern 280 located on the left and right sides of the gap etch portion 283 that have been exposed to light whose intensity has been reduced. In the region where the channel region 141c is to be formed by half ashing, the thin portion of the resist pattern 220 is completely removed, and the surface of the metal film 170 is exposed. At this time, although the film thickness of the resist pattern 220 corresponding to the light-shielding portion 291 of the halftone mask is slightly reduced, the resist pattern 285 having a sufficient film thickness as a mask for etching the metal film 170 remains.

  As shown in FIG. 13H, the metal film 170 is dry-etched using the resist pattern 285 remaining after the half ashing as a mask to form a drain electrode 171 and a source electrode 172. Thereafter, the resist pattern 285 is peeled off. Next, as shown in FIG. 13I, a protective film 180 made of SiNx is formed so as to cover the entire TFT 100 by plasma CVD. Subsequent manufacturing steps for opening a contact hole and forming a pixel electrode are the same as those in the above-described embodiment, and a description thereof will be omitted.

  Next, the effect of the manufacturing method according to this modification will be described in comparison with the manufacturing method according to the embodiment shown in FIGS. In the manufacturing method shown in FIG. 7 to FIG. 9, as shown in FIG. 8D, the resist pattern 220 is formed by halftone exposure, and the resist pattern 230 obtained by half-etching the resist pattern 220 is etched as a mask. A drain electrode 171 and a source electrode 172 are formed. Further, as shown in FIG. 9G, a resist pattern 240 is newly formed, and a gap etch portion 243 is formed by etching using the resist pattern 240 as a mask. In this case, the photomasks for forming the resist patterns 220 and 240 are aligned with the marks formed simultaneously on the insulating substrate 110 when the gate electrode 121 is formed. However, even if the alignment is performed using the same mark, there is a possibility that the deviation between the resist pattern 220 and the resist pattern 240 may be about ± 1 μm due to the mechanical accuracy and image reading accuracy of the alignment apparatus. In this case, the LDD length of the LDD region 165 is also increased or decreased by about 1 μm. On the other hand, the LDD length of the LDD region 165 formed by the present invention is about 0.5 to 3 μm, and a deviation of about ± 1 μm has a non-negligible effect.

  Therefore, in the manufacturing method according to the present modification, as shown in FIG. 12E, a resist pattern 280 is formed by halftone exposure, and a gap etch portion 283 is formed by etching using the resist pattern 280 as a mask. . Further, the resist pattern 280 is half-ashed to form a resist pattern 285, and etching is performed using the resist pattern 285 as a mask, whereby the drain electrode 171 and the source electrode 172 are formed. In this case, unlike the manufacturing method shown in FIGS. 7 to 9, the positional relationship between the drain electrode 171 and the ohmic contact layer 161 is determined only by the resist pattern 280, so it is necessary to consider the shift of the resist pattern based on the alignment accuracy. Absent. Since the edge portion of the resist pattern 280 is retreated by half ashing, the drain electrode 171 and the source electrode 172 are slightly thinned, but the retreat amount can be suppressed to 0.3 μm or less, so that the LDD length of the LDD region 165 is reduced. Can be greatly reduced. Further, if the mask pattern is resized in advance by the expected amount of recession, the dimensions of the drain electrode 171 and the source electrode 172 can be formed almost as designed.

  In addition, a resist pattern for forming the gap etch portion 283 and a resist pattern for forming the drain electrode 171 and the source electrode 172 can be formed using one photomask by utilizing halftone exposure. Therefore, the number of masks can be further reduced. The other effects of this modification are the same as the effects of the manufacturing method according to the embodiment shown in FIGS.

<3.4 Second Modification of TFT Manufacturing Method>
15 to 16 are process cross-sectional views illustrating a manufacturing method according to the second modification of the TFT 100 of the above-described embodiment. Among the manufacturing steps shown in FIGS. 15 to 16, the same or corresponding manufacturing steps as those shown in FIGS. 7 to 9 are given the same reference numerals, and are different from the manufacturing steps shown in FIGS. 7 to 9. The explanation will focus on the points.

  The steps from the step shown in FIG. 15A to the stack of the high concentration impurity film 160 shown in FIG. 15B are the same as the manufacturing steps of the TFT 100 shown in FIG. To do. Using the resist pattern (not shown) formed on the high concentration impurity film 160 as a mask, the high concentration impurity film 160 and the semiconductor film 140 are successively dry etched. As a result, the high concentration impurity film 160 and the semiconductor film 140 are removed in the left and right regions of the region where the TFT is to be formed.

  As shown in FIG. 15C, a metal film 170 made of, for example, Mo (molybdenum) or the like is formed on the entire surface of the substrate 110 by sputtering. Then, a resist is applied on the metal film 170, and exposure and development are performed, so that a resist pattern 250 is formed on regions to be the drain electrode 171 and the source electrode 172. The resist pattern 250 has an opening in a portion to be the channel region 141c above the gate electrode 121.

As shown in FIG. 15D, the substrate 110 is immersed in an etchant using the resist pattern 250 as a mask, and the metal film 170 is wet etched. The etchant used for this wet etching needs to have a resist layer with no peeling of the resist pattern and a sufficient etching selectivity with respect to the high concentration impurity film 160 below the metal film 170. Therefore, an SLA etchant well known as a metal etchant (composition: H ₃ PO ₄ (phosphoric acid): H ₂ O: HNO ₃ (nitric acid): CH ₃ COOH (acetic acid) = 16: 2: 1: 1) Is used. Subsequently, the high concentration impurity film 160 is dry etched. As a result, the metal film 170 becomes metal layers 173 and 174 separated to the left and right of the gate electrode 121, and the high-concentration impurity film 160 is separated into ohmic contact layers 161 and 162. Note that the semiconductor layer 141 under the removed high-concentration impurity film 160 is also etched to some extent by overetching during dry etching.

  As shown in FIG. 15E, the substrate 110 is immersed again in the SLA etchant in order to additionally etch the metal layers 173 and 174. The metal layers 173 and 174 are sandwiched between the resist pattern 250 and the ohmic contact layers 161 and 162, respectively. Since the ends of the metal layers 173 and 174 are exposed, when immersed in the SLA etchant, the metal layers 173 and 174 are etched from the ends along the resist pattern 250 in the right and left directions at a predetermined etching rate, respectively. For this reason, if the etching rate of SLA is obtained in advance, the length of the metal layers 173 and 174, that is, the LDD length can be set to a desired length only by adjusting the etching time of the additional etching. Then, the resist pattern 250 is removed as shown in FIG.

  Subsequent TFT manufacturing steps are the same as those shown in FIGS. 9H and 9I, and a description thereof will be omitted.

  As described above, using the resist pattern 250 shown in FIG. 15C, not only the metal film 170 and the high-concentration impurity film 160 are separated into left and right, but also the lengths of the separated metal layers 173 and 174 are adjusted. Therefore, it is not necessary to add a mask for adjusting the lengths of the metal layers 173 and 174. In addition, since the shift amount of the metal layers 173 and 174 can be adjusted by changing the additional etching time, the LDD length of the TFT can be easily adjusted.

  In addition, since there are few steps to be added to the manufacturing process of the a-Si_TFT, it is not necessary to provide a new manufacturing line. For this reason, the manufacturing cost of TFT can be reduced.

<3.5 Third Modification of TFT Manufacturing Method>
17 to 18 are process cross-sectional views illustrating a manufacturing method according to the third modification of the TFT 100 of the above-described embodiment. 17 to 18, the same or corresponding manufacturing steps as those shown in FIGS. 15 to 16 are denoted by the same reference numerals, and the manufacturing steps shown in FIGS. The difference will be mainly described.

  The manufacturing process from FIG. 17A to FIG. 17D until the high-concentration impurity film 160 is dry-etched to form the ohmic contact layers 161 and 162 is shown in FIGS. The manufacturing process shown in FIG. Next, as shown in FIG. 17D, the resist pattern 260 used as a mask when the metal film 170 and the high-concentration impurity film 160 are dry-etched is removed.

  As shown in FIG. 18E, a resist is applied, and exposure and development are performed, whereby island-like resist patterns 270 are newly formed on the upper surfaces of the separated left and right metal layers 175 and 176, respectively. Then, the drain layer 171 and the source electrode 172 are formed by etching the metal layers 175 and 176 using the resist pattern 270 as a mask. The subsequent manufacturing process is the same as the manufacturing process shown in FIG.

  As described above, since there are few steps to be added to the manufacturing process of the a-Si_TFT, it is not necessary to provide a new manufacturing line. For this reason, the manufacturing cost of TFT can be reduced.

<4. Other>
In the TFTs 100, 300, 400, and 500 according to the embodiment and the modification thereof, the semiconductor layer 141 and the ohmic contact layers 161 and 162 are formed of a silicon film. However, a SiGe (silicon germanium) film or a SiC (carbonized carbon) is used. It may be formed of a semiconductor film such as a (silicon) film.

  Although the TFTs 100, 300, 400, and 500 according to the embodiment and the modification thereof have been described as N-channel TFTs, they may be P-channel TFTs. In the case of a P-channel TFT, the ohmic contact layers 161 and 162 are doped with a P-type impurity.

  In addition, the TFTs 100, 300, 400, and 500 according to the above-described embodiments and modifications thereof are often used as pixel TFTs when used in the liquid crystal display device 10, but are used for a driver monolithic display device drive circuit. It can also be used as a TFT. Further, the TFTs 100, 300, 400, and 500 are used not only for liquid crystal display devices but also for organic EL (Organic Electro Luminescence) display devices.

10 ... Liquid crystal display device 100, 300, 400, 500 ... TFT
DESCRIPTION OF SYMBOLS 110 ... Insulating substrate 121 ... Gate electrode 130 ... Gate insulating film 141 ... Semiconductor layer 141d ... Drain region 141c ... Channel region 141s ... Source region 151, 152, 155 ... Amorphous silicon layer 155 ... Etching stopper layer 160 ... High concentration Impurity films 161, 162 ... Ohmic contact layer 165 ... LDD region 170 ... Metal film 171 ... Drain electrode 172 ... Source electrode 190, 290 ... Halftone mask 220, 250, 280, 285 ... Resist pattern 243, 283 ... Gap etch part

Claims (17)

A bottom-gate thin film transistor formed on an insulating substrate,
A gate electrode formed on the insulating substrate;
A gate insulating film formed on the gate electrode;
A semiconductor layer formed on the gate insulating film and having a channel region facing the gate electrode, and a source region and a drain region formed so as to sandwich the channel region;
A source electrode and a drain electrode formed on the semiconductor layer;
Ohmic contact layers formed between the source electrode and the source region and between the drain electrode and the drain region, respectively.
The semiconductor layer includes one of a microcrystalline semiconductor layer and a polycrystalline semiconductor layer,
The drain electrode overlaps with a part of the ohmic contact layer formed on the drain electrode, and is disposed at a predetermined distance from an end of the gate electrode in a plan view. Thin film transistor. The predetermined distance is 0.5 to 3 μm,
The thin film transistor according to claim 1, wherein the ohmic contact layer is a conductor layer having a sheet resistance of 50 k to 5000 kΩ / □.   The thin film transistor according to claim 1, wherein the ohmic contact layer is a semiconductor layer doped with impurities.   The thin film transistor according to claim 3, wherein the ohmic contact layer includes a microcrystalline semiconductor layer having a sheet resistance of 50 k to 500 kΩ / □.   The thin film transistor according to claim 4, wherein the ohmic contact layer further includes an amorphous semiconductor layer.   4. The thin film transistor according to claim 3, wherein the ohmic contact layer includes an amorphous semiconductor layer having a sheet resistance of 500 k to 5000 kΩ / □.   2. The thin film transistor according to claim 1, wherein an amorphous semiconductor layer is stacked on an upper surface of the microcrystalline semiconductor layer or the polycrystalline semiconductor layer.   2. The thin film transistor according to claim 1, wherein a channel stopper layer is formed on the channel region of the semiconductor layer.   9. A display device comprising the thin film transistor according to claim 1 as a switching element of a pixel formation portion. A method for producing a bottom-gate thin film transistor formed on an insulating substrate,
Forming a gate electrode on the insulating substrate; and
Forming a gate insulating film on the gate electrode; and
Forming a semiconductor film having a channel region opposed to the gate electrode and a source region and a drain region formed so as to sandwich the channel region on the gate insulating film;
An impurity film forming step of forming an impurity film doped with impurities on the semiconductor film;
A metal film forming step of forming a metal film on the impurity film;
Using a halftone mask having at least a semi-transmissive portion that transmits light with reduced light intensity and a light-shielding portion that blocks light, the light is left in at least a portion of the metal film corresponding to the channel region. The film thickness of the first resist film is thinner than the film thickness of the second resist film left in the region where the source electrode and the drain electrode are to be formed, and the edge of the second resist film in plan view A first patterning step of forming a first resist pattern in which a portion is arranged at a predetermined distance from an end of the gate electrode;
A selective removal step of removing the first resist film using plasma with oxygen gas and leaving the second resist film;
An electrode forming step of forming a drain electrode and a source electrode by etching the metal film using the second resist film left in the selective removal step as a mask;
An ohmic contact layer forming step of forming an ohmic contact layer on the upper surface of the source region and the drain region by etching the impurity film either before the selective removing step and after the electrode forming step, A method for producing a thin film transistor, comprising: The ohmic contact layer forming step includes
A resist film removing step of removing the second resist film left in the selective removing step after forming the drain electrode and the source electrode;
A second patterning step of forming a second resist pattern having an opening at a position corresponding to the gate electrode on the upper surface of the metal film;
11. The method of manufacturing a thin film transistor according to claim 10, further comprising: an impurity film etching step of etching the impurity film using the second resist pattern as a mask. The halftone mask has a transmission part in a part of the semi-transmission part,
The first resist pattern has an opening at a position of the first resist film corresponding to the transmission part of the halftone mask,
The ohmic contact layer forming step includes an opening portion etching step which is performed before the selective removal step and sequentially etches the metal film and the impurity film exposed to the opening portion using the first resist pattern as a mask. The method of manufacturing a thin film transistor according to claim 10, wherein: A method for producing a bottom-gate thin film transistor formed on an insulating substrate,
Forming a gate electrode on the insulating substrate; and
Forming a gate insulating film on the gate electrode; and
Forming a semiconductor film on the gate insulating film; and
An impurity film forming step of forming an impurity film doped with impurities on the semiconductor film;
A metal film forming step of forming a metal film on the impurity film;
Forming a resist pattern having an opening in a region corresponding to the gate electrode on the upper surface of the metal film;
Etching process for etching the metal film and the impurity film using the resist pattern as a mask;
An additional etching step of additionally etching the metal film by wet etching until the end of the metal film is separated from the end of the gate electrode by a predetermined distance in plan view using the resist pattern as a mask. A method for manufacturing a thin film transistor.   14. The method of manufacturing a thin film transistor according to claim 13, wherein the etching step and the additional etching step are wet-etched with an etchant containing phosphoric acid, nitric acid and acetic acid.   14. The method of manufacturing a thin film transistor according to claim 10, wherein the impurity film forming step forms the impurity film by a plasma CVD method using plasma with a gas containing impurities. The semiconductor film is a microcrystalline semiconductor film;
14. The thin film transistor manufacturing method according to claim 10, wherein the semiconductor film forming step includes a microcrystalline semiconductor film forming step of forming the microcrystalline semiconductor film by a plasma CVD method or a high density plasma CVD method. Method. The semiconductor film is a polycrystalline semiconductor film;
The semiconductor film forming step includes a polycrystalline semiconductor film forming step of generating a polycrystalline semiconductor film from either an amorphous semiconductor film or a microcrystalline semiconductor film by a laser crystallization method. Or a method for producing a thin film transistor according to 13;

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