JP2008098230A - Semiconductor testing system and semiconductor testing apparatus, wafer to be tested, and semiconductor testing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To self-diagnose an entire system up to a probe immediately before a wafer to be tested. <P>SOLUTION: This semiconductor testing system 100 electrically tests a wafer 300 to be tested by using the wafer and a semiconductor testing apparatus 200 electrically connected with the wafer. A plurality of semiconductor circuits 350 and a self diagnostic circuit 400 provided along an outer rim of the plurality of semiconductor circuits and having an electrode similar to those of the semiconductor circuits are printed on the wafer to be tested. The semiconductor testing apparatus includes a probe card 240 coming into pressure-contact with the wafer to be tested and a performance board 230 connected with the probe card for relaying an electric signal between the testing apparatus and the wafer. When the probe card is connected with the semiconductor circuits, the circuits are tested. When the probe card is connected with the self diagnostic circuit, the self diagnosis of the semiconductor testing apparatus is carried out. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor test system, a semiconductor test apparatus, a wafer under test, and a semiconductor test method for performing an electrical test on a wafer under test.

  In recent years, an integrated circuit (IC: Integrated Circuit) has been increased in capacity, speed, and size (high density). Along with the increase in the density of such integrated circuits, high-speed and complicated processes are required for electrical function testing of the integrated circuits and the wafer that is the preceding stage.

  In a semiconductor test apparatus that performs such an electrical function test, a self-diagnosis of the semiconductor test apparatus itself is performed as a test preparation for the wafer under test and to isolate a defective portion between the wafer under test and the semiconductor test apparatus. ing.

Usually, a self-diagnosis is performed by replacing a performance board regarded as one piece with a wafer under test by a diagnostic board for self-diagnosis. When such a diagnostic board is used, it is necessary to provide a special drive circuit in the test head. However, a semiconductor test system in which a selector for a relay circuit is provided in the diagnostic board to improve versatility is also disclosed (for example, Patent Document 1).
JP-A-6-324115

  However, in such a self-diagnosis based on the premise of replacement with a diagnostic board, a great deal of labor is required for replacement of the diagnostic board, and the overhead time required for attachment / detachment causes a reduction in drive rate. In particular, when testing a wafer, the performance board is provided at the bottom of the test head and the probe card is pressed from the top of the wafer to be tested.

  In addition, the conventional self-diagnosis that replaces the diagnostic board allows only the functional test of the semiconductor test equipment itself, up to the pogo pin (test terminal) of the test head, and is the probe needle that is the biggest cause of problems during mass production. It was not possible to detect poor contact due to wear or dirt on the surface.

  The present invention has been made in view of the above-mentioned problems of conventional semiconductor test equipment, and the object of the present invention is to test under test without replacement of special hardware such as existing semiconductor test equipment. To provide a new and improved semiconductor test system, semiconductor test apparatus, wafer under test, and semiconductor test method capable of self-diagnosis all systems up to the probe needle immediately before the wafer.

  In order to solve the above problems, according to an aspect of the present invention, an electrical test of a wafer under test is performed using a wafer under test and a semiconductor test apparatus electrically connected to the wafer under test. A semiconductor test system for performing printing on a wafer under test, a plurality of semiconductor circuits, and a self-diagnostic circuit that is arranged on an outer edge of the plurality of semiconductor circuits and has an electrode equal to an electrode (pad) of the semiconductor circuit The semiconductor test apparatus includes a probe card that is press-contacted to the wafer to be tested, and a performance board that is connected to the probe card and relays electrical signals between the semiconductor test apparatus and the wafer to be tested. When connected, the semiconductor circuit is tested. When the probe card is connected to the self-diagnostic circuit, the semiconductor test apparatus is self-diagnosed. The symptom, the semiconductor test system is provided.

  In the present invention, by providing a self-diagnosis circuit on the wafer under test itself, highly reliable self-diagnosis can be performed under exactly the same conditions as when actually measuring other semiconductor circuits. Accordingly, it is possible to self-diagnose all systems up to the probe needle immediately before the wafer to be tested without replacement of special hardware such as an existing semiconductor test apparatus (without manual intervention). .

  In order to solve the above-described problems, according to another aspect of the present invention, there is provided a semiconductor test apparatus that is electrically connected to a wafer under test and performs an electrical test of the wafer under test. A self-diagnostic circuit disposed on the outer edge of the plurality of semiconductor circuits and having an electrode equal to the electrode of the semiconductor circuit, a probe card pressed against the printed wafer to be tested, and the semiconductor test apparatus connected to the probe card When the probe card is connected to a semiconductor circuit, the semiconductor circuit is tested and the probe card is connected to a self-diagnosis circuit. Provides a semiconductor test apparatus characterized by performing a self-diagnosis of the semiconductor test apparatus.

  By making the wafer under test provided with the self-diagnosis circuit a part of the self-diagnosis system, it is possible to reliably isolate the defective portion between the wafer under test and the semiconductor test apparatus. That is, all the systems up to the probe needle immediately before the wafer to be tested can be self-diagnosed, and it is possible to accurately and quickly grasp the replacement time of the probe needle that is expected to be defective as a consumable.

  In addition, since the self-diagnosis can be performed in the same process as the semiconductor circuit test without replacing the performance board or probe card, there is no need for complicated processing for self-diagnosis, and contact that may occur at the time of replacement. Further troubles (secondary troubles) such as defects can be prevented, and self-diagnosis time can be shortened (improvement of operation rate) and cost can be reduced.

  Further, since it is not necessary to prepare a special test jig such as a diagnostic board or a diagnostic card for self-diagnosis, further cost reduction is expected.

  The self-diagnosis circuit may be arranged at corners of the array of the plurality of semiconductor circuits, for example, at the four corners of the semiconductor circuits arranged at the squares. In the wafer under test, the semiconductor circuits are arranged evenly in the vertical and horizontal directions. Such a plurality of semiconductor circuits often do not use the outer edges of the array, particularly corners (four corners), as a product in order to avoid yield deterioration. In the present invention, it is possible to reliably identify the defective portion at low cost by effectively utilizing such unused area and arranging the self-diagnosis circuit at the corners (four corners) of the semiconductor circuit array.

  The self-diagnosis circuit may be configured by connecting a plurality of electrodes. By matching one output with respect to the plurality of electrodes and another input, it becomes possible to test two or more electrode elements simultaneously.

  The self-diagnosis may be one or more tests selected from the group consisting of a continuity test, a short-circuit test, and a contact resistance test on the signal line to the wafer under test. By such a simple test, for example, a defective portion having a high failure rate such as probe needle wear can be roughly specified.

  In order to solve the above-described problem, according to another aspect of the present invention, a plurality of semiconductor circuits and an electrode that is disposed on an outer edge of the plurality of semiconductor circuits and is equal to the electrodes of the semiconductor circuits, the wafer under test There is also provided a wafer to be tested, which is printed with a self-diagnosis circuit used for self-diagnosis of a semiconductor test apparatus that performs the electrical test.

  In order to solve the above-mentioned problems, according to another aspect of the present invention, an electrical test of a wafer under test using a wafer under test and a semiconductor test apparatus electrically connected to the wafer under test A semiconductor test method for performing a test on a wafer to be tested on which a plurality of semiconductor circuits and a self-diagnostic circuit arranged on the outer edge of the plurality of semiconductor circuits and having electrodes equal to the electrodes of the semiconductor circuits are printed. The probe card is pressed in contact with the semiconductor circuit or the self-diagnostic circuit while being relatively moved, and when the probe card is connected to the semiconductor circuit, the semiconductor circuit is tested. There is also provided a semiconductor test method characterized by performing self-diagnosis of the semiconductor test apparatus when the probe card is connected to the self-diagnosis circuit.

  The components corresponding to the dependent claims in the semiconductor test apparatus described above and the description thereof can be applied to the wafer under test and the semiconductor test method.

  As described above, the semiconductor test apparatus according to the present invention can perform highly reliable self-diagnosis under exactly the same conditions as other semiconductor circuits without any special hardware replacement, and accurately and quickly identify defective parts. By doing so, it is possible to shorten the self-diagnosis time, improve the operation rate, and reduce the test cost.

  Exemplary embodiments of the present invention will be described below in detail with reference to the accompanying drawings. In addition, in this specification and drawing, about the component which has the substantially same function structure, duplication description is abbreviate | omitted by attaching | subjecting the same code | symbol.

  In the electrical function test of a wafer under test, for example, when a failure occurs in a plurality of semiconductor circuits, it must be determined whether the failure is caused by the semiconductor circuit being tested or by the semiconductor test equipment itself. Don't be. For example, if the semiconductor test apparatus itself is defective, the semiconductor circuit test can be continued only after the defect is completely removed.

  Therefore, in the past, the performance board and the diagnostic board provided with a diagnostic circuit have been replaced to perform self-diagnosis of the semiconductor test equipment. In addition, it was not possible to detect a problem such as a defect in a signal line and a connection part in the case of, for example, a contact failure of a probe needle. In the semiconductor test apparatus according to the present embodiment, it is possible to perform self-diagnosis of all systems up to the wafer under test including the performance board and probe card without any special hardware replacement.

(Semiconductor test system 100, 102)
FIGS. 1A and 1B are functional block diagrams showing a schematic configuration of the semiconductor test systems 100 and 102 in the present embodiment. In FIG. 1A and FIG. 1B, the semiconductor test systems 100 and 102 include a semiconductor test apparatus 200 and a wafer under test 300, and the semiconductor test apparatus 200 electrically connects the wafer under test 300. The wafers to be tested 300 are connected and subjected to an electrical test.

  The semiconductor test apparatus 200 includes a main body 210, a test head 220, a performance board 230, and a probe card 240.

  The main body 210 is provided with a control unit that performs a test process set via the user interface 212.

  The test head 220 is provided with a relay card (also referred to as a PE (Pin Electronics) card) 222 having 16 or 32 pin modules for performing a test function. Further, in the test head 220, an out relay for separating a circuit up to the test head 220 of the semiconductor test apparatus 200 and a circuit ahead thereof is provided, and self-diagnosis up to the test head 220 is possible.

  The performance board 230 is configured to be fitted to the test head 120 and the probe card 240, and relays electrical signals between the pin module of the relay card 222 and the probe card 240.

  The probe card 240 is in pressure contact with the wafer under test 300 via the probe needle 242 and electrically connects the performance circuit 230 with the electrodes of the semiconductor circuit provided on the wafer under test 300.

  In the wafer under test 300, a plurality of semiconductor circuits are arranged evenly in the vertical and horizontal directions. In the present embodiment, a self-diagnosis circuit having electrodes having the same number, shape, and arrangement as the electrodes of the semiconductor circuit is arranged on the outer edge of the semiconductor circuit, and is used for self-diagnosis of the semiconductor test apparatus 200. Such a self-diagnosis circuit will be described in detail later.

  The semiconductor test apparatus 200 having the above-described configuration has two embodiments depending on the pressing direction of the probe needle 242 to the wafer under test 300. One is a configuration in which the probe needle 242 is pressed vertically upward from the lower part of the wafer under test 300 as in the semiconductor test system 100, and the other is a mounting table 260 for mounting the wafer under test 300 as in the semiconductor test system 102. The probe needle 242 is placed on the chuck 262 and pressed vertically downward from the upper portion of the wafer under test 300. Such a test configuration can be selected depending on the test application of the wafer under test 300.

  When performing self-diagnosis with the semiconductor test systems 100 and 102 shown in FIG. 1A and FIG. 1B, the performance board 230 and the probe card 240 may be replaced with a diagnostic board or a diagnostic card. If there is a defective part on the performance board or probe card, the defective part cannot be identified. In addition, the processing becomes very complicated, and it takes time for replacement. In addition, a part of a large number of contact terminals such as connectors and pogo pins for connecting the respective devices may be damaged or broken to cause further defective portions.

  In particular, in the semiconductor test system 102 as shown in FIG. 1B, a great effort is required to rotate the heavy test head 220 around the rotation shaft 270 for replacement of the diagnostic board. The stress of the relay cable will cause further problems. In the present embodiment, the self-diagnosis is performed without such special hardware replacement.

(Wafer under test 300, 302)
In this embodiment, by providing a self-diagnosis circuit on the wafer under test 300 itself, it is possible to perform highly reliable self-diagnosis under exactly the same conditions as when actually measuring other semiconductor circuits.

  FIG. 2 is an external view showing the external appearance of the wafer under test 300 in this embodiment. Referring to FIG. 2 (a), in order to manufacture as many semiconductor circuits 350 as possible according to usage, for example, a plurality of square semiconductor circuits 350 are formed on a wafer 300 under test formed in a disk shape. Arranged.

  In order to avoid the deterioration of the yield, the outer edge of the array, particularly the four corner regions 360 in the wafer under test 300 is often not used as a product even if the semiconductor circuit 350 is printed. In the present embodiment, a self-diagnosis circuit is arranged in such an area 360 to effectively use the unused area. Therefore, the self-diagnosis of the semiconductor test apparatus 200 can be executed with a very simple configuration in which a self-diagnosis circuit is printed on a part of the print pattern of the semiconductor circuit 350 on the wafer under test 300, thereby reducing the cost of self-diagnosis. It becomes possible.

  The purpose of the self-diagnosis circuit can be achieved by providing one self-diagnosis circuit on the wafer under test 300, but it is not preferable to press the probe needle 242 against the wafer under test 300 many times due to the characteristics of the wafer under test 300. . Therefore, the probe needle 242 can be pressed against the self-diagnosis circuit only twice at most, and it is desirable to provide a plurality of self-diagnosis circuits at the same position (for example, four corners) of one wafer 300 to be tested.

  In addition, the arrangement of the self-diagnosis circuit is not limited to the above four corners. When the semiconductor circuit 350 is arranged on the semiconductor test wafer 302 in the arrangement as shown in FIG. A diagnostic circuit may be arranged, or several semiconductor circuits 350 are intentionally collapsed and a self-diagnostic circuit is provided in a predetermined region 380 in the array, and confirmation in the middle when the semiconductor circuits 350 are sequentially tested on the array It can also be used for testing.

  FIG. 3 is an electrode layout diagram showing a circuit example of the self-diagnosis circuit. Referring to FIG. 3A, the electrode 410 of the self-diagnosis circuit 400 is connected to the adjacent electrode 410 via the connection line 420. With this connection line 420, the semiconductor test apparatus 200 applies a predetermined signal to an arbitrary electrode 410 in the self-diagnostic circuit 400, and only measures the electric signal of the electrode 410 connected to the electrode 410. It can be understood at a time that the connection state to the electrode 410 is normal.

  For example, if a predetermined voltage output from the semiconductor test apparatus 200 can be accurately detected, it can be understood that there is continuity between the two systems leading to the wafer under test (continuity test) and no short circuit (short circuit test). Further, the contact resistance can also be tested (contact resistance test) by the voltage drop. Furthermore, a test (timing test) that matches the timing of signal change is also possible. By such a simple test of the DC signal level, it is possible to roughly identify a defective portion having a high failure rate such as, for example, probe needle wear.

  Further, as in the self-diagnosis circuit 402 shown in FIG. 3B, a plurality of electrodes 410 are connected by a connection line 420, and a connection state relating to the plurality of electrodes 410 is obtained only by outputting a test signal to one specific electrode 410. Can be tested. It is also possible to test a resistance value or a voltage drop by connecting a predetermined resistor instead of the connection line 420 in the self-diagnosis circuit 400 or the self-diagnosis circuit 402.

  As described above, in the semiconductor test systems 100 and 102 described above, the wafer under test 300 provided with the self-diagnosis circuits 400 and 402 is made a part of the self-diagnosis system, so that the wafer under test 300 and the semiconductor test are performed. It is possible to reliably isolate the defective portion from the apparatus 200. That is, all the systems up to the probe needle 242 immediately before the wafer to be tested 300 can be self-diagnosed, and the replacement timing of the probe needle 242 expected to be defective as a consumable can be grasped accurately and quickly.

  Further, since the self-diagnosis can be performed by the same process as the test of the semiconductor circuit 350 without accompanying the replacement of the performance board 230 and the probe card 240, the complicated process for the self-diagnosis is not required and the contact by the replacement is possible. Further troubles (secondary troubles) such as defects can be prevented, and the self-diagnosis time and cost can be reduced.

  In addition, since complicated replacement work is not involved, self-diagnosis can be easily performed and early detection of a defective portion can be achieved.

(Semiconductor test method)
Next, a semiconductor test method for conducting an electrical test of the wafer under test 300 using the semiconductor test apparatus 200 will be described.

  FIG. 4 is a flowchart showing the flow of the semiconductor test method. In this semiconductor test method, a regular semiconductor circuit on the wafer under test 300 is tested in a normal test process (S600). This is because the positions of the plurality of semiconductor circuits of the wafer under test 300 and the probe card 240 are relatively shifted, the probe needles 242 are sequentially pressed against the semiconductor circuits, and the electrodes of the semiconductor circuits and the semiconductor test apparatus are electrically connected. This is done by connecting and running the test software.

  If the failure continues in such a normal test process, it is likely that the failure is not in the semiconductor circuit but in the semiconductor test apparatus 200 itself. Therefore, it is determined whether the failure has continued (S602). A self-diagnosis is executed (S604).

  In the conventional semiconductor test system 102 as shown in FIG. 1B, such a self-diagnosis involves rotating the heavy and large test head 220 and replacing the diagnostic board. The self-diagnosis of the present embodiment can be handled only by changing the test position of the probe card 240 without replacing hardware.

  As an actual operation, the relative position of the probe card 240 with respect to the wafer under test 300 is changed from a semiconductor circuit to a self-diagnostic circuit arranged on the outer edge of the semiconductor circuit array, and the electrode arranged equal to the electrode of the semiconductor circuit is changed. The probe needle 242 is pressed and the self-diagnosis circuit is diagnosed by a separate self-diagnosis software.

  Subsequently, the result of this self-diagnosis (S604) is determined (S606), and if the diagnosis is passed, the test of the semiconductor circuit is continued again under the conclusion that it is not a malfunction of the semiconductor test apparatus 200. In this way, automatic return to the semiconductor circuit test is facilitated without human intervention, and the test operation rate of the wafer under test 300 can be improved.

  If the self-diagnosis is not passed, it is determined whether or not the treatment of the corresponding part to be described later has been completed (S608), and if it has not been treated yet, the treatment is executed (S610).

  The corresponding portion treatment (S610) includes, for example, consumable treatment such as cleaning and replacement of the probe needle 242. If the self-diagnosis does not pass even after such measures are taken, the probe card 240 or the performance board 230 may be replaced with a diagnostic card or a diagnostic board to perform a more detailed self-diagnosis.

  When the treatment of the corresponding part (S610) is completed, the process is repeated from the self-diagnosis circuit test. When all possible measures are taken as the treatment of the relevant part (S610), in the judgment of the treatment of the relevant part (S608), it is judged that the treatment is completed, that is, it is judged that the main body 210 of the semiconductor test apparatus 200 is defective. The test is stopped and the main body 210 is maintained (S612).

  Thus, in the semiconductor test method of this embodiment, when the probe card is connected to the semiconductor circuit, the semiconductor circuit is tested, and when the probe card is connected to the self-diagnosis circuit, the semiconductor test is performed. By performing self-diagnosis of the device, it is possible to perform highly reliable self-diagnosis under exactly the same conditions as other semiconductor circuits without special hardware replacement, and to identify the defective part accurately and quickly, Self-diagnosis time and cost can be reduced.

  As mentioned above, although preferred embodiment of this invention was described referring an accompanying drawing, it cannot be overemphasized that this invention is not limited to the example which concerns. It will be apparent to those skilled in the art that various changes and modifications can be made within the scope of the claims, and these are naturally within the technical scope of the present invention. Understood.

  Each block in the semiconductor test method of the present specification does not necessarily have to be processed in time series in the order described as a block diagram, and may include processing executed in parallel or individually.

  The present invention is applicable to a semiconductor test system, a semiconductor test apparatus, a wafer under test, and a semiconductor test method for performing an electrical test of a wafer under test.

It is a functional block diagram showing a schematic configuration of the entire semiconductor test system in the present embodiment. It is the external view which showed the external appearance of the to-be-tested wafer in this embodiment. It is an electrode arrangement diagram showing a circuit example of a self-diagnosis circuit. It is the flowchart which showed the flow of the semiconductor test method.

Explanation of symbols

100, 102 Semiconductor test system 200 Semiconductor test equipment 230 Performance board 240 Probe card 300, 302 Wafer under test 350 Semiconductor circuit 400, 402 Self-diagnosis circuit

Claims (7)

A semiconductor test system for performing an electrical test of a wafer under test using a wafer under test and a semiconductor test apparatus electrically connected to the wafer under test,
In the wafer under test,
A plurality of semiconductor circuits;
A self-diagnosis circuit disposed on an outer edge of the plurality of semiconductor circuits and having an electrode equal to the electrode of the semiconductor circuit, and is printed,
The semiconductor test apparatus includes:
A probe card in pressure contact with the wafer under test;
A performance board connected to the probe card and relaying electrical signals between the semiconductor test apparatus and the wafer under test;
With
When the probe card is connected to the semiconductor circuit, the semiconductor circuit is tested, and when the probe card is connected to the self-diagnostic circuit, the semiconductor test apparatus performs self-diagnosis. A semiconductor test system. A semiconductor test apparatus that is electrically connected to a wafer under test and conducts an electrical test of the wafer under test,
A plurality of semiconductor circuits, a self-diagnostic circuit having electrodes equal to the electrodes of the semiconductor circuits disposed on the outer edges of the plurality of semiconductor circuits, and a probe card that press-contacts the printed wafer to be tested;
A performance board connected to the probe card and relaying electrical signals between the semiconductor test apparatus and the wafer under test;
With
When the probe card is connected to the semiconductor circuit, the semiconductor circuit is tested, and when the probe card is connected to the self-diagnostic circuit, the semiconductor test apparatus performs self-diagnosis. Semiconductor test equipment.   The semiconductor test apparatus according to claim 2, wherein the self-diagnosis circuit is arranged at a corner of the array of the plurality of semiconductor circuits.   The semiconductor test apparatus according to claim 2, wherein the self-diagnosis circuit is configured by connecting a plurality of the electrodes.   The self-diagnosis is one or two or more tests selected from the group consisting of a continuity test, a short-circuit test, and a contact resistance test on a signal line to the wafer under test. Semiconductor test equipment. A plurality of semiconductor circuits;
A self-diagnosis circuit that is disposed on an outer edge of the plurality of semiconductor circuits and has an electrode equal to the electrode of the semiconductor circuit, and is used for self-diagnosis of a semiconductor test apparatus that performs an electrical test of the wafer under test;
A wafer under test, characterized in that is printed. A semiconductor test method for conducting an electrical test of a wafer under test using a wafer under test and a semiconductor test apparatus electrically connected to the wafer under test,
A probe card is placed on the wafer under test on which a plurality of semiconductor circuits and a self-diagnostic circuit having electrodes equal to the electrodes of the semiconductor circuits are arranged on the outer edge of the plurality of semiconductor circuits. The pressure is changed while relatively changing the position so as to be electrically connected to the self-diagnosis circuit,
When the probe card is connected to the semiconductor circuit, the semiconductor circuit is tested, and when the probe card is connected to the self-diagnostic circuit, the semiconductor test apparatus performs self-diagnosis. A semiconductor test method.

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