JP2008097523A - Plc device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a PLC device for achieving the expansion in blocks (in base units) with a simple operation without stopping the operation of the device. <P>SOLUTION: Since a lower stage expanded bus gate (601) interposed in a passage from a lower stage side receptacle (23a) to an inner bus (201) is kept in an off state as long as the power supply of a block (3) to be added is not turned on, the device may avoid a state that an abnormal signal enters the inner bus (201) if the existing system in attaching a connector by turning off the power supply of a block to be added, and since the bus gate (601) is spontaneously turned on by turning on the block to be added after attaching the connector, the device may smoothly start the added block (3). <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a PLC device in which a basic block and one or more extension blocks are connected via an extension cable.

  2. Description of the Related Art Conventionally, a PLC device in which a basic block and one or more extension blocks are connected in series via an extension cable is known (see, for example, Patent Document 1).

  An external configuration diagram of an example of such a PLC device is shown in FIG. As shown in the figure, this PLC device has one basic block 1 and one or more (two in this example) extension blocks 2 and 3 connected in series via an extension cable. It will be. FIG. 6A shows a state before the expansion block 3 is not yet connected, and FIG. 5B shows a state after the expansion when the expansion block 3 is already connected.

  The basic block 1 includes a plurality of control units in addition to the power supply unit 11 and the inter-block connection unit 14. In this example, as the control unit, a CPU unit 12 and three I / O units (including an IN unit, an OUT unit, an IN / OUT mixed unit) 13 are shown. As the unit, a communication unit (including a master / slave communication unit and a communication unit between PLCs) and various special function units (PID arithmetic unit, motion control unit, etc.) may be included.

  These units 11 to 14 are detachably attached to a base unit (also referred to as a backplane) 10 formed by laying an internal bus on a motherboard via connectors (not shown). . As a result, the CPU unit 12 and each I / O unit 13 are connected via an internal bus (not shown).

  The extension block 2 includes a plurality of control units in addition to the power supply unit 21 and the inter-block connection unit 23. In this example, five I / O units (including IN units, OUT units, IN and OUT mixed units) 22 are shown as control units. A unit (including a master / slave communication unit and a communication unit between PLCs) and various special function units (PID arithmetic unit, motion control unit, etc.) may be included.

  These units 21 to 23 are detachably attached to a base unit (also referred to as a backplane) 20 formed by laying an internal bus on a motherboard via connectors (not shown). . Thus, each I / O unit 22 is connected via an internal bus (not shown).

  The extension block 3 includes a plurality of control units in addition to the power supply unit 31 and the inter-block connection unit 33. Even in this example, five I / O units (including IN units, OUT units, IN and OUT mixed units) 32 are shown as control units, but other control units include communication units. A unit (including a master / slave communication unit and a communication unit between PLCs) and various special function units (PID arithmetic unit, motion control unit, etc.) may be included.

  These units 31 to 33 are detachably attached to a base unit (also referred to as a backplane) 30 formed by laying an internal bus on a motherboard via a board connector (not shown). Yes. As a result, each I / O unit 32 is connected via an internal bus (not shown).

  The inter-block connection units 14, 23, 33 have substantially the same structure. In other words, the back sides of these units 14, 23 and 33 are connected to internal buses (not shown) on the base units 10, 20 and 30 via the board connectors. In addition, on the front side of these units 14, 23, 33, there is provided a recess pull (one connecting member of the connector) that functions as an external outlet for leading the internal bus to the outside.

  More specifically, on the front surface of the inter-block connection unit 14 of the basic block 1, a lower external lead-out port for leading an internal bus (see reference numeral 101 in FIG. 12) laid on the base unit 10 to the outside. As a result, a lower sector pull 14a is provided.

  Further, on the front surface of the inter-block connection unit 23 of the extension block 2, a resector pull functioning as a lower external lead-out port for leading the internal bus (see reference numeral 201 in FIG. 12) laid on the base unit 20 to the outside. 23a and a recess pull 23b that functions as an upper external outlet for leading an internal bus (see reference numeral 201 in FIG. 12) laid on the base unit 20 to the outside are arranged side by side.

  Further, the front side of the inter-block connection unit 33 of the extension block 3 has a resector pull functioning as a lower external lead-out port for leading the internal bus (see reference numeral 301 in FIG. 12) laid on the base unit 30 to the outside. 33a and a resector pull 33b functioning as an upper external outlet for deriving an internal bus (see reference numeral 301 in FIG. 12) laid on the base unit 20 to the outside are arranged side by side.

  Cables are connected between the basic block 1 and the expansion block 2 and between the expansion block 2 and the expansion block 3. That is, in this example, the inter-block connection unit 14 of the basic block 1 and the inter-block connection unit 23 of the extension block 2 are connected by the cable 41. Similarly, the inter-block connection unit 23 of the expansion block 2 and the inter-block connection unit 33 of the expansion block 3 are connected by a cable 42.

  More specifically, a plug (the other connecting member of the connector) 41 a is attached to the upper end portion of the cable 41, and a plug 41 b is attached to the lower end portion of the cable 41. Similarly, a plug 42a is attached to the upper end portion of the cable 42, and a plug 42b is attached to the lower end portion of the cable 42. These plugs have substantially the same structure, and have one cable lead-in port and one connection port. The connection between the plug and the drawn cable is made by a fixed means such as screwing or soldering.

  When the inter-block connection unit 14 of the basic block 1 and the inter-block connection unit 23 of the expansion block 2 are connected by the cable 41, the plug 41a is attached to the receptacle 14a, and the plug 41b is attached to the recess pull 23b. At this time, a detachable connector is constituted by the plug 41a and the receptacle 14a, and a detachable connector is constituted by the plug 41b and the receptacle 23b.

  Similarly, when the inter-block connection unit 23 of the extension block 2 and the inter-block connection unit 33 of the extension block 3 are connected by the cable 42, the plug 42a is attached to the receptacle 23a, and the plug 42b is attached to the receptacle pull 33b. The At this time, a detachable connector is constituted by the plug 42a and the receptacle 23a, and a detachable connector is constituted by the plug 42b and the receptacle 33b.

  In other words, between the lower external lead-out port (lessa pull 14a) of the basic block 1 and the upper external lead-out port (resector pull 23b) of the extension block 2, and the lower external lead-out port of the extension block 2 located on the upper side (Resector pull 23a) and the upper external lead-out port (resector pull 33b) of the extension block 3 located on the lower side are connected through cables 41 and 42, and both ends of the cables 41 and 42 and each external A detachable connector (a set of a receptacle and a plug) is interposed between the outlets (resector pulls 14a, 23a, 23b, 33a, 33b).

  An electrical hardware configuration diagram of such a PLC device is shown in FIG. In the figure, reference numerals 10a, 20a, 30a denote regions where the units other than the CPU unit and the power supply unit on the base units 10, 20, 30 are removed and exposed.

  As shown in the figure, a base control circuit 103 composed of an ASIC is provided in the area 10 a of the base unit 10 of the basic block 1. Further, a base control circuit 203 and a power supply state notification circuit 204 each formed of an ASIC are provided in the area 20 a of the base unit 20 of the extension block 2. Further, a base control circuit 303 and a power state notification circuit 304 each formed of an ASIC are provided in the area 30 a of the base unit 30 of the extension block 3.

  The base control circuits 103, 203, and 303 include internal registers 103a, 203a, and 303a, respectively. The internal registers 103a, 203a, and 303a have the same configuration. The base control circuits 103, 203, and 303 manage read / write operations for the internal registers 103a, 203a, and 303a. The internal register stores information about whether power is supplied to each I / O unit or control unit mounted on the base unit. The CPU unit can read or write the contents of the internal registers 103a, 203a, and 303a via the bus lines 101, 201, and 301.

The power supply state notification circuits 204 and 304 have a function of monitoring the states of the power supply units 21 and 31, respectively, and transmitting the results to the CPU unit via the bus lines 206 and 306.
JP-A-6-124103

  However, in such a conventional PLC device that can be expanded in block units (base unit units), if a PLC device is newly added and continuously connected in the operating state, a bus error or expansion block An abnormality such as power OFF occurs and operation stops. Therefore, there is a problem in that the operation of the PLC device must be stopped each time in order to newly add an additional block to the PLC device that is in operation.

  The present invention has been made paying attention to the above-mentioned problems, and the object of the present invention is to provide a PLC device that can be expanded in block units (base unit units) without stopping the operation of the device. Is to provide.

  Still other objects and operational effects of the present invention will be well understood by those skilled in the art by referring to the following description of the specification.

  The above problem is solved by a PLC having the following configuration. That is, this PLC device is formed by connecting a basic block and one or more extension blocks via an extension cable.

  The basic block includes a plurality of control units including a CPU unit and an I / O unit, an internal bus that connects the control units, and a lower external lead-out port that leads the internal bus to the outside. , A plurality of control units including I / O units, an internal bus connecting the control units, an upper-side external lead-out port for leading the internal bus to the outside, or an upper-stage side external lead-out port for leading the internal bus to the outside And a lower external lead-out port.

  Also, between the lower external lead-out port of the basic block and the upper external lead-out port of the extension block, and the upper external lead-out port of the extension block located on the lower step side and the lower side of the extension block located on the upper step side The outlet is connected via a cable, and a detachable connector is interposed between both ends of the cable and each external outlet.

  Each expansion block has a lower expansion bus gate circuit that can be turned on and off between the internal bus and the lower external lead-out port, and a first memory for storing the lower expansion bus control signal. Area and a second storage area for storing the lower-stage additional power supply state notification signal, and these storage areas can be read or written via the internal bus, and the power is turned on. A power supply state notification circuit having a function of detecting whether there is a power supply cut-off state and generating a lower-stage additional power supply state notification signal to be notified to a block located in the upper stage, and a lower-stage side A function of writing a lower-stage additional power supply state notification signal coming from an additional block to be written to the second storage area of the internal register, and a lower-stage bus stored in the first storage area of the internal register ON the lower expansion bus gates in accordance with the contents of the control signal, control means and a function of OFF, it is provided.

  The newly added expansion block and the CPU unit included in the basic block exchange information via the internal register, so that the expansion block can be installed online.

  According to such a configuration, the lower expansion bus gate interposed in the path from the lower external lead-out port to the internal bus is maintained in the OFF state unless the power of the added block is turned on. By turning off the power supply to the added block, it is possible to prevent an abnormal signal from entering the internal bus of the existing system when the connector is installed. Since is turned on alone, the added block can be activated smoothly.

  In the above PLC device, a lower expansion bus gate circuit that can be turned on and off between the internal bus and the lower external lead-out port, and a first storage area for storing the lower expansion bus control signal And a second storage area for storing the lower extension power supply state notification signal, and these storage areas can be read or written via the internal bus, and the extension located on the lower stage side. A function for writing a lower-stage additional power supply state notification signal coming from the block to the second storage area of the internal register, and a lower-stage additional bus gate according to the contents of the lower-stage bus control signal stored in the first storage area of the internal register A control means having a function of turning on and off may also be provided in the basic block.

  According to such a configuration, the operation of connecting the extension block to the basic block can be performed while continuing the operation of the system.

  According to the present invention, it is possible to provide a PLC device that can be expanded in units of blocks (base units) without stopping the operation of the device.

  Hereinafter, a preferred embodiment of a PLC device according to the present invention will be described in detail with reference to the accompanying drawings. The appearance configuration diagram of the PLC device according to the present invention is the same as that in FIG.

  An electrical hardware configuration diagram of a PLC device according to the present invention is shown in FIG. In the figure, reference numerals 10a, 20a, 30a denote regions where the units other than the CPU unit and the power supply unit on the base units 10, 20, 30 are removed and exposed.

  As shown in the figure, the area 10a of the base unit 10 of the basic block 1 is provided with a lower expansion bus control means 102 and a base control circuit 103 each composed of an ASIC. The area 20a of the base unit 20 of the expansion block 2 is provided with a lower expansion bus control means 202, a base control circuit 203, and a power supply state notification circuit 204 each composed of an ASIC. Furthermore, the area 30a of the base unit 30 of the expansion block 3 is provided with a lower expansion bus control means 302, a base control circuit 303, and a power supply state notification circuit 304 each formed of an ASIC.

  The lower expansion bus control means 102, 202, and 302 each include a lower expansion bus gate circuit 601 shown in FIG. The lower expansion bus gate circuit 601 can be turned ON / OFF between the internal bus and the lower external lead-out port in each of the blocks 1 to 3. The lower expansion bus gate circuit 601 will be described in more detail with reference to FIG. In addition, in the component in the figure, the same number as FIG. 1 is attached | subjected about the same component as FIG. The lower expansion bus gate circuit 601 has a configuration in which a three-state buffer 601a is interposed between connection paths 101a, 201a, 301a and 101c, 201c, 301c extending the internal buses 101, 201, 301 of each block. . The connection paths 101c, 201c, and 301c of each block are connected to receptacles 14a, 23a, and 33a as lower stage side external outlets, respectively. The lower-stage expansion bus control signals 105a, 205a, and 305a are connected to the switching input terminal of the three-state buffer 601a as a switching control signal line. Therefore, this three-state buffer 601a is controlled to be enabled or disabled according to the logic state of the lower expansion bus control signal. As a result, the lower expansion bus gate circuit 601 can turn on and off between the internal bus and the lower external lead-out port.

  Returning to FIG. 1, more specifically, the lower expansion bus gate circuit 601 included in the lower expansion bus control means 102 in the basic block 1 is connected between the internal bus 101 and the re-sector pull (lower external lead-out port) 14a. The connection path 101a is interposed. Therefore, when the lower expansion bus gate circuit 601 is turned on, the internal bus 101 and the re-sector pull 14a are in a conductive state, and the additional expansion block can be operated. When the additional bus gate circuit 601 is turned off, the internal bus 101 and the re-sector pull 14a are in a non-conductive state, and an abnormal signal can be prevented from entering from the outside via the re-sector pull 14a.

  The lower expansion bus gate circuit 601 included in the lower expansion bus control means 202 in the expansion block 2 is interposed in the connection path 201a between the internal bus 201 and the re-sector pull (lower external lead-out port) 23a. In other words, the internal bus 201 has a connection path 201a to the re-sector pull (lower side external outlet) 23a and a connection path 201b to the lower sector (upper side external outlet) 23b. It is interposed in the connection path 201a between the bus 201 and the less sector pull (lower external lead-out port) 23a. Therefore, when the lower expansion bus gate circuit 601 is turned on, the internal bus 201 and the re-sector pull 23a are in a conductive state, and the additional expansion block can be operated. When the additional bus gate circuit 601 is turned off, the internal bus 201 and the re-sector pull 23a are in a non-conductive state, and an abnormal signal can be prevented from entering from the outside via the re-sector pull 23a.

  The lower expansion bus gate circuit 601 included in the lower expansion bus control means 302 in the expansion block 3 is interposed in the connection path 301a between the internal bus 301 and the re-sector pull (lower external lead-out port) 33a. That is, the internal bus 301 has a connection path 301a to the re-sector pull (lower side external lead-out port) 33a and a connection path 301b to the re-sector pull (upper side external lead-out port) 33b. It is interposed in the connection path 301a between the bus 301 and the re-sector pull (lower side external outlet) 33a. Therefore, when the lower expansion bus gate circuit 601 is turned on, the internal bus 301 and the re-sector pull 33a are in a conductive state, and the additional expansion block can be operated. When the additional bus gate circuit 601 is turned off, the internal bus 301 and the re-sector pull 33a are in a non-communication state, and the entry of an abnormal signal from the outside through the re-sector pull 33a can be prevented.

  The base control circuits 103, 203, and 303 include internal registers 103a, 203a, and 303a, respectively. The internal registers 103a, 203a, and 303a have the same configuration, and, for example, have a plurality of individual internal registers 1 to n as shown in FIG. In this example, a first storage area A1 and a second storage area A2 are defined in the kth individual register, and among these, the first storage area A1 contains a “lower expansion bus control signal”. State (ON / OFF, “1” / “0”) is stored, and the second storage area A2 is in a state of “lower extension power supply state notification signal” (ON / OFF, “1” / “0”). ) Is stored. The base control circuits 103, 203, and 303 manage read / write operations for the internal registers 103a, 203a, and 303a. The internal register stores information about whether power is supplied to each I / O unit or control unit mounted on the base unit. The CPU unit can read or write the contents of the internal registers 103a, 203a, and 303a via the bus lines 101, 201, and 301.

  The power supply state notification circuits 204 and 304 have a function of monitoring the state of the power supply units 21 and 31 and transmitting the results to the CPU unit via the bus lines 206 and 306, respectively.

  The lower expansion bus control means 102 in the basic block 1 includes a lower expansion power state notification circuit 603 shown in FIG. The lower expansion bus control means 202 and 302 in the expansion blocks 2 and 3 include a lower expansion power state notification circuit 602 shown in FIG.

  The lower expansion power supply state notification circuit 603 included in the lower expansion bus control means 102 of the basic block 1 will be described in more detail with reference to FIG. In addition, in the component in the figure, the same number as FIG. 1 is attached | subjected about the same component as FIG. The lower additional power supply state notification circuit 603 includes an OR circuit 603a that receives the connection path 107c and outputs the lower additional power supply state notification signal 105b. The connection path 107c is an OR circuit 602b (see FIG. 7) that receives the bus line 206 output from the power supply state notification circuit 204 of the expansion block 2 when the basic block 1 and the expansion block 2 are connected by the cable 41. ) Output signal line. Accordingly, the state of the power supply unit 21 of the extension block 2 located in the lower stage of the basic block 1 is stored in the internal register 103a of the basic block 1.

  Next, the lower added power supply state notification circuit 602 included in the lower added bus control means 202 and 302 of the added blocks 2 and 3 will be described in more detail with reference to FIG. In addition, in the component in the figure, the same number as FIG. 1 is attached | subjected about the same component as FIG. The lower expansion power supply state notification circuit 602 included in the lower expansion bus control means 202 of the expansion block 2 includes an OR circuit 602a that receives the connection path 207c and outputs the lower expansion power supply state notification signal 205b. This connection path 207c is an output signal line of the OR circuit 602b that receives the bus line 306 output from the power supply state notification circuit 304 of the expansion block 3 when the expansion block 2 and the expansion block 3 are connected by the cable 42. Connected. Therefore, the state of the power supply unit 31 of the expansion block 3 located in the lower stage of the expansion block 2 is stored in the internal register 203a of the expansion block 2. Similarly, the internal register 303a of the extension block 3 stores the state of the power supply unit of the extension block added to the lower stage of the extension block 3.

  FIG. 5 is a flowchart showing the processing of the lower expansion bus control means. As shown in FIG. 5 (b), the lower extension bus control means 102, 202 and 302 are supplied with lower extension power supply states sent from the power supply state notification circuits 204 and 304 of the blocks (bases) located at the lower stages, respectively. The notification signal is received (step 511), and the state is written in the lower extension power supply state notification signal area (second storage area A2) of the internal registers 103a, 203a, and 303a (step 512). 1 and the state reading from the lower expansion bus control signal area (first storage area A1) of the internal registers 103a, 203a, and 303a as shown in FIG. If the state of the bus control signal is set to “1” (step 502 YES), the corresponding lower expansion bus gate is turned on. Against (step 503), if it is not set to "1" (step 502NO), corresponding to so as to turn OFF the lower expansion bus gate (step 504), the second function and is incorporated.

  In other words, in each of the lower expansion bus control means 102, 202 and 302, the state of the lower expansion power supply state notification signal coming from the expansion block located on the lower side is written to the second storage area (A2) of the internal register. And a second function for turning on and off the lower expansion bus gate in accordance with the state of the lower bus control signal stored in the first storage area (A1) of the internal register. .

  On the other hand, on the side of the CPU unit 12 mounted on the basic block 1, processing for online base addition (online block addition) is incorporated as shown in FIG.

  That is, in this process, first, by accessing the internal register of the base unit of the block located at the lowest stage at that time, the lower stage expanded power supply state notification stored in the first storage area (A1) of the internal register The signal state is read (step 401).

  Here, for accessing the internal register of the base unit of the block located at the lowest stage at that time, the result of address recognition at the time of starting the system is used. That is, in this example, as shown in FIG. 9, each of the base units 10, 20, 30 has base position designation signal lines 101, 202, 301 and adders 108, 208, 308. It has been incorporated. Then, the base units 10, 20, and 30 are sequentially connected to the base units 10, 20, and 30 through the cables 41 and 42 in order to be automatically connected to the base units 10, 20, and 30 by the action of the adders 108, 208, and 308. Is assigned a unique base position (address).

  On the other hand, at the time of starting the system, as shown in FIG. 10, while accessing each unit (UNIT) and base control circuits 103, 203, 303 mounted on each base unit (step 1001), By confirming the normality / abnormality of the response (step 1002), the process of recognizing the mounting of the unit or the base control circuit at the corresponding address (step 1003) is repeated for each of all the units and the base control circuit. (Step 1004) An address recognition result is obtained. Based on the address recognition result obtained in this way, the access to the internal register of the base unit of the block located at the lowermost stage is performed.

  Returning to FIG. 4, it is determined whether the power is normal (turned on) or abnormal (not turned on) based on the state of the read lower extension power supply state notification signal (step) 402). As a premise thereof, the state of the lower additional power supply state notification signal is set to “power failure” at the time of system startup.

  If it is determined that the power supply is normal (step 402 YES), the set state (“1”) of the lower expansion bus control signal is written in the first storage area (A1) of the internal register of the base unit. Then, by the action of the second function incorporated in the lower extension bus control means described above, the lower extension bus gate of the base unit located at the lowest stage is operated from the OFF state to the ON state (step 404). As a result, the internal bus of the base unit currently located at the lowest stage is electrically connected to the internal bus of the base unit to be added. It is assumed that the lower expansion bus control signal is in a reset state (“0”) when the system is started.

  Subsequently, specified information is acquired from the added base unit (step 405), and normal / abnormal determination of the base unit is performed based on the acquired information (step 406).

  Here, if it is determined that the added base unit is normal (YES in step 406), the process proceeds to step 408, and the first stage storage area of the internal register of the added base unit contains the lower expansion bus control. The reset state (“0”) of the signal is written. Then, by the action of the second function incorporated in the above-described lower expansion bus control means, the lower expansion bus gate of the base unit located at the lowermost stage is operated from the ON state to the OFF state, and is added thereby. There is no conduction between the internal bus of the base unit and the lower external lead-out port. On the other hand, when it is determined that the added base unit is abnormal (step 406 NO), the addition is recognized as failed (step 407), and the first storage of the internal register of the lowest base is performed. The reset state (“0”) of the lower expansion bus control signal is written in the area (step 409). Then, by the action of the second function incorporated in the lower extension bus control means described above, the lower extension bus gate of the base unit located at the lowermost stage is operated from the ON state to the OFF state, thereby the current lowest stage The internal bus of the base unit located in the base unit and the internal bus of the base unit to be added will become non-conductive. If it is determined in step 402 that the power supply is not normal, it is recognized that the addition of the base unit has failed (step 403), and the process ends. As a timing for executing the processing for adding the online base, for example, it may be configured to periodically execute the processing as part of the repetitive processing of the CPU unit. It is known that the CPU unit executes an initial process after the power is turned on, and then repeatedly executes four processes including a common process, a user program execution process, an I / O refresh process, and a peripheral service process. For example, the processing shown in FIG. 4 can be executed as part of this common processing. Of course, it may be configured to detect that an extension cable has been attached for extension of the base unit, and execute the interrupt process.

  Next, based on the above-described configuration (the circuit configuration and function of the lower expansion bus control means, the internal configuration of the base control circuit, the circuit configuration and function of the power supply state notification circuit, the processing of the CPU unit), the PLC according to this embodiment The operation of the apparatus will be described with reference to the flowchart of FIG.

  As shown in the figure, the user first connects a unit base on which a unit to be added (I / O unit, communication unit, special function unit, etc.) is mounted to an operating system (step 301). That is, in the example of FIG. 1, first, as shown in FIG. 1A, the extension block 3 is prepared, and then, as shown in FIG. 1B, the extension block 2 and the extension block are prepared. 3 are connected by a cable 42. At this time, the expansion block 2 is provided with a lower-side re-sector pull 23a separately from the upper-side re-sector pull 23b.

  Subsequently, the user turns on the additional base power (step 302). That is, in the example of FIG. 1, the additional block 3 as an additional base is turned on by operating a power switch or the like. Then, by operating the power supply state notification circuit 304 described above, a lower base power supply state notification signal is sent from the expansion block 3 to the expansion block 2 via the predetermined signal line and the cable 42. Due to the action of the first function incorporated in the lower expansion bus control means 202, the lower base power supply state notification signal is automatically written in the second storage area (A2) in the internal register 203a.

  Subsequently, the CPU unit side processing (online base addition processing) described above with reference to FIG. 4 is executed (step 303). Then, the CPU unit 12 reads the lower base power supply state notification signal from the second storage area (A2) in the internal register 203a, and since this is “power normal”, the first storage in the internal register 203a. In the area (A1), “1” indicating the set state of the lower expansion bus control signal is written.

  Then, due to the action of the second function incorporated in the lower-stage expansion bus control means 202, the lower-stage expansion bus gate incorporated in the lower-stage expansion bus control means 202 is operated from the OFF state to the ON state. The internal bus 201 of the base unit 20 located at the position and the internal bus 301 of the base unit 30 to be added from now on become conductive, and the addition succeeds. In addition, when the planned success condition is not satisfied, the extension fails as described above.

  That is, if the additional base state is normal (YES in step 304), the base addition ends normally and the operation in the additional system is continued (step 305), whereas the additional base state must be normal. If this is the case (NO in step 304), the base addition ends in failure and returns to the state before the addition (step 306).

  Thus, according to this embodiment apparatus, the lower additional bus gate 601 interposed in the path from the lower receptacle 23a of the lowermost block 2 constituting the existing system to the internal bus 201 is added to the block 3 added. As long as the power is not turned on, it is maintained in the OFF state. Therefore, by disconnecting the power supply of the added block 3 when the connector is mounted, it is possible to avoid an abnormal signal entering the internal bus of the existing system when the connector is mounted. By applying power to the block 3 added after the connector is mounted, the lower expansion bus gate 601 is turned on by itself, so that the added block 3 can be started up smoothly.

  In addition, in this embodiment, since the lower expansion bus control means 102 and the base control circuit 103 are also built in the basic block 1, the operation of connecting the expansion block 2 to the basic block 1 is performed. However, it can be performed while the system is still running.

  In the above embodiment, the present invention is applied to a building block type PLC. However, the present invention incorporates a part of a bus in each unit and connects these units to each other by a connector. Thus, the present invention can also be applied to a backplane-less PLC device in which a series of internal buses appear.

  ADVANTAGE OF THE INVENTION According to this invention, the PLC apparatus which enabled realization of the addition in a block unit (base unit unit) by simple operation, without stopping driving | operation of an apparatus can be provided.

It is an electrical hardware block diagram of the PLC apparatus which concerns on this invention. It is a detailed block diagram of an internal register. It is a flowchart which shows the user operation for addition. It is a flowchart which shows the process of the CPU unit for an online base addition. It is a flowchart which shows the process of a lower stage expansion bus control means. It is the conceptual diagram (the 1) of each circuit comprised by ASIC. It is a conceptual diagram (the 2) of each circuit comprised by ASIC. It is a conceptual diagram (the 3) of each circuit comprised by ASIC. It is explanatory drawing of the allocation method of an absolute address. It is a flowchart which shows the process of the CPU unit for unit / address recognition. It is an external appearance block diagram of a conventional PLC apparatus. It is an electrical hardware block diagram of the conventional PLC apparatus.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Basic block 2 Extension block 3 Extension block 10 Base unit 10a Unit mounting area 11 Power supply unit 12 CPU unit 13 I / O unit 14 Inter-block connection unit 14a Receptacle 20 Base unit 20a Unit mounting area 21 Power supply unit 22 I / O unit 23 Inter-block connection unit 23a Receptacle 30 Base unit 30a Unit mounting area 31 Power supply unit 32 I / O unit 33 Inter-block connection unit 33a Receptacle 41 Cable 41a Plug 41b Plug 42 Cable 42a Plug 42b Plug 101 Internal bus 101a Connection path 102 Lower expansion bus Control means 103 Base control circuit 103a Internal register 201 Internal bus 201a Connection path 201b Connection path 202 Lower expansion bus control means 203 Base control circuit 203a Internal register 204 Power supply state notification circuit 301 Internal bus 301a Connection path 301b Connection path 302 Lower expansion bus control means 303 Base control circuit 303a Internal register 304 Power supply state notification circuit A1 1st Storage area A2 second storage area 601 lower bus gate circuit 602 lower power supply state notification circuit 603 lower power supply state notification circuit 603

Claims (2)

A PLC device in which a basic block and one or more extension blocks are connected via an extension cable,
The basic block is
A plurality of control units including a CPU unit and an I / O unit;
An internal bus connecting those control units,
Including a lower external lead-out port that leads the internal bus to the outside,
Expansion block is
A plurality of control units including I / O units;
An internal bus connecting these control units,
Including an upper-stage external lead-out port that leads the internal bus to the outside, or an upper-stage external lead-out port and a lower-stage side external lead-out port that leads the internal bus to the outside,
Between the lower external lead-out port of the basic block and the upper external lead-out port of the extension block, and the lower external lead-out port of the extension block located on the upper side and the upper external lead-out port of the extension block located on the lower side Are connected via a cable, and a detachable connector is interposed between both ends of the cable and each external outlet.
Each extension block has
A lower expansion bus gate circuit capable of turning on and off between the internal bus and the lower external lead-out port;
The first storage area for storing the lower expansion bus control signal and the second storage area for storing the lower expansion power supply state notification signal, and these storage areas are read or Internal registers made writable,
A power state notification circuit having a function of detecting whether the power is on or off and generating a lower additional power state notification signal to be notified to the upper block; ,
The function of writing the lower expansion power supply state notification signal coming from the expansion block located on the lower side to the second storage area of the internal register and the contents of the lower bus control signal stored in the first storage area of the internal register And a control means having a function to turn on and off the lower expansion bus gate in response,
Accordingly, the PLC device is characterized in that the expansion block added newly and the CPU unit included in the basic block exchange information via an internal register so that the expansion block can be mounted online. A lower expansion bus gate circuit capable of turning on and off between the internal bus and the lower external lead-out port;
The first storage area for storing the lower expansion bus control signal and the second storage area for storing the lower expansion power supply state notification signal, and these storage areas are read or Internal registers made writable,
The function of writing the lower expansion power supply state notification signal coming from the expansion block located on the lower side to the second storage area of the internal register and the contents of the lower bus control signal stored in the first storage area of the internal register 2. The PLC device according to claim 1, wherein a control unit having a function of turning on and off the lower expansion bus gate in response is also provided in the basic block.

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