1364639 九、發明說明： 【發明所屬之技術領域】 本發明係關於透過增設電纜來連設基本區塊及1或2以 上之增設區塊所構成之可程式控制裝置（PLC)。 【先前技術】 透過增設電纜來連設基本區塊及1或2以上之增設區塊 所構成之可程式控制裝置，係已知之先前技術（例如，參照 專利文獻1)。 第11圖顯示此種之可程式控制裝置的一例之外觀構成 圖。如同圖所示，此可程式控制裝置係透過增設電纜來連 設一台之基本區塊1及1台或2台以上（本例中爲2台）之增 設區塊2,3所構成。又，同圖（a)顯示尙未連接增設區塊3 之增設前的狀態，同圖（b)顯示已連接增設區塊3之增設後 的狀態。 基本區塊1係在電源單元11及區塊間連接單元14以外， 亦包含複數個控制單元。本例中係出示cPU單元1 2及3 台I/O單元（包含IN單元、OUT單元及IN，OUT混合單元）13 來作爲控制單元，另外，控制單元亦可包含通信單元（包含 主從通信單元、PLC間通信單元）及各種之特殊功能單元 (PID運算單元、移動控制單元等）。 這些之單元11〜14係分別透過連接器（未圖示），拆卸自 如地裝設於鋪設內部匯流排於主基板上而構成之基底單元 (亦稱爲背板）10上。藉此，CPU單元12及各I/O單元13 係分別透過內部匯流排（未圖示）所連接。 1364639 增設區塊2係在電源單元21及區塊間連接單元23以外， 亦包含複數個控制單元。本例中係出示5台I/O單元（包含 IN單元、OUT單元及IN，OUT混合單元）22來作爲控制單 元，另外’控制單元亦可包含通信單元（包含主從通信單 元、PLC間通信單元）、及各種之特殊功能單元（pid運算單 元、移動控制單元等）。 這些之單元21〜23係分別透過連接器（未圖示），拆卸自 如地裝設於鋪設內部匯流排於主基板上而構成之基底單元 (亦稱爲背面）20上。藉此，各I/O單元22係分別透過內部 匯流排（未圖示）所連接。 增設區塊3係在電源單元31及區塊間連接單元33以外， 亦包含複數個控制單元。本例中亦出示5台I/O單元（包含 IN單元、OUT單元及IN，OUT混合單元）32來作爲控制單 元’另外，控制單元亦可包含通信單元（包含主從通信單 元、PLC間通信單元）、及各種之特殊功能單元（pid運算單 元、移動控制單元等）。 這些之單元31〜33係分別透過連接器（未圖示），拆卸自 如地裝設於鋪設內部匯流排於主基板上而構成之基底單元 (亦稱爲背面）30上。藉此，各I/O單元32係分別透過內部 匯流排（未圖示）所連接。 區塊間連接單元14,23,33係具有大致相同之構造。亦 即，這些之單元14,23,33的背面側係透過基板連接器連接 於基底單元10,20,30上之內部匯流排（未圖示）。另外，在 1364639 這些之單元1 4,23,33的前面側設有將內部匯流排導出至外 部用之作爲外部導出口功能的插座（連接器之一方的連接 構件）。 更具體而言，在基本區塊1之區塊間連接單元14的前 面’設有將鋪設於主基板10上之內部匯流排（參照第12 圖’元件符號101)導出至外部用之作爲下段側外部導出口 功能的插座14 a。 在增設區塊2之區塊間連接單元23的前面，左右並排地 配置有將鋪設於主基板20上之內部匯流排（參照第12圖， 元件符號201)導出至外部用之作爲下段側外部導出口功能 的插座23a ;及將鋪設於主基板20上之內部匯流排（參照第 12圖’元件符號201)導出至外部用之作爲上段側外部導出 口功能的插座23b。 又’在增設區塊3之區塊間連接單元33的前面，左右並 排地配置有將鋪設於主基板30上之內部匯流排（參照第1 2 圖，元件符號301)導出至外部用之作爲下段側外部導出口 功能的插座33a;及將鋪設於主基板30上之內部匯流排（參 照第12圖，元件符號301)導出至外部用之作爲上段側外部 導出口功能的插座33b。 基本區塊1與增設區塊2之間、增設區塊2與增設區塊3 之間係由電纜所連結。亦即，在本例中，基本區塊1之區 塊間連接單元1 4與增設區塊2之區塊間連接單元23之間， 係由電纜41所連結。同樣，增設區塊2之區塊間連接單元 1364639 23與增設區塊3之區塊間連接單元33之間，係由電纜42 所連結。 ' 更具體而言，在電纜41之上段側端部裝設有插頭（連接 器之另一方的連接構件）41a’在電纜41之下段側端部裝設 有插頭41b。同樣，在電纜42之上段側端部裝設有插頭 42a，在電纜42之下段側端部裝設有插頭42b。這些之插頭 係具有大致相同的構造’具有—個電纜引入口及一個連接 口。插頭及引入之電纜的連接，係利用螺絲固定或焊接等 的固定手段所進行。 在由電纜41來連接基本區塊1之區塊間連接單元14與 增設區塊2之區塊間連接單元23之間的情況，插頭4 1 a係 裝設於插座14a，插頭41b係裝設於插座23b。此時，由插 頭41a與插座14a構成可拆卸之連接器，由插頭41b與插 座23b構成可拆卸之連接器。 同樣，在由電纜42來連接增設區塊2之區塊間連接單元 23與增設區塊3之區塊間連接單元33之間的情況，插頭 42a係裝設於插座23a，插頭42b係裝設於插座33b。此時， 由插頭42a與插座23a構成可拆卸之連接器，由插頭42b 與插座33b構成可拆卸之連接器。 換言之，基本區塊1之下段側外部導出口（插座14a)與增 設區塊2之上段側外部導出口（插座23b)之間、及位於上段 側之增設區塊2的下段側外部導出口（插座23a)與位於下段 側之增設區塊3的上段側外部導出口（插座3 3b)之間，係分 1364639 別透過電纜41，42所連接，同時在電纜41，42之兩端與各外 部導出口（插座14a,23a,23b，33a,33b)之間介設可拆卸之連 接器（插座與插頭的組）。 胃12圖爲顯示此種之可程式控制裝置之電性硬體構成 圖。又’圖中，l〇a 2〇a 3〇a係將基底單元1〇 2〇 3〇上之CPU 單元與電源單元以外之單元拆下而露出之區域。 如同圖所示，在基本區塊1之基底單元10的區域l〇a， 設置由ASIC所構成之基底控制電路103。另外，在增設區 塊2之基底單元20的區域20a，分別設置由ASIC所構成之 基底控制電路203及電源狀態通知電路204。又，在增設區 塊3之基底單元30的區域30a，分別設置由ASIC所構成之 基底控制電路3 03及電源狀態通知電路304。 基底控制電路103,203,303，係分別包含內部暫存器 103a，203a,303a。內部暫存器103a，203a，303a係具有相同之 構成者。基底控制電路1 03,203,303係管理對內部暫存器 103a，203a，3 03a之讀寫動作。在內部暫存器儲存有是否對裝 設於該基底單元上之I/O單元、每一控制單元進行供電之 資訊等。CPU單元係透過匯流排線101,201,301而可讀出或 寫入內部暫存器103a，203a，303a之內容。 電源狀態通知電路204,304係分別具有監視電源單元 21,31之狀態，並透過匯流排線206,3 06而將其結果傳遞至 CPU單元的功能》 [專利文獻1]日本特開平6-124103號公報 -10- 1364639 【發明內容】 (發明所欲解決之課題） 然而，在此種之習知的可在區塊單位（基底單元單位）增 設之可程式控制裝置中，當在可程式控制裝置運轉之狀態 下新追加增設區塊而加以連設時，會產生匯流排異常、增 設區塊電源OFF異常等，以致造成運轉的停止。因此爲了 新追加增設區塊而對運轉中之可程式控制裝置進行連設， 則有在此過程中必須停止可程式控制裝置之運轉的問題 點。 本發明係著眼於上述問題點而達成者，其目的在於提供 —種不用停止裝置之運轉，而可實現在區塊單位（基底單元 單位）的增設之可程式控制裝置。 針對本發明之其他目的及作用效果，參照說明書之以下 記述，若是熟悉本行業者應能容易理解》 (解決課題用之手段） 上述課題係藉由具有如下構成之可程式控制所解決。 即’此可程式控制裝置，係透過增設電纜來連設基本區塊 及1或2以上之增設區塊所構成。 基本區塊係包含有：複數個控制單元，係具有CPU單元 及I/O單元；內部匯流排，係對此些控制單元彼此作連結； 及下段側外部導出口，係將內部匯流排導出至外部，增設 區塊係包含有：複數個控制單元，係具有I/O單元；內部 匯流排’係對這些控制單元彼此作連結；及上段側外部導 -11 - 1364639 出口，係將內部匯流排導出至外部，或是，上段側外部導 出口及下段側外部導出口，係將內部匯流排導出至外部。 另外，基本區塊之下段側外部導出口與增設區塊之上段 側外部導出口之間，及位於上段側之增設區塊之下段側外 部導出口與位於下段側之增設區塊之上段側外部導出口之 間，係經由電纜而被連接，同時在電纜之兩端與各外部導 出口之間配置有可拆卸之連接器。 在各增設區塊之各個區塊設有：下段增設匯流排閘電 路，係可進行內部匯流排與下段側外部導出口之間的ON、 OFF ;內部暫存器，係具有記憶下段增設匯流排控制信號用 之第1記憶區域、及記憶下段增設電源狀態通知信號用之 第2記憶區域，同時這些之記憶區域係經由內部匯流排而 可進行讀或寫；電源狀態通知電路，係具有檢測電源是處 於施加狀態還是處於斷開狀態，以產生應通知位於上段之 區塊的下段增設電源狀態通知信號的功能；及控制手段’ 係具有將來自位於下段側之增設區塊的下段增設電源狀態 通知信號寫入內部暫存器之第2記憶區域的功能、及響應 記憶於內部暫存器之第1記憶區域的下段匯流排控制信號 的內容而將下段增設匯流排閘ON，OFF的功能。 藉此，利用新追加之增設區塊與基本區塊內所含有之 CPU單元是經由內部暫存器來進行資訊的交換’而可進行 增設區塊之線上裝設。 根據此種構成，介設於從下段側外部導出口至內部匯流 -12- 1364639 排之路徑上的下段增設匯流排閘，係只要未被施加所追加 之區塊的電源，即維持於OFF狀態，所以，藉由在裝設連 接器時切斷所追加之區塊的電源，可避免在裝設連接器 時，異常信號進入現存之系統的內部匯流排，並且藉由在 裝設連接器後對追加之區塊施加電源，以使下段增設匯流 排閘自動地成爲ON狀態，而可平穩地進行追加之區塊的 起動。 在該可程式控制裝置中，在基本區塊亦可設置：下段增 設匯流排閘電路，係可將內部匯流排與下段側外部導出口 之間0 N、0FF ;內部暫存器，係具有記憶下段增設匯流排 控制信號用之第1記憶區域、及記憶下段增設電源狀態通 知信號用之第2記憶區域，同時這些之記憶區域係經由內 部匯流排而可進行讀或寫；及控制手段’係具有將來自位 於下段側之增設區塊的下段增設電源狀態通知信號寫入內 部暫存器之第2記憶區域的功能 '及響應記憶於內部暫存 器之第1記憶區域的下段匯流排控制信號的內容而將下段 增設匯流排閘ON，OFF的功能。 根據此種構成，對於將增設區塊連接於基.本區塊之作 業，亦可一面繼續系統之運轉一面來進行。 (發明效果） 根據本發明，可提供一種不用停止裝置之運轉’而可實 現在區塊單位（基底單元單位）的增設之可程式控制裝置。 【實施方式】 -13- 1364639 以下，參照附圖詳細說明本發明之可程式控制裝置的一 較佳實施形態。又，本發明之可程式控制裝置的外觀構成 圖係與第11圖相同，在此省略其說明。 第1圖顯示本發明之可程式控制裝置的電性硬體構成 圖。又，圖中，10a，20a,30a係將基底單元ίο，20,30上之CPU 單元與電源單元以外之單元拆下而露出之區域。 如同圖所示，在基本區塊1之基底單元10的區域10a， 分別設置由ASIC所構成之下段增設匯流排控制手段102及 基底控制電路103。另外，在增設區塊2之基底單元20的 區域20a，分別設置由ASIC所構成之下段增設匯流排控制 手段202、基底控制電路203及電源狀態通知電路204。又， 在增設區塊3之基底單元30的區域30a，分別設置由ASIC 所構成之下段增設匯流排控制手段302、基底控制電路303 及電源狀態通知電路3 04。 下段增設匯流排控制手段1 02,202,302係分別包含第6圖 所示之下段增設匯流排閘電路60 1。此下段增設匯流排閘電 路60 1係在各區塊1〜3內，可進行內部匯流排與下段側外 部導出口之間的〇N、OFF。參照第6圖，更爲詳細地說明 下段增設匯流排閘電路601。又，在同圖中之構成要素中， 對與第1圖相同之構成要素，則賦予與第1圖相同之元件 符號。下段增設匯流排閘電路60 1係在延長各區塊之內部 匯流排 101,201,301 的連接路徑 101a，201a，301a 與 101c，201c，3 01c之間介設三態緩衝器601a而構成。各區塊 -14- 1364639 之連接路徑l〇lc，201c，301c係分別連接於作爲下段側外部 導出口之插座14&，233,33&。在三態緩衝器6013之切換輸入 端連接有下段增設匯流排控制信號105a，205a,305a以作爲 切換用之控制信號線。因此，此三態緩衝器60 1 a係依下段 增設匯流排控制信號之邏輯狀態而控制成允許或不允許之 狀態。其結果，此下段增設匯流排閘電路601係可進行內 部匯流排與下段側外部導出口之間的ON ' OFF。 返回第1圖，更爲具體而言，基本區塊1內之下段增設 匯流排控制手段102所含有的下段增設匯流排閘電路 601，係介設於內部匯流排101與插座（下段側外部導出 口）14a之間的連接路徑101a »因此，當下段增設匯流排閘 電路601被設定爲ON狀態時，內部匯流排101與插座14a 之間成爲導通狀態，使得追加之增設區塊的運轉成爲可 能，相反，當下段增設匯流排閘電路60 1被設定爲OFF狀 態時，內部匯流排101與插座14a之間成爲非導通狀態， 可阻止異常信號透過插座14a而從外部侵入。 增設區塊2內之下段增設匯流排控制手段202所含有的 下段增設匯流排閘電路60 1，係介設於內部匯流排20 1與插 座（下段側外部導出口）23a之間的連接路徑201a »即，內部 匯流排201雖具有與插座（下段側外部導出口）23a之連接路 徑 201a、及與插座（上段側外部導出口）23b之連接路徑 20 1 b，但下段增設匯流排閘電路60 1係介設於內部匯流排 2〇1與插座（下段側外部導出口）23a之間的連接路徑201a。 -15- 1364639 因此，當下段增設匯流排閘電路601被設定爲ON狀態時， 內部匯流排201與插座23a之間成爲導通狀態，使得追加 之增設區塊的運轉成爲可能，相反，當下段增設匯流排閘 電路601被設定爲OFF狀態時，內部匯流排201與插座23a 之間成爲非導通狀態，可阻止異常信號透過插座23a而從 外部侵入。 增設區塊3內之下段增設匯流排控制手段302所含有的 下段增設匯流排閘電路60 1，係介設於內部匯流排30 1與插 座（下段側外部導出口）33a之間的連接路徑301a。即，內部 匯流排301雖具有與插座（下段側外部導出口）33a之連接路 徑 301a、及與插座（上段側外部導出口）3 3b之連接路徑 3 0 1 b，但下段增設匯流排閘電路60 1係介設於內部匯流排 301與插座（下段側外部導出口）33a之間的連接路徑301a。 因此，當下段增設匯流排閘電路60 1被設定爲ON狀態時， 內部匯流排30 1與插座3 3 a之間成爲導通狀態，使得追加 之增設區塊的運轉成爲可能，相反，當下段增設匯流排閘 電路601被設定爲OFF狀態時，內部匯流排301與插座33a 之間成爲非導通狀態，可阻止異常信號透過插座3 3 a而從 外部侵入。 基底控制電路 1 03,203,303係分別包含內部暫存器 103a,203a,303a。內部暫存器103a，203a，303a係具有相同之 構成，例如，如第2圖所示，具有複數個之個別內部暫存 器1〜η»在本例中，在第k號之個別暫存器內定義有第1 -16- 1364639 記憶區域A1及第2記億區域A2，其中，在第1記憶區域 A1記憶有「下段增設匯流排控制信號」之狀態（ON/OFF、 "1” / “ 0” ），在第2記憶區域A2記憶有「下段增設電源 狀態通知信號」之狀態（ΟΝ/OFF、 " 1” / “ 0” ）。基底控制 電路1 03,203,3 03係管理對於內部暫存器103a，203a，303a之 讀寫動作。在內部暫存器儲存有是否對裝設於該基底單元 上之I/O單元、每一控制單元進行供電之資訊等。CPU單 元係透過匯流排線1〇1，201，301而可讀出或寫入內部暫存 器 103a，203a，303a 之內容。 電源狀態通知電路 204,304係分別具有監視電源單元 2 1，31之狀態，並透過匯流排線206,306而將其結果傳遞至 CPU單元的功能。 基本區塊1內之下段增設匯流排控制手段1 02係包含第8 圖所示之下段增設電源狀態通知電路603。又，增設區塊 2,3內之下段增設匯流排控制手段202,302係包含第7圖所 示之下段增設電源狀態通知電路602。 參照第8圖，更詳細地說明基本區塊1之下段增設匯流 排控制手段1 02所含有之下段增設電源狀態通知電路 603。又，在同圖中之構成要素中，對與第1圖相同之構成 要素，則賦予與第1圖相同之元件符號。下段增設電源狀 態通知電路603 ’係由將連接路徑107c作爲輸入’而將下 段增設電源狀態通知信號l〇5b作爲輸出之OR電路603a所 構成。此連接路徑l〇7c係在由電纜41連接基本區塊1及 -17- 1364639 增設區塊2之狀態下，與OR電路602b(參照第7圖）之輸出 信號線連接，此OR電路6 02b係將從增設區塊2之電源狀 態通知電路204所輸出之匯流排線206作爲輸入》因此， 位於基本區塊1之下段的增設區塊2的電源單元21之狀 態，係儲存於基本區塊1之內部暫存器l〇3a。 接著，參照第7圖，更爲詳細地說明增設區塊2,3之下 段增設匯流排控制手段202,302所含有之下段增設電源狀 態通知電路602。又，在同圖中之構成要素中，對與第1 圖相同之構成要素，則賦予與第1圖相.同之元件符號。增 設區塊2之下段增設匯流排控制手段202所含有之下段增 設電源狀態通知電路602，係由將連接路徑207c作爲輸 入，而將下段增設電源狀態通知信號205b作爲輸出之OR 電路602a所構成。此連接路徑207c係在由電纜42連接增 設區塊2及增設區塊3之狀態下，與OR電路60 2b之輸出 信號線連接，此OR電路602b係將從增設區塊3之電源狀 態通知電路304所輸出之匯流排線306作爲輸入。因此， 位於增設區塊2之下段的增設區塊3的電源單元31之狀 態，係儲存於增設區塊2之內部暫存器203 a。同樣，在增 設區塊3之內部暫存器303 a，儲存有增設區塊3之下段所 增設之增設區塊的電源單元之狀態。 第5圖爲顯示下段增設匯流排控制手段之處理的流程 圖。在下段增設匯流排控制手段1 〇 2，2 0 2,3 0 2分別組入第1 功能及第2功能’第1功能係如第5 (b)圖所示，具有接收 -18- 1364639 分別來自位於下段之區塊（基底）的電源狀態通知電路 204,304之下段增設電源狀態通知信號（步驟511)，同時將 此信號狀態分別寫入內部暫存器l〇3a,203a, 303a之下段增 設電源狀態通知信號區域（第2記億區域A2)(步驟512);以 及第2功能係如第5(a)圖所示，從內部暫存器 103a，203a，303a之下段增設匯流排控制信號區域（第1記憶 區域A 1)進行狀態讀出（步驟5 0 1 )，若下段增設匯流排控制 信號之狀態被設定爲“ 1 ”時（步驟502、是），進行對應之 下段增設匯流排閘之ON(步驟503)，相反若未被設定爲 “ 1 ”時（步驟502、否），則進行對應之下段增設匯流排閘 的OFF(步驟504) » 換言之，在各下段增設匯流排控制手段1 02,202,302分別 組入第1功能及第2功能，第1功能係將來自位於下段側 之增設區塊的下段增設電源狀態通知信號的狀態寫入內部 暫存器之第2記憶區域（A2)內；以及第2功能係響應記憶 於內部暫存器之第1記憶區域（A 1)的下段匯流排控制信號 的狀態而將下段增設匯流排閘ON，OFF。 另一方面，在搭載於基本區塊1之CPU單元12側，如第 4圖所示’組入追加線上基底（追加線上區塊）用之處理。 即，在此處理中，首先，藉由對此時點位於最下段之區 塊的基底單元之內部暫存器進行存取，讀出此內部暫存器 之第2記憶區域（A2)所記憶的下段增設電源狀態通知信號 的狀態（步驟401)。 •19- 1364639 在此’有關於對此時點位於最下段之區塊的基底單元之 內部暫存器的存取，係利用系統起動時之位址認識結果。 即’在本例中，如第9圖所示，在各基底單元i〇,20,30之 各單元組入基底位置指定信號線1〇1，2〇2,301及加法器 1 08,208,308。各基底單元10,20,30係利用透過電纜41,42 而依序一個接一個式地連結，並藉由加法器108,208,308之 作用，在各基底單元10,20,30自動地分配固有之基底位置 (位址）。 另一方面，在系統之起動時，如第10圖所示，一面對搭 載於各基底單元上之各單元（UNIT)及基底控制電路 103,203,303進行存取（步驟1001)，一面利用確認其反應之 正常/異常（步驟1〇〇2)，針對所有之單元及基底控制電路之 各個反覆地進行（步驟1 004)在該位址認識單元或基底控制 電路之搭載的處理（步驟1 003 )，可獲得位址認識結果。根 據此般獲得之位址認識結果，對上述之此時點位於最下段 之區塊的基底單元之內部暫存器進行存取。 返回第4圖，根據讀出之下段增設電源狀態通知信號的 狀態，進行電源是正常（施加狀態）、還是異常（未施加之狀 態）的判斷（步驟402)。又，此前提係下段增設電源狀態通 知信號的狀態在系統之起動時被設定爲“電源異常”。 在此，當判斷爲電源正常時（步驟402、是）’在此基底單 元之內部暫存器的第1記憶區域（A1)寫入下段增設匯流排 控制信號之設定狀態（“ 1 ”）。於是’藉由組入前述之下段 -20- 1364639 增設匯流排控制手段之第2功能的作用，位於此 基底單元的下段增設匯流排閘，係從OFF狀態被 態操作（步驟404)，藉此，可使得現在位於最下段 元的內部匯流排與其後欲追加之基底單元的內部 爲導通。又，此前提係在系統起動時，下段增設 制信號係被設定爲重設狀態（“ 0”）。 接著’從追加之基底單元取得規定之資訊（步驟 φ 根據此取得之資訊，進行此基底單元之正常/異 (步驟406)。 在此’當追加之基底單元被判定爲正常時（步 是）’則進入步驟408，在追加之基底單元之內部 第1記憶區域寫入下段增設匯流排控制信號的 (“ 〇” ）。於是’藉由組入上述下段增設匯流排控 第2功能的作用，位於此最下段之基底單元的下 流排閘’係從ON狀態被朝〇FF狀態操作，藉此 B 之基底單元之內部匯流排與下段側外部導出口之 導通。相對於此，當追加之基底單元被判定爲異] 406、否），則認識爲此追加失敗（步驟4〇7)，在最 之內部暫存器的第1記憶區域寫入下段增設匯流 號的重設狀態（“ 0”）（步驟409)。於是，藉由組入 增設匯流排控制手段之第2功能的作用，位於此 基底單元的下段增設匯流排閘，係從0N狀態被 態操作’藉此’現在位於最下段之基底單元之內 最下段之 朝ON狀 之基底單 匯流排成 匯流排控 405) > 並 常的判定 驟 406、 暫存器的 重設狀態 制手段之 段增設匯 ，所追加 間成爲非 言時（步驟 下段基底 排控制信 上述下段 最下段之 朝OFF狀 部匯流排 -21 - 1364639 與其後欲追加之基底單元的內部匯流排成爲非導通。又， 當在步驟4 02之處理，判定爲電源不正常時，則認識爲基 底單元之追加失敗（步驟4 03)，並結束此處理。作爲執行此 線上基底追加用之處理的時間點，例如，可考慮作爲Cpu 單元之反覆處理之一部分而周期性地加以執行的構成。已 知CPU單元係在電源ON之後，執行初期處理，其後反覆 執行共同處理、用戶程式執行處理、I/O更新處理、周邊服 務處理之4個處理。例如，作爲共同處理之一部分，可構 成爲執行第4圖所示之處理。當然，爲了增設基底單元， 亦可構成爲檢測裝設有增設電纜之情況，並利用中斷處理 來執行。 其次，以上述構成（下段增設匯流排控制手段之電路構成 及功能、基底控制電路之內部構成、電源狀態通知電路之 電路構成及功能、CPU單元之處理）爲前題，參照第3圖之 流程，說明本實施形態之可程式控制裝置的作用。 如同圖所示，用戶首先將裝設有追加之單元（I/O單元、 通信單元、特殊功能單元等）之基底單元連接於工作中的系 統（步驟301)。即，若爲第1圖之例子的話’首先，如同圖 (a)所示，準備增設區塊3’然後如同圖（b)所示，由電纜42 連結增設區塊2與增設區塊3。此時，在增設區塊2 ’與上 段側插座23b分開’另外準備下段側插座23a° 接著，用戶將追加基底之電源ON(步驟302)。即’若爲 第1圖之例子的話，利用電源開關之操作等對屬追加基底 -22- 1364639 之增設區塊3施加電源。於是，藉由上述電源狀態通 路304進行動作，透過指定之信號線及電纜42將下段 電源狀態通知信號從增設區塊3送至增設區塊2，接 信號，藉由組入下段增設匯流排控制手段202之第1 的作用，自動地將下段基底電源狀態通知信號寫入內 存器203a內之第2記憶區域（A2)。 接著，執行前面參照第4圖說明之CPU單元側之處ί 上基底追加處理）（步驟303)。於是，CPU單元12從內 存器203 a內之第2記憶區域（A2)讀出下段基底電源狀 知信號，同時根據此信號爲"電源正常”之情況，對 暫存器203a內之第1記憶區域（A1)寫入顯示下段增設 排控制信號的設定狀態的"1 ” 。 於是，藉由組入下段增設匯流排控制手段202之第 能的作用，組入下段增設匯流排控制手段202之下段 匯流排閘係從OFF狀態被朝ON狀態操作，藉此，現 於最下段之基底單元20的內部匯流排201與其後欲追 基底單元30的內部匯流301排成爲導通，成爲增設成 又，在預定之成功條件不成立之情況，如前述，成爲 失敗。 亦即，若追加基底之狀態爲正常的話（步驟304、是 底追加正常結束，而繼續追加系統之工作（步驟305)， 於此，若追加基底之狀態不正常的話（步驟304、否）， 底追加失敗，而返回追加前之狀態（步驟306)。 /τη 丸I电 基底 收此 功能 部暫 里（線 部暫 態通 內部 匯流 2功 增設 在位 加之 i功。 增設 )，基 相對 則基 -23- 1364639 如此，根據此實施例裝置，介設於從構成現存系統之最 下段區塊2的下段側插座23a至內部匯流排201之路徑間 的下段增設匯流排閘60 1係爲，只要未被施加所追加之區 塊3的電源，即維持於OFF狀態，所以，藉由在裝設連接 器時切斷所追加之區塊3的電源，可避免在裝設連接器 時，異常信號進入現存之系統的內部匯流排，並且藉由在 裝設連接器後對追加之區塊3施加電源，以使下段增設匯 流排閘60 1自動地成爲ON狀態，而可平穩地進行追加之區 塊3的起動。 此外，在本實施形態中，在基本區塊1內亦配備有下段 增設匯流排控制手段1 02、基底控制電路103，所以，有關 於將增設區塊2連結於基本區塊1之作業，亦可一面繼續 系統之工作一面來進行。 又，在以上之實施形態中，本發明係應用於建構型區塊 之PLC，但本發明亦可應用於無背板型之可程式控制裝 置，此裝置係在各單元內配置匯流排之一部分，並使這些 之單元相互鄰接而由連接器連接，以出現一系列之內部匯 流排》 (產業上之可利用性） 根據本發明，提供一種不用停止裝置之運轉’而可以簡 單之操作來實現在區塊單位（基底單元單位）的增設之可程 式控制裝置。 【圖式簡單說明】 -24- 1364639 第1圖爲本發明之可程式控制裝置的電性硬體構成圖。 第2圖爲內部暫存器之詳細構成圖。 第3圖爲顯示追加用之用戶操作的流程圖。 第4圖爲顯示線上基底追加用之CPU單元的處理之流程 圖。 第5(a)、（b)圖爲顯示下段增設匯流排控制手段之處理的 流程圖。 第6圖爲由ASIC所構成之各電路的槪念圖（其一）。 第7圖爲由ASIC所構成之各電路的槪念圖（其二）《 第8圖爲由ASIC所構成之各電路的槪念圖（其三）。 第9圖爲絕對位址之分配方法的說明圖。 第10圖爲顯示單元/位址認識用之CPU單元之處理的流 程圖。 第1 1(a)、（b)圖爲習知可程式控制裝置之外觀構成圖。 第1 2圖爲習知可程式控制裝置之電性硬體構成圖。 【主要元件符號說明】 1 基 本 區 塊 2 增 設 區 塊 3 增 設 區 塊 10 基 底 單 元 10a 單 元 裝 設區域 11 電 源 單 元 12 CPU 單 元 -25- 13646391364639 IX. Description of the Invention: [Technical Field] The present invention relates to a programmable control device (PLC) comprising a basic block and an additional block of 1 or more by means of an additional cable. [Prior Art] A programmable control device comprising a basic block and an additional block of 1 or more by adding a cable is known in the prior art (for example, refer to Patent Document 1). Fig. 11 is a view showing the appearance of an example of such a programmable control device. As shown in the figure, the programmable control device is constructed by adding a basic block 1 and one or more or more (two in this example) additional blocks 2, 3 via an additional cable. Further, the same figure (a) shows the state before the addition of the additional block 3 is not connected, and the same figure (b) shows the state after the addition of the added block 3 is connected. The basic block 1 is other than the power supply unit 11 and the inter-block connection unit 14, and also includes a plurality of control units. In this example, the cPU unit 12 and the three I/O units (including the IN unit, the OUT unit, and the IN, OUT mixing unit) 13 are shown as the control unit, and the control unit may also include the communication unit (including the master-slave communication). Unit, PLC communication unit) and various special function units (PID operation unit, mobile control unit, etc.). These units 11 to 14 are detachably attached to a base unit (also referred to as a backing plate) 10 which is formed by laying an internal bus bar on a main board via a connector (not shown). Thereby, the CPU unit 12 and each of the I/O units 13 are connected via an internal bus bar (not shown). 1364639 The additional block 2 is connected to the power supply unit 21 and the inter-block connection unit 23, and also includes a plurality of control units. In this example, five I/O units (including IN unit, OUT unit, and IN, OUT mixing unit) 22 are shown as the control unit, and the 'control unit can also include the communication unit (including the master-slave communication unit, PLC-to-PLC communication). Unit), and various special function units (pid arithmetic unit, mobile control unit, etc.). These units 21 to 23 are detachably attached to a base unit (also referred to as a rear surface) 20 formed by laying an internal bus bar on a main board through a connector (not shown). Thereby, each of the I/O units 22 is connected via an internal bus bar (not shown). The additional block 3 is other than the power supply unit 31 and the inter-block connection unit 33, and also includes a plurality of control units. In this example, five I/O units (including IN unit, OUT unit, and IN, OUT mixing unit) 32 are also shown as the control unit. In addition, the control unit may also include a communication unit (including a master-slave communication unit, PLC-to-PLC communication). Unit), and various special function units (pid arithmetic unit, mobile control unit, etc.). These units 31 to 33 are detachably attached to a base unit (also referred to as a rear surface) 30 which is formed by laying an internal bus bar on a main board through a connector (not shown). Thereby, each of the I/O units 32 is connected via an internal bus bar (not shown). The inter-block connection units 14, 23, 33 have substantially the same configuration. That is, the back sides of the units 14, 23, 33 are connected to the internal bus bars (not shown) on the base units 10, 20, 30 through the substrate connectors. Further, on the front side of the units 1 4, 23, 33 of 1364639, a socket (a connecting member which is one of the connectors) for guiding the internal bus bar to the outside as an external outlet function is provided. More specifically, the front side of the inter-block connecting unit 14 of the basic block 1 is provided with an internal bus bar (refer to FIG. 12 'equivalent symbol 101) laid on the main substrate 10 for external use as the lower stage. The socket 14 a of the side external outlet function. In the front surface of the inter-block connecting unit 23 of the additional block 2, an internal bus bar (refer to FIG. 12, component symbol 201) laid on the main substrate 20 is arranged side by side to the outside for use as a lower side external portion. The outlet 23a of the outlet function; and the internal bus bar (refer to FIG. 12 'component symbol 201) laid on the main substrate 20 are led to the external socket 23b which functions as the upper side outer outlet. Further, in the front surface of the inter-block connecting unit 33 of the additional block 3, an internal bus bar (see FIG. 2, element symbol 301) laid on the main substrate 30 is arranged side by side to be externally arranged. The socket 33a having the function of the lower side outer outlet port; and the inner bus bar (refer to FIG. 12, the reference numeral 301) placed on the main substrate 30 are led to the socket 33b for external use as the upper side outer outlet function. Between the basic block 1 and the additional block 2, the additional block 2 and the additional block 3 are connected by a cable. That is, in this example, the inter-block connecting unit 14 of the basic block 1 and the inter-block connecting unit 23 of the add-on block 2 are connected by a cable 41. Similarly, the inter-block connecting unit 1364639 23 of the add-on block 2 and the inter-block connecting unit 33 of the add-on block 3 are connected by a cable 42. More specifically, a plug (the other connecting member of the connector) 41a' is attached to the upper end portion of the cable 41, and a plug 41b is attached to the lower end portion of the cable 41. Similarly, a plug 42a is attached to the upper end portion of the cable 42 and a plug 42b is attached to the lower end portion of the cable 42. These plugs have substantially the same construction 'having a cable entry port and a connector port. The connection of the plug and the introduced cable is carried out by means of fixing means such as screw fixing or welding. In the case where the cable 41 is connected between the inter-block connecting unit 14 of the basic block 1 and the inter-block connecting unit 23 of the add-on block 2, the plug 4 1 a is mounted on the socket 14a, and the plug 41b is mounted. At the socket 23b. At this time, the detachable connector is constituted by the plug 41a and the socket 14a, and the detachable connector is constituted by the plug 41b and the socket 23b. Similarly, in the case where the cable 42 is connected between the inter-block connecting unit 23 of the add-on block 2 and the inter-block connecting unit 33 of the add-on block 3, the plug 42a is mounted on the socket 23a, and the plug 42b is mounted. At the socket 33b. At this time, the detachable connector is constituted by the plug 42a and the socket 23a, and the detachable connector is constituted by the plug 42b and the socket 33b. In other words, between the lower section side outer outlet port (socket 14a) of the basic block 1 and the upper side outer side outlet port (outlet 23b) of the extension block 2, and the lower section side outer side outlet of the additional block 2 of the upper section side ( Between the socket 23a) and the upper side outer lead-out port (socket 33b) of the additional block 3 on the lower stage side, the branch 1364639 is connected through the cables 41, 42 at the both ends of the cables 41, 42 and the outside. A detachable connector (a set of sockets and plugs) is interposed between the outlets (sockets 14a, 23a, 23b, 33a, 33b). The stomach 12 is a diagram showing the electrical hardware composition of such a programmable control device. Further, in the figure, l〇a 2〇a 3〇a is an area in which the CPU unit on the base unit 1〇 2〇 3〇 and the unit other than the power supply unit are removed and exposed. As shown in the figure, in the area 10a of the base unit 10 of the basic block 1, a base control circuit 103 composed of an ASIC is provided. Further, a base control circuit 203 composed of an ASIC and a power source state notification circuit 204 are provided in the region 20a of the base unit 20 of the add-on block 2, respectively. Further, a base control circuit 303 composed of an ASIC and a power source state notification circuit 304 are provided in the region 30a of the base unit 30 of the add-on block 3, respectively. The base control circuits 103, 203, 303 respectively include internal registers 103a, 203a, 303a. The internal registers 103a, 203a, 303a have the same constituents. The base control circuit 103, 203, 303 manages the read and write operations to the internal registers 103a, 203a, 03a. The internal register stores information on whether or not the I/O unit mounted on the base unit, each control unit is powered, and the like. The CPU unit can read or write the contents of the internal registers 103a, 203a, 303a through the bus bars 101, 201, 301. The power supply state notification circuits 204 and 304 respectively have the functions of monitoring the state of the power supply units 21 and 31 and transmitting the results to the CPU unit through the bus bars 206 and 306. [Patent Document 1] Japanese Patent Laid-Open No. Hei 6-124103 -10- 1364639 [Problem to be Solved by the Invention] However, in such a programmable control device which can be added in a block unit (base unit), when it is operated in a programmable control device When a new block is added and connected, the bus bar is abnormal, and the block power supply OFF is abnormal, which causes the operation to stop. Therefore, in order to newly add an additional block and connect the programmable control device in operation, there is a problem that the operation of the programmable control device must be stopped in the process. The present invention has been made in view of the above problems, and an object thereof is to provide a programmable control device that can be added to a block unit (base unit unit) without stopping the operation of the device. Other objects and effects of the present invention will be described below with reference to the specification. If it is familiar to the industry, it should be easy to understand. (The means for solving the problem) The above problems are solved by programmable control having the following configuration. That is, the programmable control device is constructed by adding a basic block and an additional block of 1 or more by adding a cable. The basic block system includes: a plurality of control units having CPU units and I/O units; an internal bus bar for connecting the control units to each other; and a lower side external outlet for exporting the internal bus bars to Externally, the additional block system includes: a plurality of control units having I/O units; an internal bus bar' connecting these control units to each other; and an upper side outer guide -11 - 1364639 exit, which is an internal bus bar Exported to the outside, or the upper outer side outlet and the lower side outer outlet, the internal bus bar is exported to the outside. In addition, between the lower outer side outlet of the basic block and the outer side outer outlet of the additional block, and the lower outer side outlet of the additional block on the upper side and the upper side of the upper part of the additional block on the lower side Between the outlets, they are connected via a cable, and a detachable connector is disposed between the two ends of the cable and each of the external outlets. In each block of each additional block, there is: a busbar circuit in the lower section, which can turn ON and OFF between the internal bus bar and the lower side outer lead port; the internal register has an additional busbar in the lower memory section. The first memory area for the control signal and the second memory area for the power state notification signal are added to the lower memory section, and the memory areas are read or written via the internal bus; the power status notification circuit has the detection power supply Whether it is in an applied state or in an open state to generate a function of notifying a lower power supply state notification signal in a lower segment of the block located in the upper segment; and the control means 'having a notification of adding a power state from the lower segment of the additional block located on the lower segment side The function of writing the signal to the second memory area of the internal register and the function of turning on and off the bus switch in the lower stage in response to the contents of the lower bus control signal stored in the first memory area of the internal register. Thereby, the newly added extension block and the CPU unit included in the basic block are exchanged by the internal temporary memory, and the additional block can be installed on the line. According to this configuration, the lower-side add-up busbar that is disposed on the path from the lower-side outer-side outlet to the inner-portion-12-1364639 row is maintained in the OFF state as long as the power of the added block is not applied. Therefore, by cutting off the power of the added block when installing the connector, it is possible to prevent the abnormal signal from entering the internal busbar of the existing system when the connector is installed, and by installing the connector Power is applied to the additional block so that the lower-addition bus bar gate is automatically turned ON, and the additional block can be smoothly started. In the programmable control device, the basic block can also be set: the lower section is provided with a busbar gate circuit, which can be between 0 N and 0FF between the inner bus bar and the lower side outer lead port; the internal register has a memory In the lower stage, the first memory area for the bus control signal and the second memory area for the power state notification signal are added to the lower stage, and the memory areas are read or written via the internal bus; and the control means The function of writing the lower power supply state notification signal from the lower segment of the additional block located on the lower side to the second memory area of the internal register and the lower bus control signal responsive to the first memory area of the internal register In the next section, the function of turning on and off the busbars is added. According to this configuration, the operation of connecting the additional block to the base block can be performed while continuing the operation of the system. (Effect of the Invention) According to the present invention, it is possible to provide a programmable control device which can realize the addition of a block unit (base unit unit) without stopping the operation of the device. [Embodiment] - 13 - 1364639 Hereinafter, a preferred embodiment of the programmable control device of the present invention will be described in detail with reference to the accompanying drawings. Further, the external configuration of the programmable control device of the present invention is the same as that of Fig. 11, and the description thereof is omitted here. Fig. 1 is a view showing the electrical hardware configuration of the programmable control device of the present invention. Further, in the figure, 10a, 20a, and 30a are areas in which the CPU unit and the unit other than the power supply unit on the base unit ίο, 20, 30 are removed. As shown in the figure, in the region 10a of the base unit 10 of the basic block 1, a busbar control means 102 and a base control circuit 103 are provided, respectively, which are constituted by the ASIC. Further, in the region 20a of the base unit 20 of the additional block 2, a lower busbar control means 202, a base control circuit 203, and a power state notification circuit 204, which are constituted by the ASIC, are provided. Further, in the region 30a of the base unit 30 in which the block 3 is added, a lower busbar control means 302, a base control circuit 303, and a power state notification circuit 304 are formed by the ASIC. The lower section of the upper busbar control means 102, 202, 302 respectively includes the lower section of the busbar gate circuit 601 shown in Fig. 6. In the lower stage, the bus bar circuit 60 1 is added to each of the blocks 1 to 3, and 〇N and OFF between the inner bus bar and the lower outer side outlet port can be performed. Referring to Fig. 6, the busbar gate circuit 601 is added in more detail in the lower stage. In the constituent elements in the same drawing, the same components as those in the first embodiment are denoted by the same reference numerals as those in the first embodiment. The lower stage additional bus bar circuit 60 1 is constructed by extending a tristate buffer 601a between the connection paths 101a, 201a, 301a and 101c, 201c, 310c of the inner bus bars 101, 201, 301 of each block. The connection paths l〇lc, 201c, 301c of the respective blocks -14 - 1364639 are respectively connected to the sockets 14 & 233, 33 & as the lower-side external outlets. At the switching input terminal of the tristate buffer 6013, a lower stage add bus control signal 105a, 205a, 305a is connected as a control signal line for switching. Therefore, the tristate buffer 60 1 a is controlled to a permitted or disallowed state by adding the logic state of the bus bar control signal to the lower stage. As a result, in the lower stage, the bus bar circuit 601 is added to enable ON 'OFF between the inner bus bar and the lower side outer lead port. Referring back to FIG. 1 , more specifically, the lower section of the basic block 1 is provided with a lower-addition busbar circuit 601 included in the bus bar control means 102, which is disposed in the internal bus bar 101 and the socket (the lower side external guide) The connection path 101a between the outlets 14a » Therefore, when the lower stage extension bus gate circuit 601 is set to the ON state, the internal bus bar 101 and the outlet 14a are turned on, making it possible to operate the additional additional block. On the other hand, when the lower stage bus bar circuit 60 1 is set to the OFF state, the internal bus bar 101 and the socket 14a are in a non-conduction state, and an abnormal signal can be prevented from entering the socket 14a from the outside. In the lower section of the additional block 2, the lower-stage additional bus-bar gate circuit 601 included in the bus bar control means 202 is connected to the connection path 201a between the inner bus bar 20 1 and the socket (lower-side outer lead-out port) 23a. In other words, the internal bus bar 201 has a connection path 201a with the socket (lower side outer lead-out port) 23a and a connection path 20 1b with the socket (upper side outer lead-out port) 23b, but a bus bar gate circuit 60 is added to the lower stage. 1 is a connection path 201a interposed between the inner bus bar 2〇1 and the socket (lower side outer lead-out port) 23a. -15- 1364639 Therefore, when the lower stage bus bar circuit 601 is set to the ON state, the internal bus bar 201 and the socket 23a are in an on state, so that the operation of the additional additional block is possible, and conversely, when the lower section is added When the bus gate circuit 601 is set to the OFF state, the internal bus bar 201 and the socket 23a are rendered non-conductive, and an abnormal signal can be prevented from entering the socket 23a and from the outside. The lower stage additional bus bar circuit 60 1 included in the upper section of the additional block 3 is provided with a connection path 301a interposed between the inner bus bar 30 1 and the socket (lower side outer lead outlet) 33a. . That is, the internal bus bar 301 has a connection path 301a with the socket (lower side outer lead-out port) 33a and a connection path 3 0 1 b with the socket (upper side outer lead-out port) 3bb, but a bus bar gate circuit is added in the lower stage. 60 1 is a connection path 301a interposed between the inner bus bar 301 and the socket (lower side outer lead-out port) 33a. Therefore, when the lower stage bus bar circuit 60 1 is set to the ON state, the internal bus bar 30 1 and the socket 3 3 a are turned on, making it possible to operate the additional block, and conversely, when the lower block is added When the bus gate circuit 601 is set to the OFF state, the internal bus bar 301 and the socket 33a are rendered non-conductive, and an abnormal signal can be prevented from entering the socket 3 3 a from the outside. The base control circuit 1 03, 203, 303 includes internal registers 103a, 203a, 303a, respectively. The internal registers 103a, 203a, and 303a have the same configuration. For example, as shown in FIG. 2, there are a plurality of individual internal registers 1 to η». In this example, the individual temporary storage of the kth The first -16 - 1364639 memory area A1 and the second channel area A2 are defined in the device, and the state of the "lower stage bus line control signal" is stored in the first memory area A1 (ON/OFF, "1" / "0"), in the second memory area A2, the state of "lower power supply state notification signal" (ΟΝ/OFF, " 1" / "0") is stored in the second memory area A2. The base control circuit 1 03, 203, 3 03 is managed by Read and write operations of the internal registers 103a, 203a, and 303a. The internal buffer stores information on whether or not the I/O unit mounted on the base unit and each control unit are powered. The bus lines 1〇, 201, 301 can read or write the contents of the internal registers 103a, 203a, 303a. The power status notification circuits 204, 304 respectively have the status of the monitoring power supply unit 2 1, 31 and are transmitted through the confluence. Lines 206, 306 and pass the results to the CPU unit's work The busbar control means 102 is included in the lower section of the basic block 1, and the power supply state notification circuit 603 is added to the lower section shown in Fig. 8. Further, the busbar control means 202 is added to the lower section of the additional block 2, 3, and the 302 system includes The power supply state notification circuit 602 is added to the lower stage shown in Fig. 7. Referring to Fig. 8, the lower stage power supply state notification circuit 603 included in the lower section of the basic block 1 is explained in more detail. Among the components in the same figure, the same components as those in Fig. 1 are denoted by the same reference numerals as those in Fig. 1. The lower power supply state notification circuit 603' adds the lower segment by using the connection path 107c as the input '. The power state notification signal l〇5b is configured as an output OR circuit 603a. This connection path l〇7c is connected to the OR block 602b in a state in which the basic block 1 and the -17-1364639 add block 2 are connected by the cable 41 ( Referring to the output signal line of FIG. 7), the OR circuit 205b receives the bus bar 206 output from the power state notification circuit 204 of the add-on block 2 as an input. The state of the power supply unit 21 of the add-on block 2 in the lower part of the block 1 is stored in the internal register l〇3a of the basic block 1. Next, referring to Fig. 7, the additional block 2, 3 will be described in more detail. In the lower stage, the bus bar control means 202, 302 includes a power supply state notification circuit 602 in the lower stage. Further, in the components in the same figure, the same components as those in the first figure are assigned to the first picture. Component symbol. The lower power supply state notification circuit 602 including the lower segment of the bus bar control means 202 in the lower block of the additional block 2 is constituted by the OR circuit 602a which uses the connection path 207c as an input and the lower power supply state notification signal 205b as an output. The connection path 207c is connected to the output signal line of the OR circuit 60 2b in a state where the extension block 2 and the extension block 3 are connected by the cable 42, and the OR circuit 602b notifies the circuit from the power state of the extension block 3. The bus bar 306 outputted by 304 is used as an input. Therefore, the state of the power supply unit 31 of the add-on block 3 located in the lower section of the add-on block 2 is stored in the internal register 203a of the add-on block 2. Similarly, in the internal register 303a of the add block 3, the state of the power supply unit of the add-on block added to the lower portion of the add block 3 is stored. Fig. 5 is a flow chart showing the processing of adding a busbar control means in the lower section. In the lower section, the bus control means 1 〇2, 2 0 2, 3 0 2 are respectively incorporated into the first function and the second function. The first function is as shown in the fifth (b), and has the reception -18 - 1364639 respectively. A power state notification signal is added from the lower portion of the power state notification circuit 204, 304 located in the lower block (substrate) (step 511), and the signal state is written to the internal buffers 〇3a, 203a, 303a, respectively. a status notification signal area (2nd Billion Area A2) (step 512); and a second function system as shown in FIG. 5(a), adding a bus bar control signal area from the lower part of the internal registers 103a, 203a, 303a (The first memory area A 1) performs status reading (step 501), and if the state of the lower side added bus control signal is set to "1" (step 502, YES), the corresponding lower section is added to the bus bar ON (step 503), if not set to "1" (step 502, NO), the corresponding lower section is added to the lower limit of the bus gate (step 504) » In other words, the busbar control means is added in each lower section. 1 02, 202, 302 respectively enter the first function and the second function The first function writes the state of the power supply state notification signal from the lower segment of the add-on block located on the lower side to the second memory area (A2) of the internal register; and the second function response is internally stored in the temporary memory. The state of the lower busbar control signal in the first memory area (A1) of the device turns ON and OFF the upper busbar switch. On the other hand, in the CPU unit 12 side mounted on the basic block 1, as shown in Fig. 4, the processing for the base line (additional line block) is added to the additional line. That is, in this process, first, by accessing the internal register of the base unit of the block at the lowermost time point, the second memory area (A2) of the internal register is read. The state of the power state notification signal is added to the lower stage (step 401). • 19-1364639 Here, the access to the internal register of the base unit at the time of the lowermost block is used to recognize the result using the address at the start of the system. That is, in this example, as shown in Fig. 9, each of the base units i, 20, 30 is grouped into the base position designation signal lines 1〇1, 2〇2, 301 and the adders 1 08, 208, 308. Each of the base units 10, 20, 30 is sequentially connected one by one by means of the transmission cables 41, 42 and automatically assigns an inherent base position to each of the base units 10, 20, 30 by the action of the adders 108, 208, 308. (address). On the other hand, when the system is started up, as shown in Fig. 10, each unit (UNIT) and the base control circuits 103, 203, and 303 mounted on the respective base units are accessed (step 1001), and the reaction is confirmed by use. Normal/abnormal (step 1〇〇2), for each of the unit and the base control circuit (step 1 004), the processing of the address recognition unit or the base control circuit is carried out (step 1 003), The address recognition result can be obtained. Based on the address recognition result obtained in this way, the internal register of the base unit of the block at the lowermost stage is accessed. Returning to Fig. 4, the state in which the power source is normal (applied state) or abnormal (unapplied state) is judged based on the state in which the power state notification signal is added in the lower stage of reading (step 402). Further, this premise is that the state in which the power state notification signal is added in the lower stage is set to "power supply abnormality" at the time of system startup. Here, when it is determined that the power source is normal (step 402, YES), the first memory area (A1) of the internal register of the base unit is written in the set state ("1") of the lower stage add bus control signal. Thus, by adding the second function of the busbar control means to the lower section -20-1364639, a busbar gate is added to the lower section of the base unit, and is operated from the OFF state (step 404). , the internal bus bar which is now located in the lowermost segment can be turned on with the inside of the base unit to be added later. Also, this premise is that when the system is started, the lower-end add-on signal system is set to the reset state ("0"). Then, 'the specified information is obtained from the added base unit (step φ according to the information obtained, the normal/different of the base unit is performed (step 406). Here, when the additional base unit is judged to be normal (step is) 'Go to step 408, and write the second busbar control signal ("〇") in the first memory area of the additional base unit. Then, by adding the second function of the busbar control to the lower segment, The downstream gate of the base unit located at the lowermost stage is operated from the ON state to the 〇FF state, whereby the internal bus bar of the base unit of B is electrically connected to the lower side outer lead outlet. In contrast, the additional base is added. If the unit is judged to be different, 406, No), it is recognized that the addition is unsuccessful (step 4〇7), and the reset state of the next-stage added stream number is written in the first memory area of the internal buffer ("0"). ) (step 409). Therefore, by the function of the second function of assembling the busbar control means, the busbar gate is added in the lower section of the base unit, and is operated from the 0N state by the state of "thereby" which is now located in the base unit of the lowermost section. In the lower stage, the ON-shaped single-single bus is arranged in the bus-discharge control 405) > and the usual determination step 406, the resetting state of the register is added to the segment, and the additional time becomes non-speech (the lower stage of the step) The inner control bus of the base unit of the lowermost section of the lower section of the lower section is -21648639, and the internal busbar of the base unit to be added later becomes non-conducting. Further, when it is determined in step 502 that the power supply is abnormal, Then, it is recognized that the addition of the base unit has failed (step 4 03), and the processing is ended. As a time point for performing the processing for adding the base on the line, for example, it can be periodically executed as part of the reverse processing of the CPU unit. It is known that the CPU unit performs initial processing after the power is turned ON, and then repeatedly performs common processing, user program execution processing, and I/O update processing. For example, as part of the common processing, it is possible to perform the processing shown in Fig. 4. Of course, in order to add the base unit, it is also possible to detect that the additional cable is installed and use it. The above-mentioned configuration (the circuit configuration and function of the busbar control means in the lower stage, the internal structure of the base control circuit, the circuit configuration and function of the power supply state notification circuit, and the processing of the CPU unit) are prefaced. The operation of the programmable control device of the present embodiment will be described in the flowchart of Fig. 3. As shown in the figure, the user first connects the base unit to which the added unit (I/O unit, communication unit, special function unit, etc.) is attached. The system in operation (step 301). That is, if it is the example of the first figure, 'Firstly, as shown in the figure (a), the additional block 3' is prepared and then connected by the cable 42 as shown in the figure (b). The block 2 and the additional block 3 are added. At this time, the additional block 2' is separated from the upper-side socket 23b', and the lower-side socket 23a is additionally prepared. Then, the user will add The power supply of the bottom is turned ON (step 302). That is, if the example of Fig. 1 is used, power is applied to the additional block 3 of the additional substrate 22-1364639 by the operation of the power switch, etc. 304 operates to transmit the lower power state notification signal from the add block 3 to the add block 2 through the designated signal line and cable 42, and connect the signal, and the first action of the bus bar control means 202 is added by the group. The lower base power state notification signal is automatically written in the second memory area (A2) in the memory 203a. Next, the base unit addition processing is performed on the CPU unit side described above with reference to Fig. 4 (step 303). Then, the CPU unit 12 reads out the lower-stage base power-like signal from the second memory area (A2) in the memory 203a, and at the same time, according to the case that the signal is "normal power", the first one in the register 203a. The memory area (A1) is written to display ""1" of the setting state of the lower row addition control signal. Then, by arranging the function of the third stage to add the energy of the bus bar control means 202, the lower part of the bus bar control means 202 is connected to the lower stage, and the bus bar is operated from the OFF state to the ON state, thereby being in the lowermost stage. The internal bus bar 201 of the base unit 20 and the internal bus 301 of the base unit 30 are subsequently turned on, and are added, and the predetermined success condition is not established. As described above, it becomes a failure. In other words, if the state of the additional base is normal (step 304, the bottom addition is normally completed, and the operation of the additional system is continued (step 305). If the state of the additional base is not normal (step 304, NO), The bottom addition fails, and returns to the state before the addition (step 306). /τη Pill I electric base receives the function part temporarily (the line part transient internal internal flow 2 power addition is set in place plus i work. Add), base relative Base -23- 1364639 Thus, according to the apparatus of this embodiment, the busbar gate 60 1 is added to the lower section between the paths from the lower-stage side socket 23a constituting the lowermost stage block 2 of the existing system 2 to the internal bus bar 201, As long as the power of the added block 3 is not applied, that is, it is maintained in the OFF state. Therefore, when the power supply of the added block 3 is cut off when the connector is mounted, it is possible to avoid an abnormality when the connector is mounted. The signal enters the internal bus bar of the existing system, and by applying power to the additional block 3 after installing the connector, the lower-stage add-in bus bar gate 60 1 is automatically turned ON, and the tracking can be smoothly performed. In addition, in the present embodiment, the lower block addition control means 102 and the base control circuit 103 are also provided in the basic block 1, so that the additional block 2 is connected to the basic block. The operation of the block 1 can also be carried out while continuing the operation of the system. Further, in the above embodiments, the present invention is applied to a PLC of a built-in block, but the present invention can also be applied to a backless type. Programmable control device that configures one of the busbars in each unit and connects the units to each other and is connected by a connector to present a series of internal busbars (industrial availability) according to the present invention. The invention provides a programmable control device capable of realizing the addition of a block unit (base unit unit) without a stop operation of the device. [Simple description of the drawing] -24-1364639 FIG. 1 is the present invention The electrical hardware of the programmable control device is shown in Fig. 2. Fig. 2 is a detailed configuration diagram of the internal register. Fig. 3 is a flow chart showing the user operation for adding. Flowchart for processing the CPU unit for adding an on-line base. Sections 5(a) and (b) are flowcharts showing the process of adding a busbar control means in the lower stage. Fig. 6 is a circuit composed of an ASIC. The commemorative diagram (the first one). Fig. 7 is a commemorative diagram of each circuit composed of ASICs (Part 2). Figure 8 is a commemorative diagram of each circuit composed of ASICs (Part 3). Figure 9 is an explanatory diagram of the allocation method of the absolute address. Fig. 10 is a flow chart showing the processing of the CPU unit for the unit/address recognition. The 1st (1) and (b) diagrams are conventional programmable control. The appearance of the device is shown in Fig. 12. Fig. 2 is a diagram showing the electrical structure of a conventional programmable control device. [Main component symbol description] 1 Basic block 2 Add block 3 Add block 10 Base unit 10a Unit installation area 11 Power unit 12 CPU unit -25- 1364639
13 I/O單元 14 區塊間連接單元 14a 插座 20 基底單元 20a 單元裝設區域 2 1 電源單元 22 I/O單元 23 區塊間連接單元 23a 插座 30 基底單元 30a 單元裝設區域 3 1 電源單元 32 I/O單元 33 區塊間連接單元 33a 插座 4 1 電纜 41a 插頭 41b 插頭 42 電纜 42a 插頭 42b 插頭 101 內部匯流排 101a 連接路徑 -26- 136463913 I/O unit 14 Inter-block connection unit 14a Socket 20 Base unit 20a Unit mounting area 2 1 Power supply unit 22 I/O unit 23 Inter-block connection unit 23a Socket 30 Base unit 30a Unit mounting area 3 1 Power supply unit 32 I/O unit 33 Inter-block connection unit 33a Socket 4 1 Cable 41a Plug 41b Plug 42 Cable 42a Plug 42b Plug 101 Internal bus bar 101a Connection path -26- 1364639
102 下段i 曾設匯流排控制手段 103 基底控制電路 103a 內 部 暫 存 器 201 內 部 匯 流 排 201 a 連 接 路 徑 20 1 b 連 接 路 徑 202 下 段 增 設 匯 流 排 控制 手 段 203 基 底 控 制 電 路 203a 內 部 暫 存 器 204 電 源 狀 態 通 知 電 路 301 內 部 匯 流 排 301a 連 接 路 徑 301b 連 接 路 徑 302 下 段 增 設 匯 流 排 控.制 手 段 303 基 底 控 制 電 路 303 a 內 部 暫 存 器 304 電 源 狀 態 通 知 電 路 A1 第 1 記 憶 丨品- 域 A2 第 2 記 憶 區 域 60 1 下 段 增 設 匯 流 排 閘電 路 602 下 段 增 設 電 源 狀 態通 知 電 路 603 下 段 增 設 電 源 狀 態通 知 電 路 -27-102 lower section i has set busbar control means 103 base control circuit 103a internal register 201 internal busbar 201 a connection path 20 1 b connection path 202 lower section additional bus control means 203 base control circuit 203a internal register 204 power state Notification circuit 301 internal bus 301a connection path 301b connection path 302 lower stage additional bus arrangement control means 303 base control circuit 303 a internal register 304 power supply state notification circuit A1 first memory product - domain A2 second memory area 60 1 Adding the bus bar circuit 602 in the lower section Adding the power state notification circuit 603 in the lower section Adding the power state notification circuit -27-