JPH06202714A - Parallel input/output device - Google Patents

Abstract

PURPOSE:To continue the control of each equipment and also to replace a faulty I/O card with another I/O card without turning off the power source of a power supply card and without stopping the operation of a programmable controller even in the case of a fault of either of I/O cards. CONSTITUTION:An A-side I/O card 6 and a B-side I/O card 7 constitute an I/O card pair 38, and normal one of these I/O cards 6 and 7 is automatically selected and used by a switch card 8 corresponding to the I/O card pair 38. When the A-side I/O card 6 or the B-side I/O card 7 is faulty, power switches 50 and 57 provided in the substrate of the faulty I/O card 6 or 7 are turned off to electrically interrupt the faulty I/O card, an internal I/O bus 17 and a power bus 13.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel input / output device which is connected to a programmable controller used for process control of a plant or the like and which inputs / outputs data at high speed.

[0002]

2. Description of the Related Art Conventional parallel input / output devices that are connected to a programmable controller used for process control of a plant or the like and input / output data at high speed have been conventionally used.
The device shown in FIG. 10 is known.

Each parallel input / output device 101 shown in this figure
Are the I / O chassis 102 and the power supply card 1 respectively.
03, power supply bus 104, and interface card 10
5, internal I / O bus 106, and multiple I / O cards 1
And I / O bus 108 and branch I / O.
Programmable controller (PL
C) It is serially connected to 110 and fetches a control command or control data for each device (not shown) output from the programmable controller 110 and supplies them in parallel to each device, or each of these devices. Process data or the like input from the CPU is fetched in parallel and supplied to the programmable controller 110.

The I / O chassis 102 is composed of an enclosure formed in a rectangular shape and a plurality of rails arranged in the enclosure. The power supply card 103, the interface card 105, and each I / O card. When the 107 is set, the power supply card 104 and the internal I / O bus 106 arranged on the inner surface of the housing are used to supply these power supply cards 1.
03, interface card 105, each I / O card 1
07 are connected to each other.

The power supply card 103 is provided with a substrate which is removably inserted into the I / O chassis 102, a power circuit provided on the substrate, and the like.
When it is plugged into the O chassis 102, it takes in an external AC power source to generate a DC voltage of a preset value, and the DC voltage is supplied via a power bus 104 attached to the I / O chassis 102. A voltage is supplied to the interface card 105 and each I / O card 107 to operate them.

The interface card 105 has the I / O
The I / O chassis 102 includes a substrate that is detachably inserted and a buffer circuit 112 that is provided on the substrate and that amplifies the attenuated bus signal to shape the waveform.
The internal I / O bus 10 is connected to the programmable controller 110 and another parallel input / output device 101 by an O bus 108 and a branch I / O bus 109.
6 is connected to each of the I / O cards 107, and when a control command or control data is output from the programmable controller 110, the control command or control data is captured and waveform-shaped and supplied to another parallel input / output device 101. Or each I / O card 10 via the internal I / O bus 106
Or supply to 7. In addition, another parallel input / output device 1
When process data is input from 01, branch I /
This is taken in through the O bus 109, waveform shaped and supplied to the programmable controller 110, and when process data is output from each I / O card 107, the process data is taken in and waveform shaped to the programmable controller 110. It is supplied to the controller 110.

Each of the I / O cards 107 has the I / O card
The O chassis 102 includes a substrate that is detachably inserted and an input / output circuit provided on the substrate.
When a control command or control data is output from the interface card 105, it is captured via the internal I / O bus 106 and then supplied to each device via an external input / output cable 113. External I / O cable 113 when process data is input from the device
After taking it in via the internal I / O bus 1
It is supplied to the interface card 105 via 06.

[0008]

By the way, in such a conventional parallel input / output device 101, each I / O card 10 set in the I / O chassis 102 is arranged.
If any one of 7 breaks down, data cannot be input / output through the I / O card 107 until the I / O card 107 is replaced, and the I / O card 107 is connected to the I / O card 107. There was a problem that the control of the equipment had to be stopped.

Further, since the input / output terminals of the I / O card 107 are connected to the internal I / O bus 106 while the power is supplied to the I / O card 107, the failed I / O card 107 Power supply card 1 when replacing
There was a problem that the operation of the programmable controller 110 had to be stopped at the same time as turning off the power supply of 03.

In view of the above circumstances, the present invention is capable of continuing control of each device even if any of the I / O cards fails, and is programmable without turning off the power of the power supply card. An object of the present invention is to provide a parallel input / output device that can replace a failed I / O card with a new I / O card without stopping the operation of the controller.

[0011]

In order to achieve the above-mentioned object, the present invention provides a parallel device which is interposed between a programmable controller and each device and which supports signal transfer between the programmable controller and each device. In the input / output device, it consists of multiple I / O cards,
I / O card pair provided for each device and each I
A switch card that is provided for each I / O card pair and that selects a normal one of the I / O cards that make up each I / O card pair and inserts it between the corresponding device and the programmable controller. It is characterized by having.

[0012]

In the above structure, an I / O card pair is arranged between each device and the programmable controller for each device, and each I / O card is connected by the switch card.
Of the I / O cards forming the O card pair, the normal one is selected and used.

[0013]

1 is a block diagram showing an embodiment of a parallel input / output device according to the present invention.

The parallel input / output device 1 shown in FIG.
/ O chassis 2, back panel 3, power supply card 4, interface card 5, n A side I / O cards 6, n B side I / O cards 7, and n / 2 cards Of the A side I / O card 6 or the B side I / O card 7 is selected by each switch card 8 when the device is powered on.
When the programmable controller 10 (see FIG. 2) outputs a control command or control data to each device (not shown), the control command or control data is fetched and supplied to each device in parallel. When process data or the like is input, it is taken in parallel and supplied to the programmable controller 10. When one of the A-side I / O card 6 and the B-side I / O card 7 that is currently used fails, for example, when the A-side I / O card 6 fails, The power of the A-side I / O card 6 is individually cut off by the switch card 8, and the B-side I / O card 7 corresponding to the A-side I / O card is selected to continue the processing.

The I / O chassis 2 is provided with a casing 11 formed in a rectangular shape, and has a power supply card 4, an interface card 5, each A side I / O card 6, a switch card 8, and a B side I / O. When the O card 7 is set, the housing 11
The power supply card 4, the interface card 5, and the I / Os on each A side are provided by the back panel 3 arranged on the back side of the
The card 6, the switch card 8 and the B side I / O card 7 are connected to each other.

In this case, the back panel 3 includes a substrate 12 arranged in the back of the casing 11, a power source bus 13 formed on the substrate 12, and 3n provided in a predetermined portion of the power source bus 13. Female power bus connector 14
A bus switch selection signal bus 15 formed on the substrate 13, n bus switch selection signal female connectors 16 provided at a predetermined portion of the bus switch selection signal bus 15, and formed on the substrate 13. Internal I / O
Bus 17 and 2n detachable buffer circuits 18 provided in a predetermined portion of the internal I / O bus 17 (see FIG. 2)
And an internal I / O bus female connector 19 provided for each of these detachable buffer circuits 18, and the power supply card 4, the interface card 5, and each A side I / O.
When the O card 6, switch card 8 and B side I / O card 7 are set, these power supply card 4, interface card 5, each A side I / O card 6, switch card 8 and B side I / O card 7 power supply lines and signal lines are mutually connected.

The power supply card 4 is a board 20 which is detachably inserted into the I / O chassis 2 and the board 20.
Is formed on a part of the board, and when the board 20 is set on the I / O chassis 2, the female connector 1 for the power bus is formed.
4 is provided with a power bus male connector 21 to be plugged in 4 and a power circuit 22 provided on the substrate 20. When plugged in the I / O chassis 2, an external AC power source is taken in advance. The direct current voltage of the set value is generated, and the direct current voltage is transferred through the power bus 13 attached to the I / O chassis 2 to the interface card 5, each A side I / O card 6, each switch card. 8. Supply to each B side I / O card 7 to operate them.

The interface card 5 is inserted into the I / O chassis 2 in a detachable manner, and when the substrate 23 is set in the I / O chassis 2, it is inserted into the power bus female connector 14. When the power bus male connector 24 and the board 23 are set on the I / O chassis 2, the bus switch selection signal male connector 25 to be inserted into the bus switch selection signal female connector 16 and the board 23 are An internal I / O bus male connector 26 that is inserted into the internal I / O bus female connector 19 when set in the I / O chassis 2, and an interface circuit that is provided on the board 23 and performs an interface operation. And 27.

When set in the I / O chassis 2, the I / O bus 28 and the branching I / O bus 29 connect the programmable controller 10 and other parallel input / output devices 1 and Each A via the I / O bus 17 and the bus switch selection signal bus 15.
Side I / O card 6, each switch card 8, each B side I / O
When the device is connected to the card 7 and the power of the device is turned on, each switch card 8 is controlled to select either the A side I / O card 6 or the B side I / O card 7, and then each of these A It exchanges data with the side I / O card 6 and each B side I / O card 7, and exchanges data with the programmable controller 10.

In this case, the interface circuit 27
Is a CPU 3 that performs various data processing as shown in FIG.
0, a ROM 31 in which programs for defining the operation of the CPU 30 and various constant data are stored, and a RAM 32 used as a work area of the CPU 30.
And the CPU 30 and the like and the I / O bus 28 and branch I
A dual port memory circuit (DPM) 33 for supporting data exchange with the I / O bus 29, and the CPU 30.
And a buffer switch circuit (SWB) 34 for supporting signal exchange between the bus switch selection signal bus 15 and
A buffer circuit 35 that supports data transfer between the CPU 30 and the internal I / O bus 17, and a bus 36 that connects the respective parts of the circuit.

When a control command or control data is output from the programmable controller 10, it is fetched via the I / O bus 28, waveform-shaped, and then transmitted via the internal I / O bus 17. A side I / O
The internal I / O bus 17 is supplied to the card 6 and each B side I / O card 7, and when process data is input from each A side I / O card 6 and each B side I / O card 7. After taking in this via and shaping the waveform, I /
The programmable controller 1 via the O-bus 28
Supply to 0.

As shown in FIG. 3, the dual port memory circuit 33 includes a set of each A side I / O card 6 and each B side I / O card 7 corresponding to each A side I / O card 6. It has an input / output data table 40 having n input / output data areas 39 provided for each I / O card pair 38). When a control command or various control data is output from the programmable controller 10,
The control command and various control data are temporarily stored in the input / output data area 39 corresponding to the device to which the control command and various control data are supplied, and then supplied to the CPU 30 or the like. After the process data input from the corresponding device via the card 6 or the B-side I / O card 7 is temporarily stored in the input / output data area 39 corresponding to the device, the I / O bus 28 is connected. It is supplied to the programmable controller 10 via the above.

Further, the RAM 32 is provided with a card selection flag table 42 having n selection flag areas 41 provided for each I / O card pair 38 as shown in FIG. When a failure occurs, the contents of each selection flag area 41 corresponding to each I / O card pair 38 are set by the CPU 30, and thereafter, the A side which constitutes each I / O card pair 38 based on the setting contents. Either one of the I / O card 6 and the B side I / O card 7 is used, or the use of the A side I / O card 6 and the B side I / O card 7 is prohibited.

In this case, each selection flag area 41
Is the A-side I / O that constitutes the corresponding I / O card pair 38.
When neither the O card 6 nor the B side I / O card 7 is usable, the selection prohibition flag 43 set and the use of the A side I / O card 6 forming the corresponding I / O card pair 38 are set. The A-side selection flag 44 set when the instruction is given and the B constituting the corresponding I / O card pair 38
And a B-side selection flag 45 that is set when the use of the side I / O card 7 is instructed.
The contents of use of the corresponding I / O card pair 38 are instructed based on the set contents of 3, the A side selection flag 44, and the B side selection flag 45.

Further, as shown in FIG. 5, each A-side I / O card 6 has a board 46 which is removably inserted into the I / O chassis 2, and the board 46 is mounted on the I / O chassis 2. A power bus male connector 47 to be inserted into the power bus female connector when set,
An internal I / O bus male connector 48 to be inserted into the internal I / O bus female connector 19 when the substrate 46 is set on the I / O chassis 2;
I / O circuit 49 which is provided on the I / O circuit 6 and performs I / O operation
And a power switch 50 (see FIG. 2) which is provided on the substrate 46 and which stops power supply to the corresponding I / O circuit 49 or the detachable buffer circuit 18 when turned off by an operator. When the control command or control data is output from the interface card 5, the internal I / O bus 17, the detachable buffer circuit 1
8, the internal I / O bus female connector 19 and the internal I / O bus male connector 48 are sequentially taken into the I / O circuit 46 and then supplied to the corresponding switch card 8, and also the switch card. When process data is input from 8, the process data is input to the I / O circuit 49 and
The internal I / O bus male connector 48, the internal I / O bus female connector 19, the attachment / detachment buffer circuit 18, and the internal I / O bus 17 are sequentially supplied to the interface card 5.

When the A side I / O card 6 fails and the power switch 50 provided on the A side I / O card 6 is turned off, the A side I / O card 6 is turned off as shown in FIG.
The power supply to the removable buffer circuit 18 corresponding to the side I / O card 6 is stopped to turn off the gate elements 51 and 52 constituting the removable buffer circuit 18, and the A side I / O I / O provided on the card 6
The power supply to the circuit 49 is stopped to stop the operation of the I / O circuit 49.

As a result, when the A-side I / O card 6 fails, the A-side I / O card 6 is replaced with a new A-side I / O card 6 without adversely affecting other circuits. can do.

Each B side I / O card 7 is a substrate 53 which is detachably inserted into the I / O chassis 2.
When the board 53 is set in the I / O chassis 2, the power bus male connector 54 to be inserted into the power bus female connector 14 and the board 53 are set in the I / O chassis 2. When the internal I / O
An internal I / O bus male connector 55 to be inserted into the bus female connector 19, and an I / O bus male connector 55 provided on the substrate 53.
I / O circuit 56 for performing I / O operation, and a power switch 57 provided on the substrate 53 for stopping power supply to the corresponding I / O circuit 56 and the attachment / detachment buffer circuit 18 when turned off by an operator. And the internal I / O bus 17, the detachable buffer circuit 18, the internal I / O bus female connector 1 when a control command or control data is output from the interface card 5.
9. The internal I / O bus male connector 55 is sequentially taken into the I / O circuit 56 and then supplied to the corresponding switch card 8, and when process data is input from the switch card 8, Taking this into the I / O circuit 56, the internal I / O bus male connector 55,
The internal I / O bus female connector 19, the detachable buffer circuit 18, and the internal I / O bus 17 are sequentially supplied to the interface card 5.

As with the A side I / O card 6 described above, the B side I / O card 7 fails and the B side I / O card 7
When the power switch 57 provided on the I / O card 7 is turned off, the power supply to the removable buffer circuit 18 corresponding to the B-side I / O card 7 is stopped and the removable buffer circuit 18 is turned off. Each of the constituent gate elements 51, 52
Is cut off, the power supply to the I / O circuit 56 provided on the B-side I / O card 7 is stopped, and the operation of the I / O circuit 56 is stopped.

Thus, when the B-side I / O card 7 fails, the B-side I / O card 7 is replaced with a new B-side I / O card 7 without adversely affecting other circuits. can do.

Each switch card 8 is a substrate 60 which is detachably inserted into the I / O chassis 2.
When the board 60 is set in the I / O chassis 2, the power bus male connector 61 to be inserted into the power bus female connector 14 and the board 60 are set in the I / O chassis 2. At this time, the bus switch selection signal male connector 62 to be inserted into the bus switch selection signal female connector 16 and the corresponding A side I / O card 6 or B side I / O card provided on the substrate 60.
Of the O card 7, CP of the interface card 5
A switch circuit 64 for selecting one designated by U30 and connecting to the external input / output cable 63 is provided.
When a card selection command is output from the CPU 30 of the interface card 5, the bus switch selection signal bus 1
5, the bus switch selection signal female connector 16, and the bus switch selection signal male connector 62 are sequentially taken in and the switch circuit 64 is operated to operate the corresponding A side I / O card 6 or B side I / O card 6. Of the O card 7,
The one designated by the card selection command is selected and connected to the external input / output cable 63.

Next, the initialization operation and the normal operation of this embodiment will be sequentially described with reference to the flow charts shown in FIGS.

<< Initialization Operation >> First, when the parallel input / output device 1 is powered on, the interface card 5
CPU 30 of each I / O card pair 3 as shown in FIG.
The variable i indicating the number 8 is set to "0" (step ST1), and the I / O card pair 3 corresponding to this variable i is set.
8 is accessed (step ST2) to check whether it operates normally (step ST3). When it operates normally, each of the data stored in the RAM 32 is checked. In the selection flag area 41, the A-side selection flag 44 of the selection flag area 41 corresponding to the I / O card pair 38 is set (step ST11), and the I / O card pair 38 is supported based on the set content. Control the switch card 8 to
The side I / O card 6 is selected (step ST12).

In the checking operation of the A side I / O card 6 (step ST3), if the A side I / O card 6 does not operate normally, the CPU 30 causes the I side I / O card 6 to operate.
The B side I / O card 7 of the I / O card pair 38 is accessed (step ST4) to check whether it operates normally (step ST5). If it operates normally, it is provided in the RAM 32. Among the selected selection flag areas 41, the B side selection flag 45 of the selection flag area 41 corresponding to the I / O card pair 38 is set (step ST9), and the I / O card pair is set based on the set contents. The switch card 8 corresponding to No. 38 is controlled to cause the switch circuit 64 of this switch card 8 to select the B side I / O card 7 (step S
T10).

Further, in the checking operation of the A side I / O card 6, an abnormality of the A side I / O card 6 is detected, and in the checking operation of the B side I / O card 7, the B side I / O card is detected. When the abnormality of No. 7 is detected (steps ST3 and ST5), the CPU 30 selects the selection prohibition flag of the selection flag area 41 corresponding to the I / O card pair 38 among the selection flag areas 41 provided in the RAM 32. 43 is set to prohibit the use of this I / O card pair 38 (step ST6).

Thereafter, the CPU 30 increments the variable i (step ST7), and the value of the variable i is I / O.
Until the number of the card pair 38 (for example, “9”) is exceeded (step ST8), the above-mentioned operation is repeated to perform each I / O.
Unless both the A-side I / O card 6 and the B-side I / O card 7 forming the O-card pair 38 are abnormal, the A-side I / O card 6 or the B-side I / O card 6 is provided for each I / O card pair 38. Either one of the side I / O cards 7 is selected (steps ST2 to ST12).

<Normal Operation><CommonProcessing> When this initialization processing is completed, C
The PU 30 sets the variable i indicating the number of each I / O card pair 38 to "0" as shown in FIG. 7 (step ST
15) Of the selection flag areas 41 in the RAM 32, the selection flag area 41 corresponding to the variable i is read (step ST16), and "1" is set in the selection prohibition flag 43 of the selection flag area 41. It is checked whether or not there is (step ST17).

If "1" is not set in the selection prohibition flag 43 of the selection flag area 41 (step ST17), the CPU 30 sets "1" in the A-side selection flag 44 of the selection flag area 41. It is checked (step ST18), and if this is set, the A side input / output processing is executed.

<A side input/output processing> In this processing, the CPU
As shown in FIG. 8, reference numeral 30 denotes a control command from the programmable controller 10 written in the input / output data area 39 corresponding to the variable i among the input / output data areas 39 of the dual port memory circuit 33. While fetching various control data, the control data is supplied to the buffer circuit 35 to be supplied to the A side I / O card 6 of the I / O card pair 38 designated by the variable i, or the A side I / O card 6 When the process data is input from the buffer circuit 35, is amplified by the buffer circuit 35, and is waveform-shaped and input, the process data is captured and the value of the variable i in each input / output data area 39 of the dual port memory circuit 33 is input. Input / output data area 39 corresponding to
To the programmable controller 10 (step ST19).

When this data transfer operation is not performed correctly (step ST20), the CPU 30 clears the A-side selection flag 44 in the selection flag area 41 corresponding to the variable i among the selection flag areas 41, as well as (Step ST21) After controlling the switch card 8 of the I / O card pair 38 corresponding to the variable i to cause the switch circuit 64 of this switch card 8 to select the B side I / O card 7 (step ST22). , B-side selection flag 4 in the selection flag area 41 corresponding to the variable i
5 is set (step ST23).

Next, the CPU 30 transmits the B of the I / O card pair 38 corresponding to the variable i via the buffer circuit 35.
While inputting / outputting data to / from the side I / O card 7 (step ST24), it is checked whether or not this input / output operation is normally performed (step ST25), and the input / output operation of this data is normally performed. When not opened, the B-side selection flag 4 in the selection flag area 41 corresponding to the variable i
5 is cleared (step ST26), and when the data input / output is normally performed, the process of clearing the B-side selection flag 45 is skipped and the use of the B-side I / O card 7 is started.

Further, I / I corresponding to the above-mentioned variable i
In the normal / abnormal check operation of the A side I / O card 6 of the O card pair 38 (step ST20), this A side I
If the I / O card 6 is normal, the CPU 30 causes the above-mentioned B
The normal / abnormal determination processing of the side I / O card 7 is skipped.

Further, when it is checked whether or not "1" is set in the A-side selection flag 44 of the selection flag area 41 corresponding to the above-mentioned variable i (FIG. 7, step ST18), this must be set. If CP
U30 is the B-side selection flag 4 in this selection flag area 41.
It is checked whether "1" is set in 5 (step ST27), and if it is set, B
Side I / O processing is executed.

<B side input / output processing> In this processing, the CPU
As shown in FIG. 7, reference numeral 30 denotes a control command from the programmable controller 10 which is written in the input / output data area 39 corresponding to the variable i among the input / output data areas 39 of the dual port memory circuit 33. While fetching various control data, this data is supplied to the buffer circuit 35 to be supplied to the B side I / O card 7 of the I / O card pair 38 designated by the variable i, or the B side I / O card 7 When the process data is input from the buffer circuit 35, is amplified by the buffer circuit 35, and is waveform-shaped and input, the process data is captured and the value of the variable i in each input / output data area 39 of the dual port memory circuit 33 is input. Input / output data area 39 corresponding to
To the programmable controller 10 (step ST28).

When the data transfer operation is not correctly performed (step ST29), the CPU 30 clears the B-side selection flag 45 of the selection flag area 41 corresponding to the variable i among the selection flag areas 41, as well as clearing the selection flag area 41. (Step ST30) After controlling the switch card 8 of the I / O card pair 38 corresponding to the variable i to cause the switch circuit 64 of this switch card 8 to select the A side I / O card 6 (step ST31). , A side selection flag 4 in the selection flag area 41 corresponding to the variable i
4 is set (step ST32).

Next, the CPU 30 sends the A of the I / O card pair 38 corresponding to the variable i via the buffer circuit 35.
Data is input / output to / from the side I / O card 6 (step ST33), and it is checked whether or not this input / output operation is normally performed (step ST34), and this data input / output operation is normally performed. If not, the A-side selection flag 44 of the selection flag area 41 corresponding to the variable i is cleared (step ST35), and when the data input / output is normally performed, the process of clearing the A-side selection flag 44 is skipped. Then, the use of the A side I / O card 6 is started.

I / I corresponding to the above-mentioned variable i
In the normal / abnormal check operation of the B side I / O card 7 of the O card pair 38 (step ST29), this B side I
If the I / O card 7 is normal, the CPU 30 executes the above A
The normal / abnormal determination processing of the side I / O card 6 is skipped.

When it is checked whether "1" is set in the A-side selection flag 44 and the B-side selection flag 45 of the selection flag area 41 corresponding to the above-mentioned variable i (steps ST18 and ST27), If these are not set, the CPU 30 executes the selection prohibition process.

<Selection Prohibition Processing> In this processing, the CPU 3
As shown in FIG. 7, 0 is the first I corresponding to the variable i.
The switch circuit 64 of the switch card 8 of the I / O card pair 38 is controlled to select the A side I / O card 6 (step ST36), and then the selection prohibition flag 43 of the selection flag area 41 corresponding to the variable i is set. It is set and the use of the I / O card pair 38 corresponding to the variable i is prohibited (step ST37).

Further, in the above-mentioned determination processing of the selection prohibition flag 43 in the selection flag area 41 (step ST1
7), the selection prohibition flag 43 in this selection flag area 41
If "1" is set to, the CPU 30 determines that the I / O card pair 38 corresponding to the variable i is in the use state prohibited state, and performs the standby process.

<Stand-by Process> In this process, the CPU 30 first sets the dual port memory circuit 3 as shown in FIG.
In each of the input / output data areas 39 of No. 3, the control command and various control data from the programmable controller 10 written in the input / output data area 39 corresponding to the variable i are fetched and supplied to the buffer circuit 35. I / O card pair 38 specified by the variable i
Can be supplied to the A side I / O card 6, or this A side I / O
When process data is input from the card 6 and is amplified and waveform-shaped by the buffer circuit 35, the process data is captured and the variable i in each input / output data area 39 of the dual port memory circuit 33 is input. The data is written in the input / output data area 39 corresponding to the value of and is transferred to the programmable controller 10 (step ST38).

When the data transfer operation is correctly performed (step ST39), the CPU 30 causes the A-side selection flag 4 in the selection flag area 41 corresponding to the variable i.
4 is set (step ST40), the selection prohibition flag 43 in the selection flag area 41 is cleared, and the use of the A side I / O card 6 is started (step ST4).
1).

If the data transfer operation is not performed correctly (step ST39), the CPU 30 skips the use starting process of the A side I / O card 6.

<Common Processing> When these processings are completed, the CPU 30 increments the variable i as shown in FIG. 7 (step ST42), and then the value of the variable i is stored in the I / O card pair 38. Number (eg,
Until the number exceeds "9") (step ST43), the above-described operation is repeated to configure each I / O card pair 38A.
Unless both the I / O card 6 on the side and the I / O card 7 on the B side are abnormal, A for each I / O card pair 38
Either the side I / O card 6 or the B side I / O card 7 is selected (steps ST15 to ST43).

Thus, in this embodiment, the A side I
I / O with the I / O card 6 and the B-side I / O card 7.
The card pair 38 is configured, and the normal one of the A side I / O card 6 and the B side I / O card 7 is automatically selected by the switch card 8 corresponding to the I / O card pair 38. When either the A-side I / O card 6 or the B-side I / O card 7 fails during use, the power switches 50 and 57 provided on the failed board are turned off. Broken I /
Since the O card is electrically disconnected from the internal I / O bus 17 and the power supply bus 13, either the A side I / O card 6 or the B side I / O card 7 fails. Also,
Aside I / O card 6 or B side I / O card that has failed without being able to continue control of each device and without turning off the power of power supply card 4 and without stopping the operation of programmable controller 10 7 for the new A
It can be replaced with the side I / O card 6 or the B side I / O card 7.

[0056]

As described above, according to the present invention, even if one of the I / O cards fails, the control of each device can be continued and the power of the power supply card can be turned off. It is possible to replace a failed I / O card with a new I / O card without stopping the operation of the programmable controller.

[Brief description of drawings]

FIG. 1 is a perspective view showing an embodiment of a parallel input / output device according to the present invention.

FIG. 2 is a block diagram showing a circuit configuration example of the parallel input / output device shown in FIG.

FIG. 3 is a schematic diagram showing a detailed configuration example of a dual port memory circuit shown in FIG.

FIG. 4 is a schematic diagram showing a detailed configuration example of a card selection flag table provided in the RAM shown in FIG.

5 is a block diagram showing a detailed circuit configuration example of the A-side I / O card shown in FIG.

FIG. 6 is a flowchart showing an example of initialization operation of the parallel input / output device shown in FIG.

FIG. 7 is a flowchart showing an example of normal operation of the parallel input / output device shown in FIG.

8 is a flowchart showing an example of normal operation of the parallel input / output device shown in FIG.

9 is a flowchart showing an example of normal operation of the parallel input / output device shown in FIG.

FIG. 10 is a block diagram showing a circuit configuration example of a conventionally known parallel input / output device.

[Explanation of symbols]

 1 parallel input / output device 2 I / O chassis 3 back panel 4 power supply card 5 interface card 6 A side I / O card 7 B side I / O card 8 switch card 10 programmable controller 38 I / O card pair

Claims (1)

[Claims] 1. A parallel input / output device which is interposed between a programmable controller and each device and which supports signal transmission / reception between the programmable controller and each device. An I / O card pair provided for each device and each I / O card pair provided for each I / O card pair
A parallel input / output device comprising: a switch card inserted between a corresponding device and a programmable controller by selecting a normal one of the I / O cards forming the O card pair. .