JP2008091788A - Solid state image pickup device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve a conversion efficiency of a CMOS image pickup device by reducing a parasitic capacitance of a floating diffusion section. <P>SOLUTION: The image pickup device has an arrangement of a plurality of picture elements 421, where the picture element 421 is composed of a photoelectric conversion part 55 and transistor parts, and an impurity concentration of a semiconductor well region 53 of a floating diffusion part 56 in the picture element 421 is lower than impurity concentrations of semiconductor well regions 54 of transistor parts 62, 63 of stages behind the floating diffusion part 56. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

The present invention relates to a solid-state imaging device and a manufacturing method thereof, and more particularly, to a CMOS image sensor in which a pixel includes a photoelectric conversion unit and a pixel transistor unit and a manufacturing method thereof.
Here, the CMOS image sensor is an image sensor manufactured by applying or partially using a CMOS process. Further, as a form of the solid-state imaging device, it may be configured by one chip or a plurality of chips.

  A CMOS image sensor is known as a solid-state imaging device. FIG. 18 shows an equivalent circuit showing an example of a pixel (so-called unit pixel cell) of a conventional CMOS image sensor, and FIG. 17 shows a schematic sectional structure thereof. In FIG. 18, a pixel 1 includes, for example, a photodiode (PD) 2 constituting a photoelectric conversion unit, and a plurality of charges generated by photoelectric conversion in the photodiode 2 and converted into pixel signals and read out to a vertical signal line. So-called pixel transistors are used. The plurality of pixel transistors are formed of, for example, n-channel MOS transistors. The transfer transistor 3 transfers the charge of the photodiode 2 to the floating diffusion portion FD, and the reset transistor resets the potential of the floating diffusion portion FD. 4 and an amplifying transistor 5 that converts the charge generated by the photodiode 2 into a pixel signal by converting the voltage.

  The cathode of the photodiode 2 is connected to the gate of the amplification transistor 5 through the transfer transistor 3. A node electrically connected to the gate of the amplifying transistor 5 is referred to as a floating diffusion portion FD. The floating diffusion portion FD is constituted by the drain region of the transfer transistor 3.

  The transfer transistor 3 is connected between the cathode of the photodiode 2 and the floating diffusion portion FD, and a transfer pulse φTRG is applied to the gate of the transfer transistor 3 via the transfer wiring 7. The reset transistor 4 has a drain connected to the pixel power supply line (Vdd) 9, a source connected to the floating diffusion portion FD, and a reset pulse φRST applied to the gate via the reset wiring 8.

  The amplification transistor 5 has a gate connected to the floating diffusion portion FD, a drain connected to the pixel power supply line 9, and a source connected to the vertical signal line 11.

  In this pixel 1, prior to reading out the storage pixel of the photodiode 2, the reset transistor 4 is turned on to reset the floating diffusion portion FD to the pixel power supply voltage, and the potential of the floating diffusion portion FD after reset is set to Read out to the vertical signal line 11. Next, the transfer transistor 3 is turned on, and the signal charge accumulated in the photodiode 2 is transferred to the floating diffusion portion FD, converted into a pixel signal by the amplifying transistor 5, and read out to the vertical signal line 11. The previous reset potential and the pixel signal are subjected to CDS processing by the CDS processing circuit of the column processing circuit, noise is removed, and then output as a pixel signal.

  As shown in FIG. 17, the semiconductor structure of the pixel 1 is formed on a first conductive type, for example, an n-type semiconductor substrate 21, via a second conductive type, for example, a p-type first semiconductor well region 22. The photodiode 2 is formed, and the floating diffusion portion FD and the subsequent pixel transistors 4, 5 and 6 are formed through the p-type second semiconductor well region 23. The photodiode 2 is configured as an HAD sensor including a charge storage region 24 formed of an n-type diffusion region and a p-type diffusion region (p-type accumulation layer) 25 on the surface thereof.

  The transfer transistor 3 includes a gate insulating film 27 formed so as to straddle the first and second semiconductor well regions 22 and 23 between the photodiode 2 and the n-type diffusion region 26 to be the floating diffusion portion FD. A transfer gate electrode 28 is formed through the structure. The reset transistor 4 is configured by forming a reset gate electrode 33 between a n-type diffusion region (FD) 26 and an n-type diffusion region 29 via a gate insulating film 32. The amplifying transistor 5 is configured by forming an amplifying gate electrode 35 between the n-type diffusion region 29 and the n-type diffusion region 30 via a gate insulating film 34. Although omitted in this drawing, an insulating side wall (so-called side wall) 42 is formed on the gate electrode of each of the pixel transistors 3, 4 and 5, but the n-type low concentration region is formed before the side wall is formed. In some cases, an LDD (Lightly Doped Drain) structure having

  Here, the impurity concentration of the n-type diffusion region 24 of the photodiode 2 as the photoelectric conversion portion is lower than the impurity concentration of the n-type diffusion regions 29 and 30 of the floating diffusion portion FD and other pixel transistors. .

As measures for reducing the parasitic capacitance described later, various methods for manufacturing solid-state imaging devices such as Patent Documents 1 and 2 have been proposed.
JP 2004-165479 A JP 2005-268812 A

  In the above-described CMOS image sensor, an increase in the amount of signal charges to be handled and an improvement in conversion efficiency when performing voltage conversion are required. As will be described later, the conversion efficiency in the CMOS image sensor is affected by the parasitic capacitance in the n-type diffusion region serving as the floating diffusion portion FD. When this parasitic capacitance increases, the conversion efficiency decreases.

  In particular, as the pixel cell area becomes finer, a so-called pixel sharing structure in which some of the transistors in the pixel are shared by a plurality of pixels may be employed in order to secure a light receiving area of the photoelectric conversion unit. In the case of a pixel sharing structure, the floating diffusion portion FD is often divided, and in addition to the parasitic capacitance due to the diffusion region of each floating diffusion portion FD, the divided floating diffusion portion FD is connected. The conversion efficiency is lower than that of a metal wiring having a wiring capacitance and not sharing pixels.

  By the way, the number of electrons serving as signal charges is determined by the amount of charges handled by the floating diffusion unit FD serving as the imaging unit and charge storage unit. This electron (signal charge) is output as a change in voltage to the vertical signal line by the source follower operation of the amplifying transistor. In this case, since the conversion efficiency η is expressed by the following equation 1, it is desirable to reduce the parasitic capacitance of the floating diffusion portion FD in order to improve the conversion efficiency.

  As measures for reducing the parasitic capacitance, various solid-state imaging device manufacturing methods such as Patent Documents 1 and 2 have been proposed.

  On the other hand, a constant voltage power source or a constant current power source for a source follower operation is connected to an n-type diffusion region which becomes a source / drain region of a transistor portion (amplification transistor, reset transistor) in a pixel cell. In the reset transistor, since the reset drain potential needs to be deeply formed in order to maintain the reset cutoff characteristic, a channel portion having a certain level of impurity concentration must be formed. In addition, as a pixel transistor, ion implantation for LDD formation is performed before sidewall formation in order to relax the electric field between the diffusion region and the well end, that is, relax the electric field at the pn junction of the source / drain region and maintain the response speed. There may be.

  However, if the floating diffusion portion FD and the source / drain regions of the MOS transistor in the pixel are formed at the same time, a high impurity concentration ion implantation for the n-type diffusion region of the MOS transistor and a low impurity concentration ion implantation for the LDD are performed. Enters the floating diffusion portion FD, and the parasitic capacitance of the floating diffusion portion FD increases.

  In recent years, in order to reduce 1 / f noise and kTC noise, a MOS transistor having a depletion structure in which the channel is formed deeply under the gate may be used as a transistor in the pixel cell. Is also required.

  In view of the above, the present invention provides a solid-state imaging device capable of reducing the parasitic capacitance of the floating diffusion portion to improve the conversion efficiency, and efficiently converting the photoelectrically converted charge into a voltage, and a method for manufacturing the same. To do.

  In the solid-state imaging device according to the present invention, a plurality of pixels composed of a photoelectric conversion unit and a pixel transistor unit are arranged, and the impurity concentration of the semiconductor well region under the floating diffusion unit in the pixel is higher than that of the floating diffusion unit. It is characterized in that it is set to a concentration lower than the impurity concentration of the semiconductor well region under the pixel transistor portion in the subsequent stage.

  In the solid-state imaging device of the present invention, since the impurity concentration in the semiconductor well region under the floating diffusion portion is lower than that in the semiconductor well region under the pixel transistor portion in the subsequent stage, the depletion layer extends in the floating diffusion portion. This increases the parasitic capacitance in the floating diffusion portion.

  In the method for manufacturing a solid-state imaging device according to the present invention, the first second-conductivity-type semiconductor in the photoelectric conversion unit formation region is formed in the cell region where the unit pixel cell or the pixel-sharing cell of the first-conductivity-type semiconductor substrate is to be formed. Forming a well region, a second second conductivity type semiconductor well region in the floating diffusion portion formation region, and a third second conductivity type semiconductor well region in the pixel transistor formation region, The impurity concentration of the second conductivity type semiconductor well region is formed to be lower than the impurity concentration of the third second conductivity type semiconductor well region. Forming a conversion portion; forming a first conductivity type diffusion region serving as a floating diffusion portion in the second second conductivity type semiconductor well region; and forming a first conductivity type diffusion well region in the second second conductivity type semiconductor well region. It characterized by having a step of forming a first conductivity type diffusion region in the subsequent stage of the pixel transistor from the floating diffusion portion.

  In the method for manufacturing a solid-state imaging device according to the present invention, the second second conductivity type semiconductor well having a lower concentration than the impurity concentration of the third second conductivity type semiconductor well region in the transistor formation region is formed in the floating diffusion portion formation region. Forming a first conductivity type diffusion region to be a floating diffusion portion in the second second conductivity type semiconductor well region, thereby increasing the extension of the depletion layer in the floating diffusion portion. The parasitic capacitance in the floating diffusion portion can be reduced.

According to the solid-state imaging device according to the present invention, since the extension of the depletion layer in the floating diffusion portion is increased and the parasitic capacitance is reduced, the conversion efficiency of the pixel can be improved, and the photoelectrically converted charge can be efficiently obtained. Voltage conversion can be performed.
According to the method for manufacturing a solid-state imaging device according to the present invention, it is possible to manufacture a solid-state imaging device capable of improving the conversion efficiency of pixels by greatly increasing the depletion layer in the floating diffusion portion and reducing the parasitic capacitance. Can do.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 shows a schematic configuration of an embodiment of a solid-state imaging device applied to the present invention, that is, a CMOS solid-state imaging device (image sensor). The solid-state imaging device 41 according to the present embodiment includes an imaging region 43 in which pixels 42 including a plurality of photoelectric conversion units are regularly arranged in a two-dimensional array on a semiconductor substrate, for example, a silicon substrate 100, and its peripheral circuit. And a main signal section driving circuit 44, a column signal processing circuit 45, a horizontal driving circuit 46, an output circuit 47, a control circuit 48, and the like.

  The control circuit 48 generates a clock signal, a control signal, and the like that serve as a reference for the operation of the vertical drive circuit 44, the column signal processing circuit 45, the horizontal drive circuit 46, and the like based on the vertical synchronization signal, the horizontal synchronization signal, and the master clock. To the vertical drive circuit 44, the column signal processing circuit 45, the horizontal drive circuit 46, and the like.

  The vertical drive circuit 44 is configured by, for example, a shift register, and sequentially selects and scans each pixel 42 in the imaging region 43 in the vertical direction in units of rows, and receives light in the photoelectric conversion unit (photodiode) of each pixel through the vertical signal line 49. A pixel signal based on the signal charge generated according to the above is supplied to the column signal processing circuit 45.

  The column signal processing circuit 45 is arranged, for example, for each column of the pixels 42, and signals output from the pixels 42 for one row are generated for each pixel column as a black reference signal (not shown, but formed around the effective pixel region). In other words, signal processing such as CDS and signal amplification for removing the inherent pattern noise of the pixel 42 is performed by the signal from At the output stage of the column signal processing circuit 45, a horizontal selection switch (not shown) is connected between the horizontal signal line 50 and provided.

The horizontal drive circuit 46 is constituted by, for example, a shift register, and sequentially outputs horizontal scanning pulses to select each of the column signal processing circuits 45 in order, and outputs a pixel signal from each of the column signal processing circuits 45 to the horizontal signal line. 50.
The output circuit 47 performs signal processing and outputs the signals sequentially supplied from each of the column signal processing circuits 45 through the horizontal signal line 50.

  As the configuration of the pixel 42, for example, a pixel having a three-pixel transistor structure shown by the above-described equivalent circuit of FIG. 18 can be used. Note that a pixel having a four-pixel transistor structure including a transfer transistor, a reset transistor, an amplification transistor, and a selection transistor can be used by adding a selection transistor. Pixels having other pixel transistor configurations can also be applied.

  FIG. 2 shows a first embodiment of an imaging region in the solid-state imaging device 41 described above. FIG. 2 shows a unit pixel cell portion. The imaging region in this embodiment, that is, the unit pixel cell 421 is photoelectrically connected to a first conductivity type, for example, an n-type semiconductor substrate 51 via a second conductivity type, for example, a p-type first semiconductor well region 52. A photodiode (PD) 55 serving as a conversion portion is formed, an n-type diffusion region 56 serving as a floating diffusion portion FD is formed via a p-type second semiconductor well region 53, and a p-type second The pixel transistors 62 and 63 in the subsequent stage of the floating diffusion portion FD are formed through the three semiconductor well regions 54.

  The photodiode 55 is configured as an HAD sensor including an n-type diffusion region 66 serving as a charge storage region and a p-type diffusion region (p-type accumulation layer) 67 for suppressing dark current on the surface thereof.

  The transfer transistor 61 is a gate insulating film formed so as to straddle the first and second p-type semiconductor well regions 52 and 53 between the photodiode 55 and the n-type diffusion region 56 serving as the floating diffusion portion FD. A transfer gate electrode 75 is formed via 71. The reset transistor 62 is configured by forming a reset gate electrode 63 between the n-type diffusion region (FD) 56 and the n-type diffusion region 57 via a gate insulating film 72. The amplification transistor 63 is configured by forming an amplification gate electrode 77 between the n-type diffusion region 57 and the n-type diffusion region 58 via a gate insulating film 73.

  Although not shown in this drawing, an insulating side wall (so-called side wall) 82 is formed on the gate electrode of each of the pixel transistors 61, 62 and 63, but the n-type low concentration region is formed before the side wall is formed. In some cases, an LDD (Lightly Doped Drain) structure having

  In the present embodiment, the first, second, and third p-type semiconductor well regions 52, 53, and 54 are separately formed so that the impurity concentrations thereof are different from each other, and n that is the floating diffusion portion FD. The impurity concentration of the second p-type semiconductor well region 53 in which the type diffusion region 56 is formed is set to the impurity concentration of the third p-type semiconductor well region 54 in which the n-type diffusion regions 57 and 58 of each pixel transistor in the subsequent stage are formed. Make the concentration lower than the concentration. In this case, the second p-type semiconductor well region 53 has at least the impurity concentration of the surface side region where the n-type diffusion region 56 which is the floating diffusion portion FD is formed, as the third p-type semiconductor well region 54. Each n-type diffusion region 57, 58, 59 is formed to have a lower concentration than the impurity concentration of the surface side region where it is formed.

  The impurity concentration of the first p-type semiconductor well region 52 where the photodiode 55 is formed is lower than the impurity concentration of the third p-type semiconductor well region 54.

  Further, the diffusion region 56 constituting the floating diffusion portion and the diffusion regions 57 and 58 constituting the pixel transistor portion may be simultaneously formed with the same impurity concentration, or when not formed simultaneously, The impurity concentration of the diffusion region 56 in the floating diffusion portion is formed to be lower than the impurity concentration of the diffusion regions 57 and 58 in the pixel transistor portion.

Next, the solid-state imaging device according to the present embodiment (particularly the pixel cell portion thereof) including a step of separately forming the first, second and third semiconductor well regions 52, 53 and 54 described above with reference to FIGS. ) Will be described.
First, as shown in FIG. 3A, the entire surface of a cell region in which a pixel cell of a first conductivity type semiconductor substrate, for example, an n-type semiconductor substrate 51 is to be formed, that is, a photodiode formation region 85, a floating diffusion portion (FD). ) A first p-type impurity ion is implanted into the entire surface of the pixel transistor formation region 87 subsequent to the formation region 86 and the floating diffusion portion so as to have a concentration peak at a deep portion. An implantation region 91 is formed. FIG. 3B shows the concentration distribution of the p-type impurity during the ion implantation.

Next, as shown in FIG. 4A, the floating diffusion region (FD) formation region 86 except the photodiode formation region 85 in the cell region of the n-type semiconductor substrate 51 and the MOS transistor formation region 87 in the subsequent stage are shallower than the deep portion. A second p-type impurity ion implantation region 92 is formed by ion implantation of a second p-type impurity having a concentration peak at an intermediate position deeper than the surface side. The second p-type well ion implantation region 92 is formed in contact with the first p-type well ion implantation region 91. FIG. 4B shows the concentration distribution of the p-type impurity during the ion implantation.
FIG. 7 shows a mask image of the ion implantation mask 95 when the second p-type well ion implantation region 92 is formed. A broken line 97 corresponds to one unit pixel cell. The halftone portion 95a corresponds to the photodiode formation region 85, and the white portion 95b corresponds to the floating diffusion portion formation region 86 and the pixel transistor formation region 87 in the subsequent stage.

Next, as shown in FIG. 5A, a third p-type impurity having a concentration peak on the surface side is ion-implanted only into the pixel transistor formation region 87 in the subsequent stage of the cell region of the n-type semiconductor substrate 51, thereby A p-type well ion implantation region 93 is formed. The third p-type well ion implantation region 93 is formed in contact with the second p-type well ion implantation region 92. FIG. 5B shows the concentration distribution of the third p-type impurity during the ion implantation.
FIG. 8 shows a mask image of the ion implantation mask 96 when the third p-type well ion implantation region 93 is formed. The halftone dot portion 96a corresponds to the photodiode formation region 85, the halftone dot portion 96c corresponds to the floating diffusion portion formation region 86, and the white portion 96b corresponds to the MOS transistor formation region 87 in the subsequent stage.

  Next, as shown in FIG. 6, a gate electrode is formed on the n-type semiconductor substrate 51 with a gate insulating film interposed therebetween, and a low impurity concentration region having an LDD structure is formed using the gate electrode as a mask, thereby forming a sidewall. To do.

  Thereafter, a photodiode 55 is formed in the photodiode formation region 85 by ion implantation. Further, an n-type diffusion region 56 to be a floating diffusion portion FD is formed in the floating diffusion portion formation region 86, and n-type diffusion regions 57 and 58 of each pixel transistor are ion-implanted in the pixel transistor formation region 87 in the subsequent stage. At the same time. Furthermore, each wiring is formed in a wiring formation process. In this way, a solid-state imaging device in which the pixel 421 shown in FIG. 2 is formed is obtained.

  For comparison, a conventional solid-state imaging device, that is, a method for manufacturing a semiconductor well region of the pixel will be described with reference to FIG. Conventionally, as shown in FIG. 16, the entire pixel region of the n-type semiconductor substrate 21, that is, a photodiode formation region 85, a floating diffusion portion (FD) formation region 86, and a pixel subsequent to the floating diffusion portion. A first p-type well ion implantation region 91 is formed on the entire surface of the transistor formation region 87 by ion implantation of a first p-type impurity having a concentration peak in the deep portion of the substrate.

  Next, in the floating diffusion portion (FD) formation region 86 and the subsequent pixel transistor formation region 87 except for the photodiode formation region 85 of the n-type semiconductor substrate 21, a concentration peak is formed at an intermediate position shallower than the deep portion and deeper than the surface side. A second p-type well ion implantation region 92 is formed by ion implantation of the second p-type impurity.

  Next, in the same manner, in the floating diffusion region (FD) formation region 86 excluding the photodiode formation region 85 of the n-type semiconductor substrate 21 and the pixel transistor formation region 87 in the subsequent stage, a third peak having a concentration peak on the surface side. The third p-type well ion implantation region 93 is formed by ion implantation of the p-type impurity.

  The ion implantation mask 95 shown in FIG. 7 is used for ion implantation when forming the second p-type well ion implantation region 92 and the third p-type well ion implantation region 93. Thereafter, a gate electrode is formed on the n-type semiconductor substrate 21 via a gate insulating film, and a low impurity concentration region having an LDD structure is formed using the gate electrode as a mask, thereby forming a sidewall. In addition, a photodiode and a gate portion (gate insulating film, gate electrode, sidewall, etc.) of each transistor are formed, an n-type diffusion region is formed by ion implantation using this gate portion as a mask, and each wiring is formed in a wiring formation process. Form.

  In the first embodiment described above, when a depletion structure MOS transistor in which the channel of the MOS transistor in the pixel is formed deeply under the gate is formed, ion implantation for adjusting the channel threshold of the corresponding MOS transistor is performed. is necessary. At this time, after the p-type semiconductor well region is formed as described above, impurity ions are implanted into the MOS transistor with energy that determines the channel threshold, but the p-type semiconductor well in which the floating diffusion portion FD is formed is formed. It is desirable to omit ion implantation for threshold adjustment in the region.

  According to the first embodiment described above, the impurity concentration in the second p-type semiconductor well region 53 in which the floating diffusion portion FD is formed, at least in the surface side region in which the floating diffusion portion FD is formed, is set. The impurity concentration of the third p-type semiconductor well region 54 in which the MOS transistor in the subsequent stage is formed is lower than that of the third p-type semiconductor well region 54. Since the second p-type semiconductor well region 53 under the floating diffusion portion FD has a low impurity concentration, the depletion layer spreads toward the second p-type semiconductor well region 53 in the floating diffusion portion FD. The parasitic capacitance of the floating diffusion portion FD is reduced, and the pixel conversion efficiency can be improved. As a result, the photoelectrically converted charge can be efficiently converted into a voltage.

  9A and 9B show potential distribution diagrams when a depletion layer extends from the floating diffusion portion FD to the p-type semiconductor well region side. FIG. 9A shows the extension of the depletion layer a when the impurity concentration of the p-type semiconductor well region under the floating diffusion portion FD is low in the case of the present invention. It can be seen that the length of the depletion layer b under the floating diffusion portion FD in the p-type semiconductor well region having the conventional impurity concentration in FIG.

  FIG. 10 shows the relationship between the diffusion capacitance (ie, parasitic capacitance) of the floating diffusion portion FD and the voltage. Curve I is the case of the present invention and curve II is the conventional case. FIG. 10 also shows that the diffusion capacity is reduced in the present invention. FIG. 11 is a comparative graph of the conversion efficiency. The conversion efficiency is improved in the present invention compared to the conventional case.

  Next, the relationship with the conversion efficiency when the impurity concentration of the p-type semiconductor well region under the floating diffusion portion FD is lowered will be described using the theoretical formula of the device. The conversion efficiency η is expressed by Equation 1.

変換効率＝出力部の増幅率
ｑ ：電子の電荷量
Ｇ ：ソースフォロア回路全体の利得（≒０．６〜０．９）
Ｃ_FD：フローティング・ディフージョン部ＦＤの容量

Conversion efficiency = amplification factor of output part q: charge amount of electron G: gain of entire source follower circuit (≈0.6 to 0.9)
C _FD : Capacity of floating diffusion FD

From Equation 1, the conversion efficiency η decreases by increasing the gain G of the amplifier source follower and decreasing the capacitance C _FD of the floating diffusion portion FD. Now, attention is paid to the FD capacity C _FD.
By the way, at the time of forward bias, the injected minority carriers also work as charges accumulated in the capacitor. When the capacity component due to the injected carriers is a diffusion capacity Cd and the pn junction capacity is Cj, the FD capacity _CFD is expressed by a parallel connection as shown in Equation 2.

The diffusion capacitance Cd can be reduced by reducing the diffusion region concentration of the floating diffusion portion FD. Hereinafter, the pn junction capacitance Cj will be described.
By the way, it will be described below that the FD capacitance _CFD becomes smaller when the impurity concentration in the semiconductor well region under the floating diffusion portion FD is reduced to extend the depletion layer.
In the case of one-sided step junction, a depletion layer 101 of a pn junction j as shown in FIG. 12A exists between the diffusion region of the floating diffusion portion FD and the p-type semiconductor well region. In this case, if the n-type diffusion region concentration is Nd, the p-type semiconductor well region concentration is Na, and the depletion layer elongations are Wd (n) and Wd (a), the relationship of Equation 3 is established.

となるので、空乏層は伸びる（図９Ａ参照）。 Therefore, when the concentration of the p-type semiconductor well region is reduced,

Therefore, the depletion layer extends (see FIG. 9A).

By the way, regarding the electric field distribution, the area of the triangle in FIG. 12C becomes the internal potential, and the internal potential is maintained, so that the maximum electric field strength Emax is reduced to E′max as shown in Equation 5.

の関係が成り立つ。 By the way, the depletion layer capacitance Cj is Q = CV,

The relationship holds.

Ｋ ：半導体の比誘電率
ε₀ ：真空の誘電率

Further, the relationship of Equations 7 and 8 is established from the Poisson equation.

K: relative dielectric constant of semiconductor ε ₀ : dielectric constant of vacuum

Equation 9 is derived from the above.

  That is, when the depletion layer is extended, the depletion layer capacitance Cj of the floating diffusion portion FD decreases. Therefore, the conversion efficiency decreases. In addition, from Equation 3, the effect of lowering the conversion efficiency becomes greater when both the diffusion concentration of the floating diffusion portion FD and the concentration of the p-type semiconductor well region are reduced.

  Next, FIGS. 13 to 15 show a second embodiment of the imaging region in the solid-state imaging device 41 described above. 13 to 15 have a pixel sharing structure in which a part of a pixel transistor constituting a pixel is shared by a plurality of pixels.

  First, an equivalent circuit of a pixel sharing cell sharing, for example, four pixels will be described with reference to FIG. In this example, the sources of the corresponding transfer transistors 111, 112, 113, and 114 are connected to the four photodiodes PD1, PD2, PD3, and PD4, respectively. Transfer pulses φTRG1, φTRG2, φTRG3, and φTRG4 are applied to the gates of the transfer transistors 111 to 114 via transfer wirings 116, 117, 118, and 119, respectively. The drains of the transfer transistors 111 to 114 are connected in common and connected to one reset transistor 121 and to the gate of one amplifying transistor 122 via the floating diffusion portion FD. The drains of the reset transistor 121 and the amplification transistor 122 are connected to the pixel power line 123. A reset pulse φRST is applied to the gate of the reset transistor 121 via the reset wiring 1124. Further, the source of the amplification transistor 122 is connected to the drain of one selection transistor 125. The source of the selection transistor 125 is connected to the vertical signal line 49, and the selection pulse φSEL is applied to the gate of the selection transistor 125 via the selection wiring 126.

  In this embodiment, as shown in FIG. 13, a plurality of floating diffusion portions FD are divided into three floating diffusion portions FD1, FD2, and FD3 indicated by broken lines in this example. . The floating diffusion portion FD1 is formed in the transistor occupation region 130 in which the reset transistor is formed. Reference numeral 132 denotes a reset gate. The floating diffusion portion FD2 is formed as a common drain of the two transfer transistors so as to accumulate the signal charges of the two photodiodes PD1 and PD2. 133 and 134 are transfer gates. The floating diffusion portion FD3 is formed as a common drain of the two transfer transistors so as to accumulate the signal charges of the two photodiodes PD3 and PD4. Reference numerals 135 and 136 denote transfer gates. In the transistor occupation region 131, an amplification transistor and a selection transistor are formed. The floating diffusion portions FD 1, FD 2, and FD 3 and the gate of the amplifying transistor in the transistor occupation region 131 are connected by a wiring 138.

  FIG. 14 shows a partial cross-sectional structure of the pixel sharing cell of FIG. In FIG. 14, photodiodes PD <b> 1 to PD <b> 3 that are photoelectric conversion portions are connected to a first conductivity type, for example, an n-type semiconductor substrate 141 via a p-type first semiconductor well region 142 that is a second conductivity type. The photodiode PD1 is representatively formed, and the floating diffusion portion FD is divided into a plurality of portions via the p-type second semiconductor well region 143, and the floating diffusion portions FD1 and FD2 are representatively shown in the drawing. The n-type diffusion regions 145 and 146 are formed, and the reset transistor 121, the amplification transistor 122, and the selection transistor 125 are formed at the subsequent stage of the floating diffusion portion FD through the p-type third semiconductor well region 144. Configured.

  The transfer transistors 111 to 114, which are representative in the figure, include the first and second p-type semiconductor well regions 142 between the photodiode PD1 and the n-type diffusion region 145 serving as the floating diffusion portion FD2. And a transfer gate electrode 133 is formed through a gate insulating film 151 formed so as to straddle 143. The reset transistor 121 is configured by forming a reset gate electrode 132 through a gate insulating film 152 between the n-type diffusion region 146 and the n-type diffusion region 147 to be the floating diffusion FD1. The amplification transistor 122 is configured by forming an amplification gate electrode 137 between the n-type diffusion region 148 and the n-type diffusion region 149 through a gate insulating film 153. The selection transistor 125 is configured by forming a selection gate electrode 138 between the n-type diffusion region 149 and the n-type diffusion region 150 via a gate insulating film 154. The floating diffusions FD2 and FD1 and the amplification gate electrode 137 are connected by a wiring 139. In addition, in order to alleviate the electric field at the diffusion region-well end, that is, to relax the electric field at the pn junction in the source / drain region and maintain the response speed, the LDD structure may be formed before the sidewall formation.

  In the present embodiment, the first, second, and third p-type semiconductor well regions 142, 143, and 144 are separately formed so as to have different impurity concentrations, and the floating diffusion portions FD1 to FD2 are used. The impurity concentration of the second p-type semiconductor well region 143 where the n-type diffusion regions 145 and 146 are formed is set to the third p-type semiconductor well region where the n-type diffusion regions 147 to 150 of the respective transistors in the subsequent stage are formed. The impurity concentration is lower than the impurity concentration of 144. In this case, the second p-type semiconductor well region 143 has at least the impurity concentration of the surface side region where the n-type diffusion regions 145 and 146 which are the floating diffusion portions FD1 and FD2 are formed, as the third p-type semiconductor. The n-type diffusion regions 147 to 150 of the well region 144 are formed so as to have a lower concentration than the impurity concentration of the surface region.

  The impurity concentration of the first p-type semiconductor well region 142 where the photodiode PD1 is formed is lower than the impurity concentration of the third p-type semiconductor well region 144.

  The diffusion regions constituting the floating diffusion portions FD1 to FD3, 145 and 146 in the figure, and the diffusion regions 147 to 150 constituting the pixel transistor portion may be simultaneously formed with the same impurity concentration or simultaneously formed. When not performed, the impurity concentration of the diffusion region of the floating diffusion portion is formed lower than the impurity concentration of the diffusion region of the pixel transistor portion.

  The solid-state imaging device according to the second embodiment, particularly the pixel sharing cell, can be manufactured in the same manner as described with reference to FIGS.

  According to the second embodiment, in the pixel cell having the plurality of divided floating diffusion portions FD [FD1 to FD3], the second p in which the floating diffusion portions FD [FD1 to FD3] are formed. The impurity concentration of the surface semiconductor region 143, at least the surface side region where the floating diffusion portion FD is formed, is lower than the impurity concentration of the third p-type semiconductor well region 144 where the pixel transistor of the subsequent stage is formed. Yes. By setting the second p-type semiconductor well region 142 to a low impurity concentration, the parasitic capacitance in the floating diffusion portions FD1 to FD1 can be reduced, and the conversion efficiency of the pixels can be improved. As a result, the photoelectrically converted charge can be efficiently converted into a voltage.

  In the above example, the impurity concentration of the p-type semiconductor well region in which all of the plurality of floating diffusion portions FD are formed is set to a low concentration, but the required floating diffusion of the plurality of floating diffusion portions FD is reduced. Even if only the sub-type p-type semiconductor well region is configured to have a low impurity concentration, the conversion efficiency of the pixel can be improved due to the reduction of the parasitic capacitance, and the photoelectrically converted charge can be efficiently converted into a voltage.

  In the above example, since electrons have higher mobility than holes as charges, the semiconductor well region is formed in p-type, the photodiode and floating diffusion portion are formed in n-type, and an nMOS transistor is used. However, a configuration in which holes are used as charges can also be used. In the case of holes, p-type diffusion layers (source / drain regions) to be MOS transistors are formed in the n-type semiconductor well region.

It is a schematic block diagram which shows embodiment of the solid-state imaging device applied to this invention. It is sectional drawing which shows 1st Embodiment of the pixel part of the solid-state imaging device which concerns on this invention. FIGS. 7A and 7B are manufacturing process diagrams (part 1) illustrating an embodiment of a method for manufacturing a pixel portion of the solid-state imaging device according to the first embodiment; FIGS. FIGS. 6A and 6B are manufacturing process diagrams (part 2) illustrating an embodiment of a method for manufacturing a pixel portion of the solid-state imaging device according to the first embodiment; FIGS. FIGS. 3A and 3B are manufacturing process diagrams (part 3) illustrating the embodiment of the method for manufacturing the pixel portion of the solid-state imaging device according to the first embodiment; FIGS. FIG. 7A is a manufacturing process diagram (part 4) illustrating the embodiment of the method for manufacturing the pixel portion of the solid-state imaging device according to the first embodiment; It is a top view which shows the mask for ion implantation used at the ion implantation process of FIG. It is a top view which shows the mask for ion implantation used at the ion implantation process of FIG. A, B It is an electric field distribution diagram which shows the expansion state of the depletion layer in the floating diffusion part which compared this invention and the prior art example. It is a graph which shows the relationship between the voltage and the diffusion layer capacity | capacitance in the floating diffusion part which compared this invention and the prior art example. It is a graph which shows the conversion efficiency which compared this invention and the prior art example. A, B, and C It is explanatory drawing of the depletion layer, space charge distribution, and electric field distribution of a pn junction used for description of this invention. It is a top view which shows 2nd Embodiment of the pixel part of the solid-state imaging device which concerns on this invention. FIG. 6 is a partial cross-sectional view of a pixel sharing cell according to a second embodiment. FIG. 6 is an equivalent circuit diagram of a pixel sharing cell according to a second embodiment. It is sectional drawing with which it uses for description of the manufacturing method of the pixel part of a prior art example. It is sectional drawing which shows the example of the pixel part of the conventional solid-state imaging device. It is an equivalent circuit diagram of a pixel cell having a three-transistor structure.

Explanation of symbols

  41..Solid-state imaging device, 42..Pixel, 43..Image area, 44..Vertical drive circuit, 45..Column signal processing circuit, 46..Horizontal drive circuit, 47..Output circuit, 48..Control Circuit 49... Vertical signal line 421... Pixel cell 51.. Semiconductor substrate 52, 53, 54 Semiconductor well region 55 55 Photoelectric conversion part (photodiode) 56 145 146. Diffusion region to be a floating diffusion portion, 57, 58... Diffusion region of transistor, 61, 111... Transfer transistor, 62, 121... Reset transistor, 63, 122. First p-well ion implantation region, 92, second p-well ion implantation region, 93, third p-well ion implantation region, 95, 96, ion implantation Mask

Claims (10)

A plurality of pixels composed of a photoelectric conversion unit and a pixel transistor unit are arranged,
The impurity concentration in the semiconductor well region under the floating diffusion portion in the pixel is set to be lower than the impurity concentration in the semiconductor well region under the pixel transistor portion downstream from the floating diffusion portion. Solid-state imaging device. The semiconductor well region under the photoelectric conversion portion, the semiconductor well region under the floating diffusion portion, and the semiconductor well region under the pixel transistor portion downstream from the floating diffusion portion are formed with different impurity concentrations. The solid-state imaging device according to claim 1. Some pixel transistor parts are shared by multiple pixels,
When the floating diffusion part is divided into multiple parts,
The impurity concentration of the semiconductor well region under the divided floating diffusion portion is set to be lower than the impurity concentration of the semiconductor well region under the pixel transistor portion downstream from the floating diffusion portion. The solid-state imaging device according to claim 1. Some pixel transistor parts are shared by multiple pixels,
When the floating diffusion part is divided into multiple parts,
Of the divided floating diffusion portions, the impurity concentration of the semiconductor well region below the required floating diffusion portion is lower than the impurity concentration of the semiconductor well region below the pixel transistor portion downstream from the floating diffusion portion. The solid-state imaging device according to claim 1, wherein the solid-state imaging device is set. The solid-state imaging device according to claim 1, wherein the diffusion region constituting the floating diffusion portion and the diffusion region constituting the pixel transistor portion are simultaneously formed with the same impurity concentration. 2. The solid-state imaging device according to claim 1, wherein the diffusion region constituting the floating diffusion portion is formed at a lower concentration than the impurity concentration of the diffusion region constituting the pixel transistor portion. In the cell region where the unit pixel cell or the pixel sharing cell of the first conductivity type semiconductor substrate is to be formed, the first second conductivity type semiconductor well region of the photoelectric conversion portion formation region and the floating diffusion portion formation region Forming a second second conductivity type semiconductor well region and a third second conductivity type semiconductor well region of the pixel transistor formation region;
Forming an impurity concentration of the second second conductivity type semiconductor well region to be lower than an impurity concentration of the third second conductivity type semiconductor well region;
A step of forming a photoelectric conversion portion in the first second conductivity type semiconductor well region;
A first conductivity type diffusion region serving as a floating diffusion portion is formed in the second second conductivity type semiconductor well region, and a stage subsequent to the floating diffusion portion is formed in the third second conductivity type semiconductor well region. A method of manufacturing a solid-state imaging device, comprising: forming a first conductivity type diffusion region of a pixel transistor. Ion-implanting a first second-conductivity-type impurity having a concentration peak at a deep portion over the entire surface of the cell region;
A second region having a concentration peak at an intermediate portion between the deep portion and the surface side over the floating diffusion portion forming region and the pixel transistor forming region downstream from the floating diffusion portion except for the photoelectric conversion portion forming region in the cell region. Ion implantation of the second conductivity type impurity of
Ion implantation of a third second conductivity type impurity having a concentration peak on the surface side only in the pixel transistor formation region of the cell region;
Forming a first second conductivity type semiconductor well region in the photoelectric conversion portion formation region; forming a third second conductivity type semiconductor well region in the pixel transistor formation region; and in the floating diffusion portion formation region; 8. The method of manufacturing a solid-state imaging device according to claim 7, wherein a second second conductivity type semiconductor well region having an impurity concentration lower than that of the third second conductivity type semiconductor well region is formed. The solid-state imaging device according to claim 7, wherein the first conductivity type diffusion region of the floating diffusion portion and the first conductivity type diffusion region of the pixel transistor portion are simultaneously formed with the same impurity concentration. Method. The solid-state imaging device according to claim 7, wherein the first conductivity type diffusion region of the floating diffusion portion is formed at a lower concentration than the impurity concentration of the first conductivity type diffusion region of the pixel transistor portion. Method.

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