CN113394239A - Image sensor, fingerprint identification module and electronic device - Google Patents
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- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
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Abstract
The application discloses image sensor, fingerprint identification module and electron device. The image sensor includes: a pixel array comprising a plurality of pixel cells comprising: a floating diffusion region equivalently having a floating diffusion capacitance; a reset selection transistor coupled between the floating diffusion region and a first reference voltage; a photodiode; a transfer transistor coupled between the photodiode and the floating diffusion region; a source follower transistor coupled to the floating diffusion region and the first reference voltage for generating an output voltage according to a voltage gain of the source follower transistor and a voltage of the floating diffusion region; a row select transistor coupled to the source follower transistor; and the capacitance unit is coupled to the floating diffusion region, wherein the capacitance value of the capacitance unit is influenced by the voltage of the floating diffusion region, and when the voltage of the floating diffusion region is higher, the capacitance value of the capacitance unit is higher.
Description
Technical Field
The present disclosure relates to sensors, and particularly to an image sensor, a fingerprint identification module and an electronic device.
Background
The image sensor can be used to capture images, but the image sensor generally has a problem of non-linear relationship between the incident light intensity and the sensing result. Especially, when performing machine vision applications (e.g. fingerprint recognition), if the linearity of the image sensor is not sufficient, additional hardware or software is required to perform linearity correction, which results in a drastic increase in cost.
Therefore, how to improve the linearity of the image sensor at a low cost has become one of the problems to be solved urgently in the art.
Disclosure of Invention
An objective of the present invention is to provide an image sensor, a fingerprint identification module and an electronic device, which solve the above problems.
An embodiment of the present application discloses an image sensor, including: a pixel array comprising a plurality of pixel units arranged in a plurality of rows and a plurality of columns, wherein each pixel unit comprises: a floating diffusion region equivalently having a floating diffusion capacitance; a reset selection transistor coupled between the floating diffusion region and a first reference voltage; a photodiode coupled to a second reference voltage; a transfer transistor coupled between the photodiode and the floating diffusion region for performing gate control between the photodiode and the floating diffusion region; a source follower transistor coupled to the floating diffusion region and the first reference voltage for generating an output voltage according to a voltage gain of the source follower transistor and a voltage of the floating diffusion region; a row select transistor coupled to the source follower transistor; and the capacitance unit is coupled to the floating diffusion region, wherein the capacitance value of the capacitance unit is influenced by the voltage of the floating diffusion region, and when the voltage of the floating diffusion region is higher, the capacitance value of the capacitance unit is higher.
An embodiment of the application discloses fingerprint identification module, include image sensor.
An embodiment of the application discloses an electronic device, include fingerprint identification module.
The application of the image sensor, the fingerprint identification module and the electronic device can improve the linearity of the image sensor.
Drawings
Fig. 1 shows a pixel unit in a pixel array.
The main parasitic capacitance component of the floating diffusion capacitance is shown in fig. 2.
Fig. 3 is a schematic diagram of a first embodiment of a pixel unit in a pixel array of an image sensor according to the present application.
Fig. 4 is a schematic diagram of a first embodiment of a capacitor unit of the pixel unit of fig. 3.
Fig. 5 is a diagram of a second embodiment of a capacitor unit of the pixel unit of fig. 3.
Fig. 6 is a schematic diagram of a third embodiment of a capacitor unit of the pixel unit in fig. 3.
Fig. 7 is a diagram of a second embodiment of a pixel unit in a pixel array of an image sensor according to the present application.
Fig. 8 is test data of linearity of the pixel cell of fig. 7 and the pixel cell 100 of fig. 1.
Fig. 9 is a schematic diagram of an embodiment in which a pixel unit in a pixel array of an image sensor is a two-sharing pixel.
Detailed Description
The following disclosure provides various embodiments or illustrations that can be used to implement various features of the disclosure. The embodiments of components and arrangements described below serve to simplify the present disclosure. It is to be understood that such descriptions are merely illustrative and are not intended to limit the present disclosure. For example, in the description that follows, forming a first feature on or over a second feature may include certain embodiments in which the first and second features are in direct contact with each other; and may also include embodiments in which additional elements are formed between the first and second features described above, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or characters in the various embodiments. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Although numerical ranges and parameters setting forth the broad scope of the application are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. Any numerical value, however, inherently contains certain standard deviations found in their respective testing measurements. As used herein, "about" generally refers to actual values within plus or minus 10%, 5%, 1%, or 0.5% of a particular value or range. Alternatively, the term "about" means that the actual value falls within the acceptable standard error of the mean, subject to consideration by those of ordinary skill in the art to which this application pertains. It is understood that all ranges, amounts, values and percentages used herein (e.g., to describe amounts of materials, length of time, temperature, operating conditions, quantitative ratios, and the like) are modified by the term "about" in addition to the experimental examples or unless otherwise expressly stated. Accordingly, unless indicated to the contrary, the numerical parameters set forth in the specification and attached claims are approximations that may vary depending upon the desired properties sought to be obtained. At the very least, these numerical parameters are to be understood as meaning the number of significant digits recited and the number resulting from applying ordinary carry notation. Herein, numerical ranges are expressed from one end to the other or between the two ends; unless otherwise indicated, all numerical ranges set forth herein are inclusive of the endpoints.
The present application improves an image sensor, and in particular, in an embodiment of the present application, a simple circuit can be used in a pixel array to improve linearity of the image sensor, that is, a linear relationship between a sensing result and an incident light intensity is improved. In the most important embodiment, only one additional transistor is added to each pixel unit to improve the linearity of the pixel unit, thereby greatly reducing the cost required for improving the linearity.
The image sensor comprises a pixel array, wherein the pixel array comprises a plurality of pixel units which are arranged into a plurality of rows and a plurality of columns. A pixel cell 100 in the pixel array is shown in fig. 1, and includes a photodiode 102, a transfer transistor 104, a floating diffusion region FD, a reset select transistor 106, a source follower transistor 108, and a row select transistor 110. The anode of the photodiode 102 is coupled to the second reference voltage V2, and the cathode of the photodiode 102 is coupled to the drain of the pass transistor 104. The source of the transfer transistor 104 is coupled to the floating diffusion FD, and the gate of the transfer transistor 104 is coupled to the signal TX for gating between the photodiode 102 and the floating diffusion FD according to the signal TX. The floating diffusion region FD equivalently has a floating diffusion capacitance 112. The reset select transistor 106 is coupled between the floating diffusion FD and a first reference voltage V1, and a gate of the reset select transistor 106 is coupled to a signal RST. The gate of the source follower transistor 108 is coupled to the floating diffusion FD, the drain of the source follower transistor 108 is coupled to the first reference voltage V1, the source of the source follower transistor 108 is coupled to the row selection transistor 110, and the source follower transistor 108 has a voltage gain G, such that the source follower transistor 108 can generate an output voltage VPO at the source of the row selection transistor 110 according to the voltage VFD of the floating diffusion FD, where the relationship between the voltage VPO and the voltage VFD can be expressed as:
VPO＝V1-VFD*G (1)
the gate of the row selection transistor 110 is coupled to the signal RSEL and selectively outputs the output voltage VPO according to the signal RSEL.
The floating diffusion capacitance 112 is the sum of all parasitic capacitances seen at the floating diffusion region FD. Fig. 2 illustrates the main parasitic capacitance component of the floating diffusion capacitor 112, and as shown in fig. 2, the main sources of the floating diffusion capacitor 112 include: a gate-source overlap capacitance (overlap capacitance)1121 of the transfer transistor 104, a gate-source overlap capacitance 1122 of the reset selection transistor 106, a gate-source overlap capacitance 1127 of the source follower transistor 108, a gate-drain overlap capacitance 1126 of the source follower transistor 108, an equivalent gate-source capacitance 1128 of the source follower transistor 108, a junction capacitance (junction capacitance)1123 formed at the interface of the sidewall of the floating diffusion region FD and the substrate, a junction capacitance 1124 formed at the interface of the bottom of the floating diffusion region FD and the substrate, and a parasitic capacitance 1125 caused by a metal line connecting the floating diffusion region FD and the gate of the source follower transistor 108.
In order to analyze and effectively compensate for the linearity of the image sensor, the present application first divides the parasitic capacitances into three types according to the characteristics of the parasitic capacitances. The first type of parasitic capacitance includes a junction capacitance 1123 formed at the interface between the sidewall of the floating diffusion FD and the substrate and a junction capacitance 1124 formed at the interface between the bottom of the floating diffusion FD and the substrate. The common characteristic of the junction capacitance 1123 and the junction capacitance 1124 is that the capacitance value thereof is affected by the voltage of the floating diffusion area FD, and the capacitance value of the junction capacitance 1123 and the junction capacitance 1124 is lower as the voltage of the floating diffusion area FD is higher. The reason for this is that since the junction capacitance 1123 and the junction capacitance 1124 are both inversely proportional to the thickness of the depletion layer (depletion region), which is affected by the voltage of the floating diffusion FD, and the higher the voltage of the floating diffusion FD is, the larger the thickness of the depletion layer is, and thus the higher the voltage of the floating diffusion FD is, the lower the capacitance values of both the junction capacitance 1123 and the junction capacitance 1124 are.
In other words, the first type of parasitic capacitance has a characteristic that its capacitance value is affected by the voltage of the floating diffusion region FD, and is lower as the voltage of the floating diffusion region FD is higher; the capacitance value of the first type parasitic capacitance is higher as the voltage of the floating diffusion FD is lower. That is, the first type of parasitic capacitance has a bad influence on the linear relationship between the sensing result and the intensity of the incident light.
The second type of parasitic capacitance of the three types includes a gate-source overlap capacitance 1127 of the source follower transistor 108 and an equivalent gate-source capacitance 1128 of the source follower transistor 108. Based on the Miller Effect, the capacitance 1127 and the capacitance 1128 change as the voltage gain G of the source follower transistor 108 changes. Specifically, the capacitance values of the capacitor 1127 and the capacitor 1128 are proportional to the voltage gain G. In other words, the parasitic capacitance of the second type is characterized in that its capacitance value is affected by the voltage gain G, and the higher the voltage gain G, the higher the capacitance value of the parasitic capacitance of the second type; the lower the voltage gain G, the lower the capacitance value of the parasitic capacitance of the second type.
Since the voltage gain G of the source follower transistor 108 is related to the threshold voltage (threshold voltage) of the source follower transistor 108, and the larger the voltage of the floating diffusion FD, the more serious the body effect (body effect) of the source follower transistor 108, resulting in the larger the threshold voltage, the voltage gain G of the source follower transistor 108 is not a fixed value. Thus, that is, the second type of parasitic capacitance also has an adverse effect on the linear relationship between the sensing result and the intensity of the incident light.
The third type of parasitic capacitance among the three types includes a gate-source overlap capacitance 1121 of the transfer transistor 104, a gate-source overlap capacitance 1122 of the reset selection transistor 106, a gate-drain overlap capacitance 1126 of the source follower transistor 108, and a parasitic capacitance 1125 caused by a metal line. The capacitance value of the third type parasitic capacitance is not affected by the voltage of the floating diffusion FD and the voltage gain G of the source follower transistor 108. Furthermore, the capacitance of the third type parasitic capacitor is not affected by the voltage of the floating diffusion FD, so that the capacitance of the third type parasitic capacitor can be regarded as a constant value when the incident light intensity changes, and the linear relationship between the sensing result and the incident light intensity is not adversely affected.
The present application therefore proposes to mitigate or eliminate the effect of the first of the three types of parasitic capacitance in the manner of fig. 3. Since the first type of parasitic capacitance is characterized in that its capacitance value is affected by the voltage of the floating diffusion region FD, the capacitance value of the first type of parasitic capacitance is lower as the voltage of the floating diffusion region FD is higher; since the lower the voltage of the floating diffusion FD, the higher the capacitance of the first type of parasitic capacitance, in the embodiment of the pixel unit 300 shown in fig. 3, compared with the pixel unit 100 shown in fig. 1, there is more capacitive units 312, which have the opposite characteristic to the first type of parasitic capacitance, so as to offset the influence of the voltage of the floating diffusion FD on the first type of parasitic capacitance. Specifically, the capacitance unit 312 is coupled to the floating diffusion FD, wherein the capacitance value of the capacitance unit 312 is also influenced by the voltage of the floating diffusion FD, but the capacitance unit 312 is influenced by the floating diffusion FD in a manner opposite to that of the first type of parasitic capacitance, i.e., the capacitance value of the capacitance unit 312 is higher when the voltage of the floating diffusion FD is higher; when the voltage of the floating diffusion FD is lower, the capacitance value of the capacitance unit 312 is lower.
The present application does not particularly limit the implementation of the capacitance unit 312, but an embodiment in which the capacitance unit 312 is implemented as a metal-oxide-silicon (MOS) capacitor is proposed in fig. 4 to 6. The pixel cell 400 of fig. 4 provides a first embodiment of the capacitive cell 312 of the pixel cell 300 of fig. 3. In fig. 4, the gate of the transistor 412 is coupled to the floating diffusion FD, the source and the drain of the transistor 412 are coupled to the control voltage Vctl, and the body (body) of the transistor 412 is coupled to the second reference voltage V2. The MOS capacitor formed by the transistor 412 connected in the manner of fig. 4 has the desired characteristic that the higher the voltage of the floating diffusion FD, the higher the capacitance value of the MOS capacitor formed by the transistor 412; the lower the voltage of the floating diffusion FD is, the lower the capacitance value of the MOS capacitor formed by the transistor 412 is. In this embodiment, the capacitance of the MOS capacitor formed by the transistor 412 is influenced by the control voltage Vctl, that is, the influence of the floating diffusion FD on the parasitic capacitance of the first type can be better offset by adjusting the control voltage Vctl.
It should be noted that many variations of the connection of the transistor 412 can achieve similar effects, for example, the pixel unit 500 of fig. 5 provides a second embodiment of the capacitor 312 of the pixel unit 300 of fig. 3. The only difference between fig. 5 and fig. 4 is that the bulk of transistor 412 is also coupled to the control voltage Vctl. The pixel cell 600 of fig. 6 provides a third embodiment of the capacitive cell 312 of the pixel cell 300 of fig. 3. The only difference between fig. 6 and fig. 4 is that the source and the drain of the transistor 412 are also coupled to the second reference voltage V2, so the capacitance of the capacitor formed by the transistor 412 in fig. 6 cannot be adjusted by the control voltage Vctl.
The present application also proposes to mitigate or eliminate the effect of the second type of parasitic capacitance of the three types in the manner of fig. 7. Since the parasitic capacitance of the second type is characterized in that the capacitance value thereof is affected by the voltage gain G, the higher the capacitance value of the parasitic capacitance of the second type; as the voltage gain G is lower, the capacitance of the second type parasitic capacitor is lower, and thus, in the embodiment of the pixel cell 700 shown in fig. 7, compared to the pixel cell 300 shown in fig. 3, the current mirror formed by the transistor 714 and the transistor 716, the output stage source follower transistor 718, the output stage row selection transistor 720 and the bias transistor 722 are further included. Wherein the current mirror, output stage source follower transistor 718, and native source follower transistor 108 form a single gain buffer in place of source follower transistor 108, the single gain buffer having a fixed voltage gain of 1 and generating an output voltage VPO from the drain of output stage source follower transistor 718. That is, the voltage gain G of the source follower transistor 108 is limited to 1, so that in the structure of fig. 7, the capacitance of the second type parasitic capacitor can be limited to a constant value, and no adverse effect is caused on the linear relationship between the sensing result and the incident light intensity.
Wherein the sources of the transistors 714 and 716 are coupled to the first reference voltage V1, and the gate of the transistor 714 is coupled to the gate of the transistor 716 and the drain of the transistor 714. The drain of the transistor 714 is coupled to the drain of the source follower transistor 108, the drain of the transistor 716 is coupled to the drain of the output stage source follower transistor 718, the gate of the output stage source follower transistor 718 is coupled to the drain of the output stage source follower transistor 718, the source of the output stage source follower transistor 718 is connected to the drain of the output stage row select transistor 720, the source of the output stage row select transistor 720 is coupled to the source of the row select transistor 110 and to the drain of the bias transistor 722, the gate of the output stage row select transistor 720 is coupled to the first reference voltage V1, the source of the bias transistor 722 is coupled to the second reference voltage V2, and the gate of the bias transistor 722 is coupled to the bias voltage Vb.
It should be noted that the circuit architecture capable of limiting the voltage gain G of the source follower transistor 108 to a constant value is not limited to the implementation of fig. 7. Furthermore, in some embodiments, multiple pixel cells in the pixel array of the image sensor may share an output stage source follower transistor 718, the current mirror (transistors 714 and 716), an output stage row select transistor 720, and a bias transistor 722. For example, multiple pixel cells in the same column of the pixel array of the image sensor can share the circuit to the right of the dotted line in fig. 7 to save die area while reducing the adverse effects of pixel-to-pixel variation. That is, the drain of the transistor 714 is coupled to the drain of the source follower transistor 108 of each of the plurality of pixel units in the same column of the pixel array, and the source of the output stage row selection transistor 720 is coupled to the source of the row selection transistor 110 of each of the plurality of pixel units in the same column of the pixel array.
Fig. 8 is a test data of the linearity of the pixel cell 700 of fig. 7 and the pixel cell 100 of fig. 1, wherein the horizontal axis represents the magnitude of the output voltage VPO and the vertical axis represents the normalized linearity error. Curve C1 represents the result corresponding to pixel cell 700 of fig. 7; curve C2 represents the result for the pixel cell 100 of fig. 1. It can be seen that the linearity error of curve C1 changes less as the output voltage VPO changes; the linearity error of curve C2 varies more strongly. That is, the linearity between the sensing result and the incident light intensity of the pixel cell 700 of fig. 7 is higher than the linearity between the sensing result and the incident light intensity of the pixel cell 100 of fig. 1.
The embodiments of the present application for mitigating the first type of parasitic capacitance and the second type of parasitic capacitance can also be applied to the case where each pixel cell in the pixel array is a shared pixel, such as a two-shared pixel (two-shared pixel) or a four-shared pixel (four-shared pixel). Fig. 9 is a schematic diagram of an embodiment of a pixel unit 900, the difference between the pixel unit 900 and the pixel unit 700 is that the pixel unit 900 is a two-sharing pixel, and compared to the pixel unit 700, the pixel unit 900 additionally includes another photodiode 802 having an anode coupled to a second reference voltage V2, and another transfer transistor 804 having a drain coupled to a cathode of the photodiode 802 and a source coupled to a floating diffusion region FD, the transfer transistor 804 being used for gating between the photodiode 802 and the floating diffusion region FD.
The application also provides a fingerprint identification module, which comprises the image sensor, wherein the image sensor can comprise the pixel unit 100/300/400/500/600/700/900. The application also provides an electronic device, which comprises the fingerprint identification module.
The foregoing description has set forth briefly the features of certain embodiments of the present application so that those skilled in the art may more fully appreciate the various aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should understand that they can still make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.
Claims (13)
1. An image sensor, comprising:
a pixel array comprising a plurality of pixel units arranged in a plurality of rows and a plurality of columns, wherein each pixel unit comprises:
a floating diffusion region equivalently having a floating diffusion capacitance;
a reset selection transistor coupled between the floating diffusion region and a first reference voltage;
a photodiode coupled to a second reference voltage;
a transfer transistor coupled between the photodiode and the floating diffusion region for performing gate control between the photodiode and the floating diffusion region;
a source follower transistor coupled to the floating diffusion region and the first reference voltage for generating an output voltage according to a voltage gain of the source follower transistor and a voltage of the floating diffusion region;
a row select transistor coupled to the source follower transistor; and
and the capacitance value of the capacitance unit is influenced by the voltage of the floating diffusion region, and when the voltage of the floating diffusion region is higher, the capacitance value of the capacitance unit is higher.
2. The image sensor of claim 1, wherein the floating diffusion capacitance is generated by contributions of a plurality of parasitic capacitances, the plurality of parasitic capacitances including a first type parasitic capacitance, a second type parasitic capacitance, and a third type parasitic capacitance, wherein a capacitance value of the first type parasitic capacitance is affected by a voltage of the floating diffusion region, and the capacitance value of the first type parasitic capacitance is lower as the voltage of the floating diffusion region is higher; a capacitance value of the second type parasitic capacitance is affected by the voltage gain of the source follower transistor; and a capacitance value of the third type parasitic capacitance is not affected by a voltage of the floating diffusion region and the voltage gain of the source follower transistor.
3. The image sensor of claim 2, wherein the effect of the voltage of the floating diffusion region on the capacitance value of the first type parasitic capacitance is offset by the capacitive unit.
4. The image sensor of claim 1, wherein the capacitive unit comprises a transistor having a gate coupled to the floating diffusion region and a source coupled to a drain.
5. The image sensor of claim 4, wherein the source and the drain of the transistor of the capacitive cell are coupled to a control voltage, the capacitance of the capacitive cell being affected by the control voltage.
6. The image sensor of claim 5, wherein a body of the transistor of the capacitive unit is coupled to the second reference voltage.
7. The image sensor of claim 5, wherein a body of the transistor of the capacitive unit is coupled to the control voltage.
8. The image sensor of claim 4, wherein the source, the drain, and a body of the transistor of the capacitive unit are coupled to the second reference voltage.
9. The image sensor of claim 2, wherein the pixel array further comprises:
an output stage source follower transistor;
a current mirror coupled to the first reference voltage, the source follower transistor, and the output stage source follower transistor;
an output stage row select transistor coupled to the output stage source follower transistor; and
a bias transistor coupled to the row select transistor, the output stage row select transistor, and the second reference voltage;
wherein the current mirror, the source follower transistor, and the output stage source follower transistor form a single gain buffer, keeping the voltage gain of the source follower transistor at 1.
10. The image sensor of claim 9, wherein pixel cells of a same column of the plurality of pixel cells share the output stage source follower transistor, the current mirror, the output stage row select transistor, and the bias transistor.
11. The image sensor of claim 1, wherein each pixel cell is a two-share pixel, and further comprising:
another photodiode coupled to a second reference voltage; and
another transfer transistor, coupled between the other photodiode and the floating diffusion region, for performing gate control between the other photodiode and the floating diffusion region.
12. The utility model provides a fingerprint identification module which characterized in that includes:
the image sensor of any one of claims 1 to 11.
13. An electronic device, comprising:
the fingerprint identification module of claim 12.
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| WO2023039840A1 (en) * | 2021-09-17 | 2023-03-23 | 迪克创新科技有限公司 | Comparator and related image sensor, and electronic apparatus |
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