JP2008086157A - Power converter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To overcome the problem that a current flowing in smoothing capacitors is increased and the smoothing capacitors are enlarged owing to the mutual influences of the current flowing from the DC/DC converter to the smoothing capacitors and the current flowing from the smoothing capacitors to the three-phase inverter if a three-phase inverter is connected as a load on the high voltage side of the DC/DC converter. <P>SOLUTION: A period for discharging a charge accumulated in the smoothing capacitors Cs1-Cs3 is provided in a period for making a DC side input current Ip of the inverter 20 zero. The smoothing capacitors and the power converter are downsized by minimizing a ripple current flowing in the smoothing capacitors. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a power conversion device including a DC / DC converter that converts a DC voltage into a DC voltage that is stepped up or down, and an inverter that converts the DC voltage from the DC / DC converter into an AC voltage. .

  DC / DC converters that convert DC voltages into different DC voltages are widely used, and many circuit systems have been proposed and put into practical use. As a method of a DC / DC converter, a method using a charge / discharge charge of a capacitor without using magnetic parts such as a transformer and a choke coil has been proposed.

For example, an inverter circuit including at least two semiconductor switches including a semiconductor switch connected to a positive potential and a semiconductor switch connected to a negative potential, and a plurality of rectifiers connected in series are connected in series. There has been proposed a DC / DC converter including a multiple voltage rectifier circuit including a plurality of capacitors. With such a configuration, a high-voltage DC voltage can be supplied by a combination of medium-voltage components instead of high-voltage components, and since there are no large-sized components such as transformers and choke coils, DC / DC converters Small, thin and light weight can be achieved. (See Patent Document 1)
JP-A-9-191638 (page 5, FIG. 1)

  The conventional DC / DC converter is related to the DC voltage conversion function which is a basic function. When a three-phase inverter is connected as the high-voltage side load of the DC / DC converter, the current that flows from the DC / DC converter to the smoothing capacitor and the current that is supplied from the smoothing capacitor to the three-phase inverter influence each other and flows to the smoothing capacitor. The value will increase. In order to ensure the life of the smoothing capacitor, if the ripple current flowing in each capacitor is set to be less than the allowable value, the smoothing capacitor becomes large and the entire apparatus becomes large.

  The present invention has been made to solve the above-described problems. In a power converter in which a DC / DC converter and a three-phase inverter are integrated, the ripple current flowing in the smoothing capacitor is minimized, and the power converter The purpose is to achieve miniaturization.

  According to the power converter of the present invention, a plurality of semiconductor switching elements whose ON / OFF operations are controlled by a control electrode and a smoothing capacitor are connected by arranging a series body of a capacitor and an inductor, respectively. A DC / DC converter that performs DC / DC power conversion by charging / discharging and an inverter that converts DC voltage from the DC / DC converter into AC voltage by ON / OFF control of a plurality of semiconductor switching elements. The DC / DC converter is provided with a period for discharging the electric charge charged in the smoothing capacitor during a period when the input current to the inverter becomes zero.

  Further, the power conversion device according to the present invention connects a plurality of circuits composed of a plurality of semiconductor switching elements and smoothing capacitors whose on / off operations are controlled by the control electrode by arranging a series body of capacitors and inductors, respectively. DC / DC converter that performs DC / DC power conversion by charging and discharging the capacitor, and an inverter that converts a DC voltage from the DC / DC converter into an AC voltage by ON / OFF control of a plurality of semiconductor switching elements In the apparatus, the output current of the DC / DC converter and the timing of the input current to the inverter are matched.

  The present invention can reduce the current flowing through a smoothing capacitor for DC voltage smoothing provided between the DC / DC converter and the inverter, so that the smoothing capacitor can be miniaturized and the power converter can be miniaturized. Can do.

Embodiment 1 FIG.
FIG. 1 is a configuration diagram of a semiconductor power conversion device according to Embodiment 1 of the present invention. As shown in FIG. 1, the semiconductor power conversion device includes a DC / DC converter 10 and a three-phase inverter 20. The DC / DC converter 10 has a function of converting the DC voltage V1 input between the voltage terminals VL and Vcom into a DC voltage V2 boosted about three times and outputting the voltage between the voltage terminals VH and Vcom. The three-phase inverter 20 has a function of outputting an independent AC voltage to the U terminal, the V terminal, and the W terminal from the DC voltage V2 input between VH and Vcom.

First, the main circuit configuration of the DC / DC converter 10 will be described.
The main circuit portion of the DC / DC converter 10 includes smoothing capacitors Cs1, Cs2, and Cs3 for smoothing the input voltage V1 input between the voltage terminals VL and Vcom and the output voltage V2 output between the voltage terminals VH and Vcom. And a MOS field effect transistor (hereinafter referred to as MOSFET) as a plurality of semiconductor switching elements, the MOSFET being a low voltage side switch, two MOSFETs (Mos1L, Mos1H) (Mos2L, Mos2H) (Mos3L, Mos3H) are connected in series, and circuits A1, A2, and A3 connected between both terminals of the smoothing capacitors Cs1, Cs2, and Cs3 are connected in series. Then, with the connection point of the two MOSFETs in each circuit A1, A2, A3 as an intermediate terminal, the capacitor Cr12 and the inductor Lr12 and the capacitor Cr23 and the inductor Lr23 are connected between the intermediate terminals of the adjacent circuits A1, A2, and A3. An LC series circuit configured as a series body and functioning as an energy transfer element is connected.

  Each MOSFET is a power MOSFET in which a parasitic diode is formed between a source and a drain, and is a switching element whose on / off operation is controlled by applying a signal to a gate (control electrode). Further, the capacitance values of the smoothing capacitors Cs1, Cs2, and Cs3 are set to a sufficiently large value as compared with the capacitance values of the capacitors Cr12 and Cr23 of the LC series circuit. The gate signals G1L and G1H applied to the gates of the MOSFETs (Mos1L and Mos1H) are generated by comparing the carrier signal and the command value for determining the switching frequency of the MOSFETs (Mos1L and Mos1H) as will be described later. It has come to be.

Next, the operation of the DC / DC converter 10 will be described. As an operation condition, it is assumed that the power supplied from the voltage terminal VL-Vcom is consumed by the inverter 20 as a constant power load (input current Ip to the inverter = constant value).
FIG. 2 shows gate signals G1L and G1H for driving Mos1L and Mos1H, currents flowing through the MOSFETs (Mos1L to Mos3L, Mos1H to Mos3H), and currents Ics1 to Ics3 flowing through the smoothing capacitors Cs1, Cs2, and Cs3. Here, each MOSFET is turned ON when the gate signals G1L and G1H are High, and the polarity of the current is positive in the direction in which the MOSFET flows from the drain to the source, and the smoothing capacitors Cs1 to Cs3 are charged. The direction in which the electric charge is charged in the smoothing capacitor and the energy is transferred is positive.

  The gate signals G1H and G1L are on / off signals having a cycle T slightly larger than the resonance period determined by the LC series circuit including the capacitor Cr and the inductor Lr and a duty of about 50%, and the MOSFET is turned on when the gate signal is High.

First, when the gate signal G1L becomes High and Mos1L is turned on, a part of energy stored in the smoothing capacitor Cs1 is transferred to the capacitor Cr12 through the following path.
Cs1⇒Mos2L⇒Lr12⇒Cr12⇒Mos1L
Next, when the gate signal G1H is High and Mos1H is turned on, and when the gate signal G1L is Low and Mos1L is turned off, the energy charged in the capacitor Cr12 is transferred to the smoothing capacitor Cs2 through the following path. Transition.
Cr12⇒Lr12⇒Mos2H⇒Cs2⇒Mos1H⇒Cr12
At the same time, energy is stored in the smoothing capacitor Cs1 by the DC voltage supplied from the voltage terminal VL-Vcom.

Next, when the gate signal G1L becomes High and Mos1L is turned on, a part of the energy stored in the smoothing capacitor Cs1 is transferred to the capacitor Cr12 through the same path as described above, and is stored in the smoothing capacitor Cs2. A part of the energy transferred to the capacitor Cr23 through the following path.
Cs2⇒Mos3L⇒Lr23⇒Cr23⇒Lr12⇒Cr12⇒Mos1L⇒Cs1
Next, when the gate signal G1H becomes High and Mos1H is turned on, a part of the energy charged in the capacitor Cr12 is transferred to the smoothing capacitor Cs2 through the same path as described above, and is charged in the capacitor Cr23. The energy is transferred to the smoothing capacitor Cs3 through the following path.
Cr23⇒Lr23⇒Mos3H⇒Cs3⇒Cs2⇒Mos1H⇒Cr12⇒Lr12

  In this way, energy is sequentially transferred from the smoothing capacitor Cs1 to the smoothing capacitor Cs2 and further from the smoothing capacitor Cs2 to the smoothing capacitor Cs3 by charging and discharging the capacitors Cr12 and Cr23. Then, the voltage V1 input between the voltage terminals VL and Vcom is changed to a voltage V2 boosted about three times and output between the voltage terminals VH and Vcom. In addition, since the inductors Lr12 and Lr23 are connected in series to the capacitors Cr12 and Cr23 to form an LC series circuit, the energy transfer utilizes a resonance phenomenon, and a large amount of energy can be transferred efficiently.

  As shown in FIG. 2, although the current waveforms Ics1 to Ics3 flowing through the smoothing capacitors Cs1 to Cs3 are different, the periods of the currents Ics1 to Ics3 coincide with the periods of the gate signals G1L and G1H, and the gate signal G1H is low. Sometimes the electric charge is discharged, and when the gate signal G1H is High, a current flows in the direction of charging the electric charge. Thus, although the currents Ics1 to Ics3 flowing through the smoothing capacitors Cs1 to Cs3 are different, the currents Ics1 to Ics3 and the fundamental frequencies of the gate signals G1L and G1H, and the phases of the currents Ics1 to Ics3 and the gate signals G1L and G1H are fundamental frequencies. Can be seen to be the same.

  In addition, since a parasitic diode is formed in each MOSFET, the gate control signal input of Mos2L, Mos2H, Mos3L, and Mos3H is not necessary in principle. If a gate control signal that turns on each MOSFET when a parasitic diode is turned on by using the synchronous rectification action of the MOSFET is input, the on-voltage of the MOSFET is lowered, so that the loss of the MOSFET can be reduced.

Next, the configuration of the three-phase inverter 20 will be described.
As shown in FIG. 1, the main circuit portion of the three-phase inverter 20 includes two semiconductor switching elements (SuL, SuH) (SvL, SvH) (SwL) between the voltage terminals VH and Vcom which are output terminals of the DC / DC converter 10. , SwH) are connected in series, and U-phase, V-phase, and W-phase AC power is output from the connection point of the two semiconductor switching elements, respectively. As will be described later, gate signals GuH, GVH, GwH, GuL, GVL are generated at the gate terminals of the respective semiconductor switching elements based on a comparison operation between the carrier signal and the fundamental signal of the U phase / V phase / W phase. , GwL is applied.

Next, the operation of the three-phase inverter 20 will be described.
FIG. 3 is a diagram for explaining the operation of the inverter 20. FIG. 3 shows the carrier signal waveform of the inverter, the fundamental wave signal waveforms (voltage indication values) of the U phase, V phase, and W phase, the gate signal GuH generated based on the comparison operation of the carrier signal and the fundamental wave signal, GvH, GwH, U-phase, V-phase, and W-phase motor phase currents, and input current Ip to inverter 20 are shown.
The gate signals GuH, GvH, GwH, GuL, GvL, GwL are inputted to the gate terminals of the semiconductor switching elements SuH, SvH, SwH, SuL, SvL, SwL, respectively, so that the basic of U phase, V phase, W phase An AC voltage dependent on the input voltage (VH-Vcom terminal voltage) of the inverter 20 having the same amplitude as that of the wave signal is generated at each phase terminal.

By changing the amplitude of the fundamental wave signal of each phase, the amplitude of the voltage generated at the terminal of each phase can be changed. Further, by changing the phase of each phase current and the fundamental wave signal, the terminal voltage of each phase and the phase of each phase current can be changed.
The ratio of the carrier signal zero-peak value of the inverter 2 to the amplitude value of each phase fundamental wave signal (fundamental wave amplitude value / inverter carrier zero-peak value) is referred to as a modulation rate. Also, cos φ where the phase of the phase current and the fundamental wave signal is φ is called a power factor.

Next, a description will be given of a suppression operation (minimization operation) of a ripple current flowing through the smoothing capacitors Cs1, Cs2, and Cs3 according to the first embodiment of the present invention.
The currents Ics1, Ics2, and Ics3 flowing through the smoothing capacitors Cs1, Cs2, and Cs3 are the input current Ip to the inverter 20 due to the operation of the inverter 20 and the DC / DC converter 10 that flows when the DC / DC converter 10 is operated. It is the difference between the output currents Io1, Io2, and Io3, and can be expressed by equation (1).
Ics1 = Io1-Ip
Ics2 = Io2-Ip (1)
Ics3 = Io3-Ip
Here, the output currents Io1, Io2, and Io3 of the DC / DC converter 10 are represented by the following equation (2) in FIG.
Io1 = Ih1 + Ih2 + Ih3
Io2 = Ih2 + Ih3 (2)
Io3 = Ih3
However, Ih1, Ih2, and Ih3 are currents that flow from MosxH to the smoothing capacitor Csx side.

  In order to reduce the effective current value flowing through the smoothing capacitors Cs1 to Cs3, the timing of the input current Ip to the inverter 20 and the output currents Io1 to Io3 of the DC / DC converter 10 may be matched. In order to match the timing of the input current Ip to the inverter 20 and the output currents Io1 to Io3 of the DC / DC converter 10, the basic frequencies of the input current Ip and the output currents Io1 to Io3 are matched, and the input current Ip and the output It is necessary to match the phases of the fundamental frequencies of the currents Io1 to Io3.

First, a method for matching the fundamental frequencies of the input current Ip and the output currents Io1 to Io3 will be described. The input current Ip to the inverter 20 is a pulsed current waveform, and this pulse current waveform changes depending on the drive conditions of the inverter 20 such as the power factor and the modulation factor. However, as shown in FIG. 3, the fundamental frequency of the pulsed input current Ip is twice the carrier signal frequency of the inverter 20 regardless of the drive conditions of the inverter 20. On the other hand, the fundamental frequency of the output currents Io1 to Io3 of the DC / DC converter 10 is the same as the frequency of the gate signal G1H of the DC / DC converter 10.
From the above, in order to make the input current Ip to the inverter 20 and the fundamental frequencies of the output currents Io1 to Io3 of the DC / DC converter 10 coincide with each other, the gate signal frequency of the DC / DC converter 10, that is, the switching elements G1L, G1H Is set to twice the carrier signal frequency of the inverter 20.

Next, a method for matching the phases of the input current Ip and the output currents Io1 to Io3 will be described. The input current Ip to the inverter 20 becomes zero (hereinafter referred to as a zero voltage vector state), as shown in FIG. 3, the U-phase, V-phase, and W-phase High arm side switching elements SuH, SVH, SwH. Is a period in which all the U-phase, V-phase, and W-phase Low arm side switching elements SuL, SVL, SwL are on. The time for which the inverter 20 is in the voltage zero vector state varies depending on the inverter driving conditions such as the power factor and the modulation factor, but when the carrier signal of the inverter 20 becomes a peak or a valley as shown in FIG. 20 is always in a voltage zero vector state, and the input current Ip of the inverter 20 is zero.
When the motor current is averaged over one cycle, the fundamental frequency component of the input current Ip has a minimum amplitude when the carrier signal of the inverter 20 is a peak or valley, and a maximum amplitude when the carrier signal of the inverter 20 becomes zero. It becomes.

  On the other hand, the output currents Io1 to Io3 of the DC / DC converter 10 are output when the gate signal G1H is High (a period in which charge is charged in the smoothing capacitor and energy is transferred from the LC series circuit), and the gate signal G1L is High. In this case (period in which the charge of the smoothing capacitor is discharged and energy is transferred to the LC series circuit), no output is made. Since the gate signal G1H is a fixed signal with a duty of about 50%, the phase relationship between the gate signal phase and the output currents Io1 to Io3 is constant under any operating condition.

  From the above, the timing at which the amplitude of the fundamental frequency component of the input current Ip of the inverter 20 is maximized matches the timing at which the amplitude of the fundamental frequency component of the output currents Io1 to Io3 of the DC / DC converter 10 is maximized. For example, the phase of the input current Ip to the inverter 20 and the output currents Io1 to Io3 of the DC / DC converter can be matched. That is, the center point of the timing when the carrier signal of the inverter 20 becomes zero and the period when the gate signal G1H of the DC / DC converter 10 becomes High (the period when charge is charged in the smoothing capacitor and energy is transferred from the LC series circuit). Each phase may be set so that the values match.

  Alternatively, the timing at which the amplitude of the fundamental frequency component of the input current Ip of the inverter 20 is minimized (zero), and the timing at which the amplitude of the fundamental frequency component of the output currents Io1 to Io3 of the DC / DC converter 10 is minimized (zero or less). The phase of the input current Ip to the inverter 20 and the output currents Io1 to Io3 of the DC / DC converter 10 can also be matched. That is, the timing when the carrier signal of the inverter 20 becomes a peak or a valley and the period when the gate signal G1L of the DC / DC converter 10 becomes High (the period during which the charge of the smoothing capacitor is discharged and energy is transferred to the LC series circuit). What is necessary is just to set each phase so that a center point may correspond.

FIG. 4 is a diagram showing operation waveforms when the above-described method is applied and the frequency and phase of the carrier signal of the inverter 20 and the gate signal G1H of the switching element of the DC / DC converter 10 are optimized. FIG. 5 is a diagram showing an operation waveform when the phase of the carrier signal of the inverter 20 and the phase of the gate signal of the switching element of the DC / DC converter 10 becomes worst.
4 and 5, the carrier signal waveform of the inverter 20, the gate signal waveform G1H of the switching element of the DC / DC converter 10, the output currents Io1 to Io3 of the DC / DC converter 10, the input current Ip of the inverter 20, and the smoothing capacitor Cs1. Currents Ics1 to Ics3 flowing through .about.Cs3 are shown.

  In the optimum phase condition of FIG. 4, the timing of the output currents Io1 to Io3 of the DC / DC converter 10 and the input current Ip of the inverter 20 coincide, that is, the period during which the input current Ip of the inverter 20 is zero is Since the gate signal G1H of the switching element of the DC / DC converter 10 becomes Low and it becomes a period for discharging the charges charged in the smoothing capacitors Cs1 to Cs3, the currents Ics1 to Ics3 flowing through the smoothing capacitors Cs1 to Cs3 can be reduced. . On the other hand, in the worst phase condition of FIG. 5, since the timings of the output currents Io1 to Io3 of the DC / DC converter 10 and the input current Ip of the inverter 20 do not match, the currents Ics1 to Ics3 flowing through the smoothing capacitors increase.

  FIG. 6 shows the relationship between the deviation (degree) from the optimum phase and the ripple current effective values of the currents Ics1 to Ics3 flowing through the smoothing capacitors Cs1 to Cs3. The operating conditions were a modulation factor of 0.6 and a power factor of 0.6. Thus, by optimizing the frequency and phase of the carrier signal of the inverter 20 and the gate signal of the switching element of the DC / DC converter 10, the amount of deviation from the optimal phase is −90 (degree) to 90 (degree). ) (This period corresponds to a period during which the charges charged in the smoothing capacitors Cs1 to Cs3 are discharged), and the effective values of the currents Ics1 to Ics3 flowing through the smoothing capacitors Cs1 to Cs3 can be reduced. Become.

  This means that the timing of the input current Ip of the inverter 20 and the output currents Io1 to Io3 of the DC / DC converter 10 do not necessarily coincide with each other, and smoothing is performed within a period in which the input current Ip to the inverter 20 is zero. The effective value of the ripple current flowing through the smoothing capacitors Cs1 to Cs3 is obtained by providing a period in which the charges of the capacitors Cs1 to Cs3 are discharged and energy is transferred to the LC series circuit and the output currents Io1 to Io3 of the DC / DC converter 10 are zero. It means that it can be reduced.

Next, a signal generation circuit and a signal generation method for optimizing the frequency and phase of the carrier signal of the inverter 20 and the gate signal of the switching element of the DC / DC converter 10 will be described.
FIG. 7 shows a configuration diagram of a signal generation circuit of the gate signal of the MOSFET of the DC / DC converter 10 and the gate signal of the switching element of the inverter 20, and FIG. 8 shows an operation explanatory diagram of the signal generation circuit. 3 shows a signal generation means by PWM (pulse width modulation) control of a triangular wave comparison method.

  In the signal generation circuit of FIG. 7, the gate signal of the switching element of the inverter 20 is a comparison operation between the fundamental wave of U phase, V phase, and W phase and the carrier signal 1 by the calculators 21, 22, and 23, The gate signals GuH, GVH, and GwH of the switching elements SuH, SvH, and SwH are used, and the outputs of the calculators 21 to 23 are inverted by the inverters 31, 32, and 33, thereby the gate signals GuL of the switching elements SuL, SvL, and SwL. It generates as GvL and GwL.

Further, the gate signal of the MOSFET (switching element) of the DC / DC converter 10 is obtained by comparing the carrier signal 2 different from the carrier signal 1 of the inverter 20 and the command value with the calculator 24, thereby calculating the MOSFET (Mos 1 H). The gate signal G1H is generated, and the output of the computing unit 24 is inverted by the inverter 34 to generate the gate signal G1L of the MOSFET (Mos1L).
In the first embodiment, as shown in FIG. 8, the high-side gate signal G1H comparator 24 of the DC / DC converter 10 is high when the command value is larger than the carrier signal 2 and low when the command value is small. It is said. The low-side gate signal GxL is an inverted signal of GxH. Further, as shown in FIG. 3, the high-side gate signals GuH to GwH of the inverter 20 are set to High when the fundamental waves are larger than the carrier signal 1 and set to Low when the fundamental waves are smaller.

As shown in FIG. 8, the carrier signal 1 of the inverter 20 and the carrier signal 2 of the DC / DC converter 10 are both triangular waveforms, and the carrier signal frequency of the DC / DC converter 10 is twice the carrier signal frequency of the inverter. Is set. Further, the carrier signal 2 of the DC / DC converter 10 is set to have a peak when the carrier signal 1 of the inverter 20 has a peak and a valley.
Alternatively, the carrier signal 2 of the DC / DC converter 10 may be set to have a valley when the carrier signal 1 of the inverter 20 has a peak and a valley. In this case, when the command value is larger than the carrier signal, it needs to be Low, and when the command value is smaller, it needs to be High.

  With this configuration, the gate signal G1H of the switching element of the DC / DC converter 10 can be set to the center point of the High state at the timing when the carrier signal of the inverter 20 becomes zero. As a result, it becomes possible to make the timings of the output currents Io1 to Io3 of the DC / DC converter 10 and the input current Ip of the inverter 20 match, that is, during the period when the DC side input current Ip of the inverter 20 becomes zero. By providing a period for discharging the charges charged in the smoothing capacitors Cs1 to Cs3 of the / DC converter 10, it becomes possible to reduce the ripple current flowing through the smoothing capacitors Cs1 to Cs3.

Embodiment 2. FIG.
Next, a signal generation circuit and a generation method of another embodiment for optimizing the frequency and phase of the carrier signal of the inverter 20 and the gate signal of the switching element of the DC / DC converter 10 will be described.
FIG. 9 shows a configuration diagram of a signal generation circuit of the MOSFET gate signal of the DC / DC converter 10 and the switching element gate signal of the inverter 20 in the second embodiment, and FIG. 10 shows an operation explanatory diagram of the signal generation circuit. The second embodiment also shows a signal generation means by PWM (pulse width modulation) control using a triangular wave comparison method.

  In the signal generation circuit of FIG. 9, the gate signals of the inverter 10 and the DC / DC converter 20 are generated based on a common carrier signal. The gate signal of the switching element of the inverter 20 is obtained by comparing the U-phase, V-phase, and W-phase fundamental waves with the carrier signal by the calculators 21, 22, and 23, and the output is the gate of the switching elements SuH, SvH, and SwH. The signals GuH, GVH, and GwH are used, and the outputs of the calculators 21 to 23 are inverted by the inverters 31, 32, and 33, thereby generating the gate signals GuL, GvL, and GwL of the switching elements SuL, SvL, and SwL.

  Further, the gate signal of the MOSFET (switching element) of the DC / DC converter 10 is a comparison operation between the carrier signal and the command value 1 by the calculator 25 to be a signal A, and the carrier signal and the command value 2 are compared by the calculator 26. Then, the output signal is inverted by the inverter 35 to be the signal B, the signal A and the signal B are input to the AND circuit 41, and the output is the gate signal G1H of the MOSFET (Mos1H). Further, the output of the AND circuit 41 is inverted by the inverter 36 to generate the gate signal G1L of the MOSFET (Mos1L).

Also in the second embodiment, as shown in FIG. 10, when the command values 1 and 2 are larger than the carrier signal as the comparison arithmetic units 25 and 26 for the high-side gate signal G1H of the DC / DC converter 10, respectively, the high level is high. When it is small, it is Low. Similarly to the first embodiment, the comparison arithmetic units 31 to 33 for the high-side gate signals GuH to GwH of the inverter 20 are set to High when each fundamental wave is larger than the carrier signal 1 and set to Low when each fundamental wave is smaller.
Here, when the maximum value of the carrier signal is 1 and the minimum value is −1, the command value 1 is set to 0.5, and the command value 2 is set to −0.5, thereby generating the gate signal G1H having a duty of 50%. It becomes possible.

With such a configuration, the gate signal G1H of the DC / DC converter 10 can be set to the center point of the high state at the timing when the carrier signal of the switching element of the inverter 20 becomes zero. It becomes possible to match the timings of the output currents Io1 to Io3 of the DC converter 10 and the input current Ip of the inverter 20. That is, a period for discharging the charges charged in the smoothing capacitors Cs1 to Cs3 of the DC / DC converter 10 is provided in a period in which the DC-side input current Ip of the inverter 20 is zero, and the smoothing capacitors Cs1 to Cs3 are set. It is possible to reduce the flowing ripple current.
Further, since a common carrier signal is used as the gate signal generation means of the inverter 20 and the DC / DC converter 10, it is possible to easily realize the synchronization of the gate signals of the inverter 20 and the DC / DC converter 10. Become.

1 is an overall configuration diagram of a power conversion device according to Embodiment 1 of the present invention. It is operation | movement explanatory drawing of the DC / DC converter by Embodiment 1 of this invention. It is operation | movement explanatory drawing of the inverter by Embodiment 1 of this invention. It is operation | movement explanatory drawing at the time of the optimal operation | movement by Embodiment 1 of this invention. It is operation | movement explanatory drawing at the time of the worst operation | movement when not using Embodiment 1 of this invention. It is a figure which shows the ripple current reduction effect of the smoothing capacitor by Embodiment 1 of this invention. It is a block diagram of the signal generation circuit by Embodiment 1 of this invention. It is operation | movement explanatory drawing of the signal generation circuit by Embodiment 1 of this invention. It is a block diagram of the signal generation circuit by Embodiment 2 of this invention. It is operation | movement explanatory drawing of the signal generation circuit by Embodiment 2 of this invention.

Explanation of symbols

10: DC / DC converter 20: Inverter Mos1L to Mos3L, Mos1H to Mos3H: MOSFET
SuH, SVH, SwH, SuL, SVL, SwL: Semiconductor switching elements Cs1, Cs2, Cs3: smoothing capacitors Cr12, Cr23: capacitors Lr12, Lr23: inductors 21-26: calculators 31-36: inverters 41: AND circuits

Claims (6)

  A circuit composed of a plurality of semiconductor switching elements and smoothing capacitors whose ON / OFF operations are controlled by the control electrodes is connected by connecting a series of capacitors and inductors, and DC / DC power conversion is performed by charging and discharging the capacitors. In a power conversion apparatus comprising: a DC / DC converter that performs DC conversion; and an inverter that converts a DC voltage from the DC / DC converter into an AC voltage by on / off control of a plurality of semiconductor switching elements. An electric power converter comprising: a period for discharging energy charged in the smoothing capacitor and transferring energy to a series body of the capacitor and the inductor during a period in which an input current to the inverter becomes zero.   A circuit composed of a plurality of semiconductor switching elements and smoothing capacitors whose ON / OFF operations are controlled by the control electrodes is connected by connecting a series of capacitors and inductors, and DC / DC power conversion is performed by charging and discharging the capacitors. In a power conversion device comprising: a DC / DC converter that performs DC conversion; and an inverter that converts a DC voltage from the DC / DC converter into an AC voltage by on / off control of a plurality of semiconductor switching elements. And the timing of the input current to the inverter are made to coincide with each other.   The power converter according to claim 1 or 2, wherein the switching frequency of the semiconductor switching element of the DC / DC converter is synchronized with the carrier frequency of the inverter.   The power conversion device according to claim 3, wherein the switching frequency of the semiconductor switching element of the DC / DC converter is twice the carrier frequency of the inverter.   The on / off control of the semiconductor switching elements of the inverter and the DC / DC converter is based on triangular wave comparison type PWM control, and the peak and valley timing of the carrier signal of the inverter and the peak of the carrier signal of the DC / DC converter or The power converter according to any one of claims 1 to 4, wherein trough timings are matched.   The on / off control of the semiconductor switching elements of the inverter and the DC / DC converter is based on a triangular wave comparison type PWM control that performs a comparison operation based on the same carrier signal, and the control signal of the semiconductor switching element of the DC / DC converter is The power converter according to claim 1, wherein the power converter is generated by performing a comparison operation based on at least two command values.

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