JP2008084525A - Thin magnetic film storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To read data by using a dummy memory cell in the same configuration and a shape as the normal memory cell. <P>SOLUTION: The data read circuit 160 reads the data by detecting and amplifying a difference between a current passing through a selective memory cell and a dummy cell. The normal memory cell MC has a tunnel magnetoresistive element TMR and an access transistor ATR. The dummy cell 200 has the tunnel magnetoresistive element TMR and the access transistor ATR, and a similarly composed dummy access component ATRd and a dummy magnetoresistive element TMRd, and a dummy resistance adding part 205. The dummy resistance adding part 205 is made and designed like the access transistor ATR and have transistors 206, 207 to apply adjustable control voltage Vrd to each gate. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a thin film magnetic device, and more particularly to a thin film magnetic memory device including a memory cell having a magnetic tunnel junction (MTJ).

  MRAM devices are attracting attention as storage devices that can store nonvolatile data with low power consumption. An MRAM device is a storage device capable of performing random access using a plurality of thin film magnetic bodies formed in a semiconductor integrated circuit to perform nonvolatile data storage and each thin film magnetic body as a memory cell.

  In particular, in recent years, it has been announced that the performance of MRAM devices will be dramatically improved by using a thin film magnetic body using a magnetic tunnel junction as a memory cell. For MRAM devices with memory cells with magnetic tunnel junctions, see “A 10ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in each Cell”, ISSCC Digest of Technical Papers, TA7.2, Feb 2000., “Nonvolatile RAM based on Magnetic Tunnel Junction Elements”, ISSCC Digest of Technical Papers, TA7.3, Feb. 2000., and “A 256kb 3.0V 1T1MTJ Nonvolatile Magnetoresistive RAM”, ISSCC Digest of Technical Papers, TA7. 6, Feb. 2001. and the like.

  FIG. 30 is a schematic diagram showing a configuration of a memory cell having a magnetic tunnel junction (hereinafter also simply referred to as “MTJ memory cell”).

  Referring to FIG. 30, the MTJ memory cell includes a tunnel magnetoresistive element TMR whose electric resistance changes according to the data level of magnetically written storage data, and an access transistor ATR. Access transistor ATR is connected in series with tunneling magneto-resistance element TMR between bit line BL and source voltage line SRL. Typically, a field effect transistor formed on a semiconductor substrate is applied as access transistor ATR.

  For MTJ memory cells, bit line BL and digit line DL for flowing data write currents in different directions at the time of data writing, read word line RWL for instructing data reading, and at the time of data reading A source voltage line SRL for pulling down tunneling magneto-resistance element TMR to a predetermined voltage Vss (for example, ground voltage) is provided. In data reading, tunnel magnetoresistive element TMR is electrically coupled between source voltage line SRL and bit line BL in response to turn-on of access transistor ATR.

FIG. 31 is a conceptual diagram illustrating a data write operation for the MTJ memory cell.
Referring to FIG. 31, tunneling magneto-resistance element TMR corresponds to a ferromagnetic layer (hereinafter also simply referred to as “fixed magnetization layer”) FL having a fixed fixed magnetization direction and an externally applied magnetic field. A ferromagnetic layer (hereinafter, also simply referred to as “free magnetic layer”) VL that is magnetized in the direction. A tunnel barrier (tunnel film) TB formed of an insulator film is provided between the fixed magnetic layer FL and the free magnetic layer VL. Free magnetic layer VL is magnetized in the same direction as fixed magnetic layer FL or in the opposite direction to fixed magnetic layer FL according to the level of stored data to be written. A magnetic tunnel junction is formed by these fixed magnetic layer FL, tunnel barrier TB and free magnetic layer VL.

  The electric resistance of tunneling magneto-resistance element TMR changes according to the relative relationship between the magnetization directions of fixed magnetic layer FL and free magnetic layer VL. Specifically, the electric resistance of tunneling magneto-resistance element TMR becomes the minimum value Rmin when the magnetization direction of fixed magnetic layer FL and the magnetization direction of free magnetic layer VL are the same (parallel), and the magnetization directions of both are The maximum value Rmax is obtained in the opposite (antiparallel) direction.

  At the time of data writing, read word line RWL is inactivated and access transistor ATR is turned off. In this state, the data write current for magnetizing free magnetic layer VL flows in the direction corresponding to the level of the write data in each of bit line BL and digit line DL.

  FIG. 32 is a conceptual diagram illustrating the relationship between the data write current and the magnetization direction of the tunnel magnetoresistive element at the time of data writing.

  Referring to FIG. 32, the horizontal axis H (EA) indicates a magnetic field applied in the easy axis (EA) direction in free magnetic layer VL in tunneling magneto-resistance element TMR. On the other hand, the vertical axis H (HA) indicates a magnetic field that acts in the hard magnetization axis (HA) direction in the free magnetic layer VL. Magnetic fields H (EA) and H (HA) respectively correspond to one of two magnetic fields generated by currents flowing through bit line BL and digit line DL, respectively.

  In the MTJ memory cell, the fixed magnetization direction of the fixed magnetization layer FL is along the easy magnetization axis of the free magnetization layer VL, and the free magnetization layer VL has the stored data level (“1” and “0”). Accordingly, it is magnetized in the direction parallel to the fixed magnetic layer FL or in the antiparallel (opposite) direction along the easy axis direction. The MTJ memory cell can store 1-bit data (“1” and “0”) corresponding to the two magnetization directions of the free magnetic layer VL.

  The magnetization direction of free magnetic layer VL can be rewritten only when the sum of applied magnetic fields H (EA) and H (HA) reaches a region outside the asteroid characteristic line shown in FIG. it can. That is, when the applied data write magnetic field has a strength corresponding to the region inside the asteroid characteristic line, the magnetization direction of the free magnetic layer VL does not change.

  As indicated by the asteroid characteristic line, by applying a magnetic field in the hard axis direction to the free magnetic layer VL, the magnetization threshold required to change the magnetization direction along the easy axis is lowered. be able to.

When the operating point at the time of data writing is designed as in the example shown in FIG. 32, the strength of the data write magnetic field in the easy axis direction is H _WR in the MTJ memory cell that is the data write target. Designed to be That is, the value of the data write current that flows through bit line BL or digit line DL is designed so that this data write magnetic field _HWR is obtained. Generally, data write magnetic field H _WR is the switching magnetic field H _SW necessary for switching the magnetization direction is indicated by the sum of the margin [Delta] H. That is, H _WR = H _SW + ΔH.

  In order to rewrite the storage data of the MTJ memory cell, that is, the magnetization direction of the tunnel magnetoresistive element TMR, it is necessary to pass a data write current of a predetermined level or more to both the digit line DL and the bit line BL. Thus, free magnetic layer VL in tunneling magneto-resistance element TMR is parallel to fixed magnetic layer FL or in the opposite (anti-parallel) direction according to the direction of the data write magnetic field along the easy axis (EA). Magnetized. The magnetization direction once written in tunneling magneto-resistance element TMR, that is, data stored in the MTJ memory cell is held in a nonvolatile manner until new data writing is executed.

FIG. 33 is a conceptual diagram illustrating a data read operation from the MTJ memory cell.
Referring to FIG. 33, in the data read operation, access transistor ATR is turned on in response to activation of read word line RWL. Thereby, tunneling magneto-resistance element TMR is electrically coupled to bit line BL while being pulled down to predetermined voltage Vss.

  In this state, if the bit line BL is pulled up to a predetermined voltage, the current path including the bit line BL and the tunnel magnetoresistive element TMR is changed according to the electric resistance of the tunnel magnetoresistive element TMR, that is, the stored data of the MTJ memory cell. The memory cell current Icell according to the level passes. For example, the stored data can be read from the MTJ memory cell by comparing the memory cell current Icell with a predetermined reference current.

Thus, tunnel magnetoresistive element TMR changes its electrical resistance in accordance with the direction of magnetization that can be rewritten by the applied data write magnetic field, so that tunneling magnetoresistive element TMR has electrical resistances Rmax and Rmin, and stored data By associating with the levels (“1” and “0”), nonvolatile data storage can be executed.
Roy Scheuerlein and six others, “A 10ns Read and Write Non-Volatile Memory Array Using a Magnetic Using FET Switches and Magnetic Tunnel Junctions in Each Cell Tunnel Junction and FET Switch in each Cell), (USA), 2000 Annual Meeting of the Institute of Electrical and Electronics Engineers International Solid State Circuits TA7.2 (2000 IEEE ISSCC Digest of Technical Papers, TA7.2), p. 128-129. D. Durlam and five others, “Nonvolatile RAM based on Magnetic Tunnel Junction Elements” (USA), 2000 International Institute of Electrical and Electronics Engineers of Japan Proceedings TA7.3 (2000 IEEE ISSCC Digest of Technical Papers, TA7.3), p. 130-131.

  As described above, in the MRAM device, data storage is performed using the electrical resistance difference ΔR = (Rmax−Rmin), which is the junction resistance difference in the tunnel magnetoresistive element TMR corresponding to the difference in the stored data level. That is, data reading is performed based on detection of the passing current Icell of the selected memory cell.

  In general, a reference cell for generating a reference current to be compared with the memory cell current Icell is provided in addition to a normal MTJ memory cell for performing data storage. The reference current generated by such a reference cell is designed to be an intermediate value between the two types of memory cell currents Icell corresponding to the two types of electrical resistances Rmax and Rmin, respectively, in the MTJ memory cell.

  That is, the reference cell needs to be manufactured so as to have an electric resistance at an intermediate level between the electric resistances Rmax and Rmin, and in order to realize such an electric resistance, it is necessary to perform special design and manufacturing. . This complicates the structure of the reference cell, which may cause problems such as an increase in chip area and a reduction in processing margin of the memory cell array.

  In particular, in a configuration in which such dummy cells are arranged in a separate area from the memory array in which normal memory cells are arranged, a current path including dummy cells and a current path including normal MTJ memory cells selected for access are provided. However, since they are formed in separate areas, the influence of noise and the like during data reading increases, and the read margin may be reduced.

  The present invention has been made to solve such problems, and is a thin film magnetic material capable of executing data reading using a reference cell (dummy cell) designed and manufactured in the same manner as a normal MTJ memory cell. It is to provide a configuration of a body storage device.

  The thin film magnetic memory device according to the present invention is configured such that each is magnetized in a direction corresponding to the level of stored data and has either the first or second electric resistance depending on the magnetization direction. And a plurality of memory cells including an access transistor connected in series with the magnetoresistive element and selectively turned on when reading data, and a selected memory cell selected as an access target among the plurality of memory cells when reading data First and second data lines electrically coupled to a fixed voltage via a selected memory cell and a dummy cell, respectively, at the time of data reading, and a first data line And a data read unit for reading data in accordance with the passing current difference of the second data line. The dummy cell has the same configuration and shape as each magnetoresistive element, a dummy magnetoresistive element magnetized in advance so as to have a smaller one of the first and second electric resistances, a dummy magnetoresistive element, Connected in series and selectively turned on at the time of data reading, connected in series with a dummy access transistor designed in the same way as the access transistor and a dummy magnetoresistive element, than the difference between the first and second electrical resistances And a dummy resistance adding portion having a small electric resistance. The dummy resistance adding unit includes at least one transistor designed in the same manner as the access transistor, and an adjustable control voltage is input to each gate of the transistor.

  In the thin film magnetic memory device, since the transistors and dummy access elements constituting the dummy resistance adding unit are designed to have the same size as the access elements, the dummy cells can be efficiently arranged according to the arrangement pitch of the memory cells. Memory cells and dummy cells can be continuously arranged to avoid a reduction in the processing margin of the memory array.

  A thin film magnetic memory device according to another configuration of the present invention compares a passing current between a plurality of memory cells and a selected memory cell selected as an access target among the plurality of memory cells at the time of data reading. A dummy memory cell array. Each memory cell is magnetized in a direction corresponding to the level of stored data, and has a magnetoresistive element configured to have one of the first and second electric resistances depending on the magnetization direction, and the magnetoresistive element in series And an access transistor selectively turned on at the time of data reading. The dummy cell has the same configuration and shape as the magnetoresistive element, and is in series with a dummy magnetoresistive element that is pre-magnetized to have a smaller one of the first and second electric resistances, and the dummy magnetoresistive element. And a dummy access transistor which is selectively turned on at the time of data reading and designed similarly to the access transistor. The thin-film magnetic memory device is provided corresponding to a plurality of memory cells and transmits a fixed voltage, a first voltage wiring that corresponds to a dummy cell, and a second voltage wiring that transmits a fixed voltage. At the time of data reading, the first and second data lines electrically coupled to the first and second voltage wirings through the selected memory cell and the dummy cell, respectively, and the first and second data lines A data reading unit for reading data according to the difference in passing current and an electric current smaller than the difference between the first and second electric resistances connected in series to the second voltage wiring outside the memory array And a dummy resistance adding unit having a resistor.

  The thin film magnetic memory device is configured such that the combined resistance of the dummy resistance adding unit and the dummy cell arranged outside the memory array is an intermediate value of two types of electric resistances according to the storage data of the selected memory cell. Is done. Therefore, data reading can be executed using dummy cell DMC having the same configuration as that of a normal MTJ memory cell without providing a configuration for giving an offset between the passing currents of the selected memory cell and the dummy cell on the data reading circuit side. Is possible. As a result, no special design, manufacturing process, magnetizing process, or the like is required to manufacture the dummy memory cell, which causes problems such as an increase in chip area due to a complicated structure and a decrease in processing margin of the memory array. In addition, normal memory cells and dummy memory cells can be provided in the same memory array to ensure a data read margin. Furthermore, the configuration of the data read circuit system can be simplified.

  Preferably, the dummy resistance adding unit includes a field effect transistor that is electrically coupled between the second voltage wiring and the fixed voltage and receives an adjustable control voltage to the gate.

If comprised in this way, the electrical resistance of a dummy resistance addition part can be adjusted precisely.
A thin-film magnetic memory device according to still another configuration of the present invention provides a passing current between a plurality of memory cells and a selected memory cell selected as an access target among the plurality of memory cells at the time of data reading. A memory array in which dummy cells for comparison are arranged is provided. Each memory cell is magnetized in a direction corresponding to the level of stored data, and has a magnetoresistive element configured to have one of the first and second electric resistances depending on the magnetization direction, and the magnetoresistive element in series And an access transistor selectively turned on at the time of data reading. The dummy cell has the same configuration and shape as the magnetoresistive element, and is connected in series with the dummy magnetoresistive element preliminarily magnetized so as to have one of the first and second electric resistances. And a dummy access transistor that is selectively turned on at the time of data reading and designed in the same manner as the access transistor. The thin film magnetic memory device includes a first data line and a second data line electrically coupled to a fixed voltage via one of each of the selected memory cell and the dummy cell, respectively, and the first and second data lines. A data reading portion for reading data according to the passing current difference of the data line, and one data line coupled to the selected memory cell of the first and second data lines outside the memory array , A first resistance adding unit for connecting the third electric resistance in series, and the other data line coupled to the dummy cell of the first and second data lines outside the memory array, And a second resistance adding unit for connecting the fourth electric resistance in series. In the third and fourth electric resistances, the sum of the electric resistance of the dummy cell and the fourth electric resistance is an intermediate level between the sum of the first and third electric resistances and the sum of the second and third electric resistances. To be determined.

  In the thin film magnetic memory device, the first and second resistance adding units arranged outside the memory array are connected in series with the selected memory cell and the dummy cell, so that the passing current of the dummy cell is reduced to 2 of the selected memory cell. Set to the intermediate level of the type of passing current. Therefore, data reading can be executed using dummy cell DMC having the same configuration as that of a normal MTJ memory cell without providing a configuration for giving an offset between the passing currents of the selected memory cell and the dummy cell on the data reading circuit side. Is possible. As a result, no special design or manufacturing process is required to fabricate the dummy memory cell, so that the normal memory can be used without causing problems such as an increase in chip area due to a complicated structure and a decrease in processing margin of the memory array. Cells and dummy memory cells can be provided in the same memory array to ensure a data read margin. Furthermore, the configuration of the data read circuit system can be simplified.

  Preferably, the dummy magnetoresistive element is pre-magnetized to have a smaller one of the first and second electrical resistances, the fourth electrical resistance corresponds to the difference between the first and second electrical resistances, The third electrical resistance is half of the fourth electrical resistance.

  With this configuration, it is not necessary to provide a dedicated process for magnetizing the dummy cell alone, so that the manufacturing process can be simplified.

  More preferably, the first resistance adding unit includes L transistors (L: an even and positive integer of 2 or more) connected in parallel to receive an adjustable control voltage to each gate, and the second resistor The additional unit includes (L / 2) transistors connected in parallel to receive a control voltage to each gate.

  If comprised in this way, the electrical resistance of a 1st and 2nd resistance addition part can be set correctly.

  Preferably, the thin film magnetic memory device is provided corresponding to the plurality of memory cells, and is provided corresponding to the first voltage wiring for transmitting a fixed voltage and the dummy cell, and transmits the fixed voltage. The second voltage wiring is further provided. The first resistance adding unit is connected in series between the first voltage line and the fixed voltage, and the second resistance adding unit is connected in series between the second voltage line and the fixed voltage.

  With this configuration, the connection correspondence relationship between the first and second data lines and the selected memory cell and the dummy cell is switched according to the address selection result, even for a memory array based on a folded bit line configuration. The first and second resistance adding units can be connected in series with the selected memory cell and the dummy cell without providing a connection switching circuit. Therefore, data reading with high noise resistance can be executed without increasing the circuit area.

  Alternatively, preferably, the plurality of memory cells and dummy cells are complementarily divided and arranged in first and second memory blocks to be read data, and each of the first and second memory blocks includes a dummy cell, In the memory block, each memory cell and dummy cell are electrically coupled between the first and second data lines and the fixed voltage, respectively. In the second memory block, the dummy cell and each memory cell are connected to the first data line. The thin film magnetic memory device is electrically coupled between the first data line and the second data line and the fixed voltage, respectively, and the thin film magnetic memory device has the first and second data depending on the selection result between the first and second memory blocks. Each of the lines further includes a connection switching unit for complementarily connecting one of the first and second resistance adding units in series.

  With this configuration, the load capacity of the first and second data lines can be balanced, so that data reading can be performed at high speed.

  A thin-film magnetic memory device according to still another configuration of the present invention provides a passing current between a plurality of memory cells and a selected memory cell selected as an access target among the plurality of memory cells at the time of data reading. A memory array in which dummy cells for comparison are arranged is provided, and each memory cell is magnetized in a direction corresponding to the level of stored data, and has either the first or second electric resistance depending on the magnetization direction. And an access transistor connected in series with the magnetoresistive element and selectively turned on at the time of data reading. The dummy cell has the same configuration and shape as the magnetoresistive element, and is connected in series with the dummy magnetoresistive element preliminarily magnetized so as to have one of the first and second electric resistances. And a dummy access transistor that is selectively turned on at the time of data reading and designed in the same manner as the access transistor. The thin film magnetic memory device includes a first data line and a second data line electrically coupled to a fixed voltage via one of each of the selected memory cell and the dummy cell, respectively, and the first and second data lines. A data reading unit for reading data according to the difference in current passing through the data line, and a third electrical resistance in parallel with one of the first and second data lines outside the memory array And a resistance adding unit for connecting to the. In the third electrical resistance, the electrical resistance of the dummy cell is an intermediate level between the combined resistance of the first and third electrical resistances connected in parallel and the combined resistance of the second and third electrical resistances connected in parallel. To be determined.

  In the thin film magnetic memory device, a resistance adding unit arranged outside the memory array is connected in parallel with a predetermined one of the selected memory cell and the dummy cell, thereby passing the passing current of the dummy cell through two types of the selected memory cell. Set to the middle level of the current. Therefore, data reading can be executed using dummy cell DMC having the same configuration as that of a normal MTJ memory cell without providing a configuration for giving an offset between the passing currents of the selected memory cell and the dummy cell on the data reading circuit side. Is possible. As a result, no special design or manufacturing process is required to fabricate the dummy memory cell, so that the normal memory can be used without causing problems such as an increase in chip area due to a complicated structure and a decrease in processing margin of the memory array. Cells and dummy memory cells can be provided in the same memory array to ensure a data read margin. Furthermore, the configuration of the data read circuit system can be simplified.

  Preferably, the dummy magnetoresistive element is pre-magnetized so as to have one of the first and second electric resistances smaller, and one data line to which the resistance adding unit is connected in parallel at the time of data reading is selected. It is electrically coupled to a fixed voltage through the memory cell.

  With this configuration, it is not necessary to provide a dedicated process for magnetizing the dummy cell alone, so that the manufacturing process can be simplified.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, the same code | symbol shall show the same or an equivalent part in a figure.

[Embodiment 1]
FIG. 1 is a schematic block diagram showing an overall configuration of MRAM device 1 according to the embodiment of the present invention.

  Referring to FIG. 1, MRAM device 1 according to the embodiment of the present invention performs random access in response to external control signal CMD and address signal ADD, and inputs write data DIN and outputs read data DOUT. Execute.

  The MRAM device 1 includes a control circuit 5 that controls the overall operation of the MRAM device 1 in response to a control signal CMD, and a memory array 10 that includes MTJ memory cells MC arranged in a matrix.

  In memory array 10, read word line RWL and digit line DL are arranged corresponding to each row of MTJ memory cells, and bit line BL is arranged corresponding to each column of MTJ memory cells. Alternatively, in order to obtain a folded bit line configuration, a bit line pair BLP constituted by bit lines BL and / BL may be arranged corresponding to each memory cell column. FIG. 1 shows an arrangement of one MTJ memory cell MC typically shown, and the corresponding read word line RWL, digit line DL, and bit line BL (or bit line pair BLP).

  The MRAM device 1 decodes the row address RA indicated by the address signal, decodes the row decoder 20 for executing row selection in the memory array 10, and the column address CA indicated by the address signal ADD, 10 further includes a column decoder 25 for performing column selection in 10 and read / write control circuits 30 and 35.

  Read / write control circuits 30 and 35 include a circuit group for performing a data write operation on memory array 10 and a circuit group for performing data read from memory array 10 (hereinafter referred to as “data read circuit system”). (Also referred to as).

  Digit line DL is coupled to a predetermined voltage Vss (for example, ground voltage) in a region opposite to row decoder 20 across memory array 10.

  FIG. 2 is a circuit diagram showing a configuration according to the first embodiment of the data read circuit system for executing data read from the memory array.

  Referring to FIG. 2, memory array 10 includes a plurality of normal MTJ memory cells MC (hereinafter also simply referred to as “normal memory cells MC”) arranged in a matrix and each storing 1-bit data. Have. Each normal memory cell MC has a configuration similar to that shown in FIG. 30, and includes a tunnel magnetoresistive element TMR and an access transistor (access element) ATR connected in series. Access transistor ATR has its gate connected to corresponding read word line RWL. Tunneling magneto-resistance element TMR is magnetized in a direction corresponding to stored data (“1” or “0”) and has one of electric resistances Rmax and Rmin.

  Strictly speaking, the electrical resistance of each normal memory cell is the sum of the tunnel magnetoresistive element TMR, the on-resistance of the access transistor ATR, and other parasitic resistances, but the resistance other than the tunnel magnetoresistive element TMR is stored in the stored data. Therefore, in the following, the electrical resistances of the two types of normal memory cells corresponding to the stored data are also represented by Rmax and Rmin, and the difference between them is represented by ΔR (that is, ΔR = Rmax−Rmin). Shall.

  Memory array 10 further includes a plurality of dummy cells DMC. Each dummy cell DMC is provided to compare a passing current with a normal memory cell selected as an access target (hereinafter also referred to as “selected memory cell”). Each dummy cell DMC has the same configuration and shape as the normal memory cell MC, and includes a dummy magnetoresistive element TMRd and a dummy access element ATRd.

  Dummy magnetoresistive element TMRd is designed and manufactured in the same manner as tunneling magnetoresistive element TMR in normal memory cell MC, and stored data “1” or “0” is written in advance. Dummy access element ATRd is manufactured and designed in the same manner as access transistor ATR in normal memory cell MC. That is, the on-resistances of the dummy access element ATRd and the access transistor ATR are at the same level, and the transistor size is designed in the same manner. Therefore, the electrical resistance of the dummy cell DMC is the same as the predetermined one of the two types of electrical resistances Rmax and Rmin of the normal memory cell.

  Since the dummy cells DMC have the same configuration and shape as the normal memory cells MC, they can be continuously arranged in a matrix with the normal memory cells MC in the memory array 10. In the configuration according to the first embodiment, dummy cells DMC form a dummy cell column and are arranged to share a memory cell row with normal memory cells MC.

  For each memory cell row shared by normal memory cell MC and dummy cell DMC, read word line RWL and digit line DL are arranged. On the other hand, the column of normal memory cells MC (also referred to as “normal memory cell column”) and the dummy cell column are independent, and a bit line BL is arranged for each normal memory cell column, and a dummy bit line BLd is provided for each dummy cell column. Provided.

  In FIG. 2, the read word line RWLi, digit line DLi, and bit line BL0 corresponding to the i-th (i: natural number) memory cell row and head, and the j-th (j: natural number) and last memory cell column. , BLj, BLn and dummy bit line BLd, and corresponding normal memory cell MC and dummy cell DMC are representatively shown.

  In the following description, binary high voltage states (for example, power supply voltage Vcc) and low voltage states (for example, predetermined voltage Vss) such as signals, signal lines, and data are set to “H level” and “L level”, respectively. Is also referred to.

  Further, data lines LIO and LIOr are arranged adjacent to memory array 10. In each memory cell column, a column selection gate CSG is provided between each bit line BL and the data line LIO, and a dummy column selection gate CSGd is provided between the dummy bit line BLd and the data line LIOr. Column selection gate CSG is turned on in response to activation (H level) of corresponding column selection line CSL. The dummy column selection gate CSGd is turned on in response to activation (H level) of the dummy column selection line CSLd.

  In FIG. 2, column selection lines CSL0, CSLj, CSLn, dummy column selection line CSLd, column selection gates CSG0, CSGj, CSGn, and dummy are provided corresponding to bit lines BL0, BLj, BLn and dummy bit line BLd. A column select gate CSGd is representatively shown.

  In accordance with row address RA, row decoder 20 selectively activates read word line RWL at the time of data reading (H level) and selectively activates digit line DL at the time of data writing (H level). The activated digit line DLi has one end connected to the power supply voltage Vcc by the row decoder 20 and the other end connected to the predetermined voltage Vss as shown in FIG. 1, so that data is written to the digit line of the selected row. Current Ip can flow. Although a detailed description of the data write operation is omitted, by passing a data write current in a direction corresponding to the write data level to the bit line of the selected column, both the corresponding digit line and bit line are passed. Data writing can be performed on a memory cell to which a data write current is supplied.

  Column decoder 25 selectively activates (H level) column selection line CSL and dummy column selection line CSLd according to the column selection result during data reading.

  Further, a data line equalizing circuit 50 for precharging and equalizing the data lines LIO and LIOr, and a differential amplifier 60 for executing data reading based on a difference in electrical resistance between the selected memory cell and the dummy cell are provided. .

  Data line equalize circuit 50 includes a transistor switch 51 connected between data lines LIO and LIOr, a transistor switch 52 connected between data line LIOr and predetermined voltage Vss, and between data line LIO and predetermined voltage Vss. And a transistor switch 53 connected to. Each of transistor switches 51, 52 and 53 is formed of an N-type MOS transistor, for example.

  A data line equalize signal LIOEQ generated by the row decoder 20 is input to the gates of the transistor switches 51 to 53. Data line equalize signal LIOEQ is activated to H level at least in a predetermined period before the data read operation. By the precharge / equalize operation in response to this, each of data lines LIO and LIOr is set to a predetermined voltage Vss.

  Differential amplifier 60 includes an N-type MOS transistor 61 connected between sense node Ns and data line LIO, an N-type MOS transistor 62 connected between sense node / Ns and data line LIOr, and a node Nsp. And P-type MOS transistor 63 connected between sense node Ns, P-type MOS transistor 64 connected between node Nsp and sense node / Ns, power supply voltage Vcc and node Nsp supplied as operating voltages And a P-type MOS transistor 65 connected therebetween.

  Each gate of transistors 63 and 64 is connected to one of sense nodes Ns and / Ns. FIG. 2 shows, as an example, a configuration in which the gates of transistors 63 and 64 are connected to sense node / Ns. Transistors 63 and 64 form a current mirror circuit and try to supply the same current to each of sense nodes Ns and / Ns.

  Offset control voltages Vofd and Vofr generated by voltage generation circuits 55 and 56 constituting an offset adjustment circuit are input to the gates of transistors 61 and 62, respectively. Transistors 61 and 62 maintain data lines LIO and LIOr below offset control voltages Vofd and Vofr, respectively, and amplify a passing current difference between data lines LIO and LIOr to obtain a voltage difference between sense nodes Ns and / Ns. Convert.

  Sense enable signal / SE activated by row decoder 20 to the L level during the data read operation is input to the gate of transistor 65. For example, in the configuration in which a plurality of data read circuit systems shown in FIG. 2 are arranged, row decoder 20 selectively activates sense enable signal / SE reflecting the selection results of these data read circuit systems. Turn into. Transistor 65 operates differential amplifier 60 by supplying an operating current in response to activation (L level) of sense enable signal / SE.

  Next, referring to FIG. 3, a data read operation in the MRAM device according to the first embodiment will be described. In FIG. 3, the operation when the i-th row and the j-th column are selected as the data read target will be representatively described.

  Referring to FIG. 3, data line equalize signal LIOEQ is activated to H level before time t1 before execution of data reading. Thereby, the data lines LIO and LIOr are precharged to the predetermined voltage Vss.

  When the data read operation is started at time t1, first, data line equalize signal LIOEQ is deactivated to L level, and data lines LIO and LIOr are disconnected from predetermined voltage Vss. Thus, preparations for starting data reading are completed.

  Further, at time t2, sense enable signal / SE is activated to L level, and operation of differential amplifier 60 is started. Thereby, current supply to each of data lines LIO and LIOr is started. At the same timing, the read word line RWLi of the selected row and the column selection line CSLj of the selected column are each activated to the H level.

  In response to activation of the word line WLi of the selected row and the column selection line CSLj of the selected column, the data line LIO is electrically coupled to the predetermined voltage Vss via the bit line BLj and the selected memory cell, and the data line LIOr Are electrically coupled to predetermined voltage Vss through dummy bit line BLd and dummy cell DMC. In the configuration according to the first embodiment, the connection correspondence between data lines LIO and LIOr and the selected memory cell and dummy cell is fixed. That is, at the time of data reading, data lines LIO and LIOr are electrically coupled to the selected memory cell and the dummy cell regardless of the address selection result.

  As already described, since the electrical resistance of the selected memory cell is either Rmax or Rmin according to the stored data, the passing current Idat of the data line LIO electrically coupled to the selected memory cell is Depending on the stored data, it is either Idat (Rmax) or Idat (Rmin). Hereinafter, the passing current Idat of the data line electrically coupled to the selected memory cell is also referred to as a data read current Idat, and the difference between the two types of data read currents Idat (Rmax) and Idat (Rmin) is expressed as ΔI. To do. That is, ΔI = Idat (Rmin) −Idat (Rmax).

  On the other hand, the passing current Iref of the data line LIOr is preferably set to an intermediate level between Idat (Rmax) and Idat (Rmin) so as to satisfy the following expression (1). Hereinafter, the passing current Iref of the data line electrically coupled to the dummy cell is also referred to as a reference current Iref. In other words, the differential amplifier 60 needs to give an offset that satisfies the following expression (1) to the passing currents of the data lines LIO and LIOr.

Idat (Rmax) + ΔI / 2 = Iref = Idat (Rmin) −ΔI / 2 (1)
For example, in order to give such an offset, offset control voltages Vofd and Vofr generated by voltage generation circuits 55 and 56 are set to different levels.

  More specifically, when the electric resistance of the dummy cell is preset to Rmin, an offset control voltage Vofr = Vofd is provided in order to provide an offset that decreases the reference current Iref that is a passing current of the data line LIOr by ΔI / 2. Set to -Vα. Thereby, the gate voltage of transistor 62 electrically coupled to the dummy cell is lower than the gate voltage of transistor 61 electrically coupled to the selected memory cell, so that the above-described offset can be provided. The difference Vα between the offset control voltages Vofr and Vofd is adjusted corresponding to the above ΔI / 2.

  On the other hand, when the electric resistance of the dummy cell is preset to Rmax, the offset control voltage Vofr = Vofd + Vα is set in order to give an offset that increases the passing current (reference current Iref) of the data line LIOr by ΔI / 2. . Thereby, the gate voltage of transistor 62 electrically coupled to the dummy cell becomes higher than the gate voltage of transistor 61 electrically coupled to the selected memory cell, so that the above-described offset can be provided. Similarly, the difference Vα between the offset control voltages Vofr and Vofd is adjusted corresponding to the above ΔI / 2.

  Alternatively, as another configuration for providing the above-described offset in the differential amplifier 60, the transistors 63 and 64 forming the current mirror may have different current driving capabilities (transistor sizes). In such a configuration, the offset control voltages Vofd and Vofr are set to a common level.

  Specifically, when the electric resistance of the dummy cell is preset to Rmin, the current driving capability of the transistor 64 (in order to provide an offset for reducing the passing current (reference current Iref) of the data line LIOr by ΔI / 2) The transistor size is designed to be smaller than the current driving capability (transistor size) of the transistor 63. On the other hand, when the electric resistance of the dummy cell is preset to Rmax, the current driving capability (transistor size) of the transistor 64 is provided to provide an offset for increasing the passing current (reference current Iref) of the data line LIOr by ΔI / 2. ) Is designed to be larger than the current driving capability (transistor size) of the transistor 63.

  Between times t3 and t4, the differential amplifier 60 amplifies the current difference ΔI / 2 between the data read current Idat and the reference current Iref generated by the above-described offset based on the electrical resistances of the selected memory cell and the dummy cell, The voltage is converted into a voltage difference ΔV / 2 between the sense nodes Ns and / Ns. Since this voltage difference ΔV / 2 has a polarity corresponding to the data stored in the selected memory cell, the data stored in the selected memory cell can be detected from the voltages of the sense nodes Ns and / Ns.

  At the end of data reading, at time t4, sense enable signal / SE, read word line RWLi in the selected row, and column select line CSLj in the selected column are deactivated. Further, at time t5, data line equalize signal LIOEQ is activated to H level, data lines LIO and LIOr are pre-charged again, and the circuit state before data reading is reproduced.

  As described above, in the configuration according to the first embodiment, the dummy cell for generating the reference current can have the same configuration and shape as the normal memory cell, so that it can be continuously formed in the same memory array. A dummy cell can be configured by using a part of the manufactured MTJ memory cell. That is, since a special design or manufacturing process is not required to manufacture the dummy cell, the normal memory cell and the dummy cell can be obtained without causing problems such as an increase in chip area due to a complicated structure and a decrease in processing margin of the memory array. Can be provided in the same memory array to ensure a data read margin.

  Furthermore, since the operating current of differential amplifier 60 is used as the passing current of the selected memory cell and dummy cell, the number of circuit elements in the data read circuit system can be reduced. In addition, an offset for causing a difference in passing current with a polarity corresponding to the stored data level can be provided between the selected memory cell and the dummy cell having the same characteristics without causing a complicated circuit configuration.

[Variation 1 of Embodiment 1]
FIG. 4 is a circuit diagram showing a configuration of a data read circuit system according to the first modification of the first embodiment.

  Referring to FIG. 4, in the configuration according to the first modification of the first embodiment, memory array 10 has a so-called “folded bit line configuration”, and a connection switching circuit 70 is newly provided. However, it is different from the configuration according to the first embodiment shown in FIG.

  In memory array 10, a bit line pair BLP composed of complementary bit lines BL and / BL is arranged corresponding to each memory cell column. The normal memory cells MC are alternately arranged every other row so as to be connected to the bit line BL in the odd rows and to the bit line / BL in the even rows.

  The dummy cells DMC are continuously arranged in a matrix with the normal memory cells MC in the memory array 10 to form two dummy cell rows corresponding to the odd rows and the even rows, respectively. Arranged to share columns.

  Therefore, complementary bit lines BL and / BL arranged in each memory cell column are shared by normal memory cell MC and dummy cell DMC. On the other hand, a row of normal memory cells MC (also referred to as “normal memory cell row”) and a dummy cell row are independent, and a read word line RWL and a digit line DL are arranged for each normal memory cell row. Further, dummy read word lines DRWLe and DRLLo and dummy digit lines DDLe and DDLo are arranged corresponding to the two dummy cell rows, respectively.

  In FIG. 4, read word lines RWLe, RWLo, corresponding to the even and odd rows, the two dummy cell rows, and the first and last memory cell columns, respectively, of the regular memory cells shown as representatives. Digit lines DLe, DLo, dummy read word lines DRWLe, DWLLo, dummy digit lines DDLe, DDLo, bit line pairs BLP0, BLPn, and corresponding normal memory cells MC and dummy cells DMC are representatively shown.

  The dummy cell group for the dummy read word line DRWLe is connected between the bit line BL and the predetermined voltage Vss. On the other hand, the dummy cell group corresponding to the dummy read word line DRLLo is connected between the bit line / BL and the predetermined voltage Vss.

  Complementary data lines LIO and / LIO constituting data line pair LIOP are arranged adjacent to memory array 10. Column select gates CSG0 to CSGn arranged corresponding to the respective memory cell columns are provided between data line pair LIOP and bit line pairs BLP0 to BLPn, respectively. Therefore, at the time of data reading, complementary bit lines BL and / BL corresponding to the selected column are electrically coupled to data lines LIO and / LIO, respectively. That is, when a memory array having a folded bit line configuration is provided, the coupling relationship between the data lines LIO and / LIO and the selected memory cell and dummy cell is not fixed, and either the odd row or the even row is selected. Accordingly, the connection correspondence between the data lines LIO, / LIO, the dummy cell DMC, and the selected memory cell is switched. Specifically, when an odd row is selected, data lines LIO and / LIO are electrically coupled to a selected memory cell and a dummy cell via bit lines BL and / BL, respectively. In contrast, when an even row is selected, data lines LIO and / LIO are electrically coupled to the dummy cell and the selected memory cell via bit lines BL and / BL, respectively.

  In response to this, the connection switching circuit 70 determines the connection correspondence between the differential amplifier 60 and the data lines LIO, / LIO based on the address selection result, that is, whether the even row or the odd row is selected. Switch accordingly. Connection switching circuit 70 is connected between node Nd (source side of transistor 61) to which data read current Idat is supplied and node Nr (source side of transistor 62) to which reference current Iref is supplied and data lines LIO and / LIO. Provided.

FIG. 5 is a circuit diagram illustrating the configuration of the connection switching circuit 70.
Referring to FIG. 5, connection switching circuit 70 is electrically coupled between an N-type MOS transistor 71 electrically coupled between node Nd and data line LIO, and between node Nd and data line / LIO. N-type MOS transistor 72, N-type MOS transistor 73 electrically coupled between node Nr and data line / LIO, and N-type MOS electrically coupled between node Nr and data line LIO And a transistor 74. The gates of the transistors 71 and 73 are supplied with an address signal RA0 which is set to H level (“1”) when an odd row is selected and set to L level (“0”) when an even row is selected. The address signal / RA0, which is the inverted signal, is input to each of the gates 74 and 74.

  With such a configuration, the selected memory cell and the dummy cell are electrically connected to the nodes Nd and Nr for supplying the data read current Idat and the reference current Iref, respectively, when selecting either the odd row or the even row. Can be combined.

  FIG. 6 is an operation waveform diagram illustrating a data read operation by the data read circuit system according to the first modification of the first embodiment.

  Referring to FIG. 6, in a data read operation between times t1 and t2 when an odd-numbered row is selected, address signals RA0 and / RA0 are set to H level and L level, respectively, and the selected row is read. Word line RWLo and dummy read word line DRLLo and column select line CSL0 corresponding to the selected column are activated to H level.

  Voltage generation circuits 55 and 56 and differential amplifier 60 are designed to give a desired offset between data read current Idat and reference current Iref, as in the first embodiment.

  As a result, when an odd row is selected, data read current Idat passes through data line LIO coupled to the selected memory cell, and reference current Iref passes through data line / LIO coupled to dummy cell DMC. Therefore, similarly to the data read operation according to the first embodiment, differential amplifier 60 amplifies the difference between data read current Idat and reference current Iref to convert it to a voltage difference between sense nodes Ns and / Ns, and Data stored in the selected memory cell can be detected from the voltages of Ns and / Ns.

  On the other hand, in a data read operation between times t3 and t4 when an even-numbered row is selected, address signals RA0 and / RA0 are set to L level and H level, respectively, and read word line RWLe and dummy of the selected row are set. Read word line DRWLe and column select line CSL0 corresponding to the selected column are activated to H level.

  As a result, even when an even row is selected, the data read current Idat passes through the data line (/ LIO) coupled to the selected memory cell, and the reference current Iref passes through the data line (LIO) coupled to the dummy cell DMC. To do.

  Therefore, regardless of whether the odd row or the even row is selected, current difference ΔI / 2 between data read current Idat and reference current Iref is amplified by differential amplifier 60 as in the data read operation according to the first embodiment. Since the voltage difference ΔV / 2 between the sense nodes Ns and / Ns can be converted, the data stored in the selected memory cell can be detected from the voltages at the sense nodes Ns and / Ns.

  In other words, according to the configuration according to the first modification of the first embodiment, the connection correspondence relationship between the complementary data line, the selected memory cell, and the dummy cell is changed with respect to the memory array having the folded bit line configuration that is switched according to the address selection result. However, the same effect as in the first embodiment can be enjoyed. In such a memory array having a folded bit line configuration, accurate data reading with higher noise resistance can be performed by a data reading operation based on a comparison operation between adjacent bit lines and data lines.

[Modification 2 of Embodiment 1]
In the second modification of the first embodiment, the connection correspondence between the data lines LIO, / LIO and the selected memory cell and the dummy cell shown in the first modification of the first embodiment is switched according to the address selection result. A configuration of a differential amplifier that can handle the configuration will be described.

FIG. 7 is a circuit diagram showing a configuration of the differential amplifier according to the second modification of the first embodiment.
Referring to FIG. 7, a differential amplifier 60 # according to the second modification of the first embodiment is different from the differential amplifier 60 shown in FIG. It differs in having 62A and 62B. Transistors 61A and 61B are connected in parallel between sense node Ns and data line LIO. Similarly, transistors 62A and 62B are connected in parallel between sense node / Ns and data line / LIO.

  Further, voltage generating circuits 55 'and 56' are provided in place of the voltage generating circuits 55 and 56 constituting the offset adjusting circuit, respectively. The offset control voltage Vof1 from the voltage generation circuit 55 'is input to the gates of the transistors 61A and 62B, and the offset control voltage Vof2 from the voltage generation circuit 56' is input to the gates of the transistors 61B and 62A. . Voltage generating circuit 55 'operates in response to address signal RA0 set to H level when odd rows are selected, and voltage generating circuit 56' is applied to address signal / RA0 set to H level when even rows are selected. Works accordingly.

  Although details will be described later, one of the offset control voltages Vof1 and Vof2 depends on the result of the address selection, specifically, whether the odd row or the even row is selected. One set of the transistors 61B and 62A is set to be turned off. Furthermore, the current drive capability (transistor size) of each of the transistors 61A and 62A is set to a level different from the current drive capability (transistor size) of each of the transistors 61B and 62B. Since the structure of other parts of differential amplifier 60 # is similar to that of differential amplifier 60 shown in FIG. 2, detailed description thereof will not be repeated.

FIG. 8 is an operation waveform diagram for illustrating the operation of differential amplifier 60 #.
Referring to FIG. 8, in a data read operation between times t1 and t2 when an odd-numbered row is selected, address signals RA0 and / RA0 are set to H level and L level, respectively, and the selected row is read. Word line RWLo, corresponding dummy read word line DRLLo, and column select line CSL0 corresponding to the selected column are activated to H level.

  The offset control voltage Vof1 from the voltage generation circuit 55 'is set to a level Vof that can turn on the transistors 61A and 62B, and the offset control voltage Vof2 from the voltage generation circuit 56' is used to turn off the transistors 61B and 62A. For example, the ground voltage level is set.

  In contrast, in a data read operation between times t3 and t4 when an even-numbered row is selected, address signals RA0 and / RA0 are set to L level and H level, respectively, and the read word line of the selected row RWLe and the corresponding dummy read word line DRWLe and the column selection line CSL0 corresponding to the selected column are activated to the H level.

  Offset control voltage Vof1 from voltage generation circuit 55 'is set to a level (eg, ground voltage) that turns off transistors 61A and 62B, and offset control voltage Vof2 from voltage generation circuit 56' can turn on transistors 61B and 62A. Level Vof.

  Therefore, transistor 61A or 62A is connected in series to one of data lines LIO and / LIO electrically coupled to the selected memory cell, regardless of whether odd or even rows are selected. Transistor 61B or 62B is connected in series to the other electrically coupled to the dummy cell.

  The magnitude relationship of the current drive capability at turn-on between each of these transistors 61A and 62A and each of transistors 61B and 62B is the same as that in the first embodiment between data read current Idat and reference current Iref. 2 is set in the same manner as the relationship in magnitude of the current drive capability (transistor size) of the transistors 63 and 64 for providing the offset described with reference to FIG.

  Specifically, when the electric resistance of the dummy cell is set to Rmin in advance, the current driving capability (transistor size) of the transistors 61B and 62B is set to be a transistor so as to give an offset that reduces the reference current Iref by ΔI / 2. It is designed to be smaller than the current drive capability (transistor size) of 61A and 62A. On the contrary, when the electric resistance of the dummy cell is preset to Rmax, the current driving capability of the transistors 61B and 62B (to give an offset for increasing the passing current (reference current Iref) of the data line LIOr by ΔI / 2) ( The transistor size is designed to be larger than the current driving capability (transistor size) of the transistors 61A and 61A.

  As a result, when selecting either the odd row or the even row, the data read current Idat flowing through the data line coupled to the selected memory cell and the reference current Iref flowing through the data line coupled to the dummy cell DMC are between. Thus, the same relationship as the above equation (1) can be established.

  Therefore, at the time of selecting either the odd row or the even row, the difference between data read current Idat and reference current Iref is amplified by differential amplifier 60 as in the data read operation according to the first embodiment, and the sense node By converting into a voltage difference between Ns and / Ns, the data stored in the selected memory cell can be detected from the voltages at the sense nodes Ns and / Ns.

  As described above, according to the configuration according to the second modification of the first embodiment, using differential amplifier 60 # configured by adding two transistors to differential amplifier 60 shown in FIG. 4 and FIG. 5 can be omitted, and the same data read as in the first modification of the first embodiment can be executed. Therefore, in addition to the effect of the configuration according to the first modification of the first embodiment, the circuit area can be further reduced.

[Embodiment 2]
In the second embodiment, a configuration for giving the same offset as in the first embodiment when a differential amplifier is provided in two stages will be described.

FIG. 9 is a circuit diagram showing a configuration of a data read circuit system according to the second embodiment.
Referring to FIG. 9, in the configuration according to the second embodiment, global differential amplifier 80 is further provided after differential amplifier 60. Global differential amplifier 80 converts a voltage difference between sense nodes Ns and / Ns into a passing current difference between complementary global data lines GIO and / GIO, and amplifies the current difference between global sense nodes Ngs and / Ngs. Causes a voltage difference.

  The differential amplifier 60 is provided for the memory array 10 having the configuration shown in FIG. Therefore, although not shown, at the time of data reading, data line LIO electrically coupled to sense node Ns is connected in series with the selected memory cell, and data line LIOr electrically coupled to sense node / Ns is It is connected in series with the dummy cell DMC.

  Global differential amplifier 80 includes an N-type MOS transistor 81 having a gate connected to sense node Ns, an N-type MOS transistor 82 having a gate connected to sense node / Ns, and offset control from voltage generation circuit 90. N-type MOS transistor 83 receiving voltage Vofd at its gate and N-type MOS transistor 84 receiving offset control voltage Vofr from voltage generating circuit 91 at its gate. Transistor 81 is electrically coupled between global data line GIO and predetermined voltage Vss, and transistor 82 is electrically coupled between global data line / GIO and predetermined voltage Vss. Transistor 83 is connected in series to global data line GIO, and transistor 84 is connected in series to global data line / GIO.

  Global differential amplifier 80 is further electrically coupled between P type MOS transistor 85 electrically coupled between power supply voltage Vcc and node Nspg, and between node Nspg and global sense nodes Ngs and / Ngs, respectively. P-type MOS transistors 86 and 87. A control signal / ASE corresponding to an enable signal of global differential amplifier 80 is input from row decoder 20 to the gate of transistor 85. Transistor 85 supplies an operating current in response to activation (L level) of control signal / ASE, and operates global differential amplifier 80. Each gate of transistors 86 and 87 is connected to a predetermined one of global sense nodes Ngs and / Ngs, for example, global sense node / Ngs.

  Offset control voltages Vofd and Vofr generated by voltage generation circuits 90 and 91, respectively, are different to provide a desired offset between the passing currents of complementary global data lines GIO and / GIO, as will be described in detail later. Set to level. Thus, the global differential amplifier 80 is connected to the gates of the transistors 83 and 84 in addition to the differential amplifier configured by the transistors 81, 82, 86 and 87 to amplify the voltage difference between the sense nodes Ns and / Ns. The offset control voltages Vofd and Vofr respectively inputted can provide a desired offset between the passing currents of the global data lines GIO and / GIO.

  On the other hand, a common offset control voltage Vof is input to the gates of the transistors 61 and 62 in the differential amplifier 60. That is, in the differential amplifier 60 at the previous stage, no intentional offset is given between the passing currents of the data lines LIO and LIOr. As a result, the passing currents of data lines LIO and LIOr depend on the electric resistances of the selected memory cell and the dummy cell.

  Next, the data read operation according to the second embodiment will be described with reference to FIG. In FIG. 10, the operation when the i-th row and the j-th column are selected as the data read target in the case where the electric resistance of the dummy cell is preset to Rmin will be representatively described.

  When the data read operation is started at time t1, first, data line equalize signal LIOEQ is deactivated to L level, and data lines LIO and LIOr are disconnected from predetermined voltage Vss. Thus, preparations for starting data reading are completed.

  Further, at time t2, sense enable signal / SE and control signal / ASE are activated to L level, and operations of differential amplifier 60 and global differential amplifier 80 are started. Thus, current supply to each of data lines LIO, LIOr and global data lines GIO, / GIO is started. At the same timing, the read word line RWLi of the selected row and the column selection line CSLj of the selected column are each activated to the H level.

  In response to activation of read word line RWLi of the selected row and column selection line CSLj of the selected column, data lines LIO and LIOr are electrically coupled to the selected memory cell and the dummy cell, respectively. Thereby, current starts to flow to data lines LIO and LIOr from time t3. Further, current starts to flow to global data lines GIO and / GIO from time t4 in accordance with the voltages of sense nodes Ns and / Ns respectively determined by the passing currents of data lines LIO and LIOr.

  The passing current Ild of the data line LIO electrically coupled to the selected memory cell is either Idat (Rmax) or Idat (Rmin) depending on the stored data. The difference between the currents Idat (Rmin) and Idat (Rmax) is expressed as ΔI ′.

  On the other hand, since the electric resistance of the dummy cell is preset to Rmin, the passing current Ilr of the data line LIOr is at the same level as Idat (Rmin). Therefore, when the data stored in the selected memory cell corresponds to electric resistance Rmin, no voltage difference is generated between sense nodes Ns and / Ns. As a result, when the offset control voltages Vofd and Vofr input to the gates of the transistors 83 and 84 are at the same level, no offset occurs between the passing currents Igd and Igr of the global data lines GIO and / GIO.

  On the other hand, when the data stored in the selected memory cell corresponds to the electric resistance Rmax, the passing current Idat (Rmax) of the data line LIO is smaller than the passing current Ilr of the data line LIOr, so that the sense node Ns Is higher than the voltage of the sense node / Ns by ΔV ′. Therefore, since the gate voltage of transistor 81 is higher than the gate voltage of transistor 82, even when offset control voltages Vofd and Vofr are at the same level, passing current Igd of global data line GIO is equal to the data of global data line / GIO. It becomes larger than the passing current Igr.

  Thus, when the electric resistance of dummy cell DMC corresponds to Rmin, the passing current Igd of global data line GIO corresponding to the selected memory cell is equivalent to the passing current Igr of global data line / GIO corresponding to the dummy cell. Either it is or it is larger.

  Therefore, in global differential amplifier 80, passing current Igr of global data line / GIO is intermediate between two kinds of passing currents Igd (Rmin) and Igd (Rmax) corresponding to the storage data of the selected memory cell of global data line GIO. It is necessary to give an offset that satisfies the above (2) so as to achieve a level.

Igd (Rmax) + ΔIof = Igr = Igd (Rmin) −ΔIof (2)
That is, when the electric resistance of the dummy cell is set to Rmin in advance, the offset control voltage Vofr = Vofd−Vα is set in order to give an offset for reducing the reference current Igr which is a passing current of the global data line / GIO by ΔIof. To do. The difference Vα between the offset control voltages Vofr and Vofd is adjusted corresponding to the ΔIof.

  Alternatively, the offset control voltages Vofr and Vofd are set to a common level so that an offset that reduces the passing current (reference current Iref) of the data line LIOr by ΔIof is applied to the transistor 87 connected to the global data line / GIO. The current driving capability (transistor size) may be designed to be smaller than the current driving capability (transistor size) of the transistor 86 connected to the global data line GIO.

  Further, in the case where the electric resistance Rmax of the dummy cell DMC is set, the offset control voltage Vofr = Vofd + Vα is set in order to give an offset for increasing the reference current Igr which is a passing current of the global data line / GIO by ΔIof. That's fine.

  Alternatively, the current of the transistor 87 connected to the global data line GIOr is set so that the offset control voltages Vofr and Vofd are set to a common level to give an offset that increases the passing current (reference current Iref) of the data line LIOr by ΔIof. The drive capability (transistor size) may be designed to be larger than the current drive capability (transistor size) of the transistor 86 connected to the global data line GIO.

  Between time t4 and time t5, the passing current difference ΔIof between global data lines GIO and / GIO generated based on the electrical resistances of the selected memory cell and the dummy cell due to the offset given in this way is caused by global differential amplifier 80. , Converted into a voltage difference ΔVof between global sense nodes Ngs and / Ngs. Since this voltage difference ΔVof has a polarity corresponding to the data stored in the selected memory cell, the data stored in the selected memory cell can be detected from the voltages of global sense nodes Ngs and / Ngs.

  Since the operation at the end of data reading after time t5 is the same as the operation after time t4 in FIG. 3, detailed description will not be repeated.

  In the configuration according to the second embodiment, the same data read operation as that of the first embodiment can be executed even when the differential amplifier has a two-stage configuration. By executing the data reading by the two-stage differential amplification operation, it is possible to execute the data reading with a sufficient amplification factor without providing a very large MOS transistor. The circuit area can be reduced.

[Modification 1 of Embodiment 2]
In the configuration according to the first modification of the second embodiment, the connection correspondence between the data lines LIO, / LIO and the selected memory cell and the dummy cell shown in FIG. 4 is switched according to the address selection result. A configuration for performing differential amplification in stages will be described.

  FIG. 11 is a circuit diagram showing a configuration of a data read circuit system according to the first modification of the second embodiment.

  Referring to FIG. 11, in the configuration according to the first modification of the second embodiment, in addition to the configuration according to the second embodiment shown in FIG. 9, a connection is made between differential amplifier 60 and data lines LIO and / LIO. The difference is that the switching circuit 70 is arranged. The differential amplifier 60 is provided for the memory array 10 having the configuration shown in FIG. Therefore, although not shown, at the time of data reading, data lines LIO and / LIO electrically coupled to sense nodes Ns and / Ns are respectively connected to one of selected memory cell and dummy cell DMC according to the address selection result. Connected in series.

  The configuration of connection switching circuit 70 is the same as that shown in FIG. 5, and one of data lines LIO and / LIO connected to the selected memory cell is fixed to node Nd according to the address selection result. The other side connected to the dummy cell is fixedly connected to the node Nr (transistor 62 side).

  As a result, differential amplifier 60, global differential amplifier 80 and voltage generation circuits 90 and 91 are operated in the same manner as described in the second embodiment, so that the data line between the complementary data line and the selected memory cell and dummy cell is The same effect as that of the second embodiment can be obtained also for the memory array having the folded bit line configuration in which the connection correspondence is switched according to the address selection result. Further, the memory array having a folded bit line configuration can execute accurate data reading with higher noise tolerance.

[Modification 2 of Embodiment 2]
FIG. 12 is a circuit diagram showing a configuration of a data read circuit system according to the second modification of the second embodiment.

  Referring to FIG. 12, in the configuration according to the second modification of the second embodiment, connection switching circuit 70 is provided corresponding to the inside of global differential amplifier 80. That is, connection switching circuit 70 is provided to divide global data lines GIO and / GIO, and controls the connection correspondence between transistors 81 and 82 and transistors 83 and 84 according to the address selection result.

  That is, when an odd row is selected and address signal RA0 is set to H level, connection switching circuit 70 responds to the voltage of sense node Ns electrically coupled to the selected memory cell via data line LIO. In response to the voltage of the sense node / Ns connected in series to the transistor 81 whose pass current is controlled and the transistor 83 receiving the offset control voltage Vofd at its gate and electrically coupled to the dummy cell via the data line / LIO The transistor 82 whose passing current is controlled is connected in series with the transistor 84 that receives the offset control voltage Vofr at the gate.

  In contrast, when an even-numbered row in which address signal / RA0 is set to the H level is selected, the passing current is controlled according to the voltage of sense node Ns electrically coupled to the dummy cell via data line LIO. Transistor 81 is connected in series with transistor 84 that receives offset control voltage Vofr at its gate, and the passing current is controlled according to the voltage of sense node / Ns electrically coupled to the selected memory cell via data line / LIO. The transistor 82 to be connected is connected in series with the transistor 83 receiving the offset control voltage Vofd at the gate.

  Thus, even if the connection switching circuit 70 is provided corresponding to the subsequent stage of the differential amplifier 60, that is, the global differential amplifier 80, the differential amplifier 60, the global differential amplifier 80, and the voltage generation circuits 90 and 91 are By operating in the same manner as described in the second embodiment, a memory array having a folded bit line configuration in which the connection correspondence between the complementary data line and the selected memory cell and the dummy cell is switched according to the address selection result. Also, the same effect as in the second embodiment can be obtained. Further, the memory array having a folded bit line configuration can execute accurate data reading with higher noise tolerance.

  With such a configuration, for example, in a memory array configuration divided into a plurality of memory blocks, a first-stage amplifier circuit corresponding to the differential amplifier 60 is installed for each memory block, and is common to the plurality of blocks. When the global differential amplifier 80 is provided, the number of the connection switching circuits 70 can be reduced to reduce the circuit area.

  In differential amplifiers 60 and 60 # and global differential amplifier 80 shown in the first and second embodiments, transistors 61, 61A, 61B, 62, 62A, 62B, and 81 to 84 are formed of N-type MOS transistors. Although the transistors 63 to 65 and 85 to 87 are P-type MOS transistors, the polarity of the operation voltage of each differential amplifier or the gate voltage (for example, setting of the offset control voltage) of each transistor is considered. Then, the polarity (N-type / P-type) of these transistors can be changed as appropriate.

[Embodiment 3]
In the third embodiment, another configuration example for executing data reading with dummy cells having the same configuration as a normal memory cell will be described.

  FIG. 13 is a circuit diagram showing a configuration of a data read circuit system according to the third embodiment. Referring to FIG. 13, since memory array 10 has a configuration similar to that shown in FIG. 4, detailed description will not be repeated. In FIG. 13, a read word line RWLe, a digit line DLe, bit lines BL0, / BL0 and normal memory cells, and corresponding dummy cells DMC, corresponding to the first memory cell column in one even-numbered row as representatively shown. Dummy read word line DRWLe and dummy digit line DDLe are representatively shown.

  Since the connection relationship between data line pair LIOP formed of data lines LIO and / LIO and memory array 10 is the same as in FIG. 4, detailed description will not be repeated. Compared with the configuration of FIG. 4, the arrangement of the connection switching circuit 70 is omitted, and the data reading circuit 160 is arranged instead of the differential amplifier 60. Unlike the differential amplifier 60, the data read circuit 160 does not have a function of providing an offset between the passing currents of the data lines LIO and / LIO, and the data line in which the passing current difference between the selected memory cell and the dummy cell is reflected as it is. Data reading from the selected memory cell is performed by converting the passing current difference between LIO and / LIO into a voltage difference between sense nodes Ns and / Ns.

  For example, in the differential amplifier 60, the current drive capability (transistor size) is balanced between the transistors 61 and 62 and between the transistors 63 and 64, respectively, and the common control voltage is applied to the gates of the transistors 61 and 62. By giving Vref, such a data read circuit 160 can be realized.

  In the configuration according to the third embodiment, in normal memory cell MC, the source voltage of access transistor ATR is set to a predetermined voltage Vss, while in dummy cell DMC, the source voltage of dummy access transistor ATRd is the dummy source voltage. The source voltage Vsl (Vsl ≠ Vss) supplied by the line DSL is set.

  At the time of data reading, each of data lines LIO and / LIO is set to a common voltage corresponding to control voltage Vref. As a result, a difference occurs between the voltages applied to both ends of the selected memory cell and the dummy cell in which the access transistor ATR and the dummy access transistor ATRd are turned on. As a result, the voltages applied to both ends of the tunnel magnetoresistive element TMR in the selected memory cell and the dummy magnetoresistive element TMRd in the corresponding dummy cell are different.

  For example, when the dummy cell DMC is set in advance to the electric resistance Rmin, the source voltage Vsl is set so as to be higher than the predetermined voltage Vss (Vsl> Vss), and the voltage applied to both ends of the dummy magnetoresistive element TMRd becomes the tunneling magnetoresistance. By making it smaller than the voltage applied across the element TMR, the reference current Iref passing through the dummy cell can be set to an intermediate level between the two types of data read current Idat passing through the selected memory cell. Note that, by suppressing the voltage applied across the dummy magnetoresistive element TMRd, the operation reliability of the dummy cell DMC whose access frequency is higher than that of the normal memory cell can be improved.

  On the contrary, when the electric resistance of the dummy cell DMC is preset to Rmax, the source voltage Vsl is set lower than the predetermined voltage Vss (Vsl <Vss), and the voltage applied across the dummy magnetoresistive element TMRd is set to the tunnel magnetoresistive element. By making it larger than the voltage applied across the TMR, the reference current Iref can be set to an intermediate level between the two types of passing currents of the selected memory cell.

  Thus, according to the configuration according to the third embodiment, the dummy cell DMC is supplied without providing a special configuration for giving an offset to the differential amplifier 60 side, that is, the passing current of data lines LIO and / LIO. By adjusting the source voltage, that is, by a simpler data read circuit system, it is possible to execute data read using the dummy cell DMC having the same configuration as the normal memory cell.

[Modification 1 of Embodiment 3]
FIG. 14 is a circuit diagram showing a configuration of a data read circuit system according to the first modification of the third embodiment.

  Referring to FIG. 14, in the configuration according to the modification of the third embodiment, bit line BL or / BL and the dummy source voltage are read at the time of data reading as compared with the configuration according to the third embodiment shown in FIG. The difference is that a plurality of dummy cells DMC are connected in parallel between the lines DSL.

  That is, compared to the configuration according to the third embodiment, N times (N: an integer of 2 or more) dummy cell rows are arranged in memory array 10. As an example, FIG. 14 shows a configuration in which two dummy cells DMC are connected in parallel when N = 2, that is, between the bit line BL or / BL and the dummy source voltage line DSL during data reading. It is. FIG. 14 representatively shows dummy read word lines DRWLe0 and DRWLe1 respectively corresponding to two dummy cell rows arranged corresponding to even rows, and two dummy cells in the first memory cell column corresponding thereto. It is.

  Dummy read word lines DRWLe0 and DRWLe1 are activated and deactivated in common. Therefore, at the time of data reading in which an even-numbered row is selected, two dummy cells DMC are connected in parallel between each bit line BL and dummy source voltage line DSL. Although not shown, dummy cells corresponding to odd rows are also arranged over two rows in the same manner.

  With such a configuration, since the reference current Iref is generated by the passing currents of the plurality of dummy magnetoresistive elements, the passing current per dummy cell can be suppressed. For example, when the electric resistance of each dummy cell DMC is set to Rmin, the source voltage Vsl supplied by the dummy source voltage line DSL is further increased as compared with the configuration shown in FIG. Even if the voltage applied across the resistor element TMRd is reduced, the desired reference current Iref can be generated.

  As a result, the operation reliability of the dummy cell DMC whose access frequency is higher than that of the normal memory cell can be ensured, and data reading similar to that of the third embodiment can be executed.

[Modification 2 of Embodiment 3]
FIG. 15 is a circuit diagram showing a configuration of a data read circuit system according to the second modification of the third embodiment.

  Referring to FIG. 15, in the configuration according to the second modification of the third embodiment, the current transmission for controlling the voltage of dummy source voltage line DSL is compared with the configuration according to the third embodiment shown in FIG. The difference is that the circuit 100 is further provided.

  The current transfer circuit 100 includes a transistor 101 electrically connected between a node 103 that supplies a predetermined voltage Vss and a dummy source voltage line DSL, and a source voltage Vsl corresponding to the voltage of the dummy source voltage line DSL and its reference value. And a sense amplifier 102 that amplifies the voltage difference between the two and the gate of the transistor 101. Thereby, the passing current of the transistor 101 is controlled so that the dummy source voltage line DSL is maintained at the source voltage Vsl.

  With such a configuration, in the configuration according to the third embodiment, the dummy source voltage line DSL can be stably set to the source voltage Vsl, so that stable data reading can be executed.

[Modification 3 of Embodiment 3]
FIG. 16 is a circuit diagram showing a configuration of a data read circuit system according to the third modification of the third embodiment.

  Referring to FIG. 16, in the configuration according to the third modification of the third embodiment, a predetermined voltage Vss is applied to the normal memory cell as compared with the configuration according to the second modification of the third embodiment shown in FIG. The difference is that a current transmission circuit 105 is further provided for the source voltage line SL to be supplied.

  Current transfer circuit 105 amplifies a voltage difference between transistor 106 electrically coupled between source voltage line SL and ground node 104, and a predetermined voltage Vss corresponding to the voltage of source voltage line SL and its reference value. And a sense amplifier 107 that outputs to the gate of the transistor 106. Thereby, the passing current of the transistor 106 is controlled so that the source voltage line SL is maintained at the predetermined voltage Vss. Further, also in current transmission circuit 100, transistor 101 is provided between the dummy source voltage line and ground node 104.

  Thus, in the configuration according to the third modification of the third embodiment, predetermined voltage Vss given as the source voltage of access transistor ATR of the normal memory cell is set to a voltage different from ground voltage GND.

  As shown in FIG. 17, one of the source voltage Vsl for the dummy cell and the source voltage (Vss) for the normal memory cell is generated based on the other using the same voltage dividing path. In general, it is difficult to strictly maintain the absolute levels of the source voltages Vsl and Vss generated as the reference voltages. However, with the above-described configuration, the relative voltages between the source voltages Vsl and Vss are reduced. This level difference can be maintained stably.

  In the data read operation according to the third embodiment, the reference current Iref is generated by generating a desired difference between the voltage applied across the selected memory cell and the voltage applied across the dummy cell. According to the configuration according to the modification example 3, the reference current Iref can be set more accurately while suppressing the fluctuation.

[Embodiment 4]
In the fourth embodiment, a configuration for sharing a data read circuit system between a plurality of memory blocks in a configuration in which MTJ memory cells are divided and arranged in a plurality of memory blocks will be described.

FIG. 18 is a circuit diagram showing a configuration of a data read circuit system according to the fourth embodiment.
Referring to FIG. 18, a plurality of MTJ memory cells are divided and arranged in memory blocks MBa and MBb which are selectively selected for data reading.

  A memory cell column is shared between memory blocks MBa and MBb. Therefore, column select lines CSL0-CSLn provided corresponding to the memory cell columns are shared between memory blocks MBa and MBb. Column decoder 25 selectively activates column select lines CSL0-CSLn according to column address CA.

  On the other hand, the read word line RWL corresponding to each memory cell row is arranged independently for each memory block. Further, dummy cells DMC are arranged to form dummy cell rows 110a and 110b in memory blocks MBa and MBb, respectively. For example, in memory block MBa, read word lines RWL0a to RWLma are arranged corresponding to (m + 1) (m: natural number) normal memory cell rows, respectively, and dummy read word line DRWLa corresponding to dummy cell row 110a. Is placed. Similarly, in memory block MBb, read word lines RWL0b to RWLmb are arranged corresponding to (m + 1) normal memory cell rows, and dummy read word line DRWLb is arranged corresponding to dummy cell row 110b. .

  Row decoders 20a and 20b are provided corresponding to memory blocks MBa and MBb, respectively. Row decoders 20a and 20b receive block selection signals BSa and BSb indicating the selection results of memory blocks MBa and MBb, respectively, and perform row selection according to row address RA.

  Specifically, when memory block MBa is selected as a data read target and block selection signal BSa is activated (H level), row decoder 20a reads read word lines RWL0a to RWLma based on row address RA. One of them is selectively activated. On the other hand, the row decoder 20b activates the dummy read word line DRWLb to select the dummy cell row 110b.

  On the other hand, when memory block MBb is selected as a data read target and block selection signal BSb is activated (H level), row decoder 20b reads read word lines RWL0b to RWLmb based on row address RA. One of them is selectively activated. On the other hand, the row decoder 20a activates the dummy read word line DRWLa to select the dummy cell row 110a.

  Corresponding to (n + 1) (n: natural number) memory cell columns, bit lines BL0a to BLna and BL0b to BLnb are independently arranged in memory blocks MBa and MBb, respectively. Complementary data lines LIO and / LIO are arranged along read word line RWL and are shared between memory blocks MBa and MBb. Further, column selection gates CSG0 to CSGn are arranged corresponding to the memory cell columns, respectively. Each of column selection gates CSG0 to CSGn responds to activation (H level) of corresponding one of column selection lines CSL0 to SCLn and transmits corresponding one of bit lines BL0a to BLna to data line LIO. And corresponding one of the bit lines BL0b to BLnb is connected to the data line / LIO.

  Data read circuit 161 has the same configuration and function as differential amplifier 60 # shown in FIG. Data read circuit 161 operates in accordance with block selection signals BSa and BSb instead of address signals RA0 and / RA0 in FIG. Logic gate 69 inputs the NOR operation result of block selection signals BSa and BSb to data read circuit 161 as sense enable signal / SE. Since sense enable signal / SE generated in this manner is input to the gate of transistor 65 shown in FIG. 2, one of memory blocks MBa and MBb is selected as a data read target, and block selection signal BSa and When any one of BSb is activated to H level, supply of an operating current for executing a differential amplification operation in data read circuit 161 is started.

  When memory block MBa is selected as a data read target, a selected memory cell in memory block MBa is connected to data line LIO, and a dummy cell in memory block MBb is connected to data line / LIO. . On the other hand, when memory block MBb is selected as a data read target, the selected memory cell in memory block MBb is connected to data line / LIO, and data line LIO is connected to a dummy cell in memory block MBa.

  In this manner, data reading according to the second modification of the first embodiment is executed in accordance with the passing current difference between data lines LIO and / LIO to which each of the selected memory cell and the dummy cell is connected, respectively. The stored data from the selected memory cell can be read.

  With such a configuration, the data read circuit corresponding to the complementary data lines LIO and / LIO and the differential amplifier can be shared between the two memory blocks, so that the circuit scale of the data read system circuit can be increased. Can be small.

[Modification of Embodiment 4]
FIG. 19 is a circuit diagram showing a configuration of a data read circuit system according to a modification of the fourth embodiment.

  Referring to FIG. 19, in the configuration according to the modification of the fourth embodiment, compared to the configuration according to the fourth embodiment shown in FIG. 18, in each of memory blocks MBa and MBb, dummy cells are dummy cell columns 115a and The difference is that they are arranged to form 115b.

  Therefore, each of read word lines RWL0a to RWLma and RWL0b to RWLmb arranged in memory blocks MBa and MBb is shared between normal memory cell MC and dummy cell DMC. On the other hand, bit lines BL0a to BLna are arranged corresponding to normal memory cell columns in memory block MBa, and bit lines BL0b to BLnb are arranged corresponding to normal memory cell columns in memory block MBb. The Further, in each of memory blocks MBa and MBb, dummy bit lines BLda and BLdb are arranged corresponding to dummy cell columns 115a and 115b, respectively.

  Column selection gates CSG0 to CSGn are provided corresponding to (n + 1) normal memory cell columns, respectively, and dummy column selection gate CSGd is provided corresponding to dummy cell columns 115a and 115b. Each of column select gates CSG0 to CSGn responds to activation (H level) of corresponding one of column select lines CSL0 to CSLn and transmits corresponding one of bit lines BL0a to BLna to data line LIO. And one corresponding bit line BL0b to BLnd is connected to the data line / LIO. In contrast, dummy column selection gate CSGd connects dummy bit line BLda to data line / LIO and bit line BLdb to data line LIO in response to activation of dummy column selection line CSLd.

  In the data read operation, column decoder 25 selectively activates one of column select lines CSL0-CSLn according to column address CA, while setting dummy column select line CSLd to H regardless of the address selection result. Activate to level. On the other hand, row decoder 20a selectively activates one of read word lines RWL0a to RWLma according to row address RA when memory block MBa includes a selected memory cell. Row decoder 20b selectively activates one of read word lines RWL0b to RWLmb according to row address RA when memory block MBb includes a selected memory cell. Since the configuration and operation of other parts are the same as the configuration according to the fourth embodiment shown in FIG. 18, detailed description will not be repeated.

  With such a configuration, in the data read operation in which the selected memory cell is included in memory block MBa, the selected memory cell is connected to data line LIO and the same memory as the selected memory cell in memory block MBa Dummy cells belonging to the cell row are connected to the data line / LIO. On the other hand, at the time of data reading in which the selected memory cell is included in memory block MBb, the selected memory cell is connected to data line / LIO and dummy cells belonging to the same memory cell row as the selected memory cell in memory block MBb Connected to the data line LIO.

  Therefore, even in the case where each memory block is arranged so as to constitute a memory cell column of dummy cells, complementary data lines LIO, / LIO and data read circuit 161 are provided between two memory blocks as in the fourth embodiment. By sharing, a data reading configuration with a reduced circuit scale can be realized.

  In the fourth embodiment and the modification thereof, as in the first modification of the first embodiment, the data read circuit 161 shared between the two memory blocks by the combination of the differential amplifier 60 and the connection switching circuit 70. May be configured. In this case, connection switching circuit 70 needs to switch the connection correspondence between data lines LIO, / LIO and transistors 61, 62 shown in FIG. 2 in accordance with block selection signals BSa, BSb. .

  Alternatively, in the memory blocks MBa and MBb, the source voltages supplied to the normal memory cells and the dummy cells can be made independent as in the third embodiment. In this case, data read circuit 160 shown in FIG. 13 is arranged in place of data read circuit 161. Thus, even if the configuration according to the third embodiment is combined with the fourth embodiment and its modification, the data read circuit 160, the data lines LIO, / LIO, and the sources corresponding to the normal memory cell and the dummy cell, respectively. The voltage line can be shared between the two memory blocks.

[Embodiment 5]
In the fifth embodiment, a configuration of a dummy cell that has an intermediate electrical resistance and can be efficiently arranged according to the pitch of a normal memory cell will be described.

FIG. 20 is a circuit diagram illustrating the configuration and arrangement of dummy cells according to the fifth embodiment.
Referring to FIG. 20, in the configuration according to the fifth embodiment, in memory array 10, normal memory cell MC and dummy cell 200 according to the fifth embodiment have a folded bit line configuration similar to the configuration shown in FIG. Based on this, they are alternately arranged for each row. That is, dummy cell 200 is arranged so as to form two dummy cell rows respectively corresponding to the odd-numbered and even-numbered rows of normal memory cells, similarly to dummy cell DMC shown in FIG. That is, dummy read word line DRWLo and dummy digit line DDLo are arranged corresponding to dummy cell rows corresponding to odd rows, and dummy read word line DRWLe and dummy digit line DDLe are arranged corresponding to dummy cell rows corresponding to even rows. Is done.

  In FIG. 20, typically, read word lines RWL0, RWL1, digit lines DL0, DL1, bit lines corresponding to the first memory cell row, the next memory cell row, and the j-th memory cell column are shown. A normal memory cell corresponding to the pair BLP and dummy cells corresponding to these normal memory cells are typically shown. The bit line pair BLPj is composed of complementary bit lines BLj and / BLj.

  In each memory cell column, complementary bit lines BL and / BL are connected to data buses DB and / DB constituting data bus pair DBP via corresponding column selection gate CSG, respectively. For example, bit lines BLj and / BLj corresponding to the j-th memory cell column are connected to data buses DB and / DB, respectively, in response to activation of corresponding column selection line CSLj.

  Data read circuit 160 is configured in the same manner as described in the third embodiment, and detects and amplifies the pass current difference between data buses DB and / DB in which the pass current difference between the selected memory cell and the dummy cell is reflected as it is. Read data from the selected memory cell.

  Dummy cell 200 includes a dummy access element ATRd, a dummy magnetoresistive element TMRd, and a dummy resistance adding unit 205 connected in series between a predetermined voltage Vss and the corresponding bit line BL or / BL. The dummy magnetoresistive element TMRd is magnetized in advance so that the electric resistance of each dummy cell DMC is Rmin. The gate of dummy access element ATRd is connected to one of dummy read word lines DRWLo and DRWLe in each dummy cell row.

  The electric resistance Rd of the dummy resistance adding unit 205 needs to be set to be at least smaller than ΔR, and is preferably set to ΔR / 2. Thereby, the electric resistance of the dummy cell 200 becomes Rmin + ΔR / 2, which is an intermediate level between the two types of electric resistances Rmax and Rmin of the selected memory cell.

  The dummy resistance adding unit 205 includes at least one transistor connected in parallel. FIG. 20 shows an example in which the dummy resistance adding unit 205 is composed of two field effect transistors 206 and 207. These field effect transistors 206 and 207 constituting dummy resistance adding unit 205 are manufactured and designed in the same manner as access transistor ATR in normal memory cell MC, and have the same size.

  Therefore, when the dummy cell 200 is formed on the semiconductor substrate, if the dummy access element ATRd and the field effect transistors 206 and 207 are arranged in parallel, the arrangement pitch of the normal memory cells in the row direction (that is, the bit) Each dummy cell 200 can be efficiently arranged so as to match the line pitch.

  Further, each gate of field effect transistors 206 and 207 is connected to one of control voltage lines DCLo and DCLe transmitting adjustable control voltage Vrd in each dummy cell row. Thereby, the dummy resistance Rd of the dummy resistance adding unit 205 can be tuned by adjusting the control voltage Vrd. In other words, the control voltage Vrd is adjusted so that a preferable dummy resistance value (ΔR / 2) is obtained.

  With such a configuration, the data read circuit 160 is arranged within the same pitch as the normal memory cell without requiring a special configuration for providing an offset between the passing currents of the data buses DB and / DB. Possible dummy cells with intermediate electrical resistance can be formed.

  As shown in FIG. 21, dummy cell 200 according to the fifth embodiment can be arranged in memory array 10 so as to form a dummy cell column.

  Referring to FIG. 21, a bit line BLd and a control voltage line DCL are provided for dummy cells 200 arranged to form a dummy cell column. These dummy cells 200 are arranged so as to share a memory cell row with normal memory cells MC. That is, when read word line RWL of the selected row is activated to H level according to the row selection result, dummy access element ATRd in the corresponding dummy cell is turned on.

  Dummy column selection gate CSGd is arranged corresponding to the dummy cell column, and controls between data bus / DB and bit line BLd in response to activation of dummy column selection line CSLd. At the time of data reading, dummy column selection line CSLd is activated to H level regardless of the address selection result, and data bus / DB is connected to bit line BLd connected to the dummy cell. On the other hand, a bit line (for example, bit line BLj) corresponding to the selected memory cell is connected to data bus DB. That is, at the time of data reading, one of the plurality of bit lines BL corresponding to the normal memory cell corresponding to the selected column is connected to the data bus DB according to the column selection result.

  Therefore, data reading circuit 160 can detect and amplify a passing current difference between data buses DB and / DB connected in series with the selected memory cell and the dummy cell, respectively, and execute data reading from the selected memory cell. Is possible.

  In the configuration according to FIG. 21, dummy cell 200 is a normal memory cell in the column direction by arranging dummy access transistor ATRd and field effect transistors 206 and 207, each having the same size, in the row direction. Can be arranged in accordance with the arrangement pitch (that is, the read word line pitch). Thereby, an increase in the area of the memory array 10 can be prevented, and the dummy cells 200 can be efficiently arranged.

[Embodiment 6]
In the sixth embodiment, another configuration example for performing data reading using a dummy cell having the same configuration and shape as a normal memory cell will be described.

  FIG. 22 is a circuit diagram showing a configuration of a data read circuit system according to the sixth embodiment. Referring to FIG. 22, in the configuration according to the sixth embodiment, in memory array 10, normal memory cell MC and dummy cell DMC are arranged in one row based on the folded bit line configuration, similarly to the configuration shown in FIG. Alternately arranged. As already described, since the dummy cells DMC have the same configuration and shape as the normal memory cells MC, they can be continuously arranged in a matrix with the normal memory cells MC in the memory array 10. The dummy magnetoresistive element TMRd in each dummy cell DMC is previously magnetized in the direction in which the electric resistance becomes Rmin.

  Read word line RWL and digit line DL provided corresponding to the normal memory cell row, dummy read word lines DRWLe and DRLLo provided corresponding to the dummy cell rows, dummy digit lines DDLe and DDLo, and normal memory cells and dummy cells Since complementary bit lines BL and / BL provided corresponding to the shared memory cell columns are also arranged in the same manner as in FIG. 4, detailed description will not be repeated.

  Further, source voltage lines SL0, SL1,... For setting the source of access transistor ATR to a predetermined voltage Vss are arranged corresponding to each normal memory cell row. On the other hand, for dummy cell DMC, predetermined voltage Vss is supplied to the source of dummy access transistor ATRd through dummy source voltage lines DSLe and DSLo respectively arranged corresponding to two dummy cell rows. .

  Outside the memory array 10, the dummy resistance adding unit 205 is connected between each of the dummy source voltage lines DSLe and DSLo and a predetermined voltage Vss. With such a configuration, the electric resistance Rd of the dummy resistance adding unit 205 can be added in series to each of the dummy cells DMC belonging to the dummy cell row in which the corresponding dummy read word lines DRWLe and DRLLo are activated. That is, the dummy resistance adding unit 205 can be shared between dummy cells DMC belonging to the same dummy cell row.

  By adopting such a configuration, a dummy cell can be configured by using a part of the MTJ memory cells continuously manufactured in the same memory eye as in the first embodiment. That is, since a special design or manufacturing process is not required to manufacture the dummy cell, the normal memory cell and the dummy cell can be obtained without causing problems such as an increase in chip area due to a complicated structure and a decrease in processing margin of the memory array. Can be provided in the same memory array to ensure a data read margin.

  Further, as in the third embodiment, the data read circuit 160 is not provided with a special configuration for giving an offset to the passing currents of the data buses DB, / DB, that is, the data read circuit system can provide a simpler data read circuit system. Reading can be performed.

[Modification 1 of Embodiment 6]
FIG. 23 is a circuit diagram showing a configuration of a data read circuit system according to the first modification of the sixth embodiment.

  Referring to FIG. 23, in the configuration according to the first modification of the sixth embodiment, dummy resistance adding unit 208 is added to dummy resistance adding unit 205 as compared with the configuration according to the sixth embodiment shown in FIG. Further differences are provided. Dummy resistance adding portions 205 and 208 are arranged between data buses DB, / DB and data read circuit 160 outside memory array 10. The dummy resistance adding unit 205 is connected in series with one sense input node Nsi, and the dummy resistance adding unit 208 is connected in series with the other sense input node / Nsi.

  Since the configuration of memory array 10 is the same as that of FIG. 22, detailed description will not be repeated. That is, in memory array 10, normal memory cells and dummy cells DMC are arranged based on the folded bit line configuration, so that the connection correspondence relationship between data buses DB and / DB and selected memory cells and dummy cells. Are switched depending on the address selection result, that is, whether odd or even rows are selected.

  Correspondingly, in the configuration according to the first modification of the sixth embodiment, the connection correspondence between the data buses DB and / DB and the dummy resistance adding units 205 and 208 is switched according to the address selection result. A connection switching circuit 210 is further provided.

  Connection switching circuit 210 includes transistor switches 211 and 212 that are electrically coupled between data bus / DB and dummy resistance adding sections 205 and 208, respectively, and data bus DB and dummy resistance adding sections 205 and 208. Transistor switches 213 and 214 electrically coupled to each other. Each gate of transistor switches 212 and 213 receives address signal RA0 which is set to H level when odd rows are selected, and each gate of transistor switches 211 and 214 is set to H level when even rows are selected. Address signal / RA0 is input.

  As a result, when an odd row is selected, the data bus DB electrically coupled to the selected memory cell is connected in series with the dummy resistance adding unit 205, and the data bus / DB electrically coupled to the dummy cell is added with the dummy resistance. The unit 208 is connected in series. On the other hand, when an even-numbered row is selected, the data bus DB electrically coupled to the dummy cell is connected in series with the dummy resistance adding unit 208, and the data bus DB electrically coupled to the selected memory cell is the dummy resistor. The additional unit 205 is connected in series.

  That is, the connection switching circuit 210 connects the dummy resistance adding unit 205 in series with the selected memory cell and the dummy resistance adding unit 208 in series with the dummy cell regardless of the address selection result.

  The electric resistances of the dummy resistance adding units 205 and 208 are the electric resistance indicated by the sum of the electric resistance of the dummy cell and the dummy resistance adding unit 208, and two types of electric resistances (Rmax, Rmin) of the selected memory cell and dummy resistance addition It is set to be an intermediate level between two electric resistances indicated by the sum with the unit 205. For example, when the electric resistance of the dummy cell is set to Rmin, if the electric resistance of the dummy resistance adding unit 205 is ΔR / 2 and the electric resistance of the dummy resistance adding unit 208 is ΔR, the following equation (3) is satisfied. Thus, the above conditions can be satisfied.

Rmin + ΔR / 2 <Rmin + ΔR <Rmax + ΔR / 2 (3)
FIG. 23 shows a configuration example of the dummy resistance adding units 205 and 208 designed in this way. The dummy resistance adding unit 205 includes field effect transistors 206 and 207 connected in parallel, and the dummy resistance adding unit 208 is configured by half the number of dummy resistance adding units 205, that is, one field effect transistor. The A common control voltage Vrd is input to the gates of the transistors 206 to 208. Thereby, the electrical resistance of the dummy resistance adding unit 205 is set to ½ of the electrical resistance of the dummy resistance adding unit 205. That is, if the control voltage Vrd is adjusted so that the electric resistance of the dummy resistance adding unit 208 becomes ΔR, the electric resistance of the dummy resistance adding unit 205 can be set to ΔR / 2 following this.

  By adopting such a configuration, it is possible to generate a passing current difference of polarity according to the storage data of the selected memory cell between the sense input nodes Nsi and / Nsi of the data read circuit 160. Therefore, data can be read from the selected memory cell by detecting and amplifying the passing current difference.

  As described above, even in the configuration according to the first modification of the sixth embodiment, a dummy cell can be configured by using a part of the MTJ memory cells continuously manufactured in the same memory array 10, and thus the sixth embodiment. You can enjoy the same effect.

  Further, as shown in FIG. 24, in the memory array 10, the dummy cells DMC can be arranged as dummy cell columns associated with the dummy bit lines BLd, similarly to FIG.

  In this case, as described with reference to FIG. 21, the connection correspondence between the data buses DB and / DB and the selected memory cell and the dummy cell is fixed regardless of the address selection result. That is, at the time of data reading, the data buses DB and / DB are electrically connected to the selected memory cell and the dummy cell DMC, respectively, without arranging the connection switching circuit 210 as shown in FIG. Dummy resistance adding units 205 and 208 can be arranged between / DB and sense input nodes Nsi and / Nsi, respectively.

[Modification 2 of Embodiment 6]
In the configuration shown in FIG. 24, since the load capacities of the data buses DB and / DB are unbalanced, the second modification of the sixth embodiment shows a configuration for eliminating this point.

  FIG. 25 is a circuit diagram showing a second configuration of the data read circuit system according to the second modification of the sixth embodiment.

  25, the configuration according to the second modification of the sixth embodiment is different from the configuration shown in FIG. 24 in that memory array 10 is divided into two regions 10a and 10b. For example, it is assumed that selection between regions 10a and 10b is performed according to address signal RAn. For example, it is assumed that the selected memory cell is included in region 10a when address signal RAn is at H level, and the selected memory cell is included in region 10b when address signal RAn = L level.

  In region 10a, each bit line is connected to data bus / DB through a column selection gate. On the other hand, in region 10b, each bit line is connected to data bus DB through a column selection gate. FIG. 25 representatively shows bit lines BLAj and BLBj corresponding to the jth memory cell column in each of regions 10a and 10b.

  A dummy cell column formed by the dummy cells DMC is provided in each of the regions 10a and 10b. The dummy bit line BLAd provided corresponding to the dummy cell column in the region 10a is connected to the data bus DB via the dummy column selection gate CSGAd, and the dummy bit line BLBdb corresponding to the dummy cell column in the region 10b is connected to the dummy column. It is connected to the data bus / DB through the selection gate CSGBd. Further, the arrangement relationship of data buses DB and / DB is interchanged in region 220 corresponding to the midpoint between regions 10a and 10b. With this configuration, the load capacity between the data buses DB and / DB can be balanced.

  Between data buses DB and / DB and data read circuit 160, connection switching circuit 210 and dummy resistance adding sections 205 and 208 are arranged in the same manner as described with reference to FIG.

  Connection switching circuit 210 operates in response to address signals RAn and / RAn, and connects one of data buses DB and / DB electrically coupled to the selected memory cell to dummy resistance adding unit 205. One electrically coupled to the dummy cell is connected to the dummy resistance adding unit 208.

  Therefore, in the configuration according to the second modification of the sixth embodiment, the same effect as that according to the first modification of the sixth embodiment is executed after balancing the load capacities of the data buses DB and / DB. Can do. As a result, it is possible to increase the speed of data reading.

[Modification 3 of Embodiment 6]
FIG. 26 is a circuit diagram showing a configuration of a data read circuit system according to the third modification of the sixth embodiment.

  Referring to FIG. 26, in the configuration according to the third modification of the sixth embodiment, dummy resistance adding unit 208 (electric resistance ΔR) is added to dummy cell DMC as in the first and second modifications of the sixth embodiment. Although the series connection is performed and the dummy resistance adding unit 205 (electrical resistance ΔR / 2) is connected in series to the selected memory cell, these dummy resistance adding units 205 and 208 are connected to the data read circuit 160 and the data. .., And dummy source voltage lines DSLo and DSLe are arranged corresponding to the source voltage lines SL0, SL1,.

  Specifically, a dummy resistance adding unit 205 (electric resistance ΔR / 2) is provided between the source voltage lines SL0, SL1,... And each of the predetermined voltage Vss in the normal memory cell, and the dummy source voltage lines DSLo and A dummy resistance adding unit 208 is provided between each DSLe and the predetermined voltage Vss.

  Even with such a configuration, data reading similar to that of the first and second modifications of the sixth embodiment can be executed. Further, with such a configuration, it is possible to execute data reading even for the memory array 10 using the folded bit line configuration without providing the connection switching circuit 210 shown in FIG. That is, the circuit configuration of the data read system can be simplified.

[Modification 4 of Embodiment 6]
FIG. 27 is a circuit diagram showing a configuration of a data read circuit system according to the fourth modification of the sixth embodiment.

  Referring to FIG. 27, in the configuration according to the fourth modification of the sixth embodiment, only dummy resistance adding unit 208 is connected in parallel to sense input node Nsi as compared to the configuration shown in FIG. The point is different. As already described, sense input node Nsi is electrically coupled to selected memory cell (electric resistance Rmax or Rmin) by connection switching circuit 210 regardless of the address selection result (odd row / even row selection). . On the other hand, sense input node / Nsi is connected in series with a dummy cell (electric resistance Rmin).

  Therefore, the electric resistance Rdd of the dummy resistance adding unit 208 is a combined resistance in which the electric resistance of the dummy cell is a parallel connection of the two types of electric resistances Rmax and Rmin of the selected memory cell and the electric resistance Rdd (Rmin // Rdd). ) And (Rmax // Rdd). The electric resistance Rdd of the dummy resistance adding unit 208 can be adjusted by the control voltage Vrd.

  By adopting such a configuration, it is possible to execute data reading that enjoys the same effect as that of the first modification of the sixth embodiment.

  As described above, in the sixth embodiment and its modifications 1 to 4 (FIGS. 20 to 27), the case where the electrical resistance of the dummy magnetoresistive element TMRd in the dummy cell is preset to Rmin has been described. This is because the magnetization directions of the fixed magnetic layer FL and the free magnetic layer VL are changed after the magnetization process of the fixed magnetic layer FL shown in FIG. 31 performed after the memory array 10 is manufactured in the manufacturing process of the MRAM device. This is because the electric resistances of the dummy cells are Rmin. Therefore, in order to set the electric resistance in the dummy cell DMC to Rmax, a new magnetizing process for the dummy magnetoresistive element TMRd is required. In other words, by setting the electric resistance of the dummy magnetoresistive element TMRd to Rmin, a new magnetization process for the dummy cell becomes unnecessary.

  However, even when the electric resistance of dummy cell DMC is set to Rmax in advance, the configurations shown in the first to fourth modifications of the sixth embodiment shown in FIGS. 23 to 27 can be applied. In such a case, in the configuration according to the first to third modifications of the sixth embodiment (FIGS. 23 to 26), it is only necessary to replace the dummy resistance adding units 205 and 208, which is a modification of the sixth embodiment. In the configuration according to Example 4 (FIG. 27), if the dummy resistance adding unit 208 is connected in parallel to the sense input node / Nsi always connected to the dummy cell, the same data reading can be executed. Is possible.

[Embodiment 7]
In the seventh embodiment, the data based on the difference in passing current between the selected memory cell and the dummy cell manufactured in the same manner without newly providing the dummy resistance adding portion shown in the sixth embodiment and the modification thereof is used. A configuration capable of executing reading will be described.

FIG. 28 is a circuit diagram showing a data read configuration according to the seventh embodiment.
Referring to FIG. 28, in the configuration according to the seventh embodiment, dummy resistance addition connected in series or in parallel to at least one of the dummy cell and the selected memory cell shown in the sixth embodiment and its modification example is added. Parts are not arranged. That is, in memory array 10, normal memory cells MC and dummy cells DMC are continuously arranged so as to share a memory cell column, similarly to the configuration shown in FIG.

  Bit lines BL and / BL are provided in a direction in which a magnetic field is generated along the easy axis of tunneling magneto-resistance element TMR and dummy magneto-resistance element TMRd by the passing current. On the other hand, digit line DL and dummy digit lines DDLe and DDLo are provided in a direction in which a magnetic field along the hard axis of tunneling magneto-resistance element TMR and dummy magneto-resistance element TMRd is generated by the passing current. In general, bit lines BL, / BL are arranged along the hard axis of tunneling magneto-resistance element TMR and dummy magneto-resistance element TMRd, and digit line DL and dummy digit lines DDLe, DDLo are tunneling magneto-resistance elements. Arranged along the easy axis of TMR and dummy magnetoresistive element TMRd.

  As described above, the data write current is supplied to both the corresponding bit line BL and digit line DL for the normal memory cell selected as the data write target. Thereby, data writing is executed by magnetizing tunneling magneto-resistance element TMR of the selected memory cell along the easy axis according to the direction of the data write current flowing through bit line BL.

  The electric resistance of the dummy cell DMC, that is, the magnetization direction of the dummy magnetoresistive element TMRd needs to be kept constant. Therefore, the arrangement of dummy digit lines DDLe and DDLo for performing data write selection is not always necessary. However, in the configuration according to the seventh embodiment, even during data reading, bias current Ib for applying a bias magnetic field along the hard axis direction to dummy magnetoresistive element TMRd is applied to dummy digit line DDLe or Flowed to DDLo.

  FIG. 29 is a conceptual diagram illustrating the relationship between the current flowing through the dummy digit line and the electrical resistance of the dummy magnetoresistive element.

  FIG. 29A shows the magnetization direction of the dummy magnetoresistive element TMRd when no current is passed through the dummy digit line DDLe (DDLo), that is, when I (DL) = 0. That is, when the electric resistance of the dummy magnetoresistive element TMRd is Rmin, the magnetization direction 235 of the free magnetization layer is the same as the magnetization direction 230 of the fixed magnetization layer along the easy axis direction (EA).

  In this state, as shown in FIG. 29 (b), when a bias current Ib is passed through the dummy digit line DDLe (DDLo), that is, I (DL) = Ib, the magnetization direction 235 of the free magnetic layer changes to the bias current. It is rotated by the bias magnetic field in the hard axis direction generated by Ib.

  As a result, the magnetization direction 230 of the fixed magnetization layer and the magnetization direction 235 of the free magnetization layer do not coincide with each other, so that the electrical resistance of the dummy magnetoresistive element TMRd changes to an intermediate level between Rmin and Rmax. This intermediate level electrical resistance can be tuned by the amount of bias current Ib.

  Further, as shown by dotted lines in FIGS. 29A and 29B, in the dummy magnetoresistive element TMRd, the magnetization directions 230 and 235 of the fixed magnetization layer and the free magnetization layer are set in antiparallel directions, Similarly, when the electrical resistance is set to Rmax in advance, the electrical resistance of dummy magnetoresistive element TMRd can be set to an intermediate level between electrical resistances Rmin and Rmax due to the influence of the bias magnetic field generated by bias current Ib. it can.

  Referring again to FIG. 28, a data read current flows through corresponding bit line BL or / BL to dummy cell DMC corresponding to the selected column. Normally, this data read current has an easy axis when data is written. Compared to the data write current required to reverse the direction of magnetization, it remains at a very small level. Therefore, as described above, even if the bias current Ib is supplied to the dummy digit lines DDLe and DDLo at the time of data reading, erroneous data writing to the dummy cell is not executed.

  As described above, dummy resistors are connected in series or in parallel to the current path including the dummy cell and the current path including the selected memory cell, or the connection relation to the data buses DB and / DB is determined according to the address selection result. A dummy cell manufactured and designed in the same way as a normal memory cell, without using a connection switching circuit that switches between them, and without providing a configuration for providing an offset between the passing currents of the dummy cell and the selected memory cell, Data reading can be executed according to the difference in passing current from the memory cell.

  Therefore, the data read circuit system is not complicated without increasing the circuit area, that is, without increasing the circuit area, and without complicating the processing of the memory array 10 and making the manufacturing process difficult. Can be configured.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 is a schematic block diagram showing an overall configuration of an MRAM device according to an embodiment of the present invention. 1 is a circuit diagram showing a configuration according to a first embodiment of a data read circuit system for executing data read from a memory array. FIG. FIG. 7 is an operation waveform diagram illustrating a data read operation by the data read circuit system according to the first embodiment. 6 is a circuit diagram showing a configuration of a data read circuit system according to a first modification of the first embodiment. FIG. FIG. 5 is a circuit diagram illustrating a configuration of a connection switching circuit illustrated in FIG. 4. FIG. 14 is an operation waveform diagram illustrating a data read operation by a data read circuit system according to the first modification of the first embodiment. 6 is a circuit diagram showing a configuration of a differential amplifier according to a second modification of the first embodiment. FIG. FIG. 8 is an operation waveform diagram for explaining the operation of the differential amplifier shown in FIG. 7. FIG. 6 is a circuit diagram showing a configuration of a data read circuit system according to a second embodiment. FIG. 11 is an operation waveform diagram illustrating a data read operation by a data read circuit system according to the second embodiment. FIG. 11 is a circuit diagram showing a configuration of a data read circuit system according to a first modification of the second embodiment. FIG. 11 is a circuit diagram showing a configuration of a data read circuit system according to a second modification of the second embodiment. FIG. 10 is a circuit diagram showing a configuration of a data read circuit system according to a third embodiment. FIG. 11 is a circuit diagram showing a configuration of a data read circuit system according to a first modification of the third embodiment. FIG. 11 is a circuit diagram showing a configuration of a data read circuit system according to a second modification of the third embodiment. FIG. 11 is a circuit diagram showing a configuration of a data read circuit system according to a third modification of the third embodiment. It is a conceptual diagram which shows the structure which produces | generates the reference voltage of the source voltage line shown by FIG. FIG. 10 is a circuit diagram showing a configuration of a data read circuit system according to a fourth embodiment. FIG. 11 is a circuit diagram showing a configuration of a data read circuit system according to a modification of the fourth embodiment. FIG. 10 is a circuit diagram illustrating a configuration of a dummy cell and a first arrangement example according to a fifth embodiment. FIG. 10 is a circuit diagram illustrating a configuration of a dummy cell according to a fifth embodiment and a second arrangement example. FIG. 10 is a circuit diagram showing a configuration of a data read circuit system according to a sixth embodiment. FIG. 23 is a circuit diagram showing a first configuration example of a data read circuit system according to a first modification of the sixth embodiment. FIG. 23 is a circuit diagram showing a second configuration example of the data read circuit system according to the first modification of the sixth embodiment. FIG. 23 is a circuit diagram showing a configuration of a data read circuit system according to a second modification of the sixth embodiment. FIG. 23 is a circuit diagram showing a configuration of a data read circuit system according to a third modification of the sixth embodiment. FIG. 22 is a circuit diagram showing a configuration of a data read circuit system according to a fourth modification of the sixth embodiment. FIG. 17 is a circuit diagram showing a configuration of a data read circuit system according to a seventh embodiment. It is a conceptual diagram explaining the relationship between the electric current which flows through a dummy digit line, and the electrical resistance of a dummy magnetoresistive element. It is the schematic which shows the structure of an MTJ memory cell. It is a conceptual diagram explaining the data write-in operation | movement with respect to an MTJ memory cell. It is a conceptual diagram explaining the relationship between the data write current at the time of data writing and the magnetization direction of a tunnel magnetoresistive element. It is a conceptual diagram explaining the data read-out operation | movement from an MTJ memory cell.

Explanation of symbols

  1 MRAM device, 10 memory array, 10a, 10b region, 20, 20a, 20b row decoder, 55, 56, 57, 90, 91 voltage generation circuit, 60, 60 # differential amplifier, 61-65, 61A, 61B, 62A, 62B, 81-87 transistor, 70, 210 connection switching circuit, 80 global differential amplifier, 100, 105 current transfer circuit, 160, 161 data read circuit, 200, DMC dummy cell, 205, 208 dummy resistance adding unit, 230 , 235 Magnetization direction, ATR access transistor, ATRd dummy access transistor, BL, / BL bit line, BLd dummy bit line, BSa, BSb block selection signal, DB, / DB data bus, DDLe, DDLo dummy digit line, DL, DLe , DLo Digit line, DLi digit line, DRWLa, DRWLb, DRWLe, DRLLo dummy read word line, DSL, DSLe, DSLo dummy source voltage line, GIO, / GIO global data line, GND ground voltage, Ib bias current, Idat data read current, Iref reference current, LIO, LIOr, / LIO data line, MBa, MBb memory block, MC regular memory cell, Ngs, / Ngs global sense node, Ns, / Ns sense node, Nsi, / Nsi sense input node, RA0, / RA0, RAn, / RAn Address signal, RWL, RWLi, RWLo, RWLe Read word line, SL source voltage line, TMR tunnel magnetoresistive element, TMRd dummy magnetoresistive element, Vcc power supply voltage, Vof , Vof1, Vof2 Offset control voltage, Vsl source voltage (dummy cell), Vss fixed voltage.

Claims (10)

A magnetoresistive element that is magnetized in a direction according to the level of stored data and has either a first or a second electrical resistance according to the magnetization direction; and the magnetoresistive element in series A plurality of memory cells including access transistors connected and selectively turned on when reading data;
A dummy cell for comparing a passing current with a selected memory cell selected as an access target among the plurality of memory cells at the time of data reading;
First and second data lines electrically coupled to a fixed voltage through the selected memory cell and the dummy cell, respectively, during data reading;
A data read unit for reading data in accordance with a difference in passing current between the first and second data lines;
The dummy cell has the same configuration and shape as each of the magnetoresistive elements, and a dummy magnetoresistive element that is pre-magnetized so as to have a smaller one of the first and second electric resistances;
A dummy access transistor connected in series with the dummy magnetoresistive element and selectively turned on at the time of data reading, and designed similarly to the access transistor;
A dummy resistance adding unit connected in series with the dummy magnetoresistive element and having an electric resistance smaller than a difference between the first and second electric resistances;
The dummy resistance adding section includes at least one transistor designed in the same manner as the access transistor, and an adjustable control voltage is input to each gate of the transistor. A memory array in which a plurality of memory cells and a dummy cell for comparing a passing current with a selected memory cell selected as an access target among the plurality of memory cells at the time of data reading are arranged;
Each of the memory cells
A magnetoresistive element configured to be magnetized in a direction according to a level of stored data and to have one of a first electric resistance and a second electric resistance according to a magnetization direction;
An access transistor connected in series with the magnetoresistive element and selectively turned on when reading data;
The dummy cell is
A dummy magnetoresistive element that has the same configuration and shape as the magnetoresistive element and is pre-magnetized to have a smaller one of the first and second electrical resistances;
A dummy access transistor connected in series with the dummy magnetoresistive element and selectively turned on at the time of data reading, and a dummy access transistor designed in the same manner as the access transistor;
The thin film magnetic memory device includes:
A first voltage wiring provided corresponding to the plurality of memory cells and transmitting a fixed voltage;
A second voltage wiring provided corresponding to the dummy cell and transmitting the fixed voltage;
First and second data lines electrically coupled to the first and second voltage lines through the selected memory cell and the dummy cell, respectively, during data reading;
A data reading unit for reading data in accordance with a difference between passing currents of the first and second data lines;
A thin film magnetic device further comprising: a dummy resistance addition unit connected in series to the second voltage wiring outside the memory array and having an electric resistance smaller than a difference between the first and second electric resistances. Body storage device.   3. The thin film according to claim 2, wherein the dummy resistance adding unit includes a field effect transistor that is electrically coupled between the second voltage wiring and the fixed voltage and receives an adjustable control voltage to a gate. Magnetic storage device. A memory array in which a plurality of memory cells and a dummy cell for comparing a passing current with a selected memory cell selected as an access target among the plurality of memory cells at the time of data reading are arranged;
Each of the memory cells
A magnetoresistive element configured to be magnetized in a direction according to a level of stored data and to have one of a first electric resistance and a second electric resistance according to a magnetization direction;
An access transistor connected in series with the magnetoresistive element and selectively turned on when reading data;
The dummy cell is
A dummy magnetoresistive element having the same configuration and shape as the magnetoresistive element and pre-magnetized so as to have one of the first and second electric resistances;
A dummy access transistor connected in series with the dummy magnetoresistive element and selectively turned on at the time of data reading, and a dummy access transistor designed in the same manner as the access transistor;
The thin film magnetic memory device includes:
In data reading, first and second data lines electrically coupled to a fixed voltage through one of each of the selected memory cell and the dummy cell,
A data reading unit for reading data in accordance with a difference between passing currents of the first and second data lines;
A first resistor for connecting a third electrical resistance in series to one of the first and second data lines coupled to the selected memory cell outside the memory array. An additional part;
A second resistance adding unit for connecting a fourth electric resistance in series to the other data line coupled to the dummy cell of the first and second data lines outside the memory array. And further comprising
The third and fourth electric resistances are the sum of the electric resistance of the dummy cell and the fourth electric resistance, and the sum of the first and third electric resistances and the sum of the second and third electric resistances. Thin film magnetic memory device determined to be at an intermediate level. The dummy magnetoresistive element is pre-magnetized to have a smaller one of the first and second electrical resistances;
The fourth electrical resistance corresponds to a difference between the first and second electrical resistances,
5. The thin film magnetic memory device according to claim 4, wherein the third electric resistance is half of the fourth electric resistance. The first resistance adding unit includes L transistors (L: an even and positive integer of 2 or more) connected in parallel to receive an adjustable control voltage to each gate,
The thin film magnetic memory device according to claim 5, wherein the second resistance adding unit includes (L / 2) transistors connected in parallel to receive the control voltage to each gate. A first voltage wiring provided corresponding to the plurality of memory cells for transmitting the fixed voltage;
A second voltage wiring provided corresponding to the dummy cell for transmitting the fixed voltage;
The first resistance adding unit is connected in series between the first voltage wiring and the fixed voltage,
The thin film magnetic memory device according to claim 4, wherein the second resistance adding unit is connected in series between the second voltage wiring and the fixed voltage. The plurality of memory cells and the dummy cells are separately arranged in first and second memory blocks to be read data,
Each of the first and second memory blocks includes the dummy cell;
In the first memory block, the memory cells and the dummy cells are electrically coupled between the first and second data lines and the fixed voltage, respectively.
In the second memory block, the dummy cell and each of the memory cells are electrically coupled between the first and second data lines and the fixed voltage, respectively.
The thin film magnetic memory device includes a first resistance adding unit and a second resistance adding unit for each of the first and second data lines according to a selection result between the first and second memory blocks. The thin film magnetic memory device according to claim 4, further comprising a connection switching unit for complementarily connecting one of each in series. A memory array in which a plurality of memory cells and a dummy cell for comparing a passing current with a selected memory cell selected as an access target among the plurality of memory cells at the time of data reading are arranged;
Each of the memory cells
A magnetoresistive element configured to be magnetized in a direction according to a level of stored data and to have one of a first electric resistance and a second electric resistance according to a magnetization direction;
An access transistor connected in series with the magnetoresistive element and selectively turned on when reading data;
The dummy cell is
A dummy magnetoresistive element having the same configuration and shape as the magnetoresistive element and pre-magnetized so as to have one of the first and second electric resistances;
A dummy access transistor connected in series with the dummy magnetoresistive element and selectively turned on at the time of data reading, and a dummy access transistor designed in the same manner as the access transistor;
The thin film magnetic memory device includes:
In data reading, first and second data lines electrically coupled to a fixed voltage through one of each of the selected memory cell and the dummy cell,
A data reading unit for reading data in accordance with a difference between passing currents of the first and second data lines;
A resistance adding unit for connecting a third electrical resistance in parallel to one of the first and second data lines outside the memory array;
The third electrical resistance includes: a combined resistance of the first and third electrical resistances connected in parallel and a combined resistance of the second and third electrical resistances connected in parallel. A thin film magnetic memory device determined to be at an intermediate level. The dummy magnetoresistive element is pre-magnetized to have a smaller one of the first and second electrical resistances;
10. The thin film magnetic body according to claim 9, wherein at the time of data reading, the one data line to which the resistance adding unit is connected in parallel is electrically coupled to the fixed voltage via the selected memory cell. Storage device.

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