JP2008083134A - Plasma display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a plasma display device in which the connection defect arising between printed circuit boards mounting a data electrode driving circuit can be immediately detected. <P>SOLUTION: The plasma display device comprises the printed circuit board 461 mounting a write pulse generation section 46 of the data electrode driving circuit, the printed circuit board 471 mounting a write pulse output section 47 of the data electrode driving circuit, bridge connectors 462, 472 which are respectively arranged on the printed circuit boards 461, 471, and have a plurality of electrode terminals, and a harness 51 for connecting the connectors to each other. A connection defect detection circuit 53 which detects the electrical connection defect of the printed circuit boards to each other depending upon whether at least one electrode terminal of the bridge connector 462 on the printed circuit board is grounded or electrically opened is mounted on the printed circuit board 461. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a plasma display device known as a thin, lightweight image display device having a large screen.

  A plasma display device using a typical AC surface discharge type panel as a plasma display panel (hereinafter abbreviated as “panel”) has a wide viewing angle and a large screen, and is self-luminous and image display. Due to its high quality, it is becoming the mainstream of large screen image display devices.

  In the panel, a large number of discharge cells are formed between a front plate and a back plate arranged to face each other. In the front plate, a plurality of display electrode pairs each consisting of a pair of scan electrodes and sustain electrodes are formed in parallel with each other on the front glass substrate, and a dielectric layer and a protective layer are formed so as to cover the display electrode pairs. Yes. The back plate has a plurality of parallel data electrodes on the back glass substrate, a dielectric layer so as to cover them, and a plurality of barrier ribs in parallel with the data electrodes formed on the back glass substrate. A phosphor layer is formed on the side walls of the barrier ribs. Then, the front plate and the back plate are arranged opposite to each other so that the display electrode pair and the data electrode are three-dimensionally crossed and sealed, and a discharge gas containing, for example, 5% xenon is enclosed in the internal discharge space. Has been. Here, a discharge cell is formed at a portion where the display electrode pair and the data electrode face each other. The panel is divided into an image display area for displaying an image and other non-display areas, and each electrode is formed by pulling out each electrode to the outside of the image display area on the front plate or the back plate, that is, to the non-display region. Each electrode is driven by applying a drive voltage to the lead portion.

  In the plasma display device using the panel having such a configuration, a sustain pulse is alternately applied to the display electrode pair to generate a gas discharge in each discharge cell, and red, green and blue are generated by ultraviolet rays generated by the gas discharge. A color image is displayed by exciting and emitting phosphors of the respective colors.

  As a method of driving the panel, a subfield method, that is, a method of performing gradation display by combining subfields to emit light after dividing one field period into a plurality of subfields is generally used.

  Each subfield has an initialization period, an address period, and a sustain period. In the initialization period, an initialization discharge is generated, and wall charges necessary for the subsequent address operation are formed on each electrode. In the address period, an address pulse voltage is selectively applied to the discharge cells to be displayed to generate an address discharge to form wall charges. In the sustain period, a sustain pulse is alternately applied to the display electrode pair composed of the scan electrode and the sustain electrode, and a sustain discharge is generated in the discharge cell in which the address discharge is generated, and the phosphor layer of the corresponding discharge cell is caused to emit light. The image is displayed.

  However, as the panel becomes larger and the definition becomes higher, the power for the write operation becomes so large that it cannot be ignored, and the power consumption of the data electrode driving circuit greatly increases the power consumption of the entire plasma display device. The issue has arisen.

Therefore, various methods for reducing the power consumption of the data electrode driving circuit have been proposed. For example, focusing on the fact that the data electrode is a capacitive load when viewed from the drive circuit side, there is a data electrode drive circuit having a so-called power recovery unit that drives the data electrode by resonating the load capacitance and the inductor. It is disclosed (for example, see Patent Document 1). Power consumption can be reduced by using a data electrode driving circuit including such a power recovery unit.
JP 2004-212699 A

  On the other hand, in recent years, the panel has been further increased in screen size. For example, in a panel with a display screen size of 103 inches, the length of the long side is about 2.3 m and the length of the short side is about 1.3 m. To reach. In a plasma display device using such a huge panel, it is difficult to configure each electrode to be driven by a single printed circuit board. For example, a data electrode driving circuit is used for driving a data electrode. A plurality of printed circuit boards mounted separately are required.

  When an electrical connection failure occurs between printed circuit boards on which the data electrode driving circuit is mounted for some reason, it is important to immediately detect the occurrence of the connection failure. Thereby, for example, it is possible to quickly take measures such as safely stopping the plasma display device.

  The present invention has been made to meet such a demand, and in the event that an electrical connection failure occurs between printed circuit boards on which data electrode driving circuits are mounted, plasma that can immediately detect the connection failure. An object is to provide a display device.

  In order to solve this problem, a plasma display apparatus according to the present invention includes a plasma display panel in which a plurality of data electrodes are formed on a back plate, and a write pulse generation that applies a drive voltage to the data electrodes and generates a write pulse. And a data electrode driving circuit having an address pulse output unit for outputting an address pulse output from the address pulse generating unit to the data electrode, and a main board on which the address pulse generating unit of the data electrode driving circuit is mounted. An output board on which a write pulse output unit of the data electrode drive circuit is mounted; a connector disposed on each of the main board and the output board and having a plurality of electrode terminals; and an electrical wiring member for connecting the connectors. And at least one of electrode terminals of a connector on the main board is grounded to the main board. Depending dolphin are electrically opened, characterized in that mounting the connection failure detection circuit for detecting an electrical connection failure between the output board and the main board.

  With this configuration, there is an electrical connection failure between the main board on which the data electrode drive circuit is mounted and the output board, that is, between the main board on which the write pulse generator is mounted and the output board on which the write pulse output unit is mounted. When this occurs, it is possible to provide a plasma display device that can immediately detect the occurrence of the connection failure.

  In the present invention, the electrode terminal of the connector on the output board is connected to the connection failure detection circuit connected to the electrode terminal of the connector on the main board via an electric wiring member, and is connected to the connection fault detection circuit. The output terminal connector electrode terminal is grounded.

  Further, in the plasma display device of the present invention, the connection failure detection circuit includes a plurality of resistors for resistance-dividing the power supply voltage, and a damping inserted in series between the resistance dividing point of the plurality of resistors and the electrode terminal of the connector. A resistor, a backflow preventing diode having an anode connected to the resistance dividing point, and a noise smoothing capacitor having one connected to the resistance dividing point and the other grounded, and a connector on the main board; The plurality of connection failure detection circuits are electrically connected to each other by providing the same number and connecting the cathodes of the backflow prevention diodes to each other. This allows the output potential of the diode to be displaced when a connection failure occurs in any of the connections between the main board and the plurality of output boards, resulting in a connection failure between the main board and the output board. It is possible to provide a plasma display device that can immediately detect the above.

  In the present invention, the connection failure detection circuit includes a resistor having one connected to a power supply voltage, a first capacitor having one connected to the other of the resistors and the other grounded, and the resistor and the first capacitor. A damping resistor inserted in series between the connection point of the connector and the electrode terminal of the connector; and a diode connected in parallel to the damping resistor by connecting an anode to the connection point of the resistor and the first capacitor; A Zener diode having a cathode connected to a connection point between the resistor and the first capacitor, a second capacitor having one connected to the anode of the Zener diode and the other grounded, and an anode connected to the anode of the Zener diode And the same number of connectors on the main board, and the backflow prevention diode is provided. By connecting the cathode of the diode with each other, characterized in that connected a plurality of connection failure detection circuit to each other electrically from each other.

  According to the present invention, when an electrical connection failure occurs between printed circuit boards on which the data electrode driving circuit is mounted, it becomes possible to immediately detect the connection failure.

  Hereinafter, a plasma display device according to an embodiment of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 is an exploded perspective view showing the structure of panel 10 according to Embodiment 1 of the present invention. The front plate 20 has a front substrate 21 made of glass. On the front substrate 21, a plurality of display electrode pairs 24 including scan electrodes 22 and sustain electrodes 23 are formed. A dielectric layer 25 is formed so as to cover the scan electrode 22 and the sustain electrode 23, and a protective layer 26 is formed on the dielectric layer 25.

  The back plate 30 has a back substrate 31 made of glass. A plurality of data electrodes 32 are formed on the back substrate 31, a dielectric layer 33 is formed so as to cover the data electrodes 32, and a grid-like partition wall 34 is formed thereon. A phosphor layer 35 that emits light of each color of red (R), green (G), and blue (B) is provided on the side surface of the partition wall 34 and on the dielectric layer 33.

  The front plate 20 and the back plate 30 are arranged to face each other so that the display electrode pair 24 and the data electrode 32 intersect each other with a minute discharge space interposed therebetween, and the outer peripheral portion thereof is sealed with a sealing material such as glass frit. Has been. In the discharge space, for example, a mixed gas of neon and xenon is enclosed as a discharge gas. The discharge space is partitioned into a plurality of sections by partition walls 34, and discharge cells are formed at the intersections between the display electrode pairs 24 and the data electrodes 32. When these discharge cells discharge and emit light, an image is displayed, and the panel 10 is divided into an image display area for displaying an image and a non-display area other than that.

  Note that the structure of the panel 10 is not limited to the above-described structure, and for example, the panel 10 may include a stripe-shaped partition wall.

  FIG. 2 is an electrode array diagram of panel 10 in accordance with the first exemplary embodiment of the present invention. The panel 10 includes n scan electrodes SC1 to SCn (scan electrode 22 in FIG. 1) and n sustain electrodes SU1 to SUn (FIG. 1) extending in the row direction. 1 sustain electrodes 23) are arranged, and m (in this embodiment, m = 5760) data electrodes D1 to Dm (data electrode 32 in FIG. 1) extending in the column direction are arranged. A discharge cell is formed at a portion where one pair of scan electrode SCi (i = 1 to n) and sustain electrode SUi intersects one data electrode Dj (j = 1 to m), and the discharge cell is in the discharge space. M × n are formed. As shown in FIGS. 1 and 2, scan electrode SCi and sustain electrode SUi are formed in parallel with each other, and therefore, between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn. There is a large interelectrode capacitance Cp.

  FIG. 3 is a circuit block diagram showing the configuration of the plasma display device 1 according to the embodiment of the present invention. In FIG. 3, the plasma display apparatus 1 includes the panel 10, the image signal processing circuit 41, the data electrode drive circuit 42, the scan electrode drive circuit 43, the sustain electrode drive circuit 44, the timing generation circuit 45, And a power supply circuit (not shown) for supplying necessary power to each circuit block.

  The image signal processing circuit 41 described above converts the input image signal sig into image data indicating light emission / non-light emission for each subfield. The timing generation circuit 45 described above generates various timing signals for controlling the operation of each circuit block based on the horizontal synchronization signal H and the vertical synchronization signal V, and supplies them to the respective circuit blocks. Based on the timing signal, scan electrode driving circuit 43 described above generates a sustain pulse during the sustain period, generates a ramp waveform voltage during the initialization period, and generates a scan pulse during the write period, thereby generating each scan electrode SC1. ... SCn is driven. Sustain electrode driving circuit 44 described above generates sustain pulses in the sustain period based on the timing signal to drive sustain electrodes SU1 to SUn. The data electrode driving circuit 42 described above includes an address pulse generator 46 for generating an address pulse in the address period, and an address pulse output unit 47 for outputting an address pulse to be applied to each of the data electrodes D1 to Dm. Based on the timing signal, an address pulse is generated in the address period to drive the data electrodes D1 to Dm.

  Although not shown here, the plasma display device in the present embodiment has a connection failure detection circuit for detecting a connection failure between printed circuit boards on which the data electrode drive circuit 42 is mounted. Although details will be described later, in this embodiment, this connection failure detection circuit is mounted on a printed circuit board on which the write pulse generator 46 is mounted, a printed circuit board on which the write pulse generator 46 is mounted, and a write pulse output When an electrical connection failure occurs between the printed circuit board on which the portion 47 is mounted, the occurrence of the connection failure can be immediately detected.

  Next, details of the data electrode driving circuit 42 will be described.

  FIG. 4 is a circuit diagram showing details of the data electrode driving circuit 42 of the plasma display device 1 according to the embodiment of the present invention. The data electrode drive circuit 42 includes an address pulse generator 46 and an address pulse output unit 47.

  The write pulse generator 46 includes a power recovery unit 48 and a clamp unit 49. The power recovery unit 48 includes a power recovery capacitor C1, switching elements Q1 and Q2, and backflow prevention diodes D1 and D2. The clamp portion 49 includes switching elements Q3 and Q4. Then, the electrode capacitance of the data electrode and the resonance inductor L1 are resonated to recover the power supplied to the data electrode to the power recovery capacitor C1 to generate a write pulse, and the generated write pulse is written. Output to the pulse output unit 47.

  The write pulse output unit 47 includes switch units OUT1 to OUTm that output write pulses to the data electrodes D1 to Dm, respectively. Each of the switch units OUT1 to OUTm includes a switching element QH1 to QHm for outputting an address pulse output from the address pulse generator 46 to the data electrodes D1 to Dm, and a switching element for grounding the data electrodes D1 to Dm. QL1 to QLm. Then, the switching elements are switched based on the timing signal output from the timing generation circuit 45 and the image data output from the image signal processing circuit 41, and the data electrode to which the write pulse output from the write pulse generator 46 is to be applied. Output to.

  In the present invention, the write pulse generator 46 and the write pulse output unit 47 are mounted on separate printed circuit boards, and these printed circuit boards are electrically connected to each other by a connector and an electric wiring member. A data electrode driving circuit for supplying a driving voltage to the data electrodes D1 to Dm is configured.

  As will be described in detail later, a connection failure detection circuit is mounted on a printed circuit board that is a main board on which the write pulse generator 46 is mounted, and a printed circuit board that is the main board on which the write pulse generator 46 is mounted. When an electrical connection failure occurs between the printed circuit board, which is an output board on which the write pulse output unit 47 is mounted, this can be immediately detected.

  Next, a driving voltage waveform for driving panel 10 and its operation will be described with reference to FIG. FIG. 5 is a drive voltage waveform diagram of the plasma display device in accordance with the exemplary embodiment of the present invention. FIG. 5 shows the drive voltage waveforms of two subfields, that is, the drive voltage waveforms of the first subfield (first SF) and the second subfield (second SF). The voltage waveform has almost the same form.

  First, the plasma display device in the present embodiment uses a subfield method as a method for driving panel 10. In this method, one field period is divided into a plurality of subfields, and gradation display is performed by controlling light emission and non-light emission of each discharge cell in each subfield. Each subfield has an initialization period, an address period, and a sustain period.

  In the initializing period, initializing discharge is performed in the discharge cells, and wall charges necessary for the subsequent address operation are formed. In the address period, a scan pulse is sequentially applied to the scan electrodes SC1 to SCn and an address pulse corresponding to an image signal to be displayed is applied to the data electrodes D1 to Dm to perform address discharge, thereby forming a selective wall charge. Do. In the subsequent sustain period, a predetermined number of sustain pulses corresponding to the display luminance to be emitted are applied between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn, and a discharge cell in which wall charges are formed by address discharge is selected. Discharge and emit light.

  In FIG. 5, in the first half of the initialization period of the first SF, 0 (V) is applied to the data electrodes D1 to Dm and the sustain electrodes SU1 to SUn, respectively, and the scan electrodes SC1 to SCn are applied to the sustain electrodes SU1 to SUn. Then, a ramp waveform voltage that gently rises from a voltage Vi1 that is equal to or lower than the discharge start voltage toward a voltage Vi2 that exceeds the discharge start voltage is applied. While this ramp waveform voltage rises, a weak initializing discharge occurs between scan electrodes SC1 to SCn, sustain electrodes SU1 to SUn, and data electrodes D1 to Dm. Negative wall voltage is accumulated on scan electrodes SC1 to SCn, and positive wall voltage is accumulated on data electrodes D1 to Dm and sustain electrodes SU1 to SUn. Here, the wall voltage above the electrode represents a voltage generated by wall charges accumulated on the dielectric layer covering the electrode, the protective layer, the phosphor layer, and the like.

  In the latter half of the initialization period, positive voltage Ve1 is applied to sustain electrodes SU1 to SUn. A scan waveform SC1 to SCn is applied with a ramp waveform voltage that gently decreases from voltage Vi3 that is equal to or lower than the discharge start voltage to voltage Vi4 that exceeds the discharge start voltage with respect to sustain electrodes SU1 to SUn. During this time, weak initializing discharges occur between scan electrodes SC1 to SCn, sustain electrodes SU1 to SUn, and data electrodes D1 to Dm, respectively. Then, the negative wall voltage above scan electrodes SC1 to SCn and the positive wall voltage above sustain electrodes SU1 to SUn are weakened, and the positive wall voltage above data electrodes D1 to Dm is adjusted to a value suitable for the write operation. The

  Thus, the initialization operation ends. In some of the subfields constituting one field, the first half of the initializing period may be omitted. In this case, the discharge cells that have been subjected to the sustain discharge in the immediately preceding subfield may be omitted. Then, the initialization operation is selectively performed. FIG. 5 shows drive voltage waveforms for performing the initialization operation having the first half and the latter half in the initialization period of the first SF, and performing the initialization operation having only the second half in the initialization period of the subfield after the second SF. .

  In the subsequent address period, voltage Ve2 is applied to sustain electrodes SU1 to SUn, and voltage Vc is applied to scan electrodes SC1 to SCn.

  Next, negative scan pulse voltage Va is applied to scan electrode SC1 in the first row. Then, among the switch units OUT1 to OUTm of the address pulse output unit 47, it corresponds to the data electrode Dk of the discharge cell to be lit in the first row (Dk is a data electrode selected based on image data from D1 to Dm). The switching element QHk of the switch part OUTk to be turned on (hereinafter, the operation of turning on the switching element is referred to as “on” and the action of shutting off is referred to as “off”), and the switching elements of the switch parts OUT1 to OUTm excluding the switch part OUTk QL1 to QLm are turned on. As a result, the data electrode Dk of the discharge cell to be lit in the first row and the address pulse generator 46 are electrically connected, and the data electrodes D1 to Dm excluding the data electrode Dk are grounded.

  At the same time, the switching element Q1 of the write pulse generator 46 is turned on. Then, a current begins to flow from the power recovery capacitor C1 to the data electrode Dk via the switching element Q1, the diode D1, the inductor L1, and the switching element QHk corresponding to the data electrode Dk, and the voltage of the data electrode Dk starts to increase. . When the voltage of the data electrode Dk rises to near Vd, the switching element Q3 is turned on. Then, data electrode Dk is clamped to power supply voltage Vd through switching element QHk and switching element Q3. Thus, the voltage difference at the intersection between the data electrode Dk and the scan electrode SC1 is obtained by adding the difference between the wall voltage on the data electrode Dk and the wall voltage on the scan electrode SC1 to the difference between the externally applied voltages (Vd−Va). The discharge start voltage is exceeded. Then, address discharge occurs between data electrode Dk and scan electrode SC1, and between sustain electrode SU1 and scan electrode SC1, positive wall voltage is accumulated on scan electrode SC1, and negative wall is applied on sustain electrode SU1. A voltage is accumulated, and a negative wall voltage is also accumulated on the data electrode Dk.

  Thereafter, the switching element Q3 is turned off and the switching element Q2 is turned on. Then, the charge on the data electrode Dk side starts to flow to the capacitor C1 through the switching element QHk, the inductor L1, the diode D2, and the switching element Q2, and the voltage of the data electrode Dk starts to decrease. As a result, the power supplied to the data electrode Dk is recovered by the power recovery capacitor C1 and used for generation of the next write pulse. Then, when the voltage of the data electrode Dk drops to near 0 (V), the switching element Q4 is turned on. Then, the data electrode Dk is clamped to 0 (V) through the switching element QHk and the switching element Q4. The switching element Q1 is turned off after the switching element Q3 is turned on until the switching element Q2 is turned on, and the switching element Q2 is turned on after the switching element Q4 is turned on. The switching element Q4 is turned off until it is turned on, and the switching element Q4 is turned off immediately before the switching element Q1 is turned on.

  In this way, a positive address pulse is applied to the data electrode Dk, and the address operation in the first row is performed. On the other hand, the voltage at the intersection of the data electrodes D1 to Dm to which the address pulse voltage Vd is not applied and the scan electrode SC1 does not exceed the discharge start voltage, so that address discharge does not occur. The above address operation is performed until the discharge cell in the nth row, and the address period ends.

  In the subsequent sustain period, 0 (V) is applied to sustain electrodes SU1 to SUn, and positive sustain pulse voltage Vs is applied to scan electrodes SC1 to SCn. Then, in the discharge cell in which the address discharge has occurred, the voltage difference between scan electrode SCi and sustain electrode SUi is the sum of sustain pulse voltage Vs and the difference between the wall voltage on scan electrode SCi and the wall voltage on sustain electrode SUi. The discharge start voltage is exceeded. Then, a sustain discharge occurs between scan electrode SCi and sustain electrode SUi, and phosphor layer 35 emits light by the ultraviolet rays generated at this time.

  As a result of this discharge, negative wall voltage is accumulated on scan electrode SCi, and positive wall voltage is accumulated on sustain electrode SUi. Further, a positive wall voltage is accumulated on the data electrode Dk. In the discharge cells in which no address discharge has occurred during the address period, no sustain discharge occurs, and the wall voltage at the end of the initialization period is maintained.

  Subsequently, 0 (V) is applied to scan electrodes SC1 to SCn, and positive sustain pulse voltage Vs is applied to sustain electrodes SU1 to SUn. Then, in the discharge cell in which the sustain discharge has occurred, the voltage difference between the sustain electrode SUi and the scan electrode SCi exceeds the discharge start voltage, so that the sustain discharge occurs again between the sustain electrode SUi and the scan electrode SCi. A negative wall voltage is accumulated on SUi, and a positive wall voltage is accumulated on scan electrode SCi.

  Thereafter, similarly, the number of sustain pulses corresponding to the luminance weight is alternately applied to scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn, and a potential difference is given between the electrodes of display electrode pair 24, thereby writing in the write period. The sustain discharge is continuously performed in the discharge cell that has caused the discharge.

  At the end of the sustain period, a so-called narrow pulse-like potential difference is applied between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn, and the positive wall voltage on data electrode Dk is left while scanning. The wall voltage on electrode SCi and sustain electrode SUi is reduced. Thus, the maintenance operation in the maintenance period is completed.

  By the way, in order to stably generate the address discharge in the discharge cells to emit light during the address period, the address pulse having a steep shape with an amplitude of usually several hundreds (V) or more and a rise time of 1 μsec or less is used as data. It is necessary to apply to the electrode Dk. For this reason, a large current instantaneously flows through the panel 10, but this current increases in proportion to the area of the display screen. For example, when address discharge is generated in most of all the discharge cells, in a panel having a display screen size of 50 inches, a current exceeding 100 (A) in total is instantaneously applied to the data electrodes D1 to Dm. However, in the large panel 10 having a display screen size of 103 inches, the sum of the currents flowing through the data electrodes D1 to Dm instantaneously exceeds 400 (A). Further, in a large panel such as 103 inches, the data electrodes D1 to Dm are configured to be divided into a plurality of, for example, four, and driven. In such a case, a printed circuit board on which the write pulse generator 46 is mounted and A current exceeding 100 (A) instantaneously flows between the printed circuit board on which the write pulse output unit 47 is mounted. Therefore, it is important that the electrical connection between the printed circuit board on which the write pulse generation unit 46 is mounted and the printed circuit board on which the write pulse output unit 47 is mounted is reliable. In such a case, for example, after the plasma display device is safely stopped, it is necessary to promptly take measures such as correctly reconnecting the location where the connection failure has occurred.

  In the present invention, the connection failure detection circuit is mounted on the printed circuit board on which the write pulse generator 46 is mounted, so that the printed circuit board on which the write pulse generator 46 is mounted and the printed circuit board on which the write pulse output unit 47 is mounted. The present invention is characterized in that it can be immediately detected when an electrical connection failure occurs.

  FIG. 6 is a plan view showing an example of an arrangement of a printed circuit board on which each drive circuit of the plasma display device according to one embodiment of the present invention is mounted.

  In the present embodiment, as shown in FIG. 6, the scan electrode drive circuit 43 is configured to be divided and mounted on three scan electrode drive print substrates 431. Further, the sustain electrode drive circuit 44 is configured to be divided and mounted on three printed circuit boards 441 for driving the sustain electrodes.

  In addition, the data electrode drive circuit 42 has the write pulse generator 46 mounted on each of the four printed circuit boards 461 for generating the write pulse, which are the main boards, and outputs the switch units OUT1 to OUTm constituting the write pulse output unit 47. The substrate is divided and mounted on 12 printed circuit boards 471 for writing pulse output. Note that the arrangement example shown in FIG. 6 is merely an example, and the number of printed circuit boards, the configuration of a drive circuit mounted on each printed circuit board, and the like may be changed as appropriate according to the specifications of the plasma display device.

  Further, the scanning electrode driving printed circuit board 431 includes a connector 432 for electrically connecting the scanning electrode driving printed circuit boards 431 to each other and a flexible wiring board connected to the scanning electrodes SC1 to SCn of the panel 10 (hereinafter referred to as the scanning electrode driving printed circuit boards 431). , And a connector 433 for connecting 50), and the drive voltage output from the scan electrode drive circuit 43 is sent to each scan via the connector 433 and the FPC 50 connected to the connector 433. Applied to the electrodes SC1 to SCn.

  The sustain electrode driving printed circuit board 441 includes a connector 442 for electrically connecting the sustain electrode driving printed circuit boards 441 to each other, and a connector 443 for connecting the FPC 50 connected to the sustain electrodes of the panel 10. The drive voltage output from the sustain electrode drive circuit 44 is applied to each of the sustain electrodes SU1 to SUn via the connector 443 and the FPC 50 connected to the connector 443.

  Further, the write pulse generation printed circuit board 461 and the write pulse output print circuit board 471 are bridge connectors that are connectors for electrically connecting the write pulse generation print circuit board 461 and the write pulse output print circuit board 471 to each other. 462 and 472 are installed. At this time, three bridge connectors 462 are mounted on the write pulse generation printed circuit board 461 so that one write pulse generation print circuit board 461 is connected to the three write pulse output print circuit boards 471. One bridge connector 472 is mounted on the write pulse output printed circuit board 471.

  In addition, the write pulse output printed circuit board 471 is equipped with a connector 473 for connecting the FPC 50 connected to the data electrode of the panel 10, whereby the drive voltage output from the write pulse generator 46 is This is applied to the data electrode Dk via the write pulse output printed circuit board 471 and the FPC 50 which are output boards on which the write pulse output unit 47 is mounted.

  Further, in the present embodiment, a bridge connector 474 for electrically connecting adjacent printed pulse output printed circuit boards 471 to each other is mounted, and adjacent written pulse output printed circuit boards 471 are connected to each other via the bridge connector 474. Are connected so that the current flowing during the write operation is dispersed as much as possible.

  Here, although not shown in FIG. 6, the connectors are electrically connected by electrical wiring members.

  FIG. 7 shows how the write pulse generation printed circuit board 461 and the write pulse output printed circuit board 471 are connected.

  As described above, in the case of the large panel 10 having a display screen size of 103 inches, when the address discharge is generated in the majority of all the discharge cells, the sum of the currents flowing through the data electrodes D1 to Dm is: It becomes very large instantaneously exceeding 400 (A). Therefore, in the configuration in which power is supplied from the four write pulse generation printed circuit boards 461 to the data electrodes D1 to Dm via the 12 write pulse output print circuit boards 471, the write pulse generation printed circuit board 461 and the write pulse output Current exceeding 100 (A) at the maximum flows instantaneously between the printed circuit board 471. Therefore, in the present embodiment, the harness 51 that is an electric wiring member capable of flowing a large current is used for connection between the write pulse generation printed circuit board 461 and the write pulse output printed circuit board 471. Further, the write pulse output printed boards 471 are electrically connected to each other by connecting the bridge connectors 474 to each other by the FPC 52.

  FIG. 8 is a schematic diagram showing how the power output from the write pulse generator 46 is supplied in the plasma display device according to the present embodiment.

  As indicated by the broken line in FIG. 8, the power output from the write pulse generator 46 during the write operation is transmitted from the write pulse generating printed circuit board 461 to each bridge connector 462 mounted on the write pulse generating printed circuit board 461 and each of the bridge connectors 462. It is supplied to each of the write pulse output printed circuit boards 471 via the harness 51, and further supplied to the data electrode via the switching element of the switch part constituting the write pulse output part 47.

  At this time, in this embodiment, the write pulse output printed circuit boards 471 are electrically connected to each other by the FPC 52, so that a current also flows between the write pulse output printed circuit boards 471 through the FPC 52. Therefore, in the present embodiment, not only the harness 51 that connects the write pulse generation printed circuit board 461 and each write pulse generation printed circuit board 461, but also the adjacent write pulse generation printed circuit board generates a large current generated in the write period. The current path can be distributed and flowed from the write pulse generation unit 46 to the write pulse output unit 47 via the FPC 52 that connects the 461s. For example, even when power must be supplied concentratedly to the write pulse output unit 47 mounted on a certain write pulse output printed board 471, it is connected to the write pulse output printed board 471. Not only the harness 51 but also the adjacent write pulse output printed circuit board 471 and the harness 51 connected to the write pulse output printed circuit board 471 are used to supply the necessary power to the write pulse output printed circuit board 471. be able to. As a result, the current flowing during the write operation can be dispersed, the impedance in the path to which the write pulse is supplied can be reduced, and the heat generated by Joule heat and the power consumed ineffectively can be reduced.

  Therefore, the corresponding bridge connectors 462 and 472 are securely connected by the harness 51, and the corresponding bridge connectors 474 are securely connected by the FPC 52, so that the write pulse generating printed circuit board 461 and the write pulse output printed circuit board 471 are connected. It is important that the electrical connection between the printed circuit boards is ensured.

  In the present invention, a connection failure detection circuit 53 for detecting a connection failure between the write pulse generation printed circuit board 461 and the write pulse output print circuit board 471 is mounted on the write pulse generation printed circuit board 461, and a solid line in FIG. As shown in FIG. 5, the connection failure detection circuit 53 is electrically connected to one of the electrode terminals of the bridge connector 462 on the write pulse generating printed board 461, and the write pulse output printed board 471 corresponding to the electrode terminal is connected. The electrode terminal of the bridge connector 472 is grounded. As a result, for example, when an electrical connection failure occurs between the write pulse generation printed circuit board 461 and the write pulse output print circuit board 471 due to, for example, the harness 51 being disconnected from the bridge connector 462, this is immediately detected. It becomes possible to do. Next, this configuration will be described.

  FIG. 9 is a circuit diagram showing an example of the connection failure detection circuit 53 according to the embodiment of the present invention.

  As shown in FIG. 9, in the write pulse generation printed circuit board 461, each bridge connector 462 connects one of its electrode terminals to the connection failure detection circuit 53 and connects the remaining electrode terminals to the write pulse generation unit 46. To do. In the write pulse output printed circuit board 471, the bridge connector 472 grounds the electrode terminal connected to the connection failure detection circuit 53 via the harness 51 and connects the remaining electrode terminals to the write pulse output unit 47. To the bridge connector 474. The corresponding bridge connectors 462 and 472 are connected to each other by the harness 51 and the corresponding bridge connectors 474 are connected to each other by the FPC 52. As a result, the printed circuit boards are electrically connected to each other, and the write pulse output from the write pulse generator 46 is supplied to the write pulse output unit 47 on the write pulse output printed circuit board 471 by distributing the current path. In addition, a ground potential is input to the connection failure detection circuit 53.

  The connection failure detection circuit 53 has resistances R10a and R20a that resistance-divide the power supply voltage V1 and a resistance value that is very small compared to the resistance R10a, and one of them is connected to a resistance dividing point of the resistors R10a and R20a for noise reduction damping. A resistor R30a, a noise-smoothing capacitor C10a having one connected to the resistance dividing point of the resistors R10a and R20a and the other grounded, and a backflow preventing diode D10a having the anode connected to the resistance dividing point of the resistors R10a and R20a Have. The other end of the damping resistor R30a is one of the input terminals of the connection failure detection circuit 53, and is connected to one of the electrode terminals of the bridge connector 462 described above.

  Further, the connection failure detection circuit 53 is a circuit having the same configuration as described above, including resistance dividing resistors R10b and R20b, a damping resistor R30b, a noise smoothing capacitor C10b, and a backflow preventing diode D10b. And a circuit having the same configuration as described above, including a resistor R10c, R20c for resistance division, a damping resistor R30c, a capacitor C10c for smoothing noise, and a diode D10c for preventing backflow, and the damping resistors R30b, R30c Are connected to one of the electrode terminals of the remaining bridge connector 462, respectively. The cathodes of the diodes D10a, D10b, and D10c are connected to each other to serve as the output terminal of the connection failure detection circuit 53, and are grounded, for example, via a pull-down resistor R40.

  In the connection failure detection circuit 53 having such a configuration, if the bridge connectors 462 and 472 corresponding to the respective harnesses 51 are normally connected to each other, the resistance dividing points of the resistors R10a and R20a and the resistors of the resistors R10b and R20b are used. As shown in FIG. 9, the dividing points and the resistance dividing points of the resistors R10c and R20c are grounded via the damping resistors R30a, R30b, and R30c. Therefore, the anodes of the diodes D10a, D10b, and D10c are very low in accordance with the ground potential. The potential of the connection failure detection circuit 53 is “data Lo” (here, a potential substantially equal to the ground potential).

  On the other hand, when a connection failure such as the harness 51 being disconnected from the corresponding bridge connector 462, 472 occurs in one of the harnesses 51, one of the electrode terminals connected to the connection failure detection circuit 53 is electrically opened. It becomes a state. For example, when the harness 51 shown at the top in the drawing causes a connection failure, the electrode terminal connected to the damping resistor R30a is in an electrically open state. As a result, the anode potential of the diode D10a becomes a potential obtained by dividing the power supply voltage V1 by the resistors R10a and R20a, and the cathode potential becomes a potential based on the anode potential. At this time, the resistance dividing points of the resistors R10b and R20b and the resistance dividing points of the resistors R10c and R20c remain grounded via the damping resistors R30b and R30c, but the diodes D10a and D10c are operated by the backflow preventing diodes D10b and D10c. The cathode potential is never lowered. The output signal of the connection failure detection circuit 53 becomes “data Hi” (a potential based on a potential obtained by dividing the power supply voltage V1 by the resistors R10a and R20a).

  As described above, in the present embodiment, if all the harnesses 51 are correctly connected to the corresponding bridge connectors 462 and 472, “data Lo” is output from the connection failure detection circuit 53. If a connection failure occurs, “data Hi” is immediately output from the connection failure detection circuit 53, so that when a connection failure relating to the harness 51 occurs, it can be immediately detected. Therefore, for example, by connecting the output signal of the connection failure detection circuit 53 to the microcomputer that controls the operation of the plasma display device and using it for controlling the operation of the entire device, the connection failure relating to the harness 51 can be prevented. When it occurs, it is possible to take measures such as stopping the plasma display device safely and promptly.

  In this embodiment, the power supply voltage V1 is 5 (V), the resistors R10a, R10b, and R10c are 2.2 kΩ, the resistors R20a, R20b, and R20c are 22 kΩ, the damping resistors R30a, R30b, and R30c are 220Ω, the capacitor C10a, C10b and C10c are set to 0.1 μF, and “Data Hi” is set to about 3.3 (V). However, these values are merely examples, and are optimum values according to the specifications of the plasma display device. It is desirable to set to.

  FIG. 10 is a circuit diagram showing another example of the connection failure detection circuit 53 of the present invention. In FIG. 10, only the connection failure detection circuit corresponding to one bridge connector 462 is shown.

  As shown in FIG. 10, the connection failure detection circuit 53 in the present embodiment is a resistor R11 having one connected to the power supply voltage V2, and a first capacitor having one connected to the other of the resistor R11 and the other grounded. The noise smoothing capacitor C11 has a very small resistance value compared to the resistor R11, one of which is a noise reducing damping resistor R31 connected to the connection point between the resistor R11 and the capacitor C11, and the anode of the resistor R11 and the capacitor C11. And a diode D31 connected in parallel to the resistor R31, a Zener diode D21 having a cathode connected to the connection point of the resistor R11 and the capacitor C11, one connected to the anode of the Zener diode D21 and the other. A noise-smoothing capacitor C21, which is a grounded second capacitor, and a Zener for the anode And a diode D11 for connecting backflow prevention to the anode of the diode D21. The connection point between the damping resistor R31 and the cathode of the diode D31 becomes one of the input terminals of the connection failure detection circuit 53, and is connected to one of the electrode terminals of the bridge connector 462 described above.

  Although not shown here, the connection failure detection circuit 53 is provided with the same number of circuits having the same configuration as that described above as the bridge connector 462. The cathodes of the backflow prevention diode D11 are connected to each other to serve as an output terminal of the connection failure detection circuit 53, and are grounded, for example, via a pull-down resistor R40.

  In the connection failure detection circuit 53 having such a configuration, if all the harnesses 51 are normally connected, the connection point between the resistor R11 and the capacitor C11 is as shown in FIG. 10 with the damping resistor R31 and the diode D31. Therefore, the cathode of the Zener diode D21 is at a very low potential corresponding to the ground potential. Therefore, the anode of the diode D11 is substantially equal to the ground potential, and the output signal of the connection failure detection circuit 53 is “data Lo”.

  At this time, noise at the anode of the diode D11 can be greatly reduced by the action of the damping resistor R31, the diode D31, the capacitor C11, the Zener diode D21, and the capacitor C21. Specifically, when noise that shifts from the ground potential to a positive potential is mixed in the electrode terminal, the positive energy due to the noise is charged to the capacitor C11 via the damping resistor R31, and is negative from the ground potential. In the case where noise that shifts to the electric potential is mixed into the electrode terminal, positive energy that cancels the negative energy is output from the capacitor C11 and supplied to the electrode terminal via the diode D31. Thereby, noise at the connection point between the resistor R11 and the capacitor C11 is reduced. Furthermore, in the anode of the diode D11, the minute noise remaining at the connection point between the resistor R11 and the capacitor C11 is cut off by the action of the Zener diode D21, and the noise is smoothed by the action of the capacitor C21. Noise is reduced. As a result, a signal (data Lo) with greatly reduced noise is output from the output terminal of the connection failure detection circuit 53.

  On the other hand, when the harness 51 causes a connection failure, the parallel circuit of the damping resistor R31 and the diode D31 is electrically opened. As a result, the potential at the connection point between the resistor R11 and the capacitor C11 rises, the Zener diode D21 becomes conductive, and the output signal of the connection failure detection circuit 53 becomes “data Hi”.

  As described above, in the present embodiment, if all the harnesses 51 are correctly connected to the corresponding bridge connectors 462 and 472, “data Lo” is output from the connection failure detection circuit 53, and the harness 51 If a connection failure occurs in any of them, “data Hi” is immediately output from the connection failure detection circuit 53. In addition, since the circuit for reducing noise is added to the connection failure detection circuit 53 as described above, the connection failure of the harness 51 can be detected while greatly reducing the influence of noise. .

  In this embodiment, the power supply voltage V2 is 15 (V), the resistor R11 is 4.7 kΩ, the damping resistor R31 is 330Ω, the capacitor C11 is 1 μF, the capacitor C21 is 1 μF, and the Zener diode D21 has a Zener voltage Vz of 5. 8 (V) and “Data Hi” is about 3.3 (V), but these values are merely examples, and are set to optimum values according to the specifications of the plasma display device. It is desirable.

  In the embodiment of the present invention, the configuration in which “data Hi” is output from the connection failure detection circuit when a connection failure related to the harness 51 is detected has been described. However, the polarity of the signal output from the connection failure detection circuit is It can also be configured to be reversed. Further, the connection failure detection circuit is not limited to the configuration shown in FIGS. 9 and 10, and the same operation may be performed using other configurations.

  As described above, according to the present invention, when an electrical connection failure occurs between the printed circuit boards on which the data electrode driving circuit is mounted, the connection failure can be detected immediately. It is an invention useful for enhancing the properties.

The disassembled perspective view which shows the structure of the panel in Embodiment 1 of this invention. Electrode arrangement of the panel The circuit block diagram which shows the structure of the plasma display apparatus in one embodiment of this invention Circuit diagram showing details of data electrode drive circuit of same plasma display device Driving voltage waveform diagram of the plasma display device The top view which shows an example of arrangement | positioning of the printed circuit board carrying each electrode drive circuit of the plasma display apparatus Schematic showing the connection state between the printed pulse generation printed circuit board and the write pulse output printed circuit board of the plasma display device Schematic showing a state of supply of power output from the write pulse generator of the plasma display device Circuit diagram showing an example of a connection failure detection circuit of the plasma display device Circuit diagram showing another example of connection failure detection circuit

Explanation of symbols

10 Panel (Plasma Display Panel)
22 Scan Electrode 23 Sustain Electrode 32 Data Electrode 42 Data Electrode Drive Circuit 46 Write Pulse Generator 47 Write Pulse Output 53 Connection Failure Detection Circuit 461 Write Pulse Generation Printed Circuit Board 471 Write Pulse Output Printed Circuit Board 462, 472 Bridge Connector 51 Harness SC1 to SCn Scan electrode SU1 to SUn Sustain electrode D1 to Dm Data electrode OUT1 to OUTm Switch part D10a to D10c, D11, D31 Diode D21 Zener diode R10a to R10c, R11, R20a to R20c, R30a to R30c, R31, R40 Resistor C10a ~ C10c, C11, C21 capacitors

Claims (4)

A plasma display panel having a plurality of data electrodes formed on a back plate;
A data electrode drive circuit comprising: an address pulse generator for applying a drive voltage to the data electrode and generating an address pulse; and an address pulse output unit for outputting the address pulse output from the address pulse generator to the data electrode; ,
A main board on which the write pulse generator of the data electrode drive circuit is mounted; an output board on which the write pulse output unit of the data electrode drive circuit is mounted; and a plurality of electrode terminals disposed on each of the main board and the output board And an electrical wiring member for connecting between the connectors,
Connection failure detection for detecting an electrical connection failure between the main substrate and the output substrate depending on whether at least one of the electrode terminals of the connector on the main substrate is grounded or electrically open to the main substrate A plasma display device comprising a circuit. A connection failure detection circuit connected to the electrode terminal of the connector on the main board is connected to an electrode terminal of the connector on the output board via an electric wiring member, and a connector of the output board connected to the connection failure detection circuit The plasma display device according to claim 1, wherein the electrode terminal is grounded. The connection failure detection circuit includes a plurality of resistors for dividing a power supply voltage, a damping resistor inserted in series between a resistance dividing point of the plurality of resistors and a connector electrode terminal, and an anode at the resistance dividing point. A backflow prevention diode connected and a noise smoothing capacitor having one connected to the resistance dividing point and the other grounded, and provided in the same number as the connector on the main board, and the backflow prevention diode 2. The plasma display device according to claim 1, wherein a plurality of connection failure detection circuits are electrically connected to each other by connecting the cathodes of each other. The connection failure detection circuit includes a resistor having one connected to a power supply voltage, a first capacitor having one connected to the other of the resistors and the other grounded, a connection point between the resistor and the first capacitor, and a connector A damping resistor inserted in series between the electrode terminal, a diode connected in parallel to the damping resistor with an anode connected to a connection point of the resistor and the first capacitor, the resistor and the first A Zener diode having a cathode connected to the connection point of the capacitor, a second capacitor having one connected to the anode of the Zener diode and the other grounded, and a backflow preventing diode having an anode connected to the anode of the Zener diode The same number of connectors as the connectors on the main board are provided, and the cathodes of the backflow preventing diodes are mutually connected. The plasma display apparatus of claim 1, wherein the connected plurality of connection failure detection circuit to each other electrically from each other by connecting to.

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