JP2008078578A - Semiconductor device, compound semiconductor substrate, and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a compound semiconductor substrate exhibiting broader physical properties that cannot be obtained by only a thermodynamically stable material system using a combination of a metastable material system and the thermodynamically stable high quality-crystal. <P>SOLUTION: The system is provided with a first conductive type clad layer 12, a first conductive type light guide layer 13, an active layer 16 having a light emitting layer 14 consisting of the metastable material system crystal, a second conductive type light guide layer 17, and a second conductive type cladding layer 21 each formed of chemical semiconductor layer are sequentially laminated on a substrate 11, and a bonding layer 18 to which a bonded surface 18a that divides an upper/lower layer formed in a non-light emitting region 20 between an upper surface of the light emitting layer 14 positioned at the uppermost side inside the active layer 16 and a lower surface of the second conductive type cladding layer 17 or between a lower surface of the light emitting layer 14 positioned at the lowermost side inside the active layer 16 and an upper surface of the first conductive type cladding layer 12 is bonded through a quantum dot 19 that does not continue in the inplane direction. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a compound semiconductor substrate including a metastable material system and a manufacturing method thereof, and more particularly to a compound semiconductor substrate in which a metastable material system is heterojunctioned by temperature or strain and a manufacturing method thereof. The present invention also relates to a semiconductor device manufactured using the compound semiconductor substrate.

  Attempts are being made to apply new material systems to semiconductor devices to achieve unprecedented or unfeasible characteristics. For example, attempts have been made to form InAs-based quantum dots on a GaAs substrate and apply them to the active layer of a laser. Attempts have also been made to form a GaInNAs-based material on a GaAs substrate or to form a green or red laser by forming GaInN having a high In composition on a GaN substrate. The material forming these active layers is a thermodynamically unstable metastable material system in which the lattice mismatch between the substrate and the laminated region is large or the material of the composition of the immiscible region is heated. This greatly changes the characteristics. However, since the physical properties are significantly different from the material systems that have been put to practical use, there is a possibility that an optical semiconductor device or an electronic device having characteristics that could not be achieved before can be realized. Therefore, there is a demand for a semiconductor device using this compound semiconductor substrate.

  In forming a semiconductor device using such a metastable material system, there are two structural characteristics. The first characteristic is that when a semiconductor device is configured using a heterojunction, it is desirable that the formation temperature of the semiconductor around the metastable material system be high. The metastable material system is formed by uniformly mixing a thermodynamically immiscible material system at a low temperature. In this temperature range, the mobility of elements constituting the material crystal on the crystal surface is suppressed. Crystals formed in such a temperature range have incomplete crystallinity. The material system used adjacent to or coexisting with the metastable material having incomplete crystallinity must be formed at the same temperature, resulting in incomplete characteristics of the entire crystal and sufficient characteristics as a semiconductor device. Can't get.

  The second characteristic is that, in the case of a metastable material system that forms a material system with large lattice irregularities on the crystal surface, the upper side of the crystal is spatially open at the formation stage, so that it is only on the lower side of the material. Although it is strained, strain is applied three-dimensionally when it is embedded in the crystal, so that the amount of strain received by the metastable material system is larger than that in the crystal formation stage. In addition, when the formation temperature of the metastable material system and the formation temperature of the material (peripheral material) formed on the metastable material system are different, the metastable material may differ depending on the difference in thermal expansion coefficient between the metastable material system and the peripheral material. In some cases, the strain may be larger than when the system was formed.

  Conventionally, in the manufacture of semiconductor devices, wafers are often joined to join dissimilar materials (see, for example, Patent Document 1). In Patent Document 1, a semiconductor layer including a light emitting layer is sequentially formed on a first substrate that is opaque with respect to the emission wavelength, and then a second substrate that is transparent with respect to the emission wavelength is bonded to the first substrate. A method of manufacturing a light emitting diode having a structure in which is removed in a predetermined shape is disclosed. In order to improve the external emission efficiency without reducing the internal light emission efficiency and to obtain a light emitting diode having sufficient intensity, the light emission layer is formed on the first substrate opaque to the light emission wavelength, and then the light emission A second substrate transparent to the wavelength is attached. However, this patent document 1 does not form a heterojunction with a material that can be formed only at high temperatures on both sides of a metastable material.

Japanese Patent No. 3230638

  As described above, in the case of a thermodynamically metastable material system that is in a thermodynamically immiscible region or has a large lattice irregularity, the state formed at a low temperature is maintained by some method. It is necessary to suppress the increase in the amount of strain while embedding a material having a large lattice irregularity. In such a crystal, after forming the metastable material system, if the crystal of the buried region is further grown, or if the process temperature is raised to a temperature necessary for forming the buried region at that time, spinodal decomposition occurs. Or cause strain relaxation due to plastic deformation, leading to a decrease in crystallinity.

  In order to avoid such a problem, after forming the metastable material system, a buried layer is formed without greatly increasing the temperature, and after the buried layer is formed, annealing is performed for a short time, or a layer made of the metastable material system is used. Use a material that can be formed at a low temperature as a layer to be layered after formation (hereinafter referred to as a metastable layer), or reduce the thickness of the layer after forming the metastable layer to suppress the amount of strain applied to the metastable layer. is doing.

  However, even if the buried layer is formed at a low temperature after the metastable layer is formed and annealed, the crystallinity cannot be completely recovered, and in particular, the amount of impurities added unevenly cannot be suppressed. There was a problem. Further, when a device is configured by depositing only a material that can be formed at a low temperature after the metastable layer is formed, there is a problem that a device structure cannot be freely designed and sufficient device characteristics cannot be obtained. Furthermore, when the thickness of the layer deposited after forming the metastable layer is reduced, there is a problem that it is difficult to realize sufficient characteristics due to restrictions on device design.

  The present invention has been made in view of the above, and after forming the metastable material system, high-quality crystals can be freely formed on both sides of the metastable material system without greatly changing the characteristics of the metastable material system. An object of the present invention is to provide a compound semiconductor substrate having a structure formed in (1) and a method for manufacturing the same. It is another object of the present invention to provide a semiconductor device using the compound semiconductor substrate.

  In order to solve the above-described problems and achieve the object, the present invention provides a first conductivity type cladding layer, a first conductivity type light guide layer, and a metastable material-based crystal, each formed on a substrate by a compound semiconductor. An active layer having a light emitting layer, a second conductivity type light guide layer, and a second conductivity type clad layer are laminated in order, and the upper surface of the light emitting layer located on the uppermost side in the active layer, Upper and lower portions formed in a non-light emitting region between the lower surface of the second conductivity type cladding layer or between the lower surface of the light emitting layer located at the lowest side in the active layer and the upper surface of the first conductivity type cladding layer A compound semiconductor substrate provided with a bonding layer bonded via a dot-shaped protrusion made of a compound semiconductor whose bonding surface is divided in the in-plane direction, and a first conductivity type on the first conductivity type cladding layer Supply the carrier and the second Conductivity type cladding layer on the second conductivity type first and second electrode for supplying carriers, characterized in that it comprises a.

  The present invention also provides a first conductive type cladding layer, a first conductive type light guide layer, and an active layer having a light emitting layer made of a metastable material-based crystal, each of which is formed of a compound semiconductor layer on a substrate, A conductive light guide layer and a second conductive clad layer are sequentially stacked, and between the upper surface of the uppermost light emitting layer in the active layer and the lower surface of the second conductive clad layer Or a bonding surface that divides the upper and lower layers formed in the non-light-emitting region between the lower surface of the light emitting layer located at the lowest side in the active layer and the upper surface of the first conductivity type cladding layer is in-plane It is characterized by comprising a bonding layer bonded through dot-shaped projections made of a compound semiconductor that is not continuous in the direction.

  Further, according to the present invention, a first conductivity type cladding layer and a first conductivity type light guide layer each made of a compound semiconductor are formed on a first substrate at a first temperature at which the compound semiconductor grows. And an active layer including a light-emitting layer made of a metastable material crystal made of a compound semiconductor, a lower second conductive light guide layer, and dots that are not continuous in the in-plane direction on the first conductive light guide layer A second step of forming a protrusion at a second temperature lower than the first temperature within a range in which the light emitting layer maintains a metastable state, and a compound semiconductor on the second substrate, respectively. A second step of forming a second conductive type cladding layer and an upper second conductive type light guide layer at a third temperature higher than the second temperature, and the lower second type on the first substrate. Conductive light guide layer and the second substrate The upper second-conductivity-type light guide layer is bonded through the dot-shaped protrusions, and pressure is applied to the substrate surfaces of the first and second substrates to keep the light-emitting layer in a metastable state. And a fourth step of heat-treating at a fourth temperature lower than the first and third temperatures in a range, and a fifth step of removing the second substrate.

  According to the present invention, a semiconductor heterojunction in which a material having an immiscible composition and a metastable material system in which lattice imperfection exceeds a thermodynamic critical strain amount and a material system in which high-quality crystals are difficult to grow without high temperature coexist are formed. Can be formed. As a result, there is an effect that it is possible to realize a high-quality crystalline compound semiconductor substrate combined with a material system that has not been obtained conventionally and a semiconductor device using the substrate.

  Exemplary embodiments of a semiconductor device, a compound semiconductor substrate, and a method for manufacturing the same according to the present invention will be explained below in detail with reference to the accompanying drawings. It should be noted that the present invention is not limited by these embodiments, and various modifications can be used. Further, the cross-sectional views of the compound semiconductor substrate and the semiconductor device used in the following embodiments are schematic, and the relationship between the thickness and width of the layers, the ratio of the thicknesses of the layers, and the like are different from the actual ones. Further, the compound semiconductor substrate in this specification is a metastable material system that is a thermodynamically unstable material in which the lattice mismatch between the substrate and the laminated region is large or the material of the composition of the immiscible region. As long as a structure in which a plurality of compound semiconductor layers including an active layer are stacked is formed on a substrate, the substrate may be a compound semiconductor substrate or a substrate other than a compound semiconductor substrate such as sapphire. .

(First embodiment)
FIG. 1 is a cross-sectional view schematically showing an example of the configuration of the compound semiconductor substrate according to the first embodiment of the present invention. This compound semiconductor substrate includes an N-type GaAs substrate 11, a lower cladding layer 12 made of an N-type AlGaAs layer, a lower light guide layer 13 made of an N-type GaAs layer, and a GaInAs layer that is not lattice-matched with the GaAs substrate 11. An active layer 16 having a structure in which the upper and lower light emitting layers 14 are sandwiched between barrier layers 15 made of GaAs layers, an upper light guide layer 17 made of a P-type GaAs layer, an upper cladding layer 21 made of a P-type AlGaAs layer, A contact layer 22 made of a P-type GaAs layer is stacked. Here, in the non-light emitting region 20 (here, corresponding to the upper light guide layer 17) between the uppermost light emitting layer 14 and the upper cladding layer 21, a bonding surface 18a is formed, and between the bonding surfaces 18a. The bonding layer 18 is formed by bonding the InAs quantum dots (hereinafter referred to as InAs dots) 19 formed together. In the example of FIG. 1, the first upper light guide layer 17-1 is formed on the active layer 16 including the metastable material system and has a thickness that does not cause lattice defects, and another substrate (not shown). The formed second upper light guide layer 17-2 has a configuration in which either or each of the upper light guide layers 17-2 is bonded with the InAs dots 19 formed on the upper surface of the second upper light guide layer 17-2 in accordance with the plane orientation. Here, the InAs dots 19 correspond to the dot-like projections in the claims.

  The bonding surface 18 a is formed in a non-light emitting region 20 composed of a layer having a larger band gap than the light emitting layer 14 between the upper surface of the uppermost light emitting layer 14 in the active layer 16 and the lower surface of the upper cladding layer 21. It only has to be.

  In the example of FIG. 1, InAs dots formed between the first light guide layer and the second light guide layer on the active layer are pressed and diffused at the time of bonding. In particular, In is a GaAs film. The inside diffuses very well, and the entire distortion across the InAs dots is alleviated. That is, after the formation of the active layer 16, the contact layer 22 and the upper cladding layer 21 formed on the first upper light guide layer 17-1 via the InAs dots 19 and the second upper light guide layer 17-2. Is relaxed by the InAs dots, and the influence on the active layer 16 below the bonding layer 18 is suppressed.

FIG. 2 is a cross-sectional view schematically showing an example of the configuration of a semiconductor device manufactured using such a compound semiconductor substrate. In the example of FIG. 2, the case of an edge emitting semiconductor laser is illustrated. This semiconductor device has a structure having a current confinement region whose width is narrowed in the vicinity of the in-plane center of the contact layer 22 and the upper cladding layer 21 of the compound semiconductor substrate of FIG. That is, the upper cladding layer 21 has a convex structure in the vicinity of the in-plane center. A passivation film 24 made of a SiO ₂ film is formed on the side surfaces of the upper clad layer 21 and the contact layer 22 where the convex current confinement region is formed and on the upper surface of the upper clad layer 21, and on the passivation film 24, a contact is formed. A polymer buried layer 25 is formed so as to have the same height as the surface of the layer 22. A P-type electrode 26 is formed on the entire upper surface on the contact layer 22 side, and an N-type electrode 23 is formed on the entire lower surface of the GaAs substrate 11. A semiconductor device that can operate as a semiconductor laser having a resonator structure by forming an end surface in a direction perpendicular to the substrate surface by cleavage is obtained.

  In the semiconductor device having such a structure, when a current is passed between the P-type electrode 26 and the N-type electrode 23, the active layer 16 emits light by carriers injected into the active layer 16 through the current confinement region. The light emitted from the active layer 16 is amplified by resonance between both end faces and emitted from the end face as laser light.

  Next, a method for manufacturing such a compound semiconductor substrate and semiconductor device will be described. 3A to 3D are cross-sectional views schematically showing an example of a method for manufacturing a compound semiconductor substrate according to the present invention. First, a lower cladding layer 12 (N-type AlGaAs layer) and a lower light guide layer 13 (N-type GaAs layer) are formed on an N-type first GaAs substrate 11 by MOCVD (Metal Organic Chemical Vapor Deposition). . At this time, the AlGaAs layer constituting the lower cladding layer 12 is formed at a high temperature of 650 to 800 ° C. Next, the growth temperature is lowered to, for example, 500 to 650 ° C., and the active layer 16 is formed so that the upper and lower sides of the light emitting layer 14 (GaInAs layer) are sandwiched between the barrier layers 15 (GaAs layers). Note that a barrier layer 15 is formed below the lowermost light emitting layer 14 and above the uppermost light emitting layer 14. In this example, the lower layer made of the same material as the barrier layer 15 is formed there. Since the light guide layer 13 and the upper light guide layer 17 are formed, the barrier layer 15 is not formed at those positions. Thereafter, a first upper light guide layer 17-1 (GaAs layer) and InAs dots 19 are sequentially formed at a temperature equal to or lower than the temperature at which the active layer 16 is formed (FIG. 3-1). The InAs dots 19 are formed by utilizing the feature that the amount of distortion is large and does not become a continuous film but rises. The InAs dots 19 have a projecting structure that is thicker than the light emitting layer 14 and has a height in the direction perpendicular to the substrate surface that is less than ¼ of the wavelength of light having the highest light emission intensity in the light emitting layer 14. For example, it is desirable that the height is in the range of 1 to 10 nm and the diameter is in the range of 10 to 40 nm, but a smaller size is also possible.

  On the other hand, a dummy layer 28 made of a GaAs layer for etching and removing the second GaAs substrate 27 in a later step on the P-type second GaAs substrate 27, and a second GaAs substrate 27 in a later step. An etching stop layer 29 made of an AlGaAs layer that functions as an etching stop when etching the substrate, a contact layer 22 made of a P-type GaAs layer, an upper cladding layer 21 made of a P-type AlGaAs layer, and a P-type GaAs layer The second upper light guide layer 17-2 is sequentially formed by MOCVD (FIG. 3-2). Here, the P-type AlGaAs layer constituting the upper cladding layer 21 is formed on a second GaAs substrate 27 different from the first GaAs substrate 11 on which the active layer 16 having a metastable material system is formed. Therefore, it can be formed at a temperature higher than the formation temperature of the active layer 16 from which high-quality crystals can be obtained. Further, the dummy layer 28 and the etching stop layer 29 can be omitted as necessary.

  Next, the InAs dot 19 on the first GaAs substrate 11 and the second upper light guide layer 17-2 of the second GaAs substrate 27 are faced to each other, and the first upper light guide layer 17- on each substrate is faced. The surface orientation of 1 and the surface orientation of the second upper light guide layer 17-2 are matched to bring them into contact with each other. After that, in a state in which a compressive stress is applied so that a weight is applied, for example, with a weight 41 in a direction perpendicular to the substrate surface between both substrates, the temperature is higher than the formation temperature of the upper cladding layer 21 on the second GaAs substrate 27. The first GaAs substrate 11 and the second GaAs substrate 27 are joined by annealing at a low temperature or in a shorter time than the formation time (FIG. 3-3).

  Next, the second GaAs substrate 27 and the dummy layer 28 are removed from the second GaAs substrate 27 side by etching, and a part of the etching stop layer 29 is further removed (FIG. 3-4). Subsequently, the etching stop layer 29 is removed by selective etching to expose the contact layer 22 on the surface, whereby the compound semiconductor substrate shown in FIG. 1 is obtained.

In the above process, particularly for the formation of the AlGaAs layers constituting the upper and lower cladding layers 12 and 21, it is desirable to supply active hydrogen to reduce impurities. It is desirable to supply as much of AsH ₃ : arsine as much as possible as compared to the Group III Ga raw material (for example, trimethylgallium, hereinafter referred to as TMG). Further, from the viewpoint of growing a high-quality crystal under such conditions, if the growth is performed at a GaAs congruent temperature of 550 ° C. or higher, the supplied As raw material will re-evaporate even if it is deposited on the substrate. It is desirable because the supply of As raw material can be increased, and it is more desirable to grow at a temperature exceeding 625 ° C., which is the melting point of metal Al, from the viewpoint of preventing the inclusion of precipitates such as AlAs. On the other hand, with respect to the high strain GaInAs layer that is a metastable material system constituting the light emitting layer 14, in order to suppress excessive movement of atoms on the crystal surface, congrue that can suppress supply of excessive V group source gas. It is desirable to carry out at an entry temperature of 550 ° C. or lower.

Next, a method for manufacturing a semiconductor device using such a compound semiconductor substrate will be described. 4A to 4C are cross-sectional views schematically showing an example of a method for manufacturing a semiconductor device according to the present invention. First, an SiO ₂ film is formed on the compound semiconductor substrate of the contact layer 22 shown in FIG. 1, as the SiO ₂ film remains only in the current confinement region by an ordinary lithography method, a mask 30 of a stripe of the SiO ₂ film Form (FIG. 4-1).

Next, a mesa structure is formed by etching a part of the contact layer 22 and the upper clad layer 21 using the stripe mask 30 (FIG. 4-2). Thereafter, a SiO ₂ film is deposited to form a passivation film 24, and a polymer is buried in the step portion removed in the step of FIG. 4-2 to form a polymer buried layer 25 (FIG. 4-3). Next, the SiO ₂ film (24, 30) at a predetermined position covering the mesa structure is removed by a normal lithography method to expose the lower contact layer 22. Thereafter, a contact metal layer is deposited on the exposed upper surface of the contact layer 22 to form a P-type electrode 26. Further, after the first GaAs substrate 11 is thinned (by a predetermined thickness) by etching or polishing, an N-type electrode 23 is deposited on the lower surface of the first GaAs substrate 11. Finally, the semiconductor device as shown in FIG. 2 is obtained by cleaving in a predetermined direction perpendicular to the substrate surface to form a resonator structure of the element.

  When a compound semiconductor substrate is formed by such a method, after forming a highly strained GaInAs layer (light-emitting layer 14) in a metastable state, other semiconductor layers that need to be grown on the layer at a high temperature are thickened. Since it is not formed, the first GaAs substrate 11 is not exposed to a high temperature environment for a long time. Therefore, even if the strain amount of the GaInAs layer constituting the light emitting layer 14 exceeds the critical strain amount in terms of thermal equilibrium with respect to the GaAs layer constituting the barrier layer 15 (first upper light guide layer 17-1). , Dislocation growth caused by raising the temperature can be suppressed. On the other hand, the AlGaAs layers constituting the lower clad layer 12 on the first GaAs substrate 11 and the upper clad layer 21 on the second GaAs substrate 27 also have a GaInAs layer (light emitting layer 14) in a metastable state. It is possible to grow at the optimum temperature without considering the problem of lattice irregularity with respect to the GaAs substrate 11. This makes it possible to grow extremely high quality crystals. As a result, a compound having a heterojunction structure in which a high-quality GaInAs crystal (light-emitting layer 14) having a low dislocation density is formed between high-quality AlGaAs layers (between the lower cladding layer 12 and the upper cladding layer 21). A semiconductor substrate can be formed.

  Also, by using such a compound semiconductor substrate, it is possible to realize a semiconductor device such as a high-quality semiconductor laser. For example, in the above-described semiconductor laser of the first embodiment, since introduction of dislocations into the crystal is suppressed, the threshold current density can be reduced, the maximum light output is increased, the temperature is increased. It is possible to suppress the dependency and improve the element life.

  As described above, when the InAs dots 19 are formed on the first upper light guide layer 17-1 (GaAs layer), mutual diffusion with the GaAs layer occurs in the lower portion and the peripheral portion of the InAs dots 19. A bonding layer 18 having a high In composition in the vicinity of the central axis and a high GaAs composition in the outer peripheral portion is formed. Therefore, the InAs dots 19 have a current confinement structure that is naturally embedded with a GaAs layer. When the first and second upper light guide layers 17-1 and 17-2 formed on the first and second GaAs substrates 11 and 27 are joined from above and below the InAs dots 19, InAs Since the region having a high In composition at the center tip of the dot 19 is brought into contact with and pressed against the GaAs layer of the second upper light guide layer 17-2, the In is a GaAs layer (second upper light guide layer 17-2). It becomes a state in which diffusion is likely to occur. Therefore, interdiffusion of atoms between the upper and lower substrates occurs more actively than usual, and high-quality bonding is possible.

  In FIG. 3-2 in the manufacturing process described above, the upper surface on the second GaAs substrate 27 is the GaAs layer constituting the second upper light guide layer 17-2. Similarly to the case, InAs dots may be formed on the surface of the second upper light guide layer 17-2. In this case, since the InAs dots 19 act as adhesives from both sides of the first and second GaAs substrates 11 and 27, the bonding effect can be further enhanced. Further, the InAs dots 19 may be formed only on the surface of the second upper light guide layer 17-2 of the second GaAs substrate 27.

  FIG. 5 is a sectional view showing another example of the structure of the semiconductor device using the compound semiconductor substrate according to the present invention. The semiconductor device shown in FIG. 5 includes an AlGaAs layer that accumulates carriers in the first upper light guide layer 17-1 between the junction layer 18 and the uppermost light emitting layer 14 of the active layer 16 in FIG. The carrier storage layer 31 made of is introduced. According to such a structure, the influence of defects on the bonding surface can be suppressed and carriers can be accumulated in a region away from the bonding surface, so that the characteristics of the semiconductor device can be improved. In addition, the same code | symbol is attached | subjected to the component same as FIG. 1, and the description is abbreviate | omitted. The carrier storage layer 31 is formed at a temperature of 500 to 650 ° C. on the first upper light guide layer 17-1 after the active layer 16 including the metastable material system is formed.

  In FIGS. 1 and 2, only the GaAs layer (first upper light guide layer 17-1) is formed between the light emitting region inside the active layer 16 and the bonding surface 18a (bonding layer 18). By adding impurities to the upper and lower sides of the bonding layer 18 to increase conductivity, the carrier concentration in the bonding region can be increased and the influence of defects can be reduced. It is also effective to add impurities inside the dots when forming InAs dots.

  FIG. 6 is a sectional view showing another example of the structure of the semiconductor device using the compound semiconductor substrate according to the present invention. In the example described above, the active layer 16 including the light emitting layer 14 is formed on the first GaAs substrate 11, and the bonding layer 18 is formed on the active layer 16, but as shown in FIG. The active layer 16 having the light emitting layer 14 may be formed on the second GaAs substrate side (not shown). That is, the bonding layer 18 is a non-light-emitting region 20 formed of a semiconductor layer having a band gap larger than that of the light-emitting layer 14 between the light-emitting layer 14 and the lower cladding layer 12 in the lowermost layer of the active layer 16 (FIG. 6). In this example, it may be formed in the first and second lower light guide layers 13-1 and 13-2). In addition, the same code | symbol is attached | subjected to the component same as FIG. 1, and the description is abbreviate | omitted.

  In the above description, the active layer 16 made of the metastable material system has been described by taking as an example a structure in which the upper and lower sides of the light emitting layer 14 made of the GaInAs layer are sandwiched by the barrier layer 15 made of the GaAs layer. The present embodiment is not limited, and the first embodiment can be widely applied to the active layer 16 having a metastable material system.

  For example, a GaInNAs layer may be used as the light emitting layer 14 in the compound semiconductor substrate shown in FIG. 1 or the semiconductor device shown in FIG. Since GaInNAs is more immiscible than GaInAs, when the GaInNAs layer is formed and treated at a temperature of about 650 ° C. or higher for a long time, the emission wavelength shifts to a short wavelength and the composition becomes nonuniform. For this reason, the heat treatment at a high temperature after the GaInNAs layer is formed causes the characteristics of the semiconductor device to be rapidly deteriorated.

  However, by manufacturing the compound semiconductor substrate and the semiconductor device by the above-described method, it is not necessary to expose the metastable GaInNAs layer to a high temperature. As a result, the uniformity of the GaInNAs layer can be maintained, so that the characteristics as a semiconductor device can be greatly improved.

  Further, in the compound semiconductor substrate shown in FIG. 1 or the semiconductor device shown in FIG. 2, an InAs dot crystal may be used as the light emitting layer 14. Since the InAs dots have a large amount of local strain, if the InAs dots are processed for a long time at a temperature of about 560 ° C. or higher after the InAs dots are formed, the emission wavelength is shifted to a short wavelength and the structure becomes non-uniform. For this reason, the heat treatment at a high temperature after the InAs dot formation causes the characteristics of the semiconductor device to be rapidly deteriorated.

  However, by manufacturing the compound semiconductor substrate and the semiconductor device by the above-described method, it becomes unnecessary to expose the metastable InAs dot layer to a high temperature. As a result, the uniformity of the InAs dot layer can be maintained, and the characteristics as a semiconductor device can be greatly improved.

  According to the first embodiment, after the metastable material system is formed on the first substrate, among the materials to be formed on the metastable material system, the material that places the metastable material system in a high temperature environment Since a material that excessively strains the metastable material system is formed on another second substrate, and the two are aligned after being aligned with quantum dots (dot projections), When the table material system is exposed to a high temperature environment, spinodal decomposition occurs, or excessive strain is applied to the metastable material system, causing strain relaxation due to plastic deformation, leading to a decrease in crystallinity. It has the effect of preventing. In addition, by using low-melting-point quantum dots as bumps, the material constituting the quantum dots diffuses well into other substrates at temperatures near the formation temperature of the metastable material system, and the two substrates can be joined. It is possible to suppress the occurrence of spinodal decomposition and strain relaxation of the metastable material system.

(Second Embodiment)
FIG. 7: is sectional drawing which shows typically an example of a structure of the compound semiconductor substrate concerning the 2nd Embodiment of this invention. This compound semiconductor substrate is provided on an N-type GaAs substrate 51 so as to sandwich the lower semiconductor multilayer reflector layer 52, the lower cladding layer 53, the lower light guide layer 54, the light emitting layer 56, and the upper and lower sides of the light emitting layer 56. The active layer 57 including the barrier layer 55, the upper light guide layer 58, the upper cladding layer 61, the AlGaAs layer 62, the upper semiconductor multilayer reflector layer 63, and the contact layer 64 are sequentially stacked. Here, in the upper light guide layer 58 formed on the upper side of the active layer 57, a bonding layer 60 is formed through quantum dots 59 such as InAs. That is, the first upper light guide layer 58-1 and the second upper light guide layer 58-2 having a thickness that does not cause a lattice defect formed on the active layer 57 including the metastable material system. The quantum dots 59 formed on any one or each upper surface are used as bumps and are joined together in the same plane orientation. Here, the quantum dots 59 correspond to the dot-like projections in the claims.

  Also in this second embodiment, the bonding layer 60 is a layer having a larger band gap than the light emitting layer 14 between the upper surface of the uppermost light emitting layer 56 in the active layer 57 and the lower surface of the upper cladding layer 61. What is necessary is just to be formed in the non-light-emitting area | region 20 'which consists of.

  FIG. 8 is a cross-sectional view schematically showing an example of the configuration of a semiconductor device manufactured using such a compound semiconductor substrate. The example of FIG. 8 illustrates the case of a surface emitting semiconductor laser. This semiconductor device has a mesa structure having a predetermined planar shape from which part of the lower semiconductor multilayer reflector layer 52 is removed from the contact layer 64 to the lower cladding layer 53 of the compound semiconductor substrate of FIG. ing. A current confinement region 62s is provided in a region in the vicinity of the in-plane center of the AlGaAs layer 62 formed in the mesa shape, and a current confinement structure in which an aluminum oxide layer 62x is provided in the outer peripheral portion of the current confinement region 62s is formed. Here, an optical resonator is formed in a direction perpendicular to the substrate surface by the lower semiconductor multilayer reflector layer 52 and the upper semiconductor multilayer reflector layer 63.

  In the region corresponding to the current confinement region 62s of the contact layer 64, the contact layer 64 is removed, and a contact layer opening 64a from which the upper semiconductor multilayer reflector layer 63 is exposed is provided. The contact layer 64 and the contact layer opening 64a are covered with a passivation film 65, and an opening 65a in which the contact layer 64 is exposed is provided in the passivation film 65 so as to surround the current confinement region 62s. An upper surface side electrode 66 made of, for example, metal is provided so as to embed 65a. Thereby, the upper surface side electrode 66 and the contact layer 64 are electrically connected. A region surrounded by the upper surface side electrode 66 is herein referred to as an electrode opening 66a. A substrate-side electrode 67 is provided on the lower surface side of the first GaAs substrate 51.

  In the surface-emitting type semiconductor device configured as described above, when a current is passed between the upper surface side electrode 66 and the substrate side electrode 67, the surface active semiconductor element is activated via the current confinement region 62 s disposed close to the active layer 57. Carriers are injected into the layer 57. The light emitted from the active layer 57 by the injected carriers is resonated by the optical resonator composed of the lower semiconductor multilayer reflector layer 52 and the upper semiconductor multilayer reflector layer 63, and the contact layer opening 64a and the electrode opening. Laser light is emitted to the outside from the region where 66a overlaps.

  Here, a method for manufacturing the compound semiconductor substrate shown in FIG. 7 and the semiconductor device shown in FIG. 8 will be described. The compound semiconductor substrate is manufactured in the same manner as in the first embodiment. That is, the lower semiconductor multilayer reflector layer 52, the lower cladding layer 53, the lower light guide layer 54, the active layer 57, and the first upper light guide layer 58-1 are formed on the first GaAs substrate 51 by MOCVD or the like. Further, quantum dots 59 such as InAs are formed on the upper surface of the first upper light guide layer 58-1. On the other hand, on a second GaAs substrate (not shown), a dummy layer (not shown) made of an AlGaAs layer, a contact layer 64, an upper semiconductor multilayer reflector layer 63, an AlGaAs layer 62, an upper cladding layer 61, a first layer, and the like are also formed by MOCVD or the like. 2 upper light guide layers 58-2 are formed. Next, the outer peripheral portion of the AlGaAs layer 62 that constitutes a part of the upper semiconductor multilayer reflector layer 63 is oxidized to form an aluminum oxide layer 62x. As a result, an unoxidized current confinement region 62s is formed in the vicinity of the in-plane center of the AlGaAs layer 62. Next, the first upper light guide layer 58-1 and the upper light guide layer 58-2 on the two substrates are opposed to each other through the quantum dots 59, and both surface orientations are adjusted from above and below to heat. And join. Then, by removing the second GaAs substrate and the AlGaAs layer (dummy layer) to expose the contact layer 64, the compound semiconductor substrate shown in FIG. 7 is obtained.

9A to 9D are cross-sectional views schematically illustrating an example of a method for manufacturing a semiconductor device. The SiO ₂ film 71 is deposited on the upper surface of the compound semiconductor substrate shown in FIG. 7 manufactured as described above, and the SiO ₂ film at the position where the contact layer opening 64a is formed is formed using photolithography and etching. Remove. Then, using the SiO ₂ film 71 as a mask, the contact layer 64 is etched to form a contact layer opening 64a at the center thereof, thereby exposing the upper semiconductor multilayer reflector layer 63 (FIG. 9-1). . Next, a SiO ₂ film (not shown) is deposited again, and from the contact layer 64 to the lower cladding layer 53 so as to leave a predetermined region including a region where the contact layer opening 64a is formed by using photolithography and etching. Then, a part of the lower semiconductor multilayer film reflecting mirror layer 52 is removed to form a mesa structure having a predetermined planar shape (FIG. 9-2). Thereafter, the AlGaAs layer 62 in the mesa structure is oxidized from the outer periphery to form an aluminum oxide layer 62x in which Al in the outer peripheral portion of the AlGaAs layer 62 is oxidized. At this time, the outer peripheral portion of the AlGaAs layer 62 is oxidized under the condition that the central region of the AlGaAs layer 62 substantially corresponding to the contact layer opening 64a is not oxidized. As a result, a current confinement region 62s is formed in the central portion of the AlGaAs layer 62 (FIG. 9-3).

  Next, after the passivation film 65 is formed on the compound semiconductor substrate having the mesa structure, the contact layer is formed at a portion corresponding to the position where the electrode in the region outside the contact layer opening 64a is formed using photolithography and etching. A portion of the passivation film 65 is removed so that the upper semiconductor multilayer reflector layer 63 is exposed at a portion corresponding to the current confinement region 62s in the contact layer opening 64a. Thereafter, the lift-off method using a resist is used to form the upper surface side electrode 66 in contact with the contact layer 64 through the opening 65a and the electrode opening 66a being opened (FIG. 9-4). Then, after thinning the first GaAs substrate 51 to an appropriate thickness, the substrate-side electrode 67 is formed on the lower surface of the first GaAs substrate 51, whereby the semiconductor device shown in FIG. 8 is obtained.

  Conventionally, when a highly strained active layer 57 is formed at a low temperature, the surface of the active layer 57 is uneven, and crystals grown on the surface are subjected to non-uniform strain. There was a problem that difficult crystal growth was difficult. However, in the second embodiment, the semiconductor multilayer reflector layers 52 and 63 of the high reflectivity layer formed by laminating the AlGaAs layer and the GaAs layer are directly formed on different substrates (GaAs substrates). Therefore, irregularities are not formed on the semiconductor multilayer mirror layers 52 and 63. In addition, since the active layer 57 is formed on any one of the GaAs substrates, and both are joined by the quantum dots 59, the above-described problems can be avoided and the high-quality compound semiconductor substrate and the compound semiconductor can be obtained. A semiconductor device using a substrate can be obtained.

  In addition, crystal growth at a high temperature is possible when the upper and lower semiconductor multilayer mirror layers 52 and 63 are formed. Therefore, when the AlGaAs layer having a high Al composition used for the low refractive index layers in the upper and lower semiconductor multilayer reflector layers 52 and 63 is formed, the Al oxygen uptake efficiency decreases as the temperature rises. The amount of Al bonded to oxygen decreases. Further, in crystal growth at a high temperature, C of the methyl group contained in the source gas is prevented from replacing the As site as a P-type dopant. As a result, crystal growth of a high purity AlGaAs layer having a high Al composition is possible, and the carrier concentration can be easily controlled. As described above, light absorption or lowering of reflectance in the upper and lower semiconductor multilayer mirror layers 52 and 63 hardly occurs, and the characteristics of the element can be improved.

  According to the second embodiment, a compound semiconductor substrate or semiconductor device having a structure in which a semiconductor multilayer mirror layer is formed in a vertical direction with a light emitting layer sandwiched like a surface emitting semiconductor element is also high It has the effect that it can manufacture with quality.

(Third embodiment)
FIG. 10 is a cross-sectional view schematically showing an example of the configuration of the compound semiconductor substrate according to the third embodiment of the present invention. This compound semiconductor substrate includes a low-temperature GaN layer 102, a high-temperature GaN layer 103, an N-type contact layer 104 made of N-type GaInN, an N-type GaN layer 105, and a lower clad made of an N-type AlGaN layer on a sapphire substrate 101. An active layer (quantum well layer) 110 having a barrier layer 109 made of a GaN layer sandwiched between a lower light guide layer 107 made of an N-type GaN layer, a light emitting layer made of a GaInN layer, and a barrier layer 109 made of a GaN layer. 1 upper light guide layer 111, a hole block layer (carrier block layer) 112 made of an AlGaN layer, a second upper light guide layer 113 made of a P-type GaN layer, and InN quantum dots (hereinafter referred to as InN dots) 114 A bonding layer 115 made of, a third upper light guide layer 116 made of a P-type GaN layer, and a P-type AlGaN layer. Part cladding layer 117, P-type contact layer 118 made of P-type GaN layer are laminated in this order. The InN dots 114 correspond to the dot-like projections in the claims.

  Here, the bonding layer 115 is a non-light emitting region 130 made of a semiconductor layer having a larger band gap than the light emitting layer 108 between the upper surface of the uppermost light emitting layer 108 and the lower surface of the upper clad layer 117 constituting the active layer 110. It is formed in the inside. In the example of FIG. 10, the second upper light guide layer 113 formed on the first sapphire substrate 101 having the metastable active layer 110 and the third upper sapphire substrate not shown are formed. The upper light guide layer 116 is bonded with the InN dots 114 formed on either or each of the upper surfaces thereof as bumps so that the surface orientations are aligned to form the bonding layer 115.

FIG. 11 is a cross-sectional view schematically showing an example of the configuration of a semiconductor device manufactured using such a compound semiconductor substrate. In the example of FIG. 11, the case of an edge emitting semiconductor laser is illustrated. This semiconductor device has a ridge structure in which the P-type contact layer 118 at a predetermined position on the compound semiconductor substrate of FIG. 10 is removed from the N-type GaN layer 105. This ridge-like structure forms a current confinement structure. A passivation film 119 made of a SiO ₂ film is formed on the entire surface and side surfaces of the compound semiconductor substrate on which the ridge-like structure is formed. An opening is provided at a predetermined position on the P-type contact layer 118 of the passivation film 119 so that the P-type contact layer 118 is exposed. At a predetermined position on the N-type contact layer 104 of the passivation film 119, An opening is provided so that the N-type contact layer 104 is exposed. In each opening, a P-type electrode 120 and an N-type electrode 121 are formed so as to be in contact with the P-type contact layer 118 and the N-type contact layer 104, respectively. As a result, a semiconductor device capable of laser oscillation having a resonator structure using the end face can be obtained.

  The manufacturing method for such a semiconductor substrate is also basically the same as the first and second embodiments described above. That is, on the first sapphire substrate 101, the low-temperature GaN layer 102, the high-temperature GaN layer 103, the N-type contact layer 104, the N-type GaN layer 105, the lower clad layer 106, the lower light guide layer 107, the GaInN layer and the GaN layer. The first upper light guide layer 111, the hole block layer 112, and the second upper light guide layer 113 are formed on the upper surface of the active layer 110 under the conditions that the metastable state of the active layer 110 is not broken. In addition, InN dots 114 are formed thereon. On the other hand, a low-temperature GaN buffer layer, a high-temperature GaN buffer layer, a P-type contact layer 118, a P-type upper cladding layer 117, and a third upper light guide layer 116 are sequentially formed on a second sapphire substrate (not shown). Then, the second upper light guide layer 113 on the first sapphire substrate 101 and the third upper light guide layer 116 of the second sapphire substrate are made to face each other in the crystal orientation, and the InN dots 114 are used as bumps. to paste together. Thereafter, pressure is applied between the two substrates, and heat treatment is performed at a temperature that does not destroy the state of the metastable material system, and the two substrates are bonded together to obtain the compound semiconductor substrate shown in FIG. Also, a method for manufacturing a semiconductor device using such a compound semiconductor substrate is basically the same as the steps described in the first and second embodiments, and thus detailed description thereof is omitted. To do.

  Since a GaInN-based material is more immiscible than a GaInAs-based material and phase separation easily occurs during crystal growth of the GaInN layer, growth at a low temperature is indispensable. Therefore, in the third embodiment, after the GaInN layer, which is the light emitting layer 108, is grown on the first sapphire substrate 101, it is thin on the upper surface of the GaInN layer and has the same process temperature as the GaInN layer. Only the layer is grown, and a thick crystal (layer) to be disposed on the GaInN layer is grown on the second sapphire substrate. As a result, a compound semiconductor substrate having a GaInN layer with high crystallinity can be obtained.

  Further, unlike the AlGaAs and GaAs systems shown in the first and second embodiments, the lattice mismatch between GaN and AlGaN is large, and the difference between the optimum growth temperature and GaN or AlGaN is large. Therefore, it is difficult to grow an AlGaN layer having a high Al composition on the GaN layer. However, in the third embodiment, since only one clad layer (AlGaN layer) 106, 117 is grown on each substrate, the lattice irregularity is the same as in the conventional manufacturing method. If so, the accumulated energy can be halved. As a result, the Al composition of the AlGaN layer constituting the cladding layer can be increased (the refractive index can be decreased), and light confinement in the active layer can be increased, so that a low threshold value is obtained in the laser device. It has the effect that it can be achieved. In addition, since the absorption coefficient in the cladding layers 106 and 117 can be reduced, the light extraction efficiency when an LED (Light-Emitting Diode) is manufactured can be increased.

  According to the third embodiment, it is possible to easily obtain even a compound semiconductor substrate having a structure in which material systems having large lattice irregularities are stacked one above the other.

(Fourth embodiment)
FIG. 12: is sectional drawing which shows typically an example of a structure of the compound semiconductor substrate concerning the 4th Embodiment of this invention. In this compound semiconductor substrate, in FIG. 1 of the first embodiment, the first upper light guide layer 17-1, the active layer 16, and a part of the lower light guide layer 13 are formed in a direction perpendicular to the substrate surface. It is characterized by being separated by the groove 42 formed. Since other configurations are the same as those of the first embodiment, description thereof is omitted.

  In such a compound semiconductor substrate, the lower cladding layer 12, the lower light guide layer 13, the active layer 16, and the first upper light guide layer 17-1 are formed on the first GaAs substrate 11, and then, for example, by etching, A part of the first upper light guide layer 17-1, the active layer 16, and the lower light guide layer 13 at a predetermined position is removed to form a groove. Next, InAs dots 19 are formed on the first upper light guide layer 17-1. After that, according to the procedure described in the first embodiment, the first substrate and the second substrate are bonded together, and a predetermined process is performed to obtain a compound semiconductor substrate.

  Here, the case where the groove 42 perpendicular to the substrate surface is formed in the active layer and the first upper light guide layer in the case of the first embodiment is shown, but the second and third embodiments are shown. Similarly, a groove perpendicular to the substrate surface can be formed in the active layer and the light guide layer thereabove. Further, the groove forming position and the groove depth are arbitrary.

  According to the fourth embodiment, a groove formed in a direction perpendicular to the substrate surface is provided in a part of the first upper light guide layer 17-1, the active layer 16, and the lower light guide layer 13. When the first and second substrates are bonded together, even if the substrate is warped, the other substrate can be pressed without giving a strong force, and the active layer 16 can be strained. Have

  Hereinafter, the present invention will be described in more detail with reference to examples.

In Example 1, specific examples of the compound semiconductor substrate of FIG. 1 and the semiconductor device of FIG. 2 described in the first embodiment will be described. The compound semiconductor substrate used in FIG. 1 of Example 1 is a lower clad layer comprising an Al _0.4 Ga _0.6 As layer with a thickness of 1.3 μm added with Si on an N ⁻ -type first GaAs substrate 11. 12, a lower light guide layer 13 made of a GaAs layer having a thickness of 0.15 μm, a light emitting layer (quantum well layer) 14 made of a Ga _0.6 In _0.4 As layer having a thickness of 7 nm, and a GaAs layer having a thickness of 90 nm. A first upper light guide layer 17-1, a bonding layer 18 formed of InAs dots 19 doped with Zn, a second upper light guide layer 17-2 made of a GaAs layer having a thickness of 5 nm, and a thickness of 1.3 μm. It has a structure in which an upper clad layer 21 made of a P-type Al _0.4 Ga _0.6 As layer and a contact layer 22 made of a GaAs layer with a high concentration of C having a thickness of 0.3 μm are laminated. However, in this Example 1, the active layer 16 has shown the case where it consists of one layer of GaInAs layers (light emitting layer 14).

A semiconductor device as shown in FIG. 2 is manufactured from such a compound semiconductor substrate. Here, a SiO ₂ film is used as the passivation film 24. Since the detailed structure of this semiconductor device has been described in the first embodiment, a description thereof will be omitted. Such a semiconductor device is used as an edge emitting semiconductor laser element.

  In the compound semiconductor substrate (semiconductor device) having such a structure, after the GaInAs layer (active layer 16) is formed, a GaAs layer (first upper light guide layer 17-1) is formed. A bonding layer 18 composed of InAs dots 19 is formed. For this reason, in the bonding layer 18 composed of the InAs dots 19, a GaAs layer (second upper light guide layer 17-2), an AlGaAs layer (upper cladding layer 21) and a GaAs layer (on the bonding layer 18) ( The effect of strain on the active layer by the contact layer 22) is suppressed. In particular, when the AlGaAs layer (upper clad layer 21) is grown, it is necessary to raise the temperature of the substrate to 560 ° C. or higher, whereas when bonding semiconductor layers formed on two substrates, Instead of growing the AlGaAs layer (upper clad layer 21) on the first GaAs substrate 11 having the metastable GaInAs layer (active layer 16), it may be grown on the second GaAs substrate. As a result, the GaInAs layer (active layer 16) on the first GaAs substrate 11 is not placed in a temperature environment that exceeds the process temperature after growth.

  By such a manufacturing method, in the GaInAs quantum well layer of Example 1, the gap between the GaInAs quantum well layer and the GaAs layer compared to the case where a thick clad layer is laminated on both the upper and lower surfaces sandwiching the GaInAs quantum well layer, which has been conventionally performed. It is possible to reduce the influence of the lattice irregularity. For example, in a normal GaInAs layer (manufactured by a conventional method), the In composition does not greatly exceed the thermodynamic critical composition of 0.4, but the GaInAs layer (active layer 16) is used in Example 1. ) At a low temperature of 440 ° C., it is possible to grow a high-quality GaInAs layer even if the In composition is 0.46.

  Next, a method for manufacturing such a compound semiconductor substrate and a semiconductor device will be described. Since the manufacturing procedure of the compound semiconductor substrate and the semiconductor device is shown in FIGS. 3-1 to 4-3 of the first embodiment, detailed description is omitted here and only the outline is described.

First, triethylgallium (hereinafter referred to as TEG), trimethylaluminum (hereinafter referred to as TMA), and arsine (AsH ₃ ) are used as raw materials on a Si-added N ⁻ -type first GaAs substrate 11 at 680 ° C. by MOCVD. Then, an AlGaAs layer (lower cladding layer 12) is grown at the same temperature, and a GaAs layer (lower light guide layer 13) is subsequently grown using TEG and arsine as raw materials at the same temperature. Here, for the growth of the AlGaAs layer, Si is added using silane (SiH ₃ ) as a raw material to obtain an N ⁻ type conductivity type. Next, the growth temperature is lowered to 440 ° C., and a GaInAs layer (active layer 16) is grown using TMG, trimethylindium (hereinafter referred to as TMI) and arsine as raw materials. Subsequently, at the same temperature, a GaAs layer (first upper light guide layer 17-1) is grown using TMG and arsine as raw materials, and InAs dots 19 are formed using TMI and arsine as raw materials.

On the other hand, a GaAs layer (dummy layer 28) is grown on the second GaAs substrate 27 at a temperature of 680 ° C. using TEG and arsine as raw materials. Subsequently, at the same temperature, an Al _0.4 Ga _0.6 As layer (etching stop layer 29) is grown using TEG, TMA, and arsine as raw materials, and a GaAs layer (contact layer 22) is grown using TEG and arsine as raw materials. Subsequently, an Al _0.4 Ga _0.6 As layer (upper clad layer 21) is grown using TEG, TMA, and arsine as raw materials, and a GaAs layer (second upper light guide layer 17-2) using TEG and arsine as raw materials. Grow. Here, when the AlGaAs layer (upper clad layer 21) is formed, doping of C at a concentration of 2 × 10 ¹⁸ cm ⁻³ is performed by autodoping from the raw material TMA.

Thereafter, the GaAs layer (first upper light guide layer 17-1) on the first GaAs substrate 11 and the GaAs layer (second upper light guide layer 17-2) of the second GaAs substrate 27 are made to face each other. After aligning the crystal orientation, the InAs dots 19 on the first GaAs substrate 11 are brought into contact as bumps. Then, with a load of 400 g / cm ² applied, the first GaAs is annealed at 500 ° C., which is lower than the formation temperature of the AlGaAs layer (upper cladding layer 21) on the second GaAs substrate 27, for 5 minutes. The GaAs layers of the substrate 11 and the second GaAs substrate 27 are bonded to each other through InAs dots 19. Next, with the SiO ₂ film laminated and coated on the lower surface of the first GaAs substrate 11, the second thickness of the second GaAs substrate 27 is reduced to 50 μm by wet sulfuric acid hydrogen peroxide etching. Then, the second GaAs substrate 27 and the dummy layer 28 are etched until Al is observed by dry etching. Thereafter, the AlGaAs layer (etching stop layer 29) formed on the second GaAs substrate 27 is removed using a hydrochloric acid-based or buffered hydrogen fluoride ammonia-based solution to expose the GaAs layer (contact layer 22). Let By doing in this way, the semiconductor substrate shown in FIG. 1 can be obtained.

  As for the formation of the AlGaAs layers (the lower cladding layer 12 and the upper cladding layer 21), as described in the first embodiment, active hydrogen is used to reduce the concentration of impurities C and oxygen. Since it is desirable to supply, in Example 1, the raw material supply ratio of Group V and Group III is set to 100 or more. In Example 1, the crystal growth is performed at 680 ° C., which is higher than the GaAs congruent temperature of 550 ° C. and exceeds the melting point of metal Al, which is 625 ° C., thereby realizing high-quality crystal growth. . When such conditions are selected, mixing of C and oxygen can be suppressed even for high Al composition AlGaAs having an Al composition exceeding 0.4.

  On the other hand, for the high strain GaInAs that are metastable material systems, as described in the first embodiment, crystal growth can be performed at 440 ° C. to 520 ° C. which is 550 ° C. or less of the GaAs congruent temperature. Desirably, crystal growth is performed at 440 ° C. in the above example.

After forming a SiO ₂ film on the contact layer 22 of the compound semiconductor substrate obtained as described above, a mask 30 of a SiO ₂ film on a stripe having a width of 5 μm is formed by a normal lithography method. The mesa structure is formed by etching halfway between the GaAs layer (contact layer 22) and the P-type AlGaAs layer (upper clad layer 21). Thereafter, as described in the first embodiment, a passivation film 24 made of an SiO ₂ film is formed, a step formed by etching with a polymer is buried to form a polymer buried layer 25, and a passivation on the mesa structure is formed. A contact metal layer is deposited on the contact layer 22 exposed by removing the film 24 to form a P-type electrode 26, and a contact metal layer is deposited on the lower surface of the thinned first GaAs substrate 11 to form an N-type. The electrode 23 is formed. Finally, the compound semiconductor substrate is cleaved in a direction perpendicular to the extending direction of the mesa structure to form a resonator structure of the element, thereby obtaining the semiconductor device shown in FIG.

  By using such a compound semiconductor substrate, a high-quality semiconductor device can be realized. For example, in the semiconductor laser device of Example 1, the introduction of dislocations into the crystals constituting the multiple quantum well layer is suppressed. As a result, it was confirmed that the threshold current density can be reduced and the wavelength range in which oscillation is possible can be realized to wavelengths exceeding 1.2 to 1.25 μm.

In Example 1 described above, only the GaAs layer (the first upper light guide layer 17-1) is formed between the light emitting region inside the active layer 16 and the bonding layer 18, but as shown in FIG. Further, from the Al _0.3 Ga _0.7 As layer having a thickness of 3 nm to the GaAs layer (first upper light guide layer 17-1) on the quantum well layer (active layer 16) at a position 7 nm from the upper surface of the quantum well layer. A carrier storage layer 31 may be introduced. In this way, when carriers are accumulated in a region separated from the bonding layer 18, the influence of defects in the bonding layer 18 can be suppressed, so that the characteristics of the semiconductor device can be improved.

In addition, as shown in FIG. 2, when there is a bonding layer 18 made of InAs dots 19 adjacent to the active layer 16, and there is no carrier storage layer 31, the active layer 16 that emits light and the InAs dots 19 that do not emit light have The carrier is injected almost evenly. However, as shown in FIG. 5, when the carrier accumulation layer 31 is formed, the carriers injected into the InAs dots 19 are accumulated in the carrier accumulation layer 31. As a result, in the case of the first embodiment, since the light emitting layer 14 is a single layer, the quantum efficiency when laser oscillation is performed can be improved by about twice, and the threshold current becomes about half. In order to reduce the influence of defects in the junction region, Zn may be added at a concentration of 1 × 10 ¹⁸ cm ⁻³ inside the InAs dots when the InAs dots 19 are formed.

In Example 2, in the compound semiconductor substrate shown in FIG. 1 of the first embodiment and the semiconductor device shown in FIG. 2, Ga _0.57 In which is GaInNAs higher than GaInAs having high immiscibility as the active layer 16. _0.43 N _0.005 As _0.995 crystals are used. Even in such a case, it is not necessary to raise the temperature after the growth of the GaInNAs layer, so that uniform GaInNAs growth can be realized. Further, a crystal having a high In composition can be used, and even when realizing a quantum well with the same emission wavelength of 1.31 μm, the In composition is about 0.06% higher than that of normal Ga _0.63 In _0.37 N _0.01 As _0.99. Since the composition is about 0.005% lower, the luminous efficiency is increased. In the case where the semiconductor device having such high luminous efficiency is a semiconductor laser element, the threshold current density can be reduced to about 40%. By doing so, it is not necessary to expose the GaInNAs layer to a high temperature and the uniformity can be maintained, so that the characteristics as a semiconductor device can be greatly improved.

  In Example 3, in the compound semiconductor substrate shown in FIG. 1 of the first embodiment and the semiconductor device shown in FIG. 2, an InAs dot crystal is formed as the active layer 16 using TMI and TBAs (Tertiarybutylarsine). The layer is configured to be embedded with a GaInAs layer. By using the compound semiconductor substrate having such a structure, a light emitting element that emits light with high efficiency in the 1.3 μm band can be realized.

  Since InAs dots have a large amount of local strain, it is necessary to keep the temperature at 500 ° C. or lower, which is the formation temperature, after forming the film. In Example 3, even in the compound semiconductor substrate (semiconductor device) having such InAs dots, it is unnecessary to expose the formed InAs dot layer to a high temperature, and the uniformity can be maintained. As a result, the characteristics as a semiconductor device can be greatly improved.

In Example 4, a specific example of the compound semiconductor substrate shown in FIG. 7 and the surface emitting semiconductor device shown in FIG. 8 according to the second embodiment will be described. The compound semiconductor substrate used in this Example 4 has a lower semiconductor multilayer reflector layer 52 having a thickness of 0. 10 on a GaAs substrate 51 in which 35 layers of Al _0.9 Ga _0.1 As layers and GaAs layers are alternately stacked. A lower cladding layer 53 made of 08 μm Al _0.2 Ga _0.8 As layer, a lower light guide layer 54 made of GaAs layer having a thickness of 0.05 μm, a light emitting layer 56 made of Ga _0.54 In _0.46 As layer having a thickness of 6 nm, and a thickness of 15 nm An active layer 57 in which three light emitting layers 56 are formed by alternately laminating barrier layers 55 made of GaAs layers, a first upper light guide layer 58-1 made of a GaAs layer having a thickness of 0.1 μm, and InAs. bonding layer 60 consisting of a dot 59, the upper clad layer 61 made of Al _0.2 Ga _0.8 As layer having a thickness of 0.05μm, Al _0.98 Ga _0.02 As layer 62, Al _0.92 Ga _0.08 a Has a structure in which the contact layer 64 a layer and GaAs layer is made of the upper semiconductor multilayer reflection mirror layer 63, the GaAs layer formed by laminating 28 layers alternately are stacked in this order.

Further, a semiconductor device as shown in FIG. 8 is manufactured from such a compound semiconductor substrate, and the detailed structure of this semiconductor device is the same as that described in the second embodiment, so that Description is omitted. However, an oxidized aluminum oxide layer 62x is formed on the outer peripheral portion of the AlGaAs layer 62, and a structure having a current confinement region 62s composed of a region in which an Al _0.98 Ga _0.02 As layer having a diameter of 7.5 μm is left as it is in the central portion. It has become. Such a semiconductor device is used as a surface emitting semiconductor laser.

Since such a compound semiconductor substrate and a method for manufacturing a semiconductor device using this compound semiconductor substrate are the same as those described in the second embodiment, detailed description thereof is omitted. However, in the semiconductor layer formed on the first GaAs substrate 51, the lower semiconductor multilayer reflector layer 52, the lower cladding layer 53, and the lower light guide layer 54 are each formed at a growth temperature of 700 ° C., and the active layer 57 The first upper light guide layer 58-1 is formed at a growth temperature of 490 ° C., and the InAs dots 59 are formed at a growth temperature of 500 ° C. Also, in the semiconductor layer located above the bonding layer 60, an AlGaAs layer (dummy layer), a contact layer 64, an upper semiconductor multilayer reflector layer 63, an AlGaAs layer 62, an upper clad on a second GaAs substrate (not shown). The layers 61 are formed at a growth temperature of 700 ° C., respectively. Further, the surface orientations of the first upper light guide layer 58-1 of the first GaAs substrate 51 and the upper clad layer 61 of the second GaAs substrate are aligned and bonded through InAs dots 59, and 500 g / cm ² is bonded. And heated at 500 ° C. in a nitrogen atmosphere.

In Example 5, a specific example of the compound semiconductor substrate shown in FIG. 10 and the semiconductor device shown in FIG. 11 according to the third embodiment will be described. The compound semiconductor substrate used in Example 5 is a sapphire substrate 101, a low-temperature GaN layer 102 having a thickness of 35 nm, a high-temperature GaN layer 103 having a thickness of 1.8 μm, and a Ga _0.95 containing Si having a thickness of 0.05 μm. N-type contact layer 104 made of In _0.05 N layer, 0.1-μm thick Si-added N-type GaN layer 105-1, 2-μm thick Si-added N-type GaN layer 105-2, 0. Light emission of a lower cladding layer 106 made of a 3 μm Si-doped N-type Al _0.22 Ga _0.78 N layer, a lower light guide layer 107 made of a GaN layer having a thickness of 0.05 μm, and a Ga _0.85 In _0.15 N layer having a thickness of 3.5 nm An active layer 110 in which a quantum well layer is stacked three times by combining a layer (quantum well layer) 108 and a barrier layer 109 of a GaN layer having a thickness of 7 nm, a first upper light guide layer 111 made of a GaN layer having a thickness of 50 nm, thickness nm of the hole blocking layer 112 made of Al _0.2 Ga _0.8 N layer Mg addition, a GaN layer having a thickness of 10nm second upper optical guide layer 113, the bonding layer 115 made of InN dots 114, P-type thickness 10nm A third upper light guide layer 116 made of a GaN layer, an upper cladding layer 117 made of a P-type Al _0.22 Ga _0.78 N layer having a thickness of 0.3 μm, and a P-type contact layer 118 made of a P-type GaN layer in this order. It has a laminated structure. In the fifth embodiment, the N-type GaN layer 105 is composed of two N-type GaN layers 105-1 and 105-2 having different formation temperatures.

An outline of a method for producing such a compound semiconductor substrate will be described. First, the low temperature GaN layer 102 is grown on the first sapphire substrate 101 using TMG and NH ₃ as raw materials by MOCVD at a temperature of 450 ° C., and then the growth temperature is increased to 1050 ° C. to form a high temperature GaN 103 layer. Form. Next, at a temperature of 850 ° C., a Si-added Ga _0.95 In _0.05 N layer (N-type contact layer 104) is grown using TEG, TMI and arsine as source gases, and the Si-added N-type GaN layer 105-1 is grown. Grow. Further, the growth temperature is again increased to 1050 ° C. to grow a Si-added N-type GaN layer 105-2, and TMA, TMG, and arsine are used as source gases to add Si-added n-type Al _0.22. A Ga _0.78 N layer (lower cladding layer 106) is grown, and a GaN layer (lower light guide layer 107) is further grown. Next, an active layer 110 having three quantum well layers in which a GaN layer (barrier layer 109) is sandwiched between the upper and lower sides of the Ga _0.85 In _0.15 N layer (light emitting layer 108) at a temperature of 780 ° C., a GaN layer (first layer) The upper light guide layer 111), Mg-doped Al _0.2 Ga _0.8 N layer (hole block layer 112), and GaN layer (second upper light guide layer 113) are grown. Further, InN dots 114 are formed at a temperature of 400 ° C.

On the other hand, on a second sapphire substrate (not shown), a low-temperature GaN buffer layer, a high-temperature GaN buffer layer, a GaN layer (P-type contact layer 118), an Al _0.22 Ga _0.78 N layer (upper cladding layer 117), and a GaN layer (first 3 upper light guide layers 116) are sequentially formed at a temperature of 1,050 ° C. The bonding between the substrates is performed by applying a pressure of 1 kg / cm ² from above and below and heating to 500 ° C. in a nitrogen atmosphere containing NH ₃ . After this bonding, the second sapphire substrate, the low-temperature GaN buffer layer, and the high-temperature GaN buffer layer are removed by etching or the like, and a compound semiconductor substrate as shown in FIG. 10 is obtained.

Thereafter, a ridge-like structure is formed by etching in order to form a current confinement region using the compound semiconductor substrate thus formed, and then a passivation film 119 made of an SiO ₂ film, a P-type electrode 120, an N-type electrode 121 is formed. Then, an end face is formed by cutting the substrate, polishing, and HR (High Reflection) coating to produce a resonator structure, thereby forming an edge emitting semiconductor laser.

  Since GaInN-based materials are more immiscible than GaInAs-based materials, phase separation easily occurs during GaInN growth, and growth at a low temperature of 800 ° C. or lower is essential. Also, the difference in the optimum growth temperature is large from GaN or AlGaN whose growth temperature is 1,000 ° C. or higher. For this reason, in Example 5, only the thin GaN layer (first and second upper light guide layers 111 and 113) / AlGaN layer (hole block layer 112) is grown after the growth of the GaInN layer (light emitting layer 108). The other thick crystal was grown on another second substrate, and the two were later joined through the quantum dots 114.

  In addition, unlike the AlGaAs and GaAs systems, the lattice irregularity between GaN and AlGaN is large. Therefore, in the conventional manufacturing method, an AlGaN layer having a high Al composition (the lower cladding layer 106 and the upper cladding layer 117 is formed on the GaN layers 105 and 118. ) Difficult to grow. However, according to the fifth embodiment, since only one clad layer needs to be grown on each substrate, the energy stored is halved if the lattice is the same as in the conventional method. Therefore, the Al composition of the AlGaN layer (cladding layers 106 and 117) can be increased to 0.22, and the confinement of light in the active layer 110 is increased by about 40% due to the decrease in the refractive index of the cladding layers 106 and 117. Can take. As the volume in which light is confined decreases, the light density increases, and accordingly the laser threshold can be reduced by about 40%.

  In addition, although the case where this invention was applied to the semiconductor laser was shown as Example 1-5, this invention is not restricted to a semiconductor laser, It can apply also to other light emitting elements, such as a light emitting diode. is there. In addition, although an element having a light emission wavelength of 1.3 μm is mentioned, various compositions can be selected. For example, (Ga) InAs quantum dots of 1.4 to 1.7 μm, GaInNAs quantum wells, or light emitting layers of quantum dots can be selected. Further, a quantum well or quantum dot in the 0.98 to 1.2 μm band can be selected as the light emitting layer. Furthermore, although an element that emits light at 400 nm is cited as a GaN-based material, it is not limited to this wavelength range, and it is possible to realize a light-emitting element from the ultraviolet region to the red region by controlling the composition of the GaInN layer. It becomes. In addition, the present invention can be applied to various semiconductor elements and substrates therefor without departing from the spirit of the present invention.

  Further, the material system is not limited to the semiconductor multilayer film of AlGaAs / GaAs or GaInN / AlGaN / GaN. GaAlInP / GaIn (Al) P-based material, In (Al) GaAs / AlGaInAs-based material, InP / AlInAs -Based materials, InP / GaInAsP-based materials, optical semiconductor elements using semiconductor multilayer films using AlGaAs / GaAs-based materials, or combinations of these materials with semiconductors added with N or Sb, GaSb and InAs or GaSb and GaAlSb The present invention can be applied to an optical semiconductor element to which various group III elements or group V elements are added based on these combinations or these materials.

  Further, regarding the crystal growth method related to the production method of the present invention, various raw materials such as methyl-based and ethyl-based materials can be used as raw materials for each metal element in the MOCVD method, as well as MBE (Molecular Beam Epitaxy) method. Various crystal growth techniques such as CBE (Chemical Beam Epitaxy) method and MOMBE (Metal-Organic Molecular Beam Epitaxy) method can be used without departing from the spirit of the present invention.

  As described above, the semiconductor substrate according to the present invention is useful when manufacturing a semiconductor device having a multilayer structure of a semiconductor film containing a metastable material that is not subject to a high temperature exceeding the formation temperature or excessive strain. is there.

It is sectional drawing which shows typically an example of a structure of the compound semiconductor substrate by the 1st Embodiment of this invention. It is sectional drawing which shows typically an example of a structure of the semiconductor device manufactured using the compound semiconductor substrate of FIG. It is sectional drawing which shows typically an example of the manufacturing method of the compound semiconductor substrate by this invention (the 1). It is sectional drawing which shows typically an example of the manufacturing method of the compound semiconductor substrate by this invention (the 2). It is sectional drawing which shows typically an example of the manufacturing method of the compound semiconductor substrate by this invention (the 3). It is sectional drawing which shows typically an example of the manufacturing method of the compound semiconductor substrate by this invention (the 4). It is sectional drawing which shows typically an example of the manufacturing method of the semiconductor device by this invention (the 1). It is sectional drawing which shows typically an example of the manufacturing method of the semiconductor device by this invention (the 2). It is sectional drawing which shows typically an example of the manufacturing method of the semiconductor device by this invention (the 3). It is sectional drawing which shows the other example of the structure of the semiconductor device using the compound semiconductor substrate by this invention. It is sectional drawing which shows the other example of the structure of the semiconductor device using the compound semiconductor substrate by this invention. It is sectional drawing which shows typically an example of a structure of the compound semiconductor substrate by the 2nd Embodiment of this invention. It is sectional drawing which shows typically an example of a structure of the semiconductor device manufactured using the compound semiconductor substrate of FIG. It is sectional drawing which shows an example of the manufacturing method of a semiconductor device typically (the 1). It is sectional drawing which shows an example of the manufacturing method of a semiconductor device typically (the 2). It is sectional drawing which shows an example of the manufacturing method of a semiconductor device typically (the 3). It is sectional drawing which shows an example of the manufacturing method of a semiconductor device typically (the 4). It is sectional drawing which shows typically an example of a structure of the compound semiconductor substrate by the 3rd Embodiment of this invention. It is sectional drawing which shows typically an example of a structure of the semiconductor device manufactured using the compound semiconductor substrate of FIG. It is sectional drawing which shows typically an example of a structure of the compound semiconductor substrate by the 4th Embodiment of this invention.

Explanation of symbols

11, 51 N-type GaAs substrate 12, 53, 106 Lower cladding layer 13, 13-1, 13-2, 107 Lower light guide layer 14, 56, 108 Light emitting layer 15, 55, 109 Barrier layer 16, 57, 110 Active layer 17, 17-1, 17-2, 58, 111, 113, 116 Upper light guide layer 18, 60, 115 Bonding layer 18a Bonding surface 19, 59 Quantum dot (InAs dot)
20 Non-light emitting region 21, 61, 117 Upper cladding layer 22, 64 Contact layer 23 N-type electrode 24 Passivation film 25 Polymer buried layer 26 P-type electrode 31 Carrier block layer 52 Lower semiconductor multilayer reflector layer 62 AlGaAs layer 63 Upper semiconductor Multilayer reflector layer 101 Sapphire substrate 102 Low-temperature GaN layer 103 High-temperature GaN layer 104 N-type contact layer 105 N-type GaN layer 112 Hole block layer 114 Quantum dots (InN dots)
118 P-type contact layer

Claims (6)

A first conductivity type cladding layer, a first conductivity type light guide layer, an active layer having a light emitting layer made of a metastable material-based crystal, a second conductivity type light guide layer, and a second conductivity type light guide layer, each formed of a compound semiconductor on the substrate; The second conductivity type cladding layer has a structure in which the second conductivity type cladding layer is laminated in order, and between the upper surface of the light emitting layer located on the uppermost side in the active layer and the lower surface of the second conductivity type cladding layer, or in the active layer From the compound semiconductor in which the bonding surface that divides the upper and lower layers formed in the non-light emitting region between the lower surface of the lowermost light emitting layer and the upper surface of the first conductivity type cladding layer is not continuous in the in-plane direction A compound semiconductor substrate comprising a bonding layer bonded via a dot-shaped protrusion,
First and second electrodes for supplying a first conductivity type carrier to the first conductivity type cladding layer and supplying a second conductivity type carrier to the second conductivity type cladding layer;
A semiconductor device comprising:   The dot-shaped protrusion is made of a compound semiconductor that is thicker than the light emitting layer and has a size equal to or smaller than ¼ of the wavelength of the maximum intensity light emitted from the light emitting layer. Item 14. The semiconductor device according to Item 1.   2. The semiconductor device according to claim 1, further comprising a carrier accumulation layer that accumulates carriers from the dot-shaped protrusions between the active layer and the bonding layer.   2. The semiconductor device according to claim 1, wherein a groove having a depth reaching at least a lower surface of the active layer is formed on a bonding surface including the active layer. A first conductive type cladding layer, a first conductive type light guide layer, an active layer having a light emitting layer made of a metastable material-based crystal, a second conductive type light guide layer, each formed of a compound semiconductor layer on a substrate, And a second conductivity type cladding layer are sequentially laminated,
Between the upper surface of the uppermost light emitting layer in the active layer and the lower surface of the second conductivity type cladding layer, or the lower surface of the lowermost light emitting layer in the active layer and the first conductivity type A bonding surface that divides the upper and lower layers formed in the non-light-emitting region between the upper surface of the cladding layer and the upper surface of the cladding layer includes a bonding layer bonded via a dot-shaped protrusion made of a compound semiconductor that is not continuous in the in-plane direction. A compound semiconductor substrate characterized by the above. Forming a first conductive type cladding layer and a first conductive type light guide layer each made of a compound semiconductor on a first substrate at a first temperature at which the compound semiconductor grows;
On the first conductivity type light guide layer, an active layer including a light emitting layer made of a metastable material crystal made of a compound semiconductor, a lower second conductivity type light guide layer, and dot-like projections that are not continuous in the in-plane direction. A second step of forming at a second temperature lower than the first temperature in a range where the light emitting layer maintains a metastable state;
A third step of forming a second conductive type cladding layer and an upper second conductive type light guide layer each made of a compound semiconductor on a second substrate at a third temperature higher than the second temperature;
The lower second conductivity type light guide layer on the first substrate and the upper second conductivity type light guide layer on the second substrate are bonded together via the dot-shaped projections, and the first And a fourth step of applying a pressure to the substrate surface of the second substrate and heat-treating at a fourth temperature lower than the first and third temperatures within a range in which the light emitting layer maintains a metastable state; ,
A fifth step of removing the second substrate;
A method for producing a compound semiconductor substrate, comprising:

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