JP2008072189A - Current addition type high-resolution d-a converter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a current addition type high-resolution D-A converter which can perform faster D-A conversion, has a higher resolution, and reduces a chip size. <P>SOLUTION: The current addition type high-resolution D-A converter includes transistors 31 to 37 constituting constant-current mirror circuits that a constant current mirror circuit 30 has; and Nch type transistors 61a and 61b to 68a and 68b constituting differential pair transistors at a switching section 60. Further, the constant current mirror circuit 30, the switching section 60, and a current mirror circuit 70 for output each comprise a cell comprising a fixed number of transistors, and the order of bits is weighted by the number of respective transistors. Further, the order of bits is made to correspond by combining a plurality of cells, and relative variance among respective transistors of the individual cells is reduced. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a current addition type high resolution D / A converter, and is particularly suitable for use in driving a laser diode that requires high speed switching.

  Conventionally, a current addition type D / A converter for converting a digital signal into an analog signal has been proposed in Patent Document 1, for example. Specifically, in Patent Document 1, a plurality of current cells (256), a bias circuit, a decoder that decodes a digital signal input from an input terminal, a current conversion resistor, a current / voltage conversion resistor, An 8-bit current addition type D / A converter having the above has been proposed.

  Among these, each current cell includes a current source transistor that supplies a current, and a switching PMOS transistor that switches whether the current flows into the current / voltage conversion resistor or is discarded to the ground and forms a differential pair. It is prepared for. The PMOS transistor is a ground common, and each PMOS transistor is on / off controlled by a decoder. Note that a P-channel transistor is used for the selection of the transistor because of the design of ground common.

  The bias circuit amplifies the reference voltage and inputs it to the current conversion resistor. The current flowing through the current conversion resistor is input to each current cell by being turned back by a current mirror circuit including a transistor provided in the bias circuit and a transistor provided in the current cell. The current input to the current cell by the current mirror circuit is output to the current / voltage conversion resistor or the ground by the switching PMOS transistor.

  The current flows from each current cell into the current / voltage conversion resistor, and the voltage value obtained by the product of the total value of these currents and the resistance value of the current / voltage conversion resistor is the current addition type D / A converter. Output as output.

In the current addition type D / A converter as described above, by providing 256 current cells, an 8-bit digital signal can be converted into an analog signal.
JP 2001-136068 A

  However, in the above conventional technique, switching is performed by a switching PMOS transistor in the current cell whether the current flows into the current / voltage conversion resistor or is discarded to the ground. Since the responsiveness of the PMOS transistor is generally low, the current addition type D / A converter cannot be used as a laser diode drive LSI that requires a high-speed response in, for example, a high-speed DVD recorder.

  Further, in the above conventional technique, as the maximum 8 bits data is handled, the resolution is low and the data exceeding 8 bits cannot be handled. Therefore, it is conceivable to increase the number of current cells in order to handle a data amount exceeding 8 bits. However, as the number of current cells increases, the relative variation of each current cell also increases. For example, in the case of 10 bits, 1024 current cells are required. As the number of current cells increases, it becomes difficult to control each current cell with high accuracy.

  Further, 256 decoder logics are required to correspond to each current cell. This increases the chip size of the D / A converter, which in turn increases the cost. As described above, increasing the amount of data to be handled requires an increase in the number of current cells and the corresponding logic of the decoder, resulting in a problem that the chip size increases.

  An object of the present invention is to provide a current addition type high resolution D / A converter capable of achieving high speed D / A conversion, high resolution, and chip size reduction.

  In order to achieve the above object, the present invention is provided with a plurality of Nch type transistors (31 to 37) as a current addition type high resolution D / A converter, and a plurality of constant current current mirror circuits each including the transistors. The current converted by the amplifier unit (10) is input via the input current mirror circuit unit (20), and the constant current current mirror circuit unit (30) is turned back by the constant current current mirror circuit. The transistors (61a, 61b to 68a, 68b) are provided with a plurality of differential pair transistors, and the output of the decoder (40) is input to one of the differential pair transistors and the other is the inversion of the decoder. By inputting the output, it is possible to switch whether the current input from the constant current current mirror circuit section (30) is drawn from the power supply or output. A switching unit (60) that performs switching and a plurality of output current mirror circuits are provided. The current input from the switching unit is folded back by the output current mirror circuit, and the sum of the outputs of the output current mirror circuits is output to the outside. And an output current mirror circuit section (70).

  Here, the constant current current mirror circuit section, the switching section, and the output current mirror circuit section are each provided with a constant current current mirror circuit, a differential pair transistor, and an output current mirror circuit corresponding to the order of bits. The gate structure of each transistor constituting the constant current current mirror circuit, differential pair transistor, and output current mirror circuit is unified, and each constant is configured by the number of transistors according to the bit order. The current current mirror circuit, each differential pair transistor, and each output current mirror circuit are weighted according to the order of bits.

  The bit order indicates “0th bit” or “4th bit” when the data is composed of a plurality of bits.

  Furthermore, the constant current current mirror circuit unit, the switching unit, and the output current mirror circuit unit are each composed of a certain number of cells that constitute the transistors, and the cells are combined according to the order of the bits. It is characterized by being designed.

  As described above, each transistor constituting the constant current current mirror circuit in the constant current current mirror circuit unit and the differential pair transistor in the switching unit is configured as an Nch type. Thereby, the response speed in each transistor can be increased.

  Further, each of the constant current current mirror circuit unit, the switching unit, and the output current mirror circuit unit is configured by a cell including a certain number of transistors. At this time, by weighting the bit order by the number of each transistor, the number of logics of the decoder can be reduced, and the number of transistors used as a whole can be reduced. As a result, the size of the chip constituting the D / A converter can be reduced. Can be reduced.

  Further, as described above, the transistors are grouped in cells. That is, the bit order is matched by combining a plurality of cells, and the relative variation of each transistor in each cell is reduced. Thereby, the target differential linearity error can be kept within a range of ± 1 LSB, for example, and a high resolution of the D / A converter can be realized. As data to be handled, for example, data of 10 bits or more can be handled.

  In addition, each of the constant current current mirror circuit unit, the switching unit, and the output current mirror circuit unit is configured by one cell in which each transistor corresponding to 0 bit to 4 bit is combined when the bit order is 0 bit to 4 bit. When the order of 5 bits is used, each transistor corresponding to 5 bits is configured by one cell, and when the order of bits is 6 bits or more, a plurality of cells corresponding to 5 bits can be combined.

  In addition, the code | symbol in the bracket | parenthesis of each said means shows the correspondence with the specific means as described in embodiment mentioned later.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the same or equivalent parts are denoted by the same reference numerals in the drawings.

(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. The current addition type high resolution D / A converter shown in the present embodiment is used for, for example, laser diode driving that requires high-speed switching at the time of writing or the like in a DVD recorder. In the present embodiment, a description will be given of what converts 10-bit data into an analog signal.

  FIG. 1 is an overall circuit diagram of a current addition type high resolution D / A converter according to an embodiment of the present invention. As shown in this figure, the current addition type high resolution D / A converter includes an amplifying unit 10, an input current mirror circuit unit 20, a constant current current mirror circuit unit 30, a decoder 40, an inverter unit 50, The switching unit 60 and the output current mirror circuit unit 70 are provided.

  The amplifying unit 10 amplifies the reference voltage VA and converts it into a current. The amplifier 11 receives the reference voltage VA at the non-inverting input terminal and the ground at the inverting input terminal. The transistor 12 includes an output whose input is input to a gate, and a resistor 13 through which current flows when the transistor 12 is turned on.

  The current flowing through the input current mirror circuit unit 20 and the resistor 13 of the amplifying unit 10 is turned back to the constant current current mirror circuit unit 30. Such an input current mirror circuit unit 20 includes two transistors 21 and 22 that constitute a current mirror circuit, a transistor 23 that causes a current folded by the current mirror circuit to flow to the constant current current mirror circuit unit 30, It is configured with.

  The constant current current mirror circuit unit 30 is a current mirror circuit that folds and inputs the current input from the input current mirror circuit unit 20 to the switching unit 60. Such a constant current current mirror circuit unit 30 includes an NMOS transistor 31 that is an Nch type transistor, and has a plurality of constant current current mirror circuits configured by pairing with the NMOS transistor 31.

  With respect to the gate electrode constituting the NMOS transistor 31, the length in the direction of the channel formed between the source region and the drain region is L, and the length in the direction perpendicular to the length L is W. Then, the W values of the transistors constituting each constant current current mirror circuit provided in the constant current current mirror circuit unit 30 are all the same value. Note that the W value of each transistor provided in the switching unit 60 and the output current mirror circuit unit 70 described later is also the same as the W value of each transistor of the constant current current mirror circuit unit 30.

  In order to handle 10-bit data, weighting is performed by adjusting the ratio of the W value according to the order of the bits. That is, the 0 bit is one transistor 32, the 1 bit is 2 transistors 33, the 2 bit is 4 transistors 34, the 3 bit is 8 transistors 35, the 4 bit is 16 transistors 36, and the 5 bit is 5 bits. The 32 transistors 37 and the sixth and subsequent bits are configured as a combination of a plurality of 32 transistors 37, and the number of constant current current mirror circuits corresponding to the order of each bit is configured.

  In the present embodiment, a group of 32 transistors corresponding to 5 bits is referred to as a cell. Further, “0th bit”, “1st bit”, etc. of the data are referred to as a bit order.

  For example, “× 16” shown in FIG. 1 is a part that handles the 4th bit data, and shows that a constant current current mirror circuit is constituted by one transistor 31 and 16 transistors. The currents returned by the constant current current mirror circuits of the constant current current mirror circuit unit 30 are input to the switching unit 60, respectively.

  Thus, the reason why the constant current mirror circuit after the 6th bit is adjusted by the number of cells of 32 transistors 37 is to reduce the output error per cell. For example, in the case of binary 0000100000 (decimal 32), one cell composed of 32 transistors 37 is turned on. In the case of binary number 0001,000,000 (decimal number 64), two cells composed of 32 transistors 37 are turned on. By configuring one cell with 32 transistors 37 in this manner, the allowable variation of elements in the current addition type high resolution D / A converter varies by 1/32 in one cell, and thus a variation of 3.125%. Thus, the target differential linearity error (± 1LSB) can be guaranteed.

  The decoder 40 is formed with a logic circuit that decodes encoded data or signals input from the outside into original data or signals. When 10-bit data is input from the outside, the decoder 40 decodes the data and inputs the decoded data to each current mirror circuit of the switching unit 60 and the inverter unit 50.

  The inverter unit 50 inverts the signal input from the decoder 40 and inputs the inverted signal to each differential pair transistor of the switching unit 60. Therefore, the inverter unit 50 includes inverters 51 to 58 corresponding to the differential pair transistors of the switching unit 60.

  The switching unit 60 determines whether the current input from the constant current current mirror circuit unit 30 is supplied from the power supply or input to the output current mirror circuit unit 70 in accordance with signals input from the decoder 40 and the inverter unit 50. It is what switches. Similar to the constant current current mirror circuit unit 30 and the inverter unit 50, the switching unit 60 includes a plurality of differential pair transistors forming a differential pair corresponding to the order of each bit.

  Specifically, for the 0th bit, the output of the decoder 40 is input to the differential pair transistor 61a among the differential pair transistors 61a and 61b corresponding to the 0th bit, and the inverted output of the decoder 40 is supplied to the differential pair transistor 61b. Will be entered. In this embodiment, when the differential pair transistor 61b is turned on according to the output of the decoder 40, the current flows from the output current mirror circuit unit 70 to the transistor 32 via the differential pair transistor 61b. When the differential pair transistor 61a is turned on according to the output of the decoder 40, current flows from the power source to the transistor 32 through the differential pair transistor 61a.

  In the case of the first bit, each two differential pair transistors 62a and 62b constitute a differential pair. Similarly, in the case of the second bit, four differential pair transistors 63a and 63b, and in the case of the third bit, each of the differential pair is configured by eight differential pair transistors 64a and 64b. The upper bit also forms a differential pair by the differential pair transistors 65a, 65b to 68a, 68b. Then, the output path of each differential pair transistor is selected according to the output of the decoder 40.

  The output current mirror circuit unit 70 folds the input from each differential pair transistor of the switching unit 60 by the current mirror circuit, and sums the output of each differential pair transistor of the current addition type high resolution D / A converter. Output as output.

  Such an output current mirror circuit unit 70 has a plurality of output current mirror circuits corresponding to the order of each bit, and the output current mirror circuit is composed of Pch type transistors. Specifically, in the case of 0 bit, an output current mirror circuit is configured by the PMOS transistors 71a and 71b. As a result, the current input from the transistor 61b of the switching unit 60 is folded and output by the transistors 71a and 71b.

  Similarly, each higher order bit similarly forms an output current mirror circuit with PMOS transistors 72a, 72b to 78a, 78b. Then, each output current mirror circuit of the output current mirror circuit unit 70 outputs the current input according to the output of each differential pair transistor of the switching unit 60 to the output.

  Each of the PMOS transistors 71b to 78b of the output current mirror circuit unit 70 also has a function of adjusting the gain by setting an N value (integer).

  The output of the output current mirror circuit unit 70 is input as a load to a laser diode of a DVD recorder, for example, and data is written to the DVD. The above is the overall circuit configuration of the current addition type high resolution D / A converter according to the present embodiment.

  Next, a circuit layout of the current addition type high resolution D / A converter will be described. FIG. 2 is a diagram showing a circuit layout of the current addition type high resolution D / A converter shown in FIG. As shown in the figure, first, as described above, in the constant current current mirror circuit unit 30, 32 transistors are arranged for each cell. The transistors 61a, 61b to 65a, 65b corresponding to 0 bits to 4 bits are collectively stored in one cell 81. The transistors 66a, 66b to 68a, 68b corresponding to 5 to 9 bits are accommodated in 31 cells 82, respectively. That is, in the present embodiment, 32 cells in which 32 transistors are combined are arranged in a straight line.

  As described above, the W value and the L value of each transistor are all the same value, and the transistors having the same W value and L value are arranged in a 4 × 8 array in the cell. In FIG. 2, the numerical value written in each transistor indicates a transistor corresponding to the bit order. For example, what is written as “8” indicates a transistor 35 corresponding to 3 bits, and eight transistors 35 are arranged.

  In addition, the switching unit 60 and the output current mirror circuit unit 70 also have a configuration in which the respective transistors (not shown) are arranged in each cell, and the respective cells are arranged as shown in FIG. . The numerical values entered in each cell of the switching unit 60 and the output current mirror circuit unit 70 are the values corresponding to the bit order, as described above.

  Each cell preferably has the same shape, such as the shape of the back gate surrounding each transistor and the routing of the gate line. Moreover, it is preferable that the back gate has the same shape in all the cells.

  In this embodiment, a dummy cell 83 provided with a dummy transistor is provided at the end of each arranged cell. This is for reducing variation in characteristics between the transistors in the cells at both ends and the transistors in the cells in the inside. In each cell, the gates of the transistors are connected by a stacked structure.

  And each cell is connected by each wiring 91 (part shown with the oblique line in FIG. 2), and aluminum is employ | adopted as a material of the wiring 91, for example. In the present embodiment, the wiring 91 that is connected to the ground is thickened. This is for facilitating the flow of a current to the ground, and by reducing the distance between each cell and the ground, a difference is not caused in the response speed of each cell.

  In addition, as shown in FIG. 2, a cell 81 provided with transistors 61a, 61b to 65a, 65b corresponding to 0 bits to 4 bits is arranged at the center where the cells are arranged. A wiring 92 is formed so that the current output from the input current mirror circuit unit 20 is input to the transistor 31 in the cell. The wiring 92 must first be connected to the transistor 31 from the input current mirror circuit unit 20 and then connected to the other transistors 32 to 37 from the base of the transistor 31. Further, the transistor 31 serving as a reference for each current mirror circuit of the constant current current mirror circuit unit 30 is arranged in the center of the cell, so that each transistor (each cell) constituting the constant current current mirror circuit unit 30 is arranged. Avoid making a difference in responsiveness.

  In this embodiment, the wiring 91 up to the output is formed as thick as possible on a straight line. This is to prevent a difference in the response speed of each cell. In addition, among the wirings 91 connected to the output (OUT), the shape of the wirings 91 connected to both ends of the arranged cells is not a right-angled shape, but is bent at an angle of 45 °. This is to prevent the current flow of the wiring 91 connected to the cell at a location away from the center from being hindered. Thereby, the high-speed response of a D / A converter is realizable.

  As shown in FIG. 2, the inverter unit 50, the decoder 40, the amplifier unit 10 and the like are arranged in a portion adjacent to each cell, and are connected to each other by laminated wiring. The above is the circuit layout of the D / A converter shown in FIG.

  The operation of the current addition type high resolution D / A converter having the above configuration and layout will be described. As shown in FIG. 1, the reference voltage VA is amplified by the amplifying unit 10 and converted into a current. The converted current is input to the transistor 31 of the constant current current mirror circuit unit 30 through the input current mirror circuit unit 20.

  Further, 10-bit data is input from the outside to the decoder 40, decoded, and input to the switching unit 60 and the inverter unit 50. Thereby, on / off of each differential pair of the switching unit 60 is controlled according to the content of data, and the output of each current mirror circuit of the constant current current mirror circuit unit 30 is supplied to the ground or the output current mirror circuit unit 70. Entered.

  Here, in order to improve the non-linearity error (INL), it is preferable to set the switching order for each cell constituting the constant current current mirror circuit unit 30 in the order of inner → outer → inside. That is, switching is performed in the order of numerical values shown in the table 100 at the bottom of FIG. Note that the cell 81 related to 0 bit to 4 bit is turned on first, and thereafter, switching is performed in the order of the numerical values shown in the table 100.

  Thereafter, in the output current mirror circuit unit 70, the currents input from the current mirror circuit of the switching unit 60 are folded and summed and output to the outside. In this way, D / A conversion is executed.

  As described above, the present embodiment is characterized in that Nch type transistors are first adopted for the constant current current mirror circuit unit 30 and the switching unit 60. Thereby, it is possible to increase the output speed with respect to the current input from the input current mirror circuit unit 20.

  Also, in each of the constant current current mirror circuit unit 30, the switching unit 60, and the output current mirror circuit unit 70, each transistor corresponding to 0 bits to 4 bits is integrated into one cell, and 32 transistors corresponding to 5 bits are integrated into one cell. In addition, the sixth and subsequent bits are characterized by combining a plurality of the cells. Thereby, the differential linearity error which arises in one cell can be suppressed, and the relative variation of each transistor can be reduced. Therefore, the target differential linearity error can be kept within a range of ± 1LSB. Accordingly, the data to be handled can be increased, and high resolution exceeding 10 bits can be realized.

  Further, the bit order of digital data is weighted by the number of transistors. As a result, the number of transistors constituting the constant current current mirror circuit unit 30, the switching unit 60, and the output current mirror circuit unit 70 can be reduced, and consequently the chip size of the D / A converter can be reduced. .

  Further, the present embodiment is characterized in that high-speed response is realized by the circuit layout of the D / A converter. That is, the transistors of the constant current current mirror circuit unit 30, the switching unit 60, and the output current mirror circuit unit 70 are grouped as 32 cells, and the wiring 91 that connects the cells constituting the constant current current mirror circuit unit 30 to the ground. Is thickened. As a result, it is possible to easily pass a current to the ground, and it is possible to prevent a shift in response speed of each cell according to the distance between each cell and the ground.

  Furthermore, in the wiring 91 formed to output the output of each cell constituting the output current mirror circuit unit 70 to the outside, the output current mirror circuit unit 70 is configured and arranged as shown in FIG. Of the formed cells, the shape of the wiring 91 extended from the cell located at a location away from the center is formed such that a right angle portion is not formed and the wiring 91 is bent. As a result, the flow of current can be made smooth and a difference in response speed of each cell can be prevented.

(Second Embodiment)
In the present embodiment, only different parts from the first embodiment will be described. In the first embodiment, the cell of the output current mirror circuit unit 70 corresponding to 0 bits to 4 bits is configured using 32 PMOS transistors 71a, 71b to 74a, 74b. The feature is that they are grouped into two current mirror circuits.

  FIG. 3 is a diagram illustrating a circuit of the switching unit 60 and the output current mirror circuit unit 70 corresponding to 0 bits to 4 bits in the current addition type high resolution D / A converter according to the present embodiment. As shown in this figure, the outputs of the constant current current mirror circuit unit 30 corresponding to x1 (0 bit) to x16 (4 bit) are grouped into one set as x32 in the output current mirror circuit unit 70. Also, a current mirror circuit can be formed by the PMOS transistors 79a and 79b. As a result, in the output current mirror circuit unit 70, the wirings for the respective transistors corresponding to 0 bits to 4 bits can be collected, and the error of the response of each transistor can be eliminated. As described above, the output current mirror circuit unit 70 may combine the current mirror circuits corresponding to 0 to 4 bits into one.

(Other embodiments)
In each of the above embodiments, the case of handling 10-bit data has been described, but it is also possible to handle 12-bit or higher, which is a higher resolution. In this case, the number of cells composed of 32 transistors may be increased according to the number of bits. Note that the decoder 40, the inverter unit 50, the switching unit 60, and the like may correspond to 12 bits.

  In each of the above embodiments, the arrangement of the transistors in the cell is 4 × 8, but may be an arrangement of 2 × 16, for example.

  In each of the above embodiments, a laser diode is used as a load. However, it may be used such that a D / A converted signal is input to another load.

1 is an overall circuit diagram of a current addition type high resolution D / A converter according to an embodiment of the present invention. It is the figure which showed the circuit layout of the electric current addition type high resolution D / A converter shown by FIG. It is the figure which showed the circuit of the switching part corresponding to 0 bits-4 bits, and a PMOS current mirror circuit part in the current addition type high resolution D / A converter which concerns on 2nd Embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Amplifying part, 20 ... Current mirror circuit part for input, 30 ... Constant current current mirror circuit part, 40 ... Decoder, 60 ... Switching part, 70 ... Current mirror circuit part for output

Claims (2)

A current addition type high resolution D / A converter that converts the reference voltage (VA) into a current by the amplifying unit (10) and D / A converts a signal input from the outside to the decoder (40) based on the current. There,
A plurality of Nch type transistors (31 to 37) are provided, a plurality of constant current current mirror circuits each including the transistors are provided, and the current converted by the amplifying unit is passed through the input current mirror circuit unit (20). And a constant current current mirror circuit section (30) that is folded back by the constant current current mirror circuit;
A plurality of differential pair transistors composed of Nch type transistors (61a, 61b to 68a, 68b) are provided, and the output of the decoder (40) is input to one of the differential pair transistors, and the other is A switching unit (60) for switching whether a current input from each of the constant current current mirror circuits of the constant current current mirror circuit unit is supplied to ground or output by inputting an inverted output of the decoder;
A plurality of Pch type transistors (71a, 71b to 78a, 78b) are provided, and a plurality of output current mirror circuits composed of the transistors are provided, and a current input from the switching unit is used as the output current mirror circuit. And an output current mirror circuit section (70) for outputting the sum of the outputs of the output current mirror circuits to the outside.
The constant current current mirror circuit unit, the switching unit, and the output current mirror circuit unit are provided with the constant current current mirror circuit, the differential pair transistor, and the output current mirror circuit corresponding to the order of bits, respectively. The gate structure of each of the transistors constituting the constant current current mirror circuit, the differential pair transistor, and the output current mirror circuit is unified, and the number of transistors according to the order of bits. Each constant current mirror circuit, each differential pair transistor, and each output current mirror circuit are weighted according to the order of bits by being configured,
Furthermore, the constant current current mirror circuit unit, the switching unit, and the output current mirror circuit unit are each configured by a cell in which each of the transistors constituting them is gathered in a certain number, and according to the order of bits, A current addition type high resolution D / A converter characterized in that each cell is combined. Each of the constant current current mirror circuit unit, the switching unit, and the output current mirror circuit unit is configured by one cell in which transistors corresponding to 0 bits to 4 bits are combined when the bit order is 0 bits to 4 bits. When the bit order is 5 bits, each transistor corresponding to 5 bits is composed of one cell, and when the bit order is 6 bits or more, a plurality of cells corresponding to 5 bits are combined. The current addition type high resolution D / A converter according to claim 1.

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