WO2023110110A1

WO2023110110A1 - Current-steering digital to analog converter

Info

Publication number: WO2023110110A1
Application number: PCT/EP2021/086345
Authority: WO
Inventors: Pavel ANGELOV; Niklas Andersson; Lars SUNDSTRÖM; Sunny SHARMA; Martin Andersson
Original assignee: Telefonaktiebolaget Lm Ericsson (Publ)
Priority date: 2021-12-16
Filing date: 2021-12-16
Publication date: 2023-06-22

Abstract

Herein, a current-steering digital to analog converter, IDAC, (100), comprising a first DAC cell (110) and a second DAC cell (120) is presented. The first DAC cell (110) comprises a first reference current generator (114), and a first switch device (112) connected to the first reference current generator (114) and arranged to be controlled by a first data signal (D_n) for providing a first analog output current (I₁) based on the first data signal (D_n). The second DAC cell (120) comprises a second reference current generator (124), a second switch device (122) arranged to be controlled by a second data signal (D_m) for providing a second analog output current (I_2O) based on the second data signal (D_m), and a second current-splitting circuit (125). The second current-splitting circuit (125) configured to provide a split of a current in a second current path (P124), connecting the second analog output current (I_2O) to the second reference current generator (124), into at least a second output current path (P_2O) for the second analog output current (I_2O) and a second auxiliary current path (P_2A) for a second auxiliary output current (I_2A). The second switch device (122) is connected between the second reference current generator (124) and the second current-splitting circuit (125).

Description

CURRENT-STEERING DIGITAL TO ANALOG CONVERTER

TECHNICAL FIELD

The present invention relates to a current driver and more precisely to a current driver circuit using a current-splitting technique.

BACKGROUND

The conversion of signals from the digital domain to the analog domain is a task generally performed by digital-to-analog converters (DACs). DACs are used in electronic equipment of all fields where there is a need to convert a digital signal to an analog signal. Within many of these fields, there is a demand for increased bandwidth and e.g. wireless communication standards such as 5G and beyond are likely to use ever higher bandwidth and carrier frequencies compared to current standards. This evolution poses stringent requirements on the DACs used in e.g. transmitters as they need to maintain high linearity, high SNR, low levels of spurs, and other emission contributions in the output signal spectrum. Sampling rates reaching 10’s of GHz may be needed to generate high bandwidth baseband transmitter signals or even the RF signal directly and thereby enabling bypassing of the up-conversion in the analog domain altogether. Such high capability DACs are anything but trivial to design and they are paired with extremely tight requirements on every sub-block

As is generally known for a binary-scaled current steering DAC, a set of binary signals d_n, d_n+1, d_n+2, ... serve as input to the DAC. Each binary signal d_ne{— 1,1} is driving an associated DAC cell and is weighted by a corresponding weight w_n of the DAC cell. The response of the DAC cell is filtered by a corresponding transfer function H_n(f) associated with the DAC cell. The weights may e.g. be binary weighted, i.e. W(n+i)/w_n=2, and in a circuit implementation the weight may be represented by a DC reference current that is switched by an associated binary signal. The preferred transfer function H_n(f) should in most cases be flat in amplitude and group delay frequency response for the frequency range of interest. Furthermore, in order for the relationships between the bit weights to remain constant during code transitions, the transfer functions H_n(f) should be identical for all DAC cells. Unfortunately, it is anything but, and it is a direct consequence of the circuit implementation e.g. the kind of circuit process technology being used, the circuit topology, etc. Often H_n(f) has a predominately a low-pass characteristic related to the settling behavior after each switching event.

The linearity performance heavily depends on ensuring very accurate relations between the weights w_n of the DAC cells.

One way of trying to maximize the matching is to design all cells being based on the same small unit cell. For example, a conventional binary -weighted 10-bit DAC architecture may be constructed from an array of 1023 unit cells and where the least significant bit (LSB) controls one DAC cell with one unit cell, the next higher significant bit controls a DAC cell with two unit cells etc. This technique is not suitable for RF signal generation and high sampling rates, as the overhead in signal routing etc. becomes quite excessive, which in turn reduce bandwidth substantially.

Another way of implementing the DAC architecture is to have a full custom design of every DAC cell. In doing so, it is possible to customize each DAC cell to be no more accurate than necessary in every regard. This generally leads to high bandwidth and low power consumption. Unfortunately, it will also maximize the uncertainty in matching, and each DAC cell would have to have the means to calibrate both weight and transfer function as those would vary differently with manufacturing process variation, supply Voltage, and Temperature (PVT). Equally important, means to estimate the errors to guide the calibration are needed.

In US 9,577,657 Bl, weight mismatch is calibrated by calibration of an associated reference current. To reduce amplitude and timing errors of DAC bits, deltasigma patterns are provided to two bit cells, a reference bit cell and a bit cell under calibration, to perform, e.g., amplitude calibration and timing skew calibration.

SUMMARY

It is in view of the above considerations and others that the various embodiments of this disclosure have been made. The present disclosure therefore recognizes the fact that there is a need for improvement of the existing art described above. It is a general object of the embodiments described herein to provide a new type of current-steering digital to analog converter which is improved over the prior art and which eliminates or at least mitigates one or more of the drawbacks discussed above. More specifically, an object of the embodiments discussed in this disclosure is to provide a current-steering digital to analog converter providing efficient and accurate weight scaling, matching between weights and their respective transfer functions.

This general object has been addressed by the appended independent claims. Advantageous embodiments are defined in the appended dependent claims.

In a first aspect, a current-steering digital to analog converter (ID AC) comprising a first DAC cell and a second DAC cell is presented. The first DAC cell comprises a first reference current generator, and a first switch device connected to the first reference current generator and arranged to be controlled by a first data signal for providing a first analog output current based on the first data signal. The second DAC cell comprises a second reference current generator, a second switch device arranged to be controlled by a second data signal for providing a second analog output current based on the second data signal, and a second current-splitting circuit. The second currentsplitting circuit is configured to provide a split of a current in a second current path, connecting the second analog output current to the second reference current generator, into at least a second output current path for the second analog output current and a second auxiliary current path for a second auxiliary output current. The second switch device is connected between the second reference current generator and the second current-splitting circuit.

In one variant, the second reference current generator has a size that is identical to a size of the first reference current generator. This is beneficial as the currents from the reference current generators will be equal and the output current of the second DAC cell will be determined based on other circuit differences between the first DAC cell and the DAC cell, e.g. the second current-splitting circuit. Furthermore, having the same size and nominal current means that the dynamic behavior of the reference current generators as well as the switch device of the DAC cell match better over process voltage and temperature variations as well as nominally. In one variant, a size of the first switch device is identical to a size of the second switch device. This is beneficial as the circuit differences between the first DAC cell and the second DAC cells are reduced and thereby the relation between a weight and/or a transfer functions of the first DAC cell and the second DAC cell may be more accurately controlled.

In one variant, the first DAC cell is configured with a first weight determined based on the first reference current generator and the second DAC cell is configured with a second weight determined based on the second reference current generator and the second current-splitting circuit. This is beneficial as it allows for a more accurately controlled relation between the weight of the first DAC cell and the second DAC cell.

In one variant, the second current-splitting circuit comprises a main cascode transistor and an auxiliary cascode transistor connected together. The main cascode transistor is configured to provide the second output current path and the auxiliary cascode transistor is configured to provide the second auxiliary current path. Cascode devices are beneficial as, apart from their traditional use to provide high output impedance and thereby improved isolation, they allow a current splitting circuit with a precise current splitting ratio to be built.

In one variant, the second weight is determined based on a configuration of the main cascode transistor and a configuration of the auxiliary cascode transistor. This is beneficial as transistor configuration may be accurately controlled and thereby the accuracy of the weight increases.

In one variant, the configurations of the main cascode transistor and the auxiliary cascode transistor comprise a channel width of the main cascode transistor and the auxiliary cascode transistor. This is beneficial as the channel width-to-length ratio of a transistor may be accurately controlled and thereby the accuracy of the weight increases.

In one variant, the second weight is determined by a relationship between the channel width-of the main cascode transistor and the channel width of the auxiliary cascode transistor. This is beneficial as the channel width of a transistor may be accurately controlled and thereby the accuracy of the weight increases. In one variant, the ID AC further comprises a voltage following device configured to duplicate a voltage of the second output current path onto the second auxiliary current path. This is beneficial as the load presented on the second auxiliary current path will be more similar to that on the second output current path which increases the accuracy and control of the currents split by the second current-splitting circuit. This further assists in keeping voltages across both the output current path and the auxiliary current path the same, which in turn, ensures that the output impedance of the current splitting device does not influence the current splitting ratio, and therefore it does not influence the bit weight.

In one variant, the voltage following device is a common-drain stage.

In one variant, the second current-splitting circuit further comprises an auxiliary voltage source configured to bias the second auxiliary current path. This is beneficial as it offers a simple and comparably straight forward approach to enable that one or more operating conditions for the second auxiliary current path can be controlled and more similar to that on the second output current path which increases the accuracy and control of the currents split by the second current-splitting circuit. In one variant, the auxiliary voltage source is configured to bias the second auxiliary current path at a DC voltage equal to a common mode voltage of the second output current path. This is beneficial as it minimizes the magnitude of the variation of the bit weight caused by variation of operating conditions of the devices comprising the current splitting device when an instantaneous output voltage varies

In one variant, the auxiliary voltage source comprises a common mode detector configured to detect a common mode voltage of the second output current path and bias the second auxiliary current path based on the detected common mode voltage. This is beneficial as any variations of the common mode voltage, due to e.g. temperature variations, at the second output current path will be automatically transferred to the auxiliary current path. Thus, a magnitude of the bit weight variation caused by the finite output impedance of the current splitting device when the output voltage varies will be reduced.

In one variant, the common mode detector is configured to control a unity gain amplifier of the second current-splitting circuit to bias the signal lines of the second output current path based on the detected common mode voltage. This is beneficial as the unity -gain amplifier can be designed with high output current driving capability thus ensuring accurate voltage control at the auxiliary current path.

In one variant, the second current-splitting circuit is configured to cross couple each second auxiliary current path for the second analog auxiliary current, to a second output current path for the second analog output current of opposite phase to the second auxiliary output current. This is beneficial as a DC voltage at an output of the second auxiliary current path will be identical to that at an output of the second output current path which will increase the accuracy and control of the currents split by the second current-splitting circuit.

In one variant, the second weight is different from the first weight.

In one variant, the IDAC further comprises a third DAC cell. The third DAC cell comprises a third reference current generator, a third switch device arranged to be controlled by a third data signal for providing a third analog output current based on the third data signal and a third current-splitting circuit. Wherein the third current-splitting circuit is configured to provide a split of a current in a third current path, connecting the third analog output current to the third reference current generator, into at least a third output current path for the third analog output current and a third auxiliary current path for a third auxiliary output current. The third switch device is connected between the third reference current generator and the third current-splitting circuit.

In one variant, the first DAC cell further comprises a first current-splitting circuit configured to provide a split of a current in a first current path, connecting the first analog output current to the first reference current generator, into at least a first output current path for the first analog output current and a first auxiliary current path for a first auxiliary output current. The first switch device is connected between the first reference current generator and the first current-splitting circuit.

In a second aspect, an integrated circuit (IC) is presented. The IC comprises the current-steering digital to analog converter of the first aspect.

In a third aspect, an electronic apparatus is presented. The electronic apparatus comprises the current-steering digital to analog converter according to the first aspect.

In one variant, the electronic apparatus is a network node. In one variant, the network node is a base station for a cellular communications network.

In one variant, the electronic apparatus is a wireless device.

In one variant, the wireless device is a user equipment for a cellular communications network.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the invention will be described in the following; references being made to the appended diagrammatical drawings which illustrate non-limiting examples of how the inventive concept can be reduced into practice.

Fig. l is a block diagram of a current-steering digital to analog converter (IDAC);

Fig. 2 a block diagram of a current-steering digital to analog converter according to embodiments of the present disclosure;

Fig. 3a is a simplified schematic of a single ended DAC cell according to embodiments of the present disclosure;

Fig. 3b is a simplified schematic of a differential DAC cell according to embodiments of the present disclosure;

Fig. 4a is a simplified schematic of a single ended DAC cell according to embodiments of the present disclosure;

Fig. 4b is a simplified schematic of a differential DAC cell according to embodiments of the present disclosure;

Fig. 4c is a simplified schematic of a single ended DAC cell according to embodiments of the present disclosure;

Fig. 5 is a perspective view of a transistor;

Figs. 6a-b are simplified schematic of differential DAC cells according to embodiments of the present disclosure;

Fig. 6c is a partial block diagram of an IDAC according to embodiments of the present disclosure;

Figs. 7a-c are simplified schematic of differential DAC cells according to embodiments of the present disclosure; Fig. 8 is a simplified schematic of a differential DAC cell according to embodiments of the present disclosure;

Fig. 9 is a simplified schematic of a differential DAC cell according to embodiments of the present disclosure;

Fig. 10 is a simplified schematic of a differential DAC cell according to embodiments of the present disclosure;

Fig. 11 is a block diagram of an ID AC according to embodiments of the present disclosure;

Fig. 12 is a simplified schematic of a driver circuit for an IDAC according to embodiments of the present disclosure;

Figs. 13a-b are schematic views of an integrated circuit according to embodiments of the present disclosure;

Figs. 14a-c are schematic views of electronic equipment according to embodiments of the present disclosure; and

Fig. 15 is a schematic view of a communications network according to embodiments of the present disclosure.

DETAILED DESCRIPTION

Hereinafter, certain embodiments will be described more fully with reference to the accompanying drawings. The teachings herein may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided by way of example so that this disclosure will be thorough and complete, and will fully convey the scope as it is defined in the appended claims, to those skilled in the art.

The term "coupled" is defined as connected, although not necessarily directly, and not necessarily mechanically. Two or more items that are "coupled" may be integral with each other. The terms "a" and "an" are defined as one or more unless this disclosure explicitly requires otherwise. The terms "substantially," "approximately," and "about" are defined as largely, but not necessarily wholly what is specified, as understood by a person of ordinary skill in the art. The terms "comprise" (and any form of comprise, such as "comprises" and "comprising"), "have" (and any form of have, such as "has" and "having"), "include" (and any form of include, such as "includes" and "including") and "contain" (and any form of contain, such as "contains" and "containing") are open-ended linking verbs. As a result, a method that "comprises," "has," "includes" or "contains" one or more steps possesses those one or more steps, but is not limited to possessing only those one or more steps.

With reference to Fig. 1, a simplified schematic view of a current-steering digital to analog converter (ID AC) is shown. The ID AC of Fig. 1 is differential which means that the binary signals d_n, d_n+1, d_n+2 serving as input to the ID AC control an associated switch SI, S2, S3 to switch a corresponding current source II, 12, 13 to either a positive load Lp or a negative load Lm. A DAC cell is defined as the current source II, 12, 13 and the switch SI, S2, S3, each DAC cell converts one binary signal d_n, d_n+1, d_n+2to an analogue current corresponding to its associated current source II, 12, 13. A weight w_n, w_n+1, w_n+2 of a DAC cell is the current it provides to the load Lm, Lp, i.e. the current provided by the current source II, 12, 13 including any losses and filtering provided by circuit components between the current source and the load Lm, Lp. In order to have an output that is linear in response to any binary signals d_n, d_n+1, d_n+2, the weights w_n, w_n+1, w_n+2 has to be scaled correctly. Generally, there are no restrictions on the relations between the weights w_n, w_n+1, w_n+2 of the DAC cells. However, for the sake of explanations, a binary scaled DAC cell is considered. This implies that least significant bits (LSB) will be associated with a unit DAC cell, i.e. it will have the lowest weight and provide the lowest current to the load Lm, Lp. The second least significant bit is preferably associated with a weight that is double that of the unit DAC cell and so on to the most significant bit (MSB).

A common architecture for IDACs is a mix of using a small unit DAC cell and fully customized design DAC cell. The DAC is divided into a few segments, say one for the MSBs, one for the intermediately significant bits (ISBs), and one for the LSBs. Then each segment may be optimized. However, within each segment a unit cell tailored for that segment is the preferred implementation. Any mismatches that remains are primarily those between the segments and less so within the segments. With this architecture, the number of parameters to calibrate is reduced substantially. But, a need to estimate and compensate for at least the transfer function mismatch remains. With reference to Fig. 2, an ID AC 100, with focus on high frequency signal generation will be presented. The ID AC of Fig. 2 is shown as comprising a first DAC cell 110 and a second DAC cell 120, but it may very well comprise any number of DAC cells and embodiments with more DAC cells will be presented in other parts of this disclosure. The first DAC cell 110 is driven by first binary data signal signals D_n and the second DAC cell 120 is driven by a second binary data signal D_m. The DAC cells 110, 120 are connected together to produce a composite output current from the ID AC 100 to be delivered to a load A. The first DAC cell 110 comprises a first reference current generator 114, and a first switch device 112 configured to be controlled by the first data signal D_n for providing a first analog output current Iio based on the first data signal D_n. The first switch device 112 is connected to the first reference current generator 114. Preferably, the first switch device 112 is arranged upstream from the first reference current generator 114, as illustrated in Fig. 2. In other words, the first switch device 112 is arranged such that a current provided by the first reference current generator 114 is flowing from the first switch device 112 to the first reference current generator 114. It may also be described as the first switch device 112 being arranged between a node connecting the first DAC cell 110 and the second DAC cell 120, i.e. where the composite output current is provided, and the first reference current generator 114. The second DAC cell 120 comprises a second reference current generator 124 and a second switch device 122 configured to be controlled by the second data signal D_m for providing a second analog output current I20. The second switch device 122 is connected to the second reference current generator 124. Preferably, the second switch device 122 is arranged upstream from the second reference current generator 124, as illustrated in Fig. 2. Or, as with the first DAC cell 110, the second switch device 122 is arranged such that a current provided by the second reference current generator 124 is flowing from the second switch device 122 to the second reference current generator 124. It may also be described as the second switch device 122 being arranged between the node connecting the first DAC cell 110 and the second DAC cell 120, i.e. where the composite output current is provided, and the second reference current generator 124. In addition to this, the second DAC cell comprises a second current-splitting circuit 125 configured to provide a split of a current in a second current path P124 connecting the second analog output current I20 to the second reference current generator 124. The second current path P124 is split into at least a second output current path P20 for the second analog output current I20 and a second auxiliary current path P2A for a second auxiliary output current DA. The switch devices 112, 122 are sometimes referred to as drivers 112, 122. As seen in Fig. 2, the second switch device 122 is connected between the second reference current generator 124 and the second current-splitting circuit 125. This means that the second current path P124 is split, from the second reference current generator 124, after data has been latched by the second switch device 122. Optionally the first DAC cell 110 may in some embodiments be provided with a first currentsplitting circuit 115. Similarly to the second current-splitting circuit 125, the first current-splitting circuit 115 may be configured to provide a split of a current in a first current path Pi 14 connecting the first analog output current I10 to the first reference current generator 114, into at least a first output current path Pio for the first analog output current I10 and a first auxiliary current path PIA for a first auxiliary output current IIA. Preferably, the first switch device 112 is connected between the first reference current generator 114 and the first current-splitting circuit 115.

The ID AC 100 of Fig. 2 is improved over the prior art in at least that it does not rely on segmentation in previously known forms. As is known, segments require individual delay estimation and correction, no matter if the segmentation is achieved in analog or digital domain as such processing adds risks, cost, and circuit complexity this is without providing fully matched dynamic characteristics between the different segments. The presented ID AC provides a cell scaling with improved dynamic matching beyond what is possible with the prior art scaling means as those are generally focused on balancing the delays by equalizing cell driver loads.

In Fig. 3a, a simplified circuit implementation of the first DAC cell 110 according to one single ended embodiment is shown. In this embodiment, the first current-splitting circuit 115 comprises a cascode transistor 116. The first currentsplitting circuit 115 is arranged in the first current path Pi 14 for the first output current I10 connected to the first switch device 112. The first switch device 112 is connected to the first reference current generator 114. The first switch device 112 is, in the embodiment of Fig. 3a, implemented as a switch transistor 113 controlled by the first data signal D_n. The first switch device 112 and the first current-splitting circuit 115 form a cascade connection to the first reference current generator 114.

In Fig. 3b, a simplified circuit implementation of the first DAC cell 110 according to one differential embodiment is shown. The differential first DAC cell 110 correspond to the single ended DAC cell but is configured to provide the first output current Iio as a positive first output current Iiop and a negative first output current Iiom. Each first output current Iiop, Iiom is provided on a respective positive first current path Pii4p and a negative first current path Pii4m. The first current-splitting circuit 115 is, in this differential embodiment, provided with a positive cascode transistor 116p in the positive first current path Pn4_P and a negative cascode transistor 116m in the negative first current path Pii4m. The first switch device 112 comprises, in the embodiment of Fig. 3b, a positive switch transistor 113p in the positive first current path Pn4_P controlled by the first data signal D_n and a negative switch transistor 113m in the negative first current path Pii4m controlled by an inverse of the first data signal D_n. One single first reference current generator 114 is preferably configured to provide the current for both the positive first current path Pn4_P and the negative first current path Pii4m. The first switch device 112 and the first current-splitting circuit 115 form a cascade connection to the first reference current generator 114 in both the positive first current path Pn4p and the negative first current path Pii4m. It should be noted that the first current-splitting circuit 115, as will be clear from the teachings herein, may further be configured to split the first current path Pii4p, Pii4m into at least a first output current path Piop, Piom (not shown) for the first analog output current Iiop, Iiom and a first auxiliary current path PIA_P, PiAm (not shown) for a first auxiliary output current IIA_P, I1A m (not shown).

In Fig. 4a, a simplified circuit implementation of the second DAC cell 120 according to one single ended embodiment is shown. In this embodiment, the second current-splitting circuit 125 comprises a main cascode transistor 126 and an auxiliary cascode transistor 127. The main cascode transistor 126 and the auxiliary cascode transistor 127 are connected to the second current path P124 wherein the main cascode transistor 126 is configured to form a part the second output current path P20 from the second current path P124 and the auxiliary cascode transistor 127 is configured to form a part the second auxiliary current path P2A from the second current path P124. The second switch device 122 is arranged in the second current path P124 i.e. between the main cascode transistor 126 and the auxiliary cascode transistor 127 of the second currentsplitting circuit 125 and the second reference current generator 114. In other words, the second current path P124 is split into the second output current path P20 and the second auxiliary current path P2A between the second switch device 122 and the currentsplitting circuit 125. The second switch device 122 is, in the embodiment of Fig. 4a, implemented as a switch transistor 123 controlled by the second data signal D_n. The second switch device 122 and the second current-splitting circuit 125 form a cascade connection to the second reference current generator 114.

In Fig. 4b, a simplified circuit implementation of the second DAC cell 120 according to one differential embodiment is shown. This is similar to the difference between the single ended first DAC cell 110 of Fig. 3a and the differential first DAC cell 110 of Fig. 3b. In the embodiment of Fig. 4b, the second current-splitting circuit 125 comprises a positive main cascode transistor 126p, a negative main cascode transistor 126m, a positive auxiliary cascode transistor 127p and a negative auxiliary cascode transistors 127p. The positive main cascode transistor 126p and the positive auxiliary cascode transistor 127p are connected to a positive second current path Pi24p wherein the positive main cascode transistor 126p is configured to form a part of a positive second output current path P20P from the positive second current path Pi24p and the positive auxiliary cascode transistor 127p is configured to form a part of a positive second auxiliary current path P2A_P from the positive second current path Pi24p. The negative main cascode transistor 126m and the negative auxiliary cascode transistor 127m are connected to a negative second current path Pi24m wherein the negative main cascode transistor 126m is configured to form a part of a negative second output current path P20m from the negative second current path Pi24m and the negative auxiliary cascode transistor 127m is configured to form a part of a negative second auxiliary current path P2A_P from the negative second current path Pi24m. The second switch device 122 is arranged in the second current path P124 i.e. between the main cascode transistors 126p, 126m and the auxiliary cascode transistors 127p, 127m of the second currentsplitting circuit 125 and the second reference current generator 114. The second switch device 122 comprises, in the embodiment of Fig. 4b, a positive switch transistor 123p in the positive second current path Pi24p controlled by the second data signal D_m and a negative switch transistor 123m in the negative second current path Pi24m controlled by an inverse of the second data signal D_m. In other words, the positive second current path Pi24p is split into the positive second output current path P2Op and the positive second auxiliary current path P2A_P between the second switch device 122 and the currentsplitting circuit 125. Similarly, the negative second current path Pi24m is split into the negative second output current path P20m and the negative second auxiliary current path P2A, between the second switch device 122 and the current-splitting circuit 125. The second switch device 122 and the second current-splitting circuit 125 form a cascade connection to the second reference current generator 124 in both the positive second current path Pi24p and the negative second current path Pi24m.

The current-splitting circuits 115, 125 are preferably implemented by cascode transistors 126, 126p, 126m, 127, 127p, 127m, which may use thick oxide devices to handle the large output power requirements. Large output power implies a high voltage swing at the output current paths Pio, P20 and any auxiliary output paths PIA, P2A. For linearity purposes, it is beneficial to not completely turn these cascode transistors 126, 126p 126m, 127, 127p, 127m off. For this reason, the cascode transistors 126, 126p, 126m, 127, 127p, 127m, may be configured to operate at a DC (or quiescent) current larger than the current of the current source 114, 124. This is accomplished by applying a bias voltage Vb to the gates of the transistors in the current-splitting circuits 115, 125, and a bias current source I_b, see Fig. 4c, connected between e.g. ground and a node between the reference current splitting circuit 115, 125 and the switch device 112, 122. In Fig. 4c, this is illustrated in relation to the single ended embodiment of the second DAC cell 120, but the skilled person will understand after reading this disclosure, that the corresponding arrangement may be applied to any of the embodiments herein. Based on this, the first current splitting circuit 115 may in some embodiments be configured with a bias current determined by a bias current source Ib of the first DAC cell 110. This bias current is provided regardless of the state of the first switch device 112. Correspondingly, the second current splitting circuit 125 may in some embodiments be configured with a bias current determined by a bias current source Ib of the second DAC cell 120. This bias current is provided regardless of the state of the second switch device 122. As indicated above, the bias current will increase the linearity of the DAC cell 110, 120.

Anyone skilled in the art of current-steering DACs appreciates that the DAC cells 110, 120 presented herein are simplified for the sake of clarity. One such simplification not visualized in all embodiment are the above explained bias current sources lb configured to control the operating point of the cascode transistors 126, 126p, 126m, 127, 127p, 127m independently from the reference current sources. As previously mentioned, the use of bias current sources lb is compatible with any embodiment of the DAC cells 110, 120 disclosed herein. Further to this, the DAC cells 110, 120 may include any other suitable circuit elements that are known best practice techniques.

The embodiments presented above enable the creation of a unit cell from the first DAC cell 110 having a first weight w comprising at least of a reference current source 114, a set of switches 113, and a first and, in differential operation, second cascode device 116p, 116m associated with respective output net of a differential output. The second DAC cell 120 is preferably identical to the first DAC cell 110 in every aspect except that each of the cascode devices 116p, 116m, is split in two parts, having common source and gate terminals and separate drain terminals, to form one differential main output and one differential (or single-ended) auxiliary output. The splitting of the cascode translates to current attenuation (splitting) such that the main output will only output current in relation to size of first and second part of the split cascode.

As taught by the present disclosure, digital data signals D_n, D_m are supplied to the ID AC 100 together with a clock (not shown). The data signals D_n, D_m received are encoded to generate control signals that in turn controls a number of differential output current generating DAC cells 110, 120. Each DAC cell 110, 120 provides an output current Iio, I20 that is combined with the output currents I10, 120 of other cells 110, 120 to yield a sum of DAC cell currents that is delivered to a load A. A DAC cell 110, 120 may also provide an auxiliary output current EA. The ID AC 100 will comprise at least two DAC cells 110, 120. Some DAC cells 110, 120 may be arranged to form a set of thermometer coded DAC cells 110, 120. Other DAC cells 110, 120 may be arranged to form a set of binary coded DAC cells 110, 120 and may represented by a number of DAC cells 110, 120 that are scaled to generate binary scaled currents. These are but some examples, and other scaling principles may also be considered. Preferably, the first DAC cell 110 is configured with the first weight w and the second DAC cell is configured with a second weight w₂

where the second DAC cell 120 is based on the circuit topology and sizing as described herein.

In the following, the basic principle of weight scaling according to the present disclosure will be explained by comparing Fig. 3b to Fig. 4b. The starting point is the first DAC cell 110 of Fig. 3b. At the bottom of the first DAC cell 110, as illustrated in Fig 3b, there is a first reference current generator 114, that in an exemplary embodiment may be configured to provide a reference current I_s. Above, as illustrated in Fig 3b, the first reference current generator 114, the first switch device 112 is provided with its two switches 113p, 113m. It should be mentioned that other switching schemes can be used too, like quad-switching. The switches 113p, 113m of the first switch device are configured to either direct the reference current I_s to the left or right output via either cascode transistor 116p, 116m depending on the first data signal D_n, D_n. As mentioned, the first DAC cell 110 is associated with a first weight w that is related to the reference current I_s provide by the first reference current generator 114 and therefore to the magnitude of current provided by the first DAC cell 110. Assume, as way of exemplifying, that a channel width W (see Fig. 5) of each cascode transistor 116p, 116m is represented by m₁₁₆, which, typically but not always, is an integer multiplier representing a number of unit devices connected in parallel. The differential output current from the first DAC cell 110 is given by I_lout = I_10p — I_10m- Below, I_lout, I_10p, and I_10m will refer to the currents in this first DAC cell 110 and DAC cells with scaling will relate to these quantities.

To represent a weight less than w the circuit in Fig. 4b is used. The first reference current generator 114 and second reference current generator 124 together with the first switching device 112 and the second switch device 122 are preferably designed/ drawn to be substantially the same irrespective of the targeted weight equal to or smaller than w_n. Being the same in this respect meaning that they are substantially equal, or in other words, that the same building blocks are used when creating these components for the first DAC cell 110 and the second DAC cell 120. The skilled person will appreciate that although specified to be equal, this is to mean substantially equal taking normal process variations and spread into account. The splitting by the second current-splitting circuit 125 is what determines the effective weight w₂ of second DAC cell 120. The first current-splitting circuit 115 of Fig. 3b comprises two cascode transistors 116p, 116m, and the second current-splitting circuit 125 may be seen as a split of the first current-splitting circuit 115 into two parts; a first part 126p, 126m with drain connected to provide the positive second output current hop and the negative second output current hom; and a second part 127p, 127m with drain connected to provide the positive second auxiliary output current LAP and the negative second auxiliary output current IiAm. Assume, as way of exemplifying, that the channel width W of the main cascode transistor 126p, 126m is equal and represented by m₁₂₆ and that a channel width of the auxiliary cascode transistor 127p, 127m is equal and represented If so, the second current-splitting circuit 125 is configured such that m₁₂₆ = m₁₂₇ and m₁₂₆ + m₁₂₇ = m₁₂₅ where m₁₂₅ is preferably the same as the channel width 77*116 °f the cascode devices 116pm 116p of the first current-splitting circuit 115. In other embodiment, the second current-splitting circuit 125 is configured such that 77*126 77*127, which makes it possible to configure the second output current I_2out =

^2Op ~ ^2Om Such that

In order to further benefit from the scaling provided by the second currentsplitting circuit 125, it is preferable to configure the second reference current generator 124 with a size that is substantially identical to a size of the first reference current generator 114. Accordingly, it may further, or alternatively, be considered to configure the second switch device 122 with a size that is substantially identical to a size of the first switch device 112. As is known, the weight of the DAC cells 110, 120 is determined by a maximum current delivered by the DAC cell 110, 120. Consequently, it should be understood that, in view of this, the size reference above is to mean the features of the switch devices 112, 122 and the reference current generators 110, 120 affecting their contribution to the weight of the associated DAC cell 110, 120. The size of a reference current generator may in other words refer to the nominal current it provides, the physical dimensions of the devices comprising it, their electrical strength, etc. Furthermore, having the same size and nominal current means that the dynamic behavior of the reference current generators 110, 120 as well as the switch device 112, 122 of the DAC cells 110, 120 matches better over process voltage and temperature variations as well as nominally.

There are several beneficial effects stemming from the teaching of this disclosure, and a non-limiting selection comprises the effect that nominal dynamic weight scaling mismatch due to scaling while minimizing process mismatch is avoided. This thereby substantially improves the linearity of the ID AC 100 when generating RF signals at several GHz and higher. In addition to this, a need for driver load scaling, and/or driver scaling is removed thereby assuring that no systematic timing mismatch in the digital domain occurs. The teachings herein also orthogonalize design requirements of DAC cells 110, 120 by allowing the unit current, i.e. substantially the current provided by the first reference current generator 114, to be selected independently from a current desired for other subsequent DAC cells including an LSB DAC cell. This provides more freedom to select the transistor operating points and to obtain a high speed of internal nodes of the DAC cells. As the DAC cells are scaled, it is possible to allow areas of the devices making up the DAC cells to be selected large enough to fulfill requirements for random mismatch. Furthermore, it is possible to physically place the devices, i.e. DAC cells, whose ratio determines the bit weight very close together, this minimizes mismatch and differential nonlinearity (DNL.)

The examples given above with regards to the scaling of the second weight w₂ in relation to the first weight w , i.e. the weight of the second DAC cell 120 in relation to the weight of the first DAC cell 110, were given with reference to the channel width W, or width W, (see Fig. 5) of the cascode transistors 126p, 126m, 127p, 127m. Particularly, the second weight w₂ was described as determined by a relationship between the width m₁₂₆ of the main cascode transistor 126, 126p, 126m and the width ^mi27 °f the auxiliary cascode transistor 127, 127p, 127m. However, according to the teachings herein, the second weight w₂ may be determined based on a configuration of the main cascode transistor 126, 126p, 126m, if present, and a configuration of the auxiliary cascode transistors 127, 127p, 127m.

As an alternative, or an addition, to the width m₁₁₆, m₁₂₆, m₁₂₇, such configurations may comprise a multiplier, a number of fins, a number of fingers, a length, a bias configuration etc. The configuration of the cascode transistors 126, 126p, 126m, 127, 127p, 127m may in one embodiment comprise an effective-width w_e i2₆, w_e i27 and an effective length L₁₂₆, L₁₂₇. The effective-width w_{e 126}, w_{e 127} may be a function of the channel width, multiplier, number of fins and fingers, such that a an effective-width-to-length ratio w_{e 126}/LI₂₆, w_{e l27}/L₁₂₇ of the main and auxiliary cascode transistors 126p, 126m, 127p, 127m may be obtained. It should be mentioned that preferably, the effective lengths L₁₂₆, L₁₂₇ are substantially the same between the cascade transistors and the effective widths w_{e 126}, w_{e 127} are configured to obtain the desired effect.

Fig. 5 illustrates a principal geometry of a basic N-type C MOS (complementary metal-oxide-silicon) transistor 900 in bulk CMOS technology. A transistor channel 910 is formed, in a p-type substrate or a well 920, between the source and drain n-type diffusion layer 923, 925 with a gate layer 960 on top of the channel 910 separated by an insulating (oxide) layer 960. In this geometry, there is a length 1 of the channel 910 represented by the gate structure length 1 in the direction of the channel 910 between source 930 and drain 940. Correspondingly, there is a width W of the channel 910, the channel width W, represented by the gate structure width W as shown in the Fig. 5. The width W and length 1 typically refer to dimensions of geometries as drawn in IC CAD layout tools. From Fig. 5 it is readily understood that a transistor 900 with a width w can be split in two to give two transistors 900 with same length 1 but having different widths Wi and W2 such that Wi+W2=W. Alternatively the transistor 900 may be split in say N equisized transistors 900, each having a width W/N. Correspondingly, a transistor 900 with a channel width W can be duplicated M times to yield M transistors 900. If the terminals of the M transistors 900 are connected together, they will form a larger transistor 900 with an equivalent width of M*W. In fact, this latter approach, starting with a smaller unit transistor 900 and then duplicating it to yield an accurately scaled transistor (in integer increments) with regards to the width W, is a design technique that yields the best possible matching with other transistors based on the same unit transistor 900. It is also worth noting that the duplication of unit transistors 900 as described above can be simplified by observing that unit transistors 900 can be laid out such that the source 930 and drain layers 940 can be shared between neighboring unit transistors 900. This gives a transistor geometry with alternating source 930 and drain 940 layers with multiple gates, often referred to as fingers, where the number of fingers becomes an important design parameter to represent the multiplicity of the unit transistor.

Transistor geometries more advanced than bulk CMOS are often used today including e.g. FD-SOI and FinFET. FD-SOI (fully-depleted silicon-on-insulator) transistors are similar to bulk CMOS transistors with regards to the dimensional parameters width and length. The FinFET (fin field-effect-transistor) geometry however is quite different, its geometry is naturally discretized as the channel is formed by a fin structure (extending the transistor channel into the vertical third dimension), with the gate on the sides and on the top of the fin. Since the fins have a fixed height and width, a larger transistor may generally only be created by connecting together multiples of such unit transistors, hence multiples of fins, it is not possible to scale the width of the transistor continuously as is the case for bulk CMOS and FD-SOI transistors. But regardless of what kind of transistor geometry and technology being used, it is clear that one can always start with a unit transistor 900, multiply it, and connect all unit transistors 900 in parallel to form a transistor with a width being an integer of the width of the unit transistor 900, or accordingly, one can start with an M unit transistor and divide it in say two parts each consisting of an integer number of unit cells.

The accuracy of weight scaling by cascode splitting may depend on the ability to maintain the same voltage waveforms, including DC components, on all the terminals of the split cascode parts. From a load perspective of the first DAC cell 110, the first current path Piu, Pii4p, Pii4m will be subjected to an output voltage from all DAC cells of the ID AC 100 as the currents from all cells are combined and fed to the common load A. Consequently, in order to further increase the accuracy of the weight scaling, and ensure that a current flowing in second current path P124, Pi24p, Pi24m is substantially equal to a current flowing in the first current path P114, Pii4p, Pii4m, the second auxiliary current path P2A, P2Ap, P2Am is preferably subjected to a load, i.e. voltage, substantially equal to a load of the second output current path P20, P2Op, P20m and a second auxiliary current path P₂A, P2Ap, P2Am.

Fig. 6a illustrates a second DAC cell 120 according to some embodiments of the present disclosure that has increased weight scaling precision by controlling a load presented to the second auxiliary current path P2A, P2A_P, P2Am. In Fig. 6a, this is accomplished by configuring a voltage following device 128 to inject a voltage of the second output current paths P2O_P, P20m onto the second auxiliary current paths P2A_P, P2Am. This means that a voltage v_p, v_m from the main outputs to P2o_p, P20m is transferred to a voltage v'_p, v'_m at the auxiliary outputs such that v'_p « v_p and v'_m ~ v_m. In one embodiment, the voltage following device 128 may be implemented as a common-drain (CD) stage as shown in Fig. 6b. This embodiment will yield an offset in the transferred voltage v'_p, v'_m such that v'_p ~ v_p — V_gs and v'_m

is a gate-source voltage of the CD stage. The current sources shown in the middle of Fig. 6b aim to sink a DC current from the CD stage to maintain a more stable operating point when the second DAC cell 120 is operating with the currents being switched, i.e. when the second data signal D_m, D_m. changes state.

In the above the main output voltage is copied to the auxiliary output locally within a DAC cell, in close proximity (adjacent) to the split cascodes, i.e. the auxiliary cascode transistor 127, 127p, 127m of the second current-splitting circuit 125. This enables the smallest possible delay (and widest bandwidth) in the voltage following device 128. When this is of less concern it is also possible to have a common voltage following device for at least two DAC cells and where the second auxiliary current paths P2A_P, P2Am of those least two cells are connected together. This is illustrated in Fig. 6c showing a block diagram of a connection between the second DAC cell 120 and a third DAC cell 130. The third DAC cell 130 will be further explained with reference to Fig. 11, and the main takeaway from Fig. 6c is that one common voltage following device 128 is used to inject a voltage of the load A onto both the second auxiliary current path P2A and a third auxiliary current path P3A from a third current-splitting circuit 135 of the third DAC cell 130. An alternative embodiment of the second DAC cell 120 with increased weight scaling precision by controlling a load presented to the second auxiliary current path P2A, P2Ap, P2Am will be explained with reference to Figs. 7a-c. In some scenarios it is more important (or sufficient) to maintain a DC voltage on the auxiliary output paths P2A, P2Ap, P2Am in correspondence to the DC voltage delivered to the load A. In other words, the signal part of the voltage delivered to the load A is less important and may consequently be neglected. This is particularly true if the load A of the ID AC has a low impedance such that a signal voltage swing across the load A and at the auxiliary output paths P2A, P2A_P, P2Am becomes low. Preferably the drain terminals of the auxiliary cascode transistors 127mp 127m is biased at a voltage close to that of the common mode voltage of the DC voltage delivered to the load A. Furthermore, the drain terminals of the auxiliary cascode transistors 127p, 127m may be connected together as illustrated in Fig. 7a. Fig. 7a further illustrates a basic configuration where an auxiliary voltage source 129 biases the drain terminals of the auxiliary cascode transistors 127p, 127m. A more elaborate scheme is outlined in Fig. 7b wherein a common mode detector 129cm drives a unity gain voltage amplifier 129g such that a common mode voltage V_cm may be approximated as V_cm « (v_p + v_m) /2, where v_p is a voltage of the positive second output current path P2Op and v_m is a voltage of the negative second output current path P20m. As for the embodiments of Figs. 6a-c, the teachings related to the auxiliary voltage source 129 may be implemented locally within a DAC cell 110, 120, 130, as shown in Figs. 7a-c, or made common for at least two cells analogously to the teachings of Fig. 6c.

Since the sum of the currents of the auxiliary output paths P2A, P2Ap, P2Am is statically independent of the input code, i.e. the data of the data signals D_n, D_m, the voltage on an auxiliary paths P2A, P2Ap, P2Am may be derived by drawing this current through a resistor 129, see Fig. 7c. An impedance of the resistor 129 is selected such that a voltage bias of the auxiliary paths P2A, P2Ap, P2Am is substantially the common mode voltage delivered to the load A. To that end the circuit in Fig. 7c may be viewed as a practical implementation of Fig. 7a. The resistor 129 is preferably connected to a suitable DC voltage higher than the common mode voltage delivered to the load A. This solution does not suffer from bandwidth limitations and is preferred when an output impedance of the current-splitting circuit 115, 125, 135 is high enough such that some error of the common mode voltage delivered to the load A may be tolerated.

Fig. 8 illustrates an alternative embodiment of the second DAC cell 120 with increased weight scaling precision by controlling a load presented to the second auxiliary current path P2A, PiAp, PiAm. The embodiment of Fig. 8 does not require any additional components to maintain an auxiliary output common mode voltage of the auxiliary paths P2A, P2Ap, P2Am aligned with the common mode voltage delivered to the load A. Following the justification above for cases when the signal swing at the load A may be disregarded, and where it becomes more important to secure the common mode level than tracking a signal voltage waveform; one may connect the auxiliary current paths P2A, P2Ap, P₂Amin a cross-coupled fashion as shown in Fig 8. This means that, in this embodiment, the second current-splitting circuit 125 is configured to cross couple each second auxiliary current path P2A_P, P2Am for the second analog auxiliary current l2Ap, l2Am, to the second output current path P20P, P20m for the second analog output current hop, hom of opposite phase to the second auxiliary output current HAP, l2Am. In other words, the positive second auxiliary current path P2A_P is coupled to the negative second output current path P20m and the negative second auxiliary current path P2Am is connected to the positive second output current path P20p. However, in this embodiment, the weight scaling in relation to the widths of the split cascode devices will be different from the example described above. More precisely a differential output current i_outcc, iⁿ relation a positive differential output current i_pcc and a negative differential output current i_mcc, of the cross-coupled second DAC cell 120 of Fig. 8 becomes:

Furthermore, with this approach the main output nodes will not only be loaded by the parasitic capacitances associated with the drains of the main cascode transistors 126, 126p, 126m but also of the auxiliary cascode transistors 127, 127p, 127m. Whether or not this affects the high frequency performance or not will depend on the impedance of the load A presented to the ID AC 100.

In Fig. 9, a more elaborate scheme is shown that may be based on any of the above techniques or embodiments. The scheme of Fig. 9 involves splitting a DAC cell 110, 120, 130 into a first sub DAC cell 120a and a second sub DAC dell 120b where cascode devices 126pa, 126ma, 127pa, 127ma of the current-splitting circuit 125a of the first sub cell 120a is split slightly different from cascade devices 126pb, 126mb, 127pb, 127mb of the current-splitting circuit 125b of the second sub cell 120b to yield a Vernier-like scaling. This embodiment may be referred to as double-splitting (ds) as splitting is done on both cell level and cascode level. As a result of the split, the second output currents hop, hom are a subtraction of currents in the output current paths P2Opa, P20ma, P2Opb, P20mb of the first a second sub DAC cells 120a, 120b. This will yield a small weight of the second DAC cell 120. A generalization would allow also the switch devices 122a, 122b and the current sources 124a, 124b to be different. However, the switch devices 122a, 122b and the current sources 124a, 124b are preferably equal as this will improve matching properties and will increase the overall accuracy of the second DAC cell 120. For the sake of simplicity in explaining the technique, assume, in the present embodiment, that any difference in splitting only applies to the cascode devices 126pa, 126ma, 127pa, 127ma, 126pb, 126mb, 127pb, 127mb. Thus, one may assume that the switch devices 122a, 122b are designed to be identical as well as the current sources 124a, 124b I_124a ⁼ 24&) but that the cascodes are scaled slightly different and where the two sub cells 120a, 120b are connected to yield a current subtraction such that

Assume that the starting point, i.e. a unit cell or the first DAC cell 110, is a cascade, i.e. a current-splitting circuit 115, 125, 135 with total width m₁₂₅ = ni._125a + m_125b = ^mi26a + ^mi27a + ^mi26b + ^mi27b ⁼ 16 and that the basic technique described in previously in this disclosure when comparing Fig. 4b to Fig. 3b is used. This means that the cascode splitting may accomplish down scaling of a weight of a DAC cell to 1/16 of the non-split cell weight, e.g. a unit cell or the first DAC cell 110 (compared to the Fig. 4b wherein

Now, consider an exemplary embodiment where it is not allowed to use a total width higher than m₁₂₅ = 16. In the double-split technique, one may then choose the next lower odd number to get the smallest possible difference between the two cell halves 120a, 120b, i.e. m₁₂₅ = 15 = m_125a + m_125Z, = 7 + 8. The output current i_2out of the second DAC cell 120 then becomes

This exemplary embodiment yields a smallest weight of 1/56 of the original case largest weight without any cascade splitting, i.e. almost 4x smaller compared to the basic cascode splitting of e.g. Fig. 4b.

The embodiment of the double splitting technique as illustrated in Fig. 9 may be modified as shown in an alternative embodiment as illustrated in Fig. 10. In this embodiment, the second DAC cell 120 is, as in Fig. 9, split into a first sub DAC cell 120a and a second sub DAC dell 120b where cascode devices 126pa, 126ma, 127pa, 127ma of the current-splitting circuit 125a of the first sub cell 120a is split slightly different from cascade devices 126pb, 126mb, 127pb, 127mb of the current-splitting circuit 125b of the second sub cell 120b. However, the combination of the outputs of the sub DAC cells 120a, 120b differs from the embodiment in Fig. 9. In Fig. 10, the positive second output current hop is formed by adding the positive second output current hopb of the second sub DAC cell 120b to the positive second output current hopa of the first sub DAC cell 120a. In Fig. 9, the positive second output current hop is formed by adding the negative second output current homb of the second sub DAC cell 120b to the positive second output current hop_a of the first sub DAC cell 120a. Corresponding differences can be seen for the negative second output current hom and the scaling formulas presented above are adjusted accordingly, e.g. I_2out ⁼ hop ~

It should be mentioned that is may seem tempting to assume a larger width (^mns) to start with, e.g. a width m₁₁₅ of the first current-splitting circuit 115. Basically, it is possible to select the starting width m₁₁₅ arbitrarily large to get to any scaling. However, in the design of a DAC cell there is a minimum size of a unit transistor that one can then multiply to give a larger (wider) transistor. The size of this unit transistor may not be determined by limitations in lithography chip process being used, but rather, and more importantly, by a design choice to get the desired performance (e.g. the lowest parasitic capacitances and resistors per unit width of transistor, and/or the best matching properties, etc.). It is also worth noting here that it is not always that one targets a strictly binary scaling, using non-binary DAC weight leads to a more complicated encoder design but there are other benefits, e.g. that INL breaks (due to weight mismatch) can be redistributed to yield a smaller impact, e.g. on the ID AC 100 linearity and consequently on undesired emissions in the ID AC 100 output signal spectrum. In other words, more elaborates schemes for scaling, as allowed by the double-splitting method, can be justified in some applications.

Turning briefly to Fig. 11, one further embodiment if the ID AC 100 will be presented. In this embodiment, the ID AC 100 comprises the first DAC cell 100, the second DAC cell 120 and one or more additional DAC cells including the third DAC cell 130. The IDAC 100 may comprise any number of DAC cells in addition to the three illustrated in Fig. 11 and the skilled person will, after digesting the teachings of this disclosure, know how to apply the current splitting techniques taught herein on any number of DAC cells. The third DAC cell 130 is configured similarly to the second DAC cell 120 but preferably with a weight w_n+2 that differs from the weight w_n, w_n+1 of the other DAC cells 110, 120. The third DAC cell 130 is driven by a third binary data signal Di. The third DAC cell 130 is connected together with any other DAC cells 110, 120 of the IDAC 100 to produce the composite output current from the IDAC 100 to be delivered to the load A. The third DAC cell 130 further comprises a third reference current generator 134 and a third switch device 132 configured to be controlled by the third data signal Di for providing a third analog output current I30. In addition to this, the third DAC cell 130 comprises a third current-splitting circuit 135 configured to provide a split of a current in a third current path P134 connecting the third analog output current I30 to the third reference current generator 134. The third current path P134 is split into at least a third output current path P30 for the third analog output current I30 and a third auxiliary current path P3A for a third auxiliary output current FA. As in the embodiment of in Fig. 2, the third switch devices 112, 122, 132 are connected between the reference current generator 114, 124, 134 and the current-splitting circuit 115, 125, 135 of the associated DAC cell 110, 120, 130.

Most of the embodiments of this disclosure have been focused on the second DAC cell 120, but the skilled person will appreciate, after reading this disclosure, that these embodiments may be applied to any DAC cell 110, 120, 130, including the first DAC cell 110. The relationship between the DAC cells 110, 120, 130 of the IDAC 100, or particularly the weights of the DAC cells 110, 120, 130, is what the current splitting technique taught herein focuses on.

Generally, the data signals D_n, D_m, Di at inputs of the DAC cells 110, 120, 130 are updated in synchrony, usually to a reference clock signal, CLK, such that the DAC cells 110, 120, 130 are only ever configured to output analog levels corresponding to the set of binary signals D. This is known as glitch-free operation. A delay through any given logic circuitry is dependent on a combination of circuit parameters, e.g. device size, threshold voltages, driving strength, output load and self-load, input slew rate etc. The input slew rate means that the delay through a given gate depends not only on its intrinsic parameters, but also, on how its inputs are driven. Therefore, since the circuit parameters vary randomly for each circuit instance, in order to minimize the delay variation of otherwise identical chains of CMOS gates, it is important to minimize both the number of devices involved as well as the number of intermediate nodes that have to transition each time clock and/or data changes state. Spread in delay between DAC cells 110, 120, 130 will introduce glitches when the binary signal is updated, i.e. changes state. It is generally known that, in order to maintain an operating point of a reference current generator used to drive a DAC cell 110, 120, 130, and therefore, the linearity of an IDAC 100, it is necessary to ensure that a conduction path for the reference current is maintained at all times.

In order to address these issues, a driver circuit 600 as illustrated in Fig. 12 may be introduced in some embodiments of the IDAC 650. The driver circuit 600 of Fig. 12 is a differential driver circuit 600, but the skilled person will be able to limit this to a single ended embodiment. The differential driver circuit 600 comprises a first single ended driver circuit 650 and a second single ended driver circuit 650, each according to any suitable embodiment of this disclosure. A positive drive signal S^p is provided by the first single ended driver circuit 650 by connecting a positive edge latched data signal S^+p of a first positive single-edge latch 800 of the first single ended driver circuit 650 to a negative edge latched data signal S'^p of a first negative singleedge latch 700 of the first single ended driver circuit 650. Similarly, a negative drive signal S^N is provided by connecting a positive edge latched data signal S^+N of a second positive single-edge latch 800 of the second single ended driver circuit 650 to a negative edge latched data signal S'^N of a second negative single-edge latch 700 of a second single ended driver circuit 650 of the second single ended driver circuit 650. The data signal D provided to the second positive single-edge latch 800 and the second negative single-edge latch 700 is an inverse of the data signal D’_n provided to the second positive single-edge latch 800 and the second negative single-edge latch 700. The drive signals S^N, S^p are for operatively connection to a DAC cell 110, 120, 130.

The first positive single-edge latch 800 is configured to provide the positive edge latched data signal S⁺ of the data signal D’_n. The second positive single-edge latch 800 is configured to provide the positive edge latched data signal S⁺ of an inverse of the data signal D’_n. In the following, the general workings of the first positive single-edge latch 800 will be given, but the same is true for the second positive single-edge latch 800. The positive single-edge latch 800 comprises a high side drive transistor 840, a first high side transistor switch 810, a first low side transistor switch 820 and a second low side transistor switch 830. The first high side transistor 810, the first low side transistor switch 820 and the second low side transistor switch 830 are connected in series between negative feed V- and a positive feed V+. The series connection is such that the low side transistor switches 820, 830 are arranged downstream from the first high side transistor switch 810. The first high side transistor switch 810 and the second low side transistor switch 830 are configured to be controlled by the data signal D’_n and the first low side transistor switch 820 is configured to be controlled by the first clock signal CLKi. The high side drive transistor 840 is controlled by an output signal D⁺ provided between the first high side transistor switch 810 and the series connection of the low side transistor switches 820, 830. The high side drive transistor 840 is configured to provide the positive edge latched data signal S⁺ at an open drain of the high side drive transistor 840. In the positive single-edge latch 800 of Fig. 12, when the data signal D’_n is low, the output signal D⁺ between the first high side transistor switch 810 and the series connection of the low side transistor switches 820, 830 will always be high regardless of the state of the first clock signal CLKi. In other words, as soon as the data signal D’_n goes low, the output signal D⁺ will go high and stay high at least for the duration of the data signal D being low. When the data signal D’_n is high, the output signal D⁺ will depend on the state of the first clock signal CLKi. If the data signal D’_n goes high at a point in time when first clock signal CLKi is also high, the output signal D⁺ will be driven low by the series connection of the low side transistor switches 820, 830. However, if the first clock signal CLKi is low when the data signal D’_n goes high, the output signal D⁺ will remain at a high state subject to e.g. gate source leakage currents of the high side drive transistor 840. However, when the first clock signal CLKi changes to a high state, the output signal D⁺ will be driven low and the gate of the high side drive transistor 840 will be discharged. As the positive edge latched data signal S⁺ is provided at an open drain of the high side drive transistor 840, it will be the inverse of the output signal D⁺ and, the positive single-edge latch 800 of Fig. 12 will only be able to drive the positive edge latched data signal S⁺ high and this will be in response to the data signal D’_n and the first clock signal CLKi being high at the same time.

In the positive single-edge latch 800 of Fig. 12, the working of the negative single-edge latch 700 are similar to those of the positive single-edge latch 800, but the negative single-edge latch 700 is configured to provide the negative edge latched data signal S' of the data signal D’_n. The negative single-edge latch 700 comprises a low side drive transistor 740, a first high side transistor switch 710, a second high side transistor switch 720 and a first low side transistor switch 730. The first high side transistor 710, the second high side transistor switch 720 and the first low side transistor switch 730 are connected in series between negative feed V' and a positive feed V⁺. The series connection is such that the high side transistor switches 710, 720 are arranged upstream from the first low side transistor switch 730. The first high side transistor switch 710 and the first low side transistor switch 730 are configured to be controlled by the data signal D and the second high side transistor switch 720 is configured to be controlled by the second clock signal CLK2. The low side drive transistor 740 is controlled by an output signal D' provided between the series connection of the high side transistor switches 710, 720 and the first low side transistor switch 730. The low side drive transistor 740 is preferably configured to provide the positive edge latched data signal S+ at an open source of the low side drive transistor 740.

In the negative single-edge latch 700 of Fig. 12, when the data signal D’_n is high, the output signal D' between the first low side transistor switch 730 and the series connection of the high side transistor switches 710, 3800 will always be low regardless of the state of the second clock signal CLK2. In other words, as soon as the data signal D goes high, the output signal D' will go low and stay low at least for the duration of the data signal D being high. When the data signal D is low, the output signal D' will depend on the state of the second clock signal CLK2. If the data signal D’_n goes low at a point in time when second clock signal CLK2 is also low, the output signal D' will be driven high by the series connection of the high side transistor switches 710, 720. However, if the second clock signal CLK2 is high when the data signal D’_n goes low, the output signal D' will remain at a low state. However, when the second clock signal CLK2 changes to a low state, the output signal D' will be driven high and the gate of the low side drive transistor 740 will be charged. As the negative edge latched data signal S' is provided at an open source of the low side drive transistor 740, it will be the inverse of the output signal D' and the negative single-edge latch 700 if Fig. 4 will only be able to drive the negative edge latched data signal S' low and this will be in response to the data signal D and the second clock signal CLK2 being low at the same time.

The driver circuit 600 as presented herein allows global generation of an on- state overlap and the possibility to share it with one, some or all DAC cells 110, 120, 130, the number of nodes in the timing critical path is greatly reduced which in turn reduces the current consumption of the circuitry as fewer gates needs to be switched. In the prior art, one clock signal is distributed to an array of switch drivers of a DAC and locally delayed to create the on-state overlap. In the present solution, two clocks CLKi, CLK2 are distributed to the array of switch drivers of the ID AC 100. One clock controls turn on events and the other clock controls turn off events, such that, in differential operation, when these clocks are mixed with the data signal D’, four separate signals are provided (four timing paths), each carrying one timing event. In addition, a delay period TD specifying the overlap time, i.e. the time both switches are conducting, may be generated globally for all timing paths and the resulting delay period TD may be distributed similarly to a main clock. Therefore, its timing skew contribution can be completely eliminated. Furthermore, since it is outside of the sensitive timing path, the circuit can be made substantially more advanced and still allows for lower random timing skew.

In Fig. 13a, one embodiment of an integrated circuit, IC, 300 is illustrated. The IC 300 comprises the IDAC 100 according to any of the embodiments presented herein. This is further illustrated in the block diagram of the IC 300 presented in Fig. 13b.

In Fig. 14a, one embodiment of an electronic apparatus 400 is shown. The electronic apparatus comprises the IDAC 100 according to any of the embodiments presented herein.

In Fig. 14b a further embodiment of the electronic apparatus 400 is illustrated wherein the electronic apparatus is a network node 400. In further embodiments, the network node 400 may be a base station 400 for a cellular communications network 500 (see Fig. 15).

In Fig. 14c, an alternative embodiment of the electronic apparatus 400 is shown. In this embodiment, the electronic apparatus is a wireless device 400. In further embodiments, the wireless device may be a user equipment 400 for the cellular communications network 500.

Fig. 15 shows one embodiment of a cellular communications network 500 comprising a user equipment 400 according to embodiments of the present disclosure and a base station 400 according to embodiments of the present disclosure.

Modifications and other variants of the described embodiments will come to mind to one skilled in the art having benefit of the teachings presented in the foregoing description and associated drawings. Therefore, it is to be understood that the embodiments are not limited to the specific example embodiments described in this disclosure and that modifications and other variants are intended to be included within the scope of this disclosure. For example, while embodiments of the invention have been described with reference to a current-steering digital to analog converter, persons skilled in the art will appreciate that the embodiments of the invention can equivalently be applied to other technical areas wherein accurate scaling of currents is important. Furthermore, although specific terms may be employed herein, they are used in a generic and descriptive sense only and not for purposes of limitation. Therefore, a person skilled in the art would recognize numerous variations to the described embodiments that would still fall within the scope of the appended claims. Furthermore, although individual features may be included in different claims (or embodiments), these may possibly advantageously be combined, and the inclusion of different claims (or embodiments) does not imply that a combination of features is not feasible and/or advantageous. In addition, singular references do not exclude a plurality. Finally, reference signs in the claims are provided merely as a clarifying example and should not be construed as limiting the scope of the claims in any way.

Claims

33 CLAIMS

1. A current-steering digital to analog converter, ID AC, (100), comprising a first DAC cell (110) and a second DAC cell (120), wherein: the first DAC cell (110) comprises: a first reference current generator (114), and a first switch device (112) connected to the first reference current generator (114) and arranged to be controlled by a first data signal (D_n) for providing a first analog output current (Ii, Ii_p, Iim) based on the first data signal (D_n); the second DAC cell (120) comprises: a second reference current generator (124), a second switch device (122) arranged to be controlled by a second data signal (D_m) for providing a second analog output current (I20, top, hom) based on the second data signal (D_m), and a second current-splitting circuit (125) configured to provide a split of a current in a second current path (P124, Pi24p, Pi24m), connecting the second analog output current (I20, 120P, hom) to the second reference current generator (124), into at least a second output current path (P20, P2Op, P20m) for the second analog output current (I20, l2Op, hom) and a second auxiliary current path (P2A, P2A_P, P2Am) for a second auxiliary output current (I2A, LA_P, l2Am); wherein the second switch device (122) is connected between the second reference current generator (124) and the second currentsplitting circuit (125).

2. The current-steering digital to analog converter (100) of claim 1, wherein the second reference current generator (124) has a size that is identical to a size of the first reference current generator (114). 34

3. The current-steering digital to analog converter (100) of claim 1 or 2, wherein a size of the first switch device (112) is identical to a size of the second switch device (122).

4. The current-steering digital to analog converter (100) of any of the preceding claim, wherein the first DAC cell (110) is configured with a first weight (Wi) determined based on the first reference current generator (114) and the second DAC cell (120) is configured with a second weight (W2) determined based on the second reference current generator (124) and the second current-splitting circuit (125).

5. The current-steering digital to analog converter (100) of any of the preceding claims, wherein the second current-splitting circuit (125) comprises a main cascode transistor (126, 126p, 126m) and an auxiliary cascode transistor (127, 127p, 127m) connected together, wherein the main cascode transistor (126, 126p, 126m) is configured to provide the second output current path (P20, P2Op, P20m) and the auxiliary cascode transistor (127, 127p, 127m) is configured to provide the second auxiliary current path (P₂A, P2Ap, P2Am).

6. The current-steering digital to analog converter (100) of claim 5, wherein the second weight (W2) is determined based on a configuration (wne) of the main cascode transistor (126, 126p, 126m) and a configuration (W127) of the auxiliary cascode transistor (127, 127p, 127m).

7. The current-steering digital to analog converter (100) of claim 6, wherein the configurations (wne) of the main cascode transistor (126, 126p, 126m) and the auxiliary cascode transistor (127, 127p, 127m) comprise a channel width (wi26, W127) of the main cascode transistor (126, 126p, 126m) and the auxiliary cascode transistor (127, 127p, 127m) .

8. The current-steering digital to analog converter (100) of claim 7, wherein the second weight (W2) is determined by a relationship between the channel width (mne) of the main cascode transistor (126, 126p, 126m) and the channel width (m 127) of the auxiliary cascode transistor (127, 127p, 127m).

9. The current-steering digital to analog converter (100) of the preceding claims, wherein the second current-splitting circuit (125) further comprises a voltage following device (128) configured to duplicate a voltage of the second output current path (P20, P2Op, P20m) onto the second auxiliary current path (P2A, P2Ap, P2Am).

10. The current-steering digital to analog converter (100) of claim 9, wherein the voltage following device (128) is a common-drain stage (127).

11. The current-steering digital to analog converter (100) of any of the claims 1 to 8, wherein the second current-splitting circuit (125) further comprises an auxiliary voltage source (129) configured to bias the second auxiliary current path (P2A, P2Ap, P2Am).

12. The current-steering digital to analog converter (100) of claim 11, wherein the auxiliary voltage source (129) is configured to bias the second auxiliary current path (P2A_P, P2Am) at a DC voltage equal to a common mode voltage of the second output current path (P2O_P, P20m).

13. The current-steering digital to analog converter (100) of claim 12, wherein the auxiliary voltage source (129) comprises a common mode detector (129cm) configured to detect a common mode voltage of the second output current path (P2O_P, P20m) and bias the second auxiliary current path (P2A_P, P2Am) based on the detected common mode voltage.

14. The current-steering digital to analog converter (100) of claim 13, wherein the common mode detector (129cm) is configured to control a unity gain amplifier (129g) of the second current-splitting circuit (125) to bias the signal lines of the second auxiliary current path (P2A_P, P2Am) based on the detected common mode voltage.

15. The current-steering digital to analog converter (100) of any of the preceding claims, wherein the second current-splitting circuit (125) is configured to cross couple each second auxiliary current path (P2Ap, P2Am) for the second analog auxiliary current (l2Ap, l2Am), to a second output current path (P2Op, P20m) for the second analog output current (hop, hom) of opposite phase to the second auxiliary output current (LAP, l2Am).

16. The current-steering digital to analog converter (100) of any of the preceding claims, wherein the second weight (W2) is different from the first weight (Wi).

17. The current-steering digital to analog converter (100) of any of the preceding claims, further comprising a third DAC cell (130), wherein the third DAC cell (130) comprises: a third reference current generator (134), a third switch device (132) arranged to be controlled by a third data signal (Di) for providing a third analog output current (I30, hop, bom) based on the third data signal (Di), and a third current-splitting circuit (135) configured to provide a split of a current in a third current path (P134, Pi34p, Pi34m), connecting the third analog output current (I30, Lop, bom) to the third reference current generator (134), into at least a third output current path (P30, P3Op, P30m) for the third analog output current (I30, hop, hom) and a third auxiliary current path (P3A, P3A_P, P3Am) for a third auxiliary output current (LA, LAP, l3Am); wherein the third switch device (132) is connected between the third reference current generator (134) and the third current-splitting circuit (125).

18. The current-steering digital to analog converter (100) of any of the preceding claims, wherein the first DAC cell (110) further comprises: 37 a first current-splitting circuit (115) configured to provide a split of a current in a first current path (Pin, Pii4p, Pii4m), connecting the first analog output current (Iio, Iiop, Iiom) to the first reference current generator (114), into at least a first output current path (Pio, Piop, Piom) for the first analog output current (Iio, Iiop, Iiom) and a first auxiliary current path (PIA, PIA_P, PiAm) for a first auxiliary output current (IIA, IIA_P, IiAm); wherein the first switch device (112) is connected between the first reference current generator (114) and the first current-splitting circuit (115).

19. An integrated circuit, IC, (300), comprising the current-steering digital to analog converter (100) of any of the preceding claims.

20. An electronic apparatus (400), comprising the current-steering digital to analog converter (100) of any of the claims 1 to 18.

21. The electronic apparatus (400) of claim 20, wherein the electronic apparatus is a network node (400).

22. The electronic apparatus (400) of claim 21, wherein the network node (400) is a base station (400) for a cellular communications network (500).

23. The electronic apparatus (400) of claim 20, wherein the electronic apparatus is a wireless device (400).

24. The electronic apparatus (400) of claim 23, wherein the wireless device (400) is a user equipment (400) for a cellular communications network (500).