JP2008066657A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the reliability and element characteristics, while the product cost for a semiconductor device that includes a high-power amplifying element is reduced. <P>SOLUTION: The semiconductor chip IC includes HBT, as a high electric power amplifying element, formed on the main face of a semiconductor substrate 1 made of a GaAs substrate; a back electrode 8 formed on a backside of the semiconductor substrate 1; and a bump electrode 13 electrically connected to the back electrode 8 and formed on the backside of the semiconductor substrate 1. The back electrode 8 electrically connected to a reference potential feed bump electrode 13b is formed over the entire backside of the semiconductor substrate 1 that excludes the peripheral portion of a signal bump electrode 13a. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing technique thereof, and more particularly to a technology that is effective when applied to a semiconductor device including a semiconductor element that handles a large current such as a large power amplifying element.

  In recent years, mobile communication devices represented by communication systems such as GSM (Global System for Mobile Communications) system, PCS (Personal Communication Systems) system, PDC (Personal Digital Cellular) system, and CDMA (Code Division Multiple Access) system (for example, mobile phones) Phone) is widespread worldwide.

  In general, this type of mobile communication device uses an antenna that radiates and receives radio waves, an RF (Radio Frequency) module that amplifies a power-modulated high-frequency signal and supplies it to the antenna, and processes the high-frequency signal received by the antenna. Receiving section, a control section for performing these controls, and a battery (battery) for supplying a power supply voltage thereto.

  Monolithic microwave integrated circuits (hereinafter referred to as “MMIC: Monolithic Microwave Integrated Circuits”) that constitute an RF module are, for example, active devices (such as transistors) on a semiconductor substrate such as gallium arsenide (GaAs) or silicon (Si). Microwave / power amplifiers) and passive devices (resistors, capacitors, coils, transmission lines), and passive functional circuits such as signal distribution / combination circuits, which are manufactured collectively and integrally through a semiconductor manufacturing process This is a millimeter wave band high frequency circuit.

  In the active element, a semiconductor element (power semiconductor element) that handles a large current such as a large power amplifier element that constitutes an MMIC, a DRAM (Dynamic Random Access Memory), and a nonvolatile memory (electrical writing and erasing) It can be classified into semiconductor elements that handle small currents used in memory LSIs such as EEPROM (Electrically Erasable Programmable Read Only Memory).

Incidentally, in an active element that handles a small current, a semiconductor chip having a stackable structure in which a bump electrode is provided on the back side of the substrate and a pad electrode is provided on the front side is disclosed in Japanese Patent Application Laid-Open No. 8-213427 (Patent Document 1). ), JP-A-2001-68618 (Patent Document 2) and JP-A-2001-60654 (Patent Document 3). Of these, Japanese Patent Application Laid-Open No. 8-213427 (Patent Document 1) discloses a structure of a semiconductor chip for the purpose of increasing the mounting density per unit volume.
JP-A-8-213427 JP 2001-68618 A JP 2001-60654 A

  The present inventor has studied a semiconductor device and an RF (Radio Frequency) module including a high power amplifier (HPA) such as a heterojunction bipolar transistor (hereinafter referred to as “HBT”). is doing. FIG. 14 is a layout diagram of a semiconductor chip (hereinafter referred to as “chip”) 100 on which, for example, an MMIC is formed, which constitutes the RF module studied by the present inventors. 15 is a cross-sectional view showing a state in which the chip 100 is disposed on the module substrate 114, and FIG. 16 is an enlarged cross-sectional view of the main part of FIG.

  As shown in FIG. 14, on the main surface (element formation surface) of a semiconductor substrate 101 made of, for example, a GaAs substrate constituting the chip 100, an HBT that is a high power amplification element, a capacitor, a resistor, and a coil that are passive elements are formed. Each layout area 126, 127, 128, 129 is shown. Further, the chip 100 employs a die bonding method, and a pad electrode 103 a for wire bonding is disposed on the outer peripheral side of the chip 100. Further, in order to dissipate the heat generated by the chip 100, a ViA 107 that is a through electrode in which a conductor is embedded in a hole penetrating from the back surface side to the main surface side of the semiconductor substrate 101 is disposed.

  As shown in FIGS. 15 and 16, the chip 100 is disposed on the module substrate 114 by a mounting method in which die bonding is performed using a die bonding material 116 such as Ag (silver) paste. Therefore, input / output of the RF signal is performed through the bonding wire 119, and a reference potential (GND) through which a large current flows flows from the back surface of the chip 100 to the module substrate 114 side through the ViA 107. Similarly, the heat generated by the chip 100, in particular, the heat generated by the HBT, is also dissipated through the ViA 107 to the module substrate 114 side. In configuring the RF module, in addition to the chip 100, an IC chip including a circuit associated with the MMIC is disposed on the module substrate 114.

  Since the GaAs substrate used as the semiconductor substrate 101 has a higher wafer unit price than the Si substrate, the chip area of the chip 100 is shrunk and the RF module is reduced to reduce the cost of the RF module using the chip 100 made of the GaAs substrate. Reduction of the mounting area is under consideration. If the mounting area on the RF module can be reduced in this way, the RF module can be reduced in size.

  However, when the die bonding method is adopted, the parasitic inductor component of the bonding wire is large, and this parasitic inductor causes deterioration of characteristics. That is, since the number of inductors for wiring including bonding wires increases, passive elements (capacitors, resistors, coils) formed on the same chip 100 together with the HBT as shown in FIG. 14 are arranged on another chip. That is, in addition to the chip including the HBT, another chip including the passive element cannot be disposed. For this reason, the passive element must be built in the chip 100 together with the HBT which is a high power amplifying element. This makes chip shrinking difficult.

  Further, since the chip 100 includes an HBT that is a high-power amplification element and heat generation becomes large, heat must be dissipated to the module substrate 114 via the ViA 107. For this reason, the chip size of the chip 100 becomes large in order to secure the ViA 107. When the chip size increases, the chip mounting portion in the module substrate 114 becomes a dead space, which makes it difficult to reduce the size of the RF module. In the present application, “dead space” refers to a case where a chip such as another active element cannot be disposed in a layout area where a chip (chip 100) including an HBT is disposed. .

  Further, the chip 100 causes a large current to flow to the module substrate 114 side through the ViA 107. However, when the thickness of the plating film made of, for example, Au (gold) constituting the back electrode 108 of the chip 100 is thin, an electromigration problem occurs. Resulting in. This can be dealt with by increasing the thickness of the plating film, but the cost increases because Au is used for the plating film.

  In addition, heat is dissipated through the ViA 107 to the module substrate 114, but if the heat dissipation effect is small, the characteristics and reliability of the HBT are adversely affected. For this reason, when ViA107 is increased and heat dissipation is improved, a chip area will become large and cost will increase. In other words, characteristics / reliability and cost are in a trade-off relationship.

  On the other hand, it is also conceivable to adopt a bump (BUMP) system as shown in Patent Documents 1 to 3 instead of the die bonding system. For example, a chip on which an HBT or the like is formed is mounted on a module substrate by a flip-chip method. However, when it is affected by electromagnetic noise generated by an HBT that is a semiconductor element that handles a large current, other elements have the same layout. Cannot be placed in the area. That is, other elements can be placed in the same layout area of a semiconductor element that handles a small current because electromagnetic noise from a semiconductor element that handles a small current is unlikely to affect other elements. However, when it is affected by electromagnetic noise, other elements cannot be arranged in the same layout area of a semiconductor element that handles a large current. For this reason, other elements are disposed outside the chip on which the HBT is formed, and the chip mounting portion becomes a dead space, making it difficult to reduce the size of the RF module.

  In general, in a chip adopting a bump method, a semiconductor element that handles a small current is formed instead of a semiconductor element such as an HBT that is a large current amplifying element capable of handling a large current. The electromagnetic wave noise from the semiconductor element having a small current hardly affects other elements. For this reason, in the techniques as shown in the above Patent Documents 1 to 3, when the influence of electromagnetic wave noise on other elements emitted by the HBT is taken into consideration, the HBT which is a large current amplifying element studied by the present inventor is used. Cannot be used for chips containing.

  An object of the present invention is to provide a technique capable of reducing the product cost, improving the reliability, and improving the element characteristics of a semiconductor device including a large power amplifying element.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  The semiconductor device according to the present invention is electrically connected to the HBT, which is a high power amplifying element formed on the main surface of a semiconductor substrate made of a GaAs substrate, the back electrode formed on the back surface of the semiconductor substrate, and the back electrode. A back electrode electrically connected to the reference potential supply bump electrode on the entire back surface of the semiconductor substrate excluding the periphery of the signal bump electrode. Is formed.

  In the method of manufacturing a semiconductor device according to the present invention, first, (a) a high power amplifying element is formed on the main surface of the semiconductor substrate. Next, (b) a plurality of pad electrodes including a signal pad electrode and a reference potential supply pad electrode which are electrically connected to the high power amplifier element are formed on the main surface of the semiconductor substrate. Next, (c) a plurality of through holes are formed in the semiconductor substrate from the back surface side of the semiconductor substrate to the back surfaces of the plurality of pad electrodes. Next, (d) a plurality of through electrodes are formed by filling a plurality of through holes with a conductor. Next, (e) a conductor film that covers the entire back surface of the semiconductor substrate and contacts the plurality of through electrodes is formed. Next, (f) a signal bump electrode electrically connected to the signal pad electrode and a reference potential supply pad electrically connected to the reference potential supply pad electrode through a plurality of through electrodes and a conductor film A plurality of bump electrodes including the bump electrodes are formed. At that time, after the step (e), the conductor film around the signal bump electrode is removed.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  According to the present invention, it is possible to reduce the product cost, improve the reliability, and improve the characteristics of a semiconductor device including a large power amplifying element.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted. Further, in order to facilitate understanding of the contents of the invention, even a plan view may be hatched.

(Embodiment 1)
In the first embodiment of the present invention, a semiconductor device including a semiconductor chip (hereinafter referred to as “chip”) will be described. In this chip, an HBT that is a large current amplifying element constituting the MMIC of the RF module is formed.

  1 to 3 are a plan view of the main surface (element forming surface) side of the chip 1C according to the first embodiment, a plan view of the back surface side, and a cross-sectional view taken along line XX. In FIGS. 1 and 2, the protective films 4 and 10 shown in FIG. 3 are removed.

  As shown in FIGS. 1 to 3, the chip 1 </ b> C includes a semiconductor substrate (hereinafter referred to as “substrate”) 1 made of, for example, a GaAs substrate, and an HBT (High Power Amplifying Element) formed on the main surface of the substrate 1. (Not shown). The HBT formed on the GaAs substrate has a shorter electron transit time than the Si device, and can increase the response speed of the transistor, that is, operate at a high frequency.

  Further, the chip 1C is arranged in a matrix on the main surface of the substrate 1 as shown in FIG. 1 and a plurality of pad electrodes 3 arranged and formed on the main surface of the substrate 1 and on the back surface thereof as shown in FIG. And a plurality of formed bump electrodes 13. The plurality of pad electrodes 3 correspond to the plurality of bump electrodes 13 and are electrically connected.

  Further, as shown in FIG. 3, the chip 1 </ b> C is formed on the substrate 1, and has a plurality of through holes 2 reaching the respective back surfaces of the plurality of pad electrodes 3 from the back surface side of the substrate 1, and conductors in the plurality of through holes 2. And a back electrode 8 made of a conductor film that contacts the plurality of ViA 7 and covers the back surface of the substrate 1.

  The plurality of ViAs 7 are formed with a plurality of through holes 2 reaching the respective back surfaces of the plurality of pad electrodes 3 disposed on the main surface of the substrate 1 from the back surface side of the substrate 1, and then the base electrode 8 a Is formed by sputtering or the like, and the inside of the through-hole 2 is filled with a conductive and heat-conductive conductor. The base electrode 8a is made of, for example, a Pt (platinum) / Ti (titanium) / Au (gold) film. Instead of Ti, Cr (chromium), TiW (titanium tungsten), Cu (copper), Ni (nickel), etc. can be applied instead of Au. Further, the ViA7 conductor is composed of an Au plating film, a Cu plating film, or solder using a plating method.

  Further, the back electrode 8 is composed of, for example, a Pt / Ti film formed by sputtering or the like on the entire back surface of the substrate 1 so as to cover the plurality of ViA 7, and an Au film formed by plating, for example. Patterning is performed using photolithography and etching. For this reason, ViA7 and the back surface electrode 8 are contacting. Instead of Ti, Cr (chromium), TiW (titanium tungsten), Cu (copper), Ni (nickel), etc. can be applied instead of Au. Further, instead of the Au plating film, a Cu plating film, a Ni plating film, a Cr plating film, or the like can be applied.

  As described above, the plurality of pad electrodes 3 are electrically connected to the plurality of bump electrodes 13 through the ViA 7 and the back electrode 8, respectively. The plurality of pad electrodes 3 include a signal pad electrode 3a and a reference potential (GND) supply pad electrode 3b which are electrically connected to the HBT which is a high power amplification element. The plurality of bump electrodes 13 include a signal bump electrode 13a electrically connected to the signal pad electrode 3a and a reference potential supply bump electrode 13b electrically connected to the reference potential supply pad electrode 3b. It is included.

  The back electrode 8 is patterned as described above, but is obtained by removing the conductive film (back electrode 8) around the signal bump electrode 13a. For this reason, the back electrode 8 disposed on almost the entire back surface of the substrate 1 is electrically connected to the reference potential supply bump electrode 13b. On the other hand, since the conductive film around the signal bump electrode 13a is removed, the signal bump electrode 13a and the reference potential supply bump electrode 13b are not electrically connected.

  Here, the back electrode 8 disposed on almost the entire back surface of the substrate 1 serves as a shield film that shields electromagnetic noise generated during operation. That is, the back surface electrode 8 formed on almost the entire back surface of the substrate 1 can be connected to the reference potential (GND) to have a shielding effect of blocking electromagnetic wave noise generated from the chip 1C.

  Further, stabilization of the reference potential (GND) line (power supply line) has a great influence on the element characteristics. For this reason, it is necessary to take measures such as making the power line as thick as possible. In this respect, since the back electrode 8 is provided on the entire back surface of the chip 1C, the power supply line can be stabilized.

  As shown in FIG. 3, the chip 1 </ b> C has a protective film 4 made of a SiN film, a polyimide film, or the like formed on the main surface of the substrate 1, and an opening 5 formed in the protective film 4 The surfaces of the plurality of pad electrodes 3 are exposed. The chip 1 </ b> C has a UBM (Under Bump Metal) 12 formed so as to cover the back electrode 8 exposed by the opening 11 formed in the protective film 10. In the chip 1 </ b> C, bumps are formed on the UBM 12. An electrode 13 is formed. As a material of the bump electrode 13, Au plating is desirable for improving electrical characteristics, but Cu plating or solder can be applied to reduce the product cost. In the first embodiment, the opening 5 is provided in the pad electrode 3, but the opening 5 may not be provided when electrically connected to the module substrate or the like by the bump electrode 13 on the back surface. .

  4 is a cross-sectional view showing a state in which the chip 1C is arranged on the module substrate 14, and FIG. 5 is a cross-sectional view showing an enlarged main part of FIG. On the surface of the module substrate 14, wirings 15 and elements not shown are formed. The bump electrode 13 of the chip 1C is connected to the wiring 15 on the module substrate 14. Thus, the wiring 15 includes an electrode connected to face the bump electrode 13.

  Here, the chip 100 mounted on the module substrate 114 by the die bonding method shown in FIGS. 15 and 16 will be described below.

  As shown in FIG. 15, the module substrate 114 has wiring 115 and passive elements (capacitance, resistance, coil) (not shown) and the like formed on the surface thereof. The chip 100 is disposed (mounted) on a wiring 115 serving as an electrode for supplying a reference potential (GND) on the module substrate 114 by a die bonding material 116. That is, the wiring 115 serving as the reference potential (GND) supply electrode on the module substrate 114 is electrically connected to the back electrode 108 and the pad electrode 103b of the chip 1C via the die bonding material 116 made of Ag paste. ing. Further, the pad electrode 103a of the chip 1C is electrically connected to the wiring 115 serving as the signal electrode via the bonding wire 119.

  As shown in FIG. 16, in the die bonding method, the cavity 117 is formed because the die bonding material 116 does not completely fill the through hole 102 penetrating from the back surface side to the main surface side of the substrate 101. Therefore, the current from the pad electrode 103b to the wiring 115 flows through the back electrode 108 made of the conductor film on the side surface of the ViA 107 to the wiring 115 serving as the reference potential (GND) supply electrode of the module substrate 114 (path 118).

  The current flowing through the ViA 107 is limited to the thickness (t) of the back electrode 108. In the HBT that is a large power amplifying element, it is necessary to increase the thickness of the conductor film constituting the back electrode 108 as a measure against electromigration in order to flow a large current. For this reason, for example, an Au plating film of about 5 to 10 μm is applied as the conductive film of the back electrode 108. Further, since the substrate 101 and the cavity 117 made of a GaAs substrate have very low thermal conductivity, the heat generated by the chip 100 is hardly diffused to the relay module 114 via the back electrode 108. That is, the heat dissipation also depends on the thickness (t) of the back electrode 108 made of a conductor film, and as the thickness decreases, the heat dissipation decreases. Further, it is desirable to use Au for the back electrode 108 from the viewpoint of electrical resistance and thermal conductivity. Therefore, when an Au plating film is used for the back electrode 108, the heat dissipation improves as the film thickness (t) is increased, while Au is expensive, so that the product cost increases. There is.

  However, in the present invention, as shown in FIGS. 4 and 5, since the through hole 2 is filled with a conductor, current can flow from the pad electrode 3 to the wiring 15 not only on the side wall of the ViA 7 but also on the entire ViA 7. Yes (path 18). Therefore, the resistance to electromigration is significantly improved. Similarly, since heat is dissipated in the entire ViA 7, the heat dissipation effect is also improved.

  Further, as shown in FIG. 16, in the die bonding method, an Au plating film is used for the back electrode 108 for electric resistance and thermal conductivity. However, in the present invention, as shown in FIGS. 4 and 5, both current and heat flow to the module substrate 14 through the ViA 7 and the bump electrode 13 (path 18). Further, it is not necessary to increase the thickness of the back electrode 108 for resistance to electromigration. For this reason, it is not necessary to use an expensive Au plating film for the back electrode 8. That is, an inexpensive Cr plating film or Ni plating film can be used, and the product cost can be reduced.

  Further, as shown in FIG. 15, in the die bonding method, the signal pad electrode 103a other than the reference potential supply pad electrode 103b is connected by wire bonding, and other than the pad electrode 103b passes through the bonding wire 119 and is heated. Will run away. For this reason, the die bonding method has poor heat dissipation. However, in the present invention, as shown in FIG. 4, all the pad electrodes 3 are connected to the bump electrodes 13, and there are more paths 18 through which heat escapes through the ViA 7, thereby improving the heat dissipation of the chip 1 </ b> C. This stabilizes the characteristics of the semiconductor device and improves the reliability.

  Next, a manufacturing method of the chip 1C shown in FIGS. 1 to 3 will be described with reference to FIGS. 6 to 11 are cross-sectional views schematically showing the semiconductor chip 1C during the manufacturing process. In addition, although HBT which is a high power amplification element will be formed in the main surface of the board | substrate 1 which comprises the chip | tip 1C, since it forms with a well-known manufacturing method, the description is abbreviate | omitted and about the process after that explain.

  After forming HBT (not shown) which is a high power amplification element on the main surface of the substrate 1, as shown in FIG. 6, after depositing a conductor film on the main surface of the substrate 1 by sputtering, photolithography and etching The pad electrode 3 is formed using a technique. The substrate 1 is made of, for example, an insulating GaAs substrate and has a thickness of about 625 nm, for example. The pad electrode 3 includes a signal pad electrode 3a and a reference potential supply pad electrode 3b that are electrically connected to the HBT.

  Subsequently, as shown in FIG. 7, a protective tape 31 is first attached to the main surface of the substrate 1, a wax material 32 is applied, and then a quartz glass substrate 33 is attached. These are performed in order to facilitate a process such as polishing on the substrate 1. Next, the back surface of the substrate 1 is ground and further etched for chamfering. Next, a through hole 2 reaching the back surface of the pad electrode 3 from the back surface side is formed in the substrate 1 using photolithography and etching techniques. For the etching, wet etching and dry etching are performed.

  Subsequently, as shown in FIG. 8, the base electrode 8 a is formed on the side wall of the through hole 2 and the back surface of the substrate 1. The base electrode 8a is made of, for example, a Pt / Ti / Au film using a sputtering method. Note that Cu, Ni, or Cr may be used instead of Au. Next, the through hole 2 is filled with a conductor to form a ViA 7 that is a through electrode.

  The filling of the through holes 2 is performed by, for example, printing a solder. At that time, after the base electrode 8a is formed, solder is applied (printed) to the entire back surface of the substrate 1 so as to embed the through hole 2, and then other than the solder embedded in the through hole 2 is removed by lift-off. .

  Further, instead of print printing, a plating method may be used. At that time, a conductor is filled inside the through hole 2 to form a ViA 7 as a through electrode. The conductor filling the through hole 2 by plating may be formed as a plated film of Ni, Cu, Al, etc., instead of expensive Au. Moreover, when using Cu as a plating film, you may form the bump electrode 13 which consists of Cu by continuing plating as it is.

  Subsequently, as shown in FIG. 9, a back electrode 8 made of a conductor film that covers the entire back surface of the substrate 1 and is in contact with the ViA 7 is formed. Specifically, after forming ViA7, a Pt / Ti / Au film is formed again by sputtering, and then a plating film is formed by plating. This plating film needs to be an Au plating film in the die bonding method investigated by the present inventor. However, in the present invention, the plating film may be formed of a metal such as Cu, Ni, or Cr that is less expensive than Au. When the Au plating film is not used for the back electrode 8, as described above, the resistance to electromigration and heat dissipation are not lowered, and the product cost can be reduced as compared with the case where the Au plating film is used.

  Subsequently, as shown in FIG. 10, the back electrode 8 made of a conductor film around the signal bump electrode 13a (not shown) is removed (patterned) using photolithography and etching techniques. For this reason, the back surface electrode 8 is connected only to the reference potential supply pad electrode 3b (reference potential supply bump electrode 13b).

  As described above, the back electrode 8 formed on almost the entire back surface of the substrate 1 can be connected to the reference potential (GND) to have a shielding effect of blocking electromagnetic wave noise generated from the chip 1C.

  Further, stabilization of the reference potential (GND) line (power supply line) has a great influence on the element characteristics. For this reason, it is necessary to take measures such as making the power line as thick as possible. In this respect, since the back electrode 8 is provided on the entire back surface of the chip 1C, the power supply line can be stabilized.

  Next, after depositing a protective film 10 made of, for example, a polyimide film covering the entire back surface of the substrate 1, an opening 11 that opens a peripheral region of the ViA 7 is formed in the protective film 10 to expose the back electrode 8. Next, a UBM (Under Bump Metal) 12 made of, for example, an Au plating film is formed using a plating method so as to cover the exposed back electrode 8.

  Subsequently, as shown in FIG. 11, bump electrodes 13 are formed on the UBM 12. In other words, the signal bump electrode 13a and the reference potential supply pad electrode 3b, which are electrically connected to the signal pad electrode 3a, are electrically connected via the through electrode ViA7 and the back electrode 8 made of a conductor film. A reference potential supply bump electrode 13b is formed.

  Next, after removing the glass substrate 33, the wax material 32 and the tape, a protective film 4 made of, for example, a polyimide film is deposited so as to cover the entire main surface of the substrate 1 so that the surface of the pad electrode 3 is exposed. Then, the opening 5 is formed in the protective film 4. Thereby, the semiconductor chip 1C as shown in FIG. 3 is almost completed.

  Such a chip 1C has improved electromigration resistance, thereby improving reliability and reducing product cost. That is, the chip 1 </ b> C can pass current through the entire ViA 7 instead of flowing current through the side surface of the ViA 7. Further, the chip 1C does not need to thicken the plating film of the back electrode 8 as a countermeasure against migration, and it is not necessary to use expensive Au.

  Further, the heat dissipation of the chip 1C is improved, so that the amplification characteristics are improved, the reliability is improved, and the product cost is further reduced. That is, the chip 1 </ b> C can release heat not in the side surface of the ViA 7 but in the entire ViA 7. Further, the chip 1C can be provided with a large number of ViAs 7 as heat dissipation paths. Further, the characteristics of the chip 1C are stabilized when the thermal gradient is reduced. Further, the junction temperature Tj of the HBT is lowered, and the reliability is improved. For this reason, it is not necessary to use an Au plating film having high thermal conductivity for the back electrode 8.

(Embodiment 2)
In the second embodiment, a laminated chip structure using the chip having the structure shown in the first embodiment will be described.

  As described above, FIG. 14 shows the layout of the chip 100 on which, for example, the MMIC that constitutes the RF module studied by the present inventor is formed. A main surface of a semiconductor substrate 101 made of a GaAs substrate constituting the chip 100 is formed with an HBT that is a high power amplifying element, a capacitor, a resistor, and a coil that are passive elements. The layout areas 126, 127, and 128 are respectively arranged. 129 is shown. The chip 100 employs a die bonding method, and a pad electrode 103 for wire bonding is disposed on the outer peripheral side of the chip 100. Furthermore, in order to dissipate the heat generated by 100 chips, a ViA 107 which is a through electrode in which a conductor is embedded in a hole penetrating from the back surface side to the main surface side of the substrate is disposed.

  In FIG. 14, the MMIC is composed of one chip 100. In the second embodiment, the MMIC including the HBT that is a large power amplifying element and the passive element is a chip including the HBT as shown in FIG. 1C and a chip 51C including passive elements are configured in a laminated chip structure as shown in FIG. FIG. 13 also shows a state in which a laminated chip structure is applied and two chips 1C and 51C are arranged (mounted) on the module substrate 14.

  As shown in FIG. 12A, an HBT is formed in the HBT layout area 26 on the main surface of the chip 1C. The chip 1C is the same chip as described in the first embodiment, and the substrate 1 constituting the chip 1C is made of an insulating GaAs substrate. The chip 1 </ b> C includes a pad electrode 3 formed on the main surface of the substrate 1, a through hole 2 formed on the substrate 1, reaching each back surface of the pad electrode 3 from the back surface side of the substrate 1, and through holes 2. ViA7, which is a through electrode formed by filling a conductor, and backside electrode 8 composed of a conductor film that contacts ViA7 and covers the backside of substrate 1, and ViA7 are each formed with a conductor film in between. And a bump electrode 13. The pad electrode 3 includes a signal pad electrode 3a and a reference potential supply pad electrode 3b which are electrically connected to the HBT which is a high power amplifying element, and the bump electrode 13 includes the back electrode 8 and the ViA7. Bump electrode for signal 13a electrically connected to signal pad electrode 3a via the reference electrode, and bump electrode for reference potential supply electrically connected to reference potential supply pad electrode 3b via back electrode 8 and ViA7 13b. A back electrode 8 is formed on the entire back surface of the substrate 1 except for the periphery of the signal bump electrode 13a.

  As shown in FIG. 12B, capacitors, resistors, and coils are formed in the capacitor layout area 27, the resistor layout area 28, and the coil layout area 29 on the main surface of the chip 51C. The substrate 51 constituting the chip 51 is made of a conductive Si substrate. The chip 51C is formed on the main surface of the substrate 51 and has a plurality of pad electrodes 53 that are electrically connected to passive elements (capacitors, resistors, and coils). In this manner, the passive element can be formed as an IPD (Integrated Passive Device) using a Si substrate that is cheaper than the GaAs substrate.

  Further, as shown in FIG. 13, the chip 51 </ b> C has a protective film 54 made of a polyimide film or the like formed on the main surface of the substrate 51, and the pad electrode 53 is formed by an opening formed in the protective film 54. The surface of is exposed. The chip 51 </ b> C is formed by connecting the bump electrode 63 to the pad electrode 58 exposed through the opening formed in the protective film 60. As a material of the bump electrode 63, Au plating is desirable for improving electrical characteristics, but Cu plating or solder can be applied to reduce the product cost. The bump electrode 63 and the pad electrode 53 are electrically connected via a ViA 57 formed by filling a through hole reaching the back surface of the pad electrode 53 from the back surface side of the substrate 51.

  As shown in FIG. 13, the chip 1C and the chip 51C have a laminated chip structure in which the pad electrode 53 is connected to face the reference potential supply bump electrode 13b and the signal bump electrode 13a, respectively. That is, the substrate 1 is disposed on a substrate 51 including a passive element and a pad electrode 53 electrically connected to the passive element, and the plurality of pad electrodes 53 of the substrate 51 are respectively opposed to the plurality of bump electrodes 13. Connecting. Thereby, a laminated chip structure is obtained.

  Further, as shown in FIG. 13, the module substrate 14 is formed with wiring 15 and elements not shown on the surface thereof. The bump electrode 63 of the chip 51C is connected to the wiring 15 on the module substrate. Thus, the wiring 15 includes an electrode connected to face the bump electrode 63.

  Such a chip 1 </ b> C can form a laminated chip structure together with a chip 51 </ b> C formed of a Si substrate on which ViA 57 is formed, and the size of the module can be reduced. That is, in the chip 1C, since the back electrode 8 serves as a shield, the chips can be stacked. Further, since the bump electrode 13b of the chip 1C is connected to the wiring 15 of the module substrate 14 via the ViA 57 of the chip 51C, a large current of the HBT formed on the chip 1C can flow. Further, since the back electrode 8 serves as a shield, the chip 51C can be disposed between the chip 1C and the module substrate 14 without considering the influence of electromagnetic noise.

  Further, as shown in FIG. 14, the HBT and the passive element are not formed on one chip 100 made of the GaAs substrate, but the HBT and the passive element are made of separate chips, thereby forming the expensive GaAs substrate. The chip can be shrunk. That is, by forming the HBT on the chip 1C made of the GaAs substrate and forming the passive element on the chip 51C made of the Si substrate instead of the GaAs substrate, the chip made of the expensive GaAs substrate can be shrunk. Product cost can be reduced. Further, by adopting the laminated chip structure, the passive element of the chip 51C can be disposed in the vicinity of the bump electrode 13 of the chip 1C, so that the parasitic inductor can be reduced.

  Further, by adopting the bump system instead of the bonding system chip 100 as shown in FIG. 14, it is not necessary to form the pad electrode 103a, and chip shrinking can be performed.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the above embodiment, the case where the semiconductor element that handles a large current is formed on the insulating GaAs substrate has been described, but such an element may be formed on the Si substrate. In this case, an insulating film is not provided on the side surface of the reference potential ViA connected to the back electrode, and an insulating film is provided on the side surface of the signal ViA. That is, the reference potential ViA is short-circuited to the Si substrate, and the signal ViA is separated from the Si substrate by the insulating film. For this reason, the power supply line can be stabilized.

  Further, for example, in the second embodiment, the laminated chip system composed of two semiconductor chips, that is, a semiconductor chip made of a GaAs substrate and a semiconductor chip made of a Si substrate has been described, but the invention is not limited to two semiconductor chips. The present invention can also be applied to a laminated chip system composed of two or more semiconductor chips.

  The present invention is widely used in the manufacturing industry for manufacturing semiconductor devices.

FIG. 3 is a plan view of the main surface side of the semiconductor chip in the first embodiment. FIG. 2 is a plan view of the back surface side of the semiconductor chip of FIG. 1. It is sectional drawing of the XX line of FIG. FIG. 2 is a cross-sectional view of a state in which the semiconductor chip of FIG. 1 is arranged on a module substrate. FIG. 5 is an enlarged cross-sectional view of FIG. 4. It is principal part sectional drawing in the manufacturing process of the semiconductor device in Embodiment 1 of this invention. FIG. 7 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 6; FIG. 8 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 7; FIG. 9 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 8; FIG. 10 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 9; FIG. 11 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 10; FIG. 6 is a plan view of the main surface side of two semiconductor chips in the present second embodiment, where (a) is a semiconductor chip composed of a GaAs substrate, and (b) is a semiconductor chip composed of a Si substrate. FIG. 13 is a cross-sectional view showing a state where two semiconductor chips of FIG. 12 are arranged on a module substrate. It is a top view of the main surface side of the semiconductor chip which the inventor is examining. FIG. 15 is a cross-sectional view of a state in which the semiconductor chip of FIG. 14 is arranged on a module substrate. It is sectional drawing to which FIG. 15 was expanded.

Explanation of symbols

1 Semiconductor substrate (substrate)
1C Semiconductor chip (chip)
2 Through-hole 3 Pad electrode 3a Signal pad electrode 3b Reference potential supply pad electrode 4 Protective film 5 Opening 7 ViA
8 Back electrode 8a Base electrode 10 Protective film 11 Opening 12 UBM
13 Bump electrode 13a Signal bump electrode 13b Reference potential supply bump electrode 14 Module substrate 15 Wiring 18 Path 26 HBT layout area 27 Capacity layout area 28 Resistance layout area 29 Coil layout area 31 Protective tape 32 Wax material 33 Glass substrate 51 Semiconductor substrate (substrate)
51C Semiconductor chip (chip)
53 Pad electrode 54 Protective film 57 ViA
58 Pad electrode 60 Protective film 63 Bump electrode 100 Semiconductor chip (chip)
101 Semiconductor substrate 102 Through-hole 103a, 103b Pad electrode 104 Protective film 107 ViA
108 Back electrode 114 Module substrate 115 Wiring 116 Die bonding material 117 Cavity 118 Path 119 Bonding wire 126 HBT layout area 127 Capacitance layout area 128 Resistance layout area 129 Coil layout area

Claims (5)

A semiconductor substrate;
A high power amplifying element formed on the main surface of the semiconductor substrate;
A plurality of pad electrodes formed on the main surface of the semiconductor substrate;
A plurality of through holes formed in the semiconductor substrate and reaching the back surfaces of the plurality of pad electrodes from the back surface side of the semiconductor substrate;
A plurality of through electrodes formed by filling the plurality of through holes with a conductor; and
A conductor film in contact with the plurality of through electrodes and covering the back surface of the semiconductor substrate;
The plurality of through electrodes have a plurality of bump electrodes respectively formed with the conductor film interposed therebetween,
The plurality of pad electrodes include a signal pad electrode and a reference potential supply pad electrode that are electrically connected to the high power amplification element,
The plurality of bump electrodes include a signal bump electrode electrically connected to the signal pad electrode through the conductor film and the through electrode, and the reference potential supply through the conductor film and the through electrode. And a reference potential supply bump electrode electrically connected to the pad electrode,
The semiconductor device, wherein the conductor film is formed on the entire back surface of the semiconductor substrate except the periphery of the signal bump electrode. A semiconductor device including a high power amplifier circuit configured to include a high power amplifier element and a passive element,
The high power amplifying element is formed on the main surface of the first semiconductor chip,
The passive element is formed on the main surface of the second semiconductor chip,
The first semiconductor chip is
(A1) a first semiconductor substrate;
(A2) a plurality of first pad electrodes formed on the main surface of the first semiconductor substrate;
(A3) a plurality of through holes that are formed in the semiconductor substrate and reach the back surfaces of the plurality of first pad electrodes from the back surface side of the semiconductor substrate;
(A4) a plurality of through electrodes formed by filling the plurality of through holes with a conductor;
(A5) a conductor film that contacts the plurality of through electrodes and covers the back surface of the first semiconductor substrate;
(A6) The plurality of through electrodes include a plurality of bump electrodes formed with the conductor film interposed therebetween,
The plurality of first pad electrodes include a signal pad electrode and a reference potential supply pad electrode that are electrically connected to the high power amplifier element,
The plurality of bump electrodes include a signal bump electrode electrically connected to the signal pad electrode through the conductor film and the through electrode, and the reference potential supply through the conductor film and the through electrode. And a reference potential supply bump electrode electrically connected to the pad electrode,
The conductor film is formed on the entire back surface of the semiconductor substrate excluding the periphery of the signal bump electrode,
The second semiconductor chip is
(B1) a second semiconductor substrate;
(B2) having a plurality of second pad electrodes formed on the main surface of the second semiconductor substrate and electrically connected to the passive element;
The semiconductor device, wherein the plurality of second pad electrodes are connected to face the reference potential supply bump electrode and the signal bump electrode, respectively. (A) forming a high power amplifying element on the main surface of the semiconductor substrate;
(B) forming a plurality of pad electrodes including a signal pad electrode and a reference potential supply pad electrode electrically connected to the high power amplification element on the main surface of the semiconductor substrate;
(C) forming a plurality of through holes in the semiconductor substrate from the back surface side of the semiconductor substrate to the respective back surfaces of the plurality of pad electrodes;
(D) filling the plurality of through holes with a conductor to form a plurality of through electrodes;
(E) forming a conductor film that covers the entire back surface of the semiconductor substrate and contacts the plurality of through electrodes;
(F) A signal bump electrode electrically connected to the signal pad electrode and a reference potential electrically connected to the reference potential supply pad electrode through the plurality of through electrodes and the conductor film Forming a plurality of bump electrodes including a supply bump electrode,
After the step (e), the conductor film around the signal bump electrode is removed. (G) further including a step of disposing the semiconductor substrate on a substrate provided with a passive element and a plurality of electrodes electrically connected to the passive element;
4. The method of manufacturing a semiconductor device according to claim 3, wherein in the step (g), the plurality of electrodes of the substrate are respectively connected to face the plurality of bump electrodes.   4. The method of manufacturing a semiconductor device according to claim 3, wherein in the step (e), the conductor film is formed by depositing a plating film not containing Au.

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