JP2008059891A - Plasma display panel - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a plasma display panel which works as a high definition panel and yet hardly causes the separation or deterioration of a bus electrode, a connection line, and an electrode terminal. <P>SOLUTION: The plasma display panel includes a front face panel 20 having a plurality of paired display electrodes each composed of a scanning electrode 22 and a sustaining electrode 23, a back face panel 30 which is disposed opposite to the front face panel 20 and has a plurality of data electrodes 32 that are arranged in the direction crossing the direction of the paired display electrodes, and a sealing member 40 which seals the periphery of the front face panel 20 and that of the back face panel 30. The scanning electrode 22 and the sustaining electrode 23 have bus electrodes 22b and 23b that are composed of black layers 22c and 23c and conductive layers 22d and 23d. The black layers 22c and 23c and conductive layers 22d and 23d of the bus electrodes 22b and 23b are extended to a location inside the sealing member 40, and the conductive layers 22d and 23d are extended to a location outside the sealing member 40 to serve as an electrode terminal 50. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an AC type plasma display panel used for a display device or the like.

  A typical AC surface discharge type panel as a plasma display panel (hereinafter abbreviated as “panel”) has a large number of discharge cells formed between a front plate and a back plate arranged to face each other. On the front plate, a plurality of pairs of display electrodes composed of a pair of scan electrodes and sustain electrodes are formed in parallel with each other on a glass front substrate, and a dielectric layer and a protective layer are formed so as to cover the display electrode pairs Has been. The back plate is formed of a plurality of parallel data electrodes on a glass back substrate, a dielectric layer so as to cover them, and a plurality of barrier ribs formed in parallel to the data electrodes on the dielectric layer. A phosphor layer is formed on the surface and the side surfaces of the barrier ribs. Then, the front plate and the rear plate are arranged opposite to each other so that the display electrode pair and the data electrode are three-dimensionally crossed and sealed, and a discharge gas is sealed in the internal discharge space. Here, a discharge cell is formed at a portion where the display electrode pair and the data electrode face each other. In the panel having such a configuration, ultraviolet light is generated by gas discharge in each discharge cell, and phosphors of red, green, and blue colors are excited and emitted by the ultraviolet light to perform color display.

  The display electrode pair includes, for example, a transparent electrode and a bus electrode that is a conductive electrode. The bus electrode includes black ruthenium oxide and the like, and a black layer as a lower layer for making the display electrode pair appear black when the panel is viewed from the display surface side, and a display electrode mainly composed of highly conductive Ag or the like It is formed by laminating a conductive layer as an upper layer that plays the role of lowering the resistance value of the pair.

  The bus electrode is formed by first applying a photosensitive material containing ruthenium oxide or the like to the front substrate to form a black layer. Next, a photosensitive material containing Ag or the like is applied on the black layer to form a conductive layer. Then, exposure and development are performed using an exposure mask to perform patterning. Thereafter, firing is performed to form a bus electrode in which a conductive layer is laminated on a black layer.

However, deterioration such as peeling between the bus electrode and the glass substrate may occur during the baking or in the subsequent process. As a method of preventing such deterioration, a method of suppressing peeling by forming a portion having a film thickness of 5 μm or less on an electrode terminal is disclosed (for example, see Patent Document 1).
JP 2003-68216 A

  However, as the definition of the panel increases, the number of display electrode pairs increases, and accordingly, the bus electrode and the electrode terminal portion drawn to the outside also become thinner, the bonding area with the glass substrate becomes narrower, and peeling and deterioration occur. It is becoming easier to occur.

  The present invention has been made in view of these problems, and an object of the present invention is to provide a panel that is less likely to cause electrode peeling or deterioration even in a high-definition panel.

  In order to solve this problem, the present invention provides a front plate in which a plurality of display electrode pairs each formed of a scan electrode and a sustain electrode are formed, and a plurality of data electrodes that are arranged to face the front plate and intersect the display electrode pairs. A back plate and a sealing member that seals the periphery of the front plate and the back plate, the scan electrode and the sustain electrode have a conductive electrode composed of a lower layer and an upper layer, and a lower layer of the conductive electrode The upper layer is drawn out to a position in the sealing member, and the upper layer of the conductive electrode is extended to a position outside the sealing member to be drawn out to form an electrode terminal. With this configuration, even a high-definition panel can provide a panel that is less likely to cause electrode peeling or deterioration.

  In the present invention, the front plate has a dielectric layer formed so as to cover the scan electrode and the sustain electrode, and the end of the dielectric layer is formed so as to be located in the sealing member. The risk of peeling off the dielectric layer is eliminated.

  Further, in the present invention, the front plate has an alignment mark at a position outside the sealing member, and the alignment mark is formed of a material for forming the upper layer of the conductive electrode, so that the lower layer printing that becomes the black layer is printed. The mask can be designed small.

  ADVANTAGE OF THE INVENTION According to this invention, even if it is a high-definition panel, it becomes possible to provide the panel which is hard to generate | occur | produce and peeling of an electrode.

  Hereinafter, a panel according to an embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 is an exploded perspective view showing a structure of a panel according to an embodiment of the present invention. The panel 10 is composed of a front plate 20 and a back plate 30 that are arranged to face each other, the front plate 20 and the back plate 30 are arranged to face each other, and the periphery is sealed by a sealing member (not shown). A number of discharge cells are formed.

  The front plate 20 includes a plurality of display electrode pairs 28 formed of a pair of scanning electrodes 22 and sustain electrodes 23 formed on a glass front substrate 21 in parallel with each other, and a dielectric material covering the display electrode pairs 28. A layer 24 and a protective layer 25 are formed. The scanning electrode 22 includes a transparent electrode 22a and a bus electrode 22b that is a conductive electrode. Similarly, sustain electrode 23 includes transparent electrode 23a and bus electrode 23b.

The transparent electrodes 22a and 23a are formed by forming a conductive metal oxide such as ITO, SnO ₂ , or ZnO in a band shape on the front substrate 21. The bus electrode 22b is formed by stacking a black layer 22c as a lower layer and a conductive layer 22d as an upper layer, and the bus electrode 23b is similarly formed by stacking a black layer 23c and a conductive layer 23d. The black layers 22c and 23c are formed by laminating a black material mainly composed of ruthenium oxide on each of the transparent electrodes 22a and 23a so as to have a width narrower than that of the transparent electrode. The conductive layers 22d and 23d are formed by laminating a conductive material containing Ag on the black layers 22c and 23c.

  The back plate 30 has a plurality of parallel data electrodes 32 formed on a glass back substrate 31. The data electrode 32 is made of a conductive material containing Ag as a main component. Then, a dielectric layer 33 is formed so as to cover the data electrode 32, and a grid-like partition wall 34 is formed on the dielectric layer 33. A phosphor layer 35 is formed.

  The front plate 20 and the back plate 30 are arranged to face each other so that the display electrode pair 28 and the data electrode 32 are three-dimensionally crossed, and a discharge cell is formed at a portion where the display electrode pair 28 and the data electrode 32 face each other. . The front plate 20 and the back plate 30 are sealed using low melting point glass at a position outside the image display area where the discharge cells are formed, and a discharge gas is sealed in the internal discharge space.

  FIG. 2 is an electrode array diagram of panel 10 in accordance with the exemplary embodiment of the present invention. N scanning electrodes 22 and n sustaining electrodes 23 that are long in the row direction are arranged, and m data electrodes 32 that are long in the column direction are arranged. A discharge cell is formed at a portion where a pair of scan electrode 22 and sustain electrode 23 intersects with one data electrode 32, and m × n discharge cells form an image display area.

  FIG. 3A is a cross-sectional view showing the configuration of the panel 10 according to the embodiment of the present invention on the side where the scan electrode is drawn out, and FIG. 3B is the same as that on the side where the sustain electrode is drawn out. It is sectional drawing which shows a structure. FIG. 4 is a plan view showing an arrangement relationship of each component of the front plate 20 in the embodiment of the present invention. In FIGS. 3A, 3B, and 4, reference numeral 40 denotes a sealing member made of low-melting glass.

  As shown in FIGS. 3A, 3B, and 4, the scan electrode 22 is composed of the transparent electrode 22a and the bus electrode 22b that is a conductive electrode, as described above. The layer 22c and the upper conductive layer 22d are stacked. Further, as described above, the sustain electrode 23 is composed of the transparent electrode 23a and the bus electrode 23b, which is a conductive electrode, and the bus electrode 23b is composed of the lower black layer 23c and the upper conductive layer 23d. ing.

  Then, the black layers 22c and 23c and the conductive layers 22d and 23d of the bus electrodes 22b and 23b, which are the conductive electrodes, are pulled out to a position in the sealing member 40 in a laminated state, and the upper conductive layer 22d, Only 23d extends from the position to a position outside the sealing member 40 and is drawn out. In the upper conductive layers 22d and 23d, the portion extended to the outer side of the sealing member 40 is configured as an electrode terminal 50 to which a flexible wiring board for connecting to an external drive circuit is connected. Has been.

  Further, the dielectric layer 24 formed on the front plate 20 so as to cover the scanning electrodes 22 and the sustaining electrodes 23 is formed so that the end 24 a thereof is located in the sealing member 40.

  In this way, the black layers 22c, 23c and the conductive layers 22d, 23d of the bus electrodes 22b, 23b are drawn out to the position in the sealing member 40 in a stacked state, and only the upper conductive layers 22d, 23d are pulled from the position to the seal. Since the electrode terminal 50 is configured by extending and extending to the position outside the attachment member 40, the conductive layers 22d and 23d containing Ag are directly formed on the front substrate 21 made of glass, and peeling occurs. Since the boundary between the easy black layers 22c and 23c is located in the sealing member 40 and is fixed by the sealing member 40 at the time of sealing, there is no possibility of peeling of the bus electrodes 22 and 23.

  Further, in the present embodiment, as shown in FIG. 3, the boundary of the dielectric layer 24 covering the display electrode pair 28 formed on the front substrate 21 is also located in the sealing member 40. Therefore, the boundary portion of the dielectric layer 24 is also fixed by the sealing member 40 at the time of sealing, and there is no possibility of peeling of the dielectric layer 24 itself.

  Further, in the present invention, alignment marks 61, 62, 63 are formed at positions outside the sealing member 40 of the front plate 20, and the alignment marks 61, 62, 63 are bus electrodes that are conductive electrodes. Alignment marks 61, 62, which are necessary for the manufacturing process of the panel 10 when forming the conductive layers 22d, 23d made of Ag. 63 can be formed simultaneously.

  Here, the alignment mark 61 is used for alignment with the back plate 30, and is formed in a cross shape at the four corners of the front plate 20, for example. The alignment marks 62 and 63 are used for alignment when the flexible wiring board is connected to the electrode terminals 50 of the scan electrodes and the sustain electrodes.

  Thus, when forming the conductive layers 22d and 23d, the alignment marks 61, 62, and 63 required in the manufacturing process of the panel 10 are simultaneously formed, so that the alignment mark printing mask is used for forming the conductive layer. Can be shared with a mask. Further, since it is not necessary to provide a pattern for the alignment mark on the printing mask for forming the black layer, the printing mask can be designed to be smaller accordingly.

  The present invention can prevent the peeling and deterioration of bus electrodes and electrode terminals even in a high-definition panel, and is useful as an AC type plasma display panel used for a display device or the like.

The disassembled perspective view which shows the structure of the panel in embodiment of this invention Electrode arrangement of the panel Sectional view showing the lead-out structure on the scan electrode side and sustain electrode side of the panel Schematic diagram showing the relationship between display electrode pairs, electrode terminals, connection lines and sealing positions on the front panel of the panel

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Panel 20 Front plate 21 Front substrate 22 Scan electrode 22a, 23a Transparent electrode 22b, 23b Bus electrode 22c, 23c Black layer 22d, 23d Conductive layer 23 Sustain electrode 24 Dielectric layer 25 Protective layer 28 Display electrode pair 30 Back plate 31 Back surface Substrate 32 Data electrode 34 Bulkhead 35 Phosphor layer 40 Sealing member 50 Electrode terminal 61, 62, 63 Alignment mark

Claims (3)

A front plate having a plurality of display electrode pairs each formed of a scan electrode and a sustain electrode; a back plate having a plurality of data electrodes arranged opposite to the front plate and intersecting the display electrode pairs; and the front plate and the back plate A sealing member for sealing a peripheral portion with the face plate, the scanning electrode and the sustain electrode have a conductive electrode composed of a lower layer and an upper layer, and the lower layer and the upper layer of the conductive electrode are the sealing member A plasma display panel, wherein the electrode layer is pulled out to an inner position, and the upper layer of the conductive electrode is extended to a position outside the sealing member to be pulled out to be an electrode terminal. The front plate has a dielectric layer formed so as to cover a scan electrode and a sustain electrode, and an end portion of the dielectric layer is formed to be positioned in the sealing member. 2. The plasma display panel according to 1. 2. The plasma display panel according to claim 1, wherein the front plate has an alignment mark at a position outside the sealing member, and the alignment mark is formed of a material forming an upper layer of the conductive electrode.

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