JP2008053758A - 半導体集積回路装置 - Google Patents

半導体集積回路装置 Download PDF

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Publication number
JP2008053758A
JP2008053758A JP2007292929A JP2007292929A JP2008053758A JP 2008053758 A JP2008053758 A JP 2008053758A JP 2007292929 A JP2007292929 A JP 2007292929A JP 2007292929 A JP2007292929 A JP 2007292929A JP 2008053758 A JP2008053758 A JP 2008053758A
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JP
Japan
Prior art keywords
wiring
plug
film
insulating film
integrated circuit
Prior art date
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Pending
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JP2007292929A
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English (en)
Japanese (ja)
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JP2008053758A5 (https=
Inventor
Takako Fujii
貴子 藤井
Hidekazu Murakami
英一 村上
Kazumasa Yanagisawa
一正 柳沢
Miki Takeuchi
幹 竹内
Hideo Aoki
英雄 青木
Hide Yamaguchi
日出 山口
Takafumi Oshima
隆文 大島
Kazuyuki Tsukuni
和之 津国
Kosuke Okuyama
幸祐 奥山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Technology Corp
Original Assignee
Renesas Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Priority to JP2007292929A priority Critical patent/JP2008053758A/ja
Publication of JP2008053758A publication Critical patent/JP2008053758A/ja
Publication of JP2008053758A5 publication Critical patent/JP2008053758A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2007292929A 2007-11-12 2007-11-12 半導体集積回路装置 Pending JP2008053758A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2007292929A JP2008053758A (ja) 2007-11-12 2007-11-12 半導体集積回路装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007292929A JP2008053758A (ja) 2007-11-12 2007-11-12 半導体集積回路装置

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP2002181974A Division JP2004031439A (ja) 2002-06-21 2002-06-21 半導体集積回路装置およびその製造方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2009099263A Division JP2009158987A (ja) 2009-04-15 2009-04-15 半導体集積回路装置

Publications (2)

Publication Number Publication Date
JP2008053758A true JP2008053758A (ja) 2008-03-06
JP2008053758A5 JP2008053758A5 (https=) 2008-08-14

Family

ID=39237422

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007292929A Pending JP2008053758A (ja) 2007-11-12 2007-11-12 半導体集積回路装置

Country Status (1)

Country Link
JP (1) JP2008053758A (https=)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08316330A (ja) * 1995-05-12 1996-11-29 Hitachi Ltd 半導体集積回路のレイアウト方法
JP2001337440A (ja) * 2000-03-24 2001-12-07 Toshiba Corp 半導体集積回路のパターン設計方法、フォトマスク、および半導体装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08316330A (ja) * 1995-05-12 1996-11-29 Hitachi Ltd 半導体集積回路のレイアウト方法
JP2001337440A (ja) * 2000-03-24 2001-12-07 Toshiba Corp 半導体集積回路のパターン設計方法、フォトマスク、および半導体装置

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