JP2008053755A - Semiconductor device and production method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of coping with the increase of outer terminals (enlarging the number of pins) allocatable on the mounting surface, and a production method thereof. <P>SOLUTION: This semiconductor device comprises: a first semiconductor chip 15 which has a first main surface 15a having a plurality of first pads 14, a second main surface 15c having an area larger than that of the first main surface and opposite to the first main surface, and a side wall surface 15b connecting the first main surface with the second main surface; a semiconductor chip loading part 12 which has a third main surface 12a having a first region 12b loading the first semiconductor chip and a second region 12c surrounding the first region, and a fourth main surface 12i opposite to the third main surface; a first outer terminal 24 provided on the first main surface of the first semiconductor chip; a second outer terminal 24 provided on the second region of the semiconductor chip loading part; a first wiring 18 connecting the first pad with the first outer terminal; and a second wiring 18 connecting the first pad with the second outer terminal and provided over the first main surface, the side wall surface and the second region. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device having a package structure and a method for manufacturing the same.

  In recent years, there has been an increasing demand for downsizing, higher density, and higher transmission signal of semiconductor devices mounted on electronic devices such as portable devices. Along with this, CSP (Chip Size Package), which is a semiconductor device in which packaging is performed to approximately the same outer size as the semiconductor chip, has attracted attention.

  In recent years, in particular, for the purpose of reducing manufacturing costs and the like, the technology of WCSP (Waferlevel Chip Size Package), which is a CSP separated by dicing after completing the external terminal formation process in the wafer state. Development has been actively conducted (for example, see Non-Patent Document 1).

  Some WCSPs have a structure in which an electrode pad on a semiconductor chip and an external terminal are electrically connected via a wiring layer that rearranges the external terminal at a desired position. This wiring layer is formed by patterning and is also referred to as a rewiring layer or a wiring pattern.

  A WCSP having such a rewiring layer has an advantage that the degree of freedom in wiring design can be improved by the rewiring layer.

  On the other hand, in recent years, MCP (Multi Chip Package) in which a plurality of chips are arranged in one package or stacked in the thickness direction of a semiconductor chip has been put into practical use in order to realize high-density packaging. (See, for example, Non-Patent Document 2).

Further, as a structure for further increasing the mounting density, a package stack (stack) type MCP in which a plurality of packages are stacked in the thickness direction of a semiconductor chip has been proposed.
Nikkei Microdevice, February 1999, p. 48-56, FIG. 1, FIG. 4) Nikkei Microdevice, February 2000, p. 50-52, FIG. 1)

  However, the WCSP having the redistribution layer as described above has the same package outer dimensions as the semiconductor chip as already described, and therefore, the number of external terminals that can be arranged on the mounting surface is limited. The

  More specifically, since the current WCSP has a fan-in structure, that is, a structure in which external terminals are arranged above the semiconductor chip, the maximum number of external terminals that can be arranged is about 160 (pins). The minimum distance (pitch) between the external terminals is about 0.5 mm.

  In order to meet the demand for a higher number of pins due to the recent high integration, it may be necessary to reduce the minimum interval between the external terminals to about 0.4 mm, for example.

  However, although it is technically possible to set the interval between the external terminals to about 0.4 mm, it is not desirable because a high level mounting technique is required when mounting on the mounting board.

  In the case of a multi-pin class of about 300 pins, it may be difficult to arrange these pins on the mounting board no matter how narrow the interval between the external terminals.

  Therefore, a BGA (Ball) employing a wire bonding (hereinafter sometimes simply referred to as WB) system, which is a package in which a semiconductor chip is mounted on a wiring board and has a structure in which external terminals can be arranged on the entire back surface of the package. A Grid Array type or an LGA (Land Grid Array) type has been proposed.

  However, in the case of these structures in which a wire bonding (hereinafter, sometimes simply referred to as WB) method is usually employed, since the inductance of the WB portion is high, impedance matching with a circuit in the semiconductor chip is intended. Have difficulty. Further, since a wiring board or the like having bonding pads is necessary, not only the package becomes thick but also the product cost increases.

  On the other hand, a flip chip method has been proposed as a wireless bonding, but since an interval between pads (electrode pads) on a semiconductor chip is 0.1 mm or less, an expensive build-up substrate is required and a flip bonding is performed. Since it takes a long time to process, it is not suitable for mass production.

  Also, in the MCP as described above, in the case of a structure adopting the WB method, problems such as an increase in inductance due to WB, an increase in package outer shape and a package thickness occur as described above. .

  Further, in the case of the package stacked MCP as described above, in the case of the structure adopting the WB method, as described above, an increase in inductance caused by WB, an increase in package outer shape and package thickness, etc. Not only is there a problem, but since the MCP cannot have a fan-in structure, it is not suitable for increasing the number of pins of the MCP.

  Accordingly, an object of the present invention is to realize a higher pin count by expanding the mounting surface based on a WCSP structure that is expected to be further expanded in the future, and to achieve a smaller size (smaller package size) than before. It is an object of the present invention to provide a semiconductor device that can be designed to be MCP, package stack type MCP, and the like.

  Therefore, the semiconductor device of the present invention has the following structural features.

  That is, the semiconductor device of the present invention includes a first main surface having a plurality of first pads, a second main surface that faces the first main surface and has a larger area than the first main surface, and a first main surface A first semiconductor chip having a side wall surface connecting to the second main surface is provided. The first semiconductor chip has a third main surface having a first region and a second region surrounding the first region, and a semiconductor chip mounted having a fourth main surface facing the third main surface. On the first region of the part. A first external terminal is provided on the first main surface of the first semiconductor chip. A second external terminal is provided on the second region of the semiconductor chip mounting portion. A first wiring for connecting the first pad and the first external terminal is formed. In addition, a second wiring provided to connect the first pad and the second external terminal and to extend over the first main surface, the side wall surface, and the second region is formed.

  According to this configuration, not only the external terminal (first external terminal) is arranged in the region above the first semiconductor chip (that is, the fan-in portion), but also the region other than above the first semiconductor chip (that is, the fan). An external terminal (second external terminal) can also be arranged in the (out portion), and the semiconductor device can cope with an increase in the number of pins as compared with a normal WCSP.

  Further, in this configuration, the first pad on the semiconductor chip and the first external terminal are electrically connected via the first wiring, and the first pad and the second external terminal are connected to the first pad. Since it is electrically connected through the two wirings, the total signal wiring length can be shortened as compared with the WB system, and thus a semiconductor device having excellent high frequency characteristics can be obtained.

  In addition, the semiconductor device of the present invention preferably has a second wiring in a direction substantially orthogonal to the extending direction of the second wiring at a portion located on the boundary between the first main surface and the side wall surface. The width is preferably formed so as to be wider than the width of the other (remaining) portion of the second wiring. According to this configuration, it is possible to reinforce the second wiring on these boundaries that are weak against impact and stress concentration.

  In the semiconductor device of the present invention, preferably, the wiring section is provided at a position crossing the second main surface with respect to the first pad together with the second wiring, and the first pad and the second external terminal. It is preferable to form a path that electrically connects the two. According to this configuration, the wiring portion can be connected to the second external terminal provided at a position crossing the second main surface with respect to a certain first pad, so that the wiring can be freely routed. The degree can be further improved.

  Therefore, the number of chips collected per wafer can be improved, and an increase in product cost can be suppressed.

  According to the present invention, not only the external terminal (first external terminal) is disposed in the region above the first semiconductor chip (that is, the fan-in portion), but also the region other than the region above the first semiconductor chip (that is, the fan-in portion) A fan-out structure in which an external terminal (second external terminal) is also arranged in the fan-out portion) can be obtained, and a semiconductor device that can cope with a larger number of pins than a normal WCSP.

  Furthermore, electrode pads (that is, first pads) on the semiconductor chip and first and second external terminals are electrically connected via first and second wirings (also referred to as wiring layers or rewiring layers). Since they are connected, the total signal wiring length can be shortened as compared with the WB system, and thus the semiconductor device has excellent high frequency characteristics.

  Hereinafter, an embodiment of the present invention will be described with reference to FIGS. Each drawing schematically shows one configuration example of the semiconductor device according to the present invention. Each drawing merely schematically shows the shape, size, and arrangement relationship of each component to the extent that the present invention can be understood, and the present invention is not limited to these illustrated examples. Further, in order to make the drawing easy to understand, hatching (diagonal lines) showing a cross section is omitted except for a part. In the following description, specific materials and conditions may be used. However, these materials and conditions are only preferred examples, and are not limited to these. Moreover, in each figure, the same component is attached | subjected and shown, and the duplicate description may be abbreviate | omitted. In the following description, the planar shape of each of the semiconductor chip and the semiconductor chip mounting portion is described as a quadrangle, but these shapes may be arbitrarily suitable depending on the design.

<First Embodiment>
With reference to FIGS. 1 to 3, a semiconductor device and a manufacturing method thereof according to a first embodiment of the present invention will be described. FIG. 1A is a plan view schematically showing a semiconductor device 10 of this embodiment. 1B does not correspond to FIG. 1A, but is a cross-sectional view schematically illustrating the connection and arrangement of each component of the semiconductor device 10 by changing them. It is. In FIG. 1A, illustration of external terminals and the like formed on the post portion 20 is omitted, and outlines of parts of the first pad 14, the first wiring layer 18, and the post portion 20 are shown in FIG. The illustration is omitted except for the region (the same applies to the following embodiments).

  As shown in FIG. 1A, a first pad (electrode pad) 14 made of aluminum (Al) is formed on a main surface 15a as a first main surface of a first semiconductor chip 15 included in the semiconductor device 10. It arrange | positions along the outer periphery of the 1st semiconductor chip 15 for every predetermined space | interval. In the example shown in FIG. 1A, since the planar shape of the first semiconductor chip 15 is a square, the first pads 14 are arranged linearly along each side of the square. And the 1st pad 14 and the post part 20 which consists of copper (Cu) corresponding to it are electrically connected via the 1st wiring layer 18 which consists of copper (it mentions later in detail). The number and positions of the first pads 14 are not limited to this, and can be arbitrarily arranged according to the design (the same applies to the following embodiments).

  As shown in FIG. 1B, on the mounting surface 12a as the third main surface of the semiconductor chip mounting portion 12, the first semiconductor chip 15 having an outer dimension smaller than the mounting surface 12a is placed and fixed. Has been. In this configuration example, the substrate 12 is used as a semiconductor chip mounting portion. Of the mounting surface 12a that is the third main surface, the first semiconductor chip 15 is actually placed, that is, the first surface that faces the back surface 15c that is the second main surface facing the first main surface 15a. This area portion is referred to as a mounting surface 12b.

  The four side walls 15x of the first semiconductor chip 15 are inclined walls. A side wall surface (inclined side wall surface) 15b of the inclined wall intersects the mounting surface 12b at an acute angle θ (0 ° <θ <90 °). In this configuration example, each side wall 15x has one inclined side wall surface 15b, but the present invention is not limited to this. That is, as long as the wiring layer can be patterned by sputtering or the like, a configuration in which a plurality of steps are formed on one side wall may be used.

  The back surface 15c, which is the second main surface of the first semiconductor chip 15, and the mounting surface 12b, which is the first region, are fixed (adhered) by an adhesive (not shown) such as a dice bond agent. . In the following description, the mounting surface 12a, which is the third main surface, is a region other than the first region 12b where the first semiconductor chip 15 is placed, and surrounds the first region 12b. The second region is referred to as a non-mounting surface 12c. Further, as the substrate 12, any one of a single-sided substrate, a double-sided substrate and a multilayer substrate, for example, any inorganic material substrate such as a silicon (Si) substrate, a ceramic substrate and a metal base substrate, or a glass epoxy substrate and Any organic material substrate such as a polyimide substrate can be used. In this configuration example, the substrate 12 is described as an example of the semiconductor chip mounting portion. However, the configuration is not limited to this, and any substrate that functions as a semiconductor chip mounting portion may be used. Further, the intersection angle between the mounting surface 12a and the side wall surface 15b is set to an acute angle θ, and the acute angle θ is set to a value within the range of 45 ° to 60 °, thereby improving the number of chips collected per wafer. Needless to say, it is possible to secure a margin for avoiding chip damage due to blurring of a blade or the like when individual chips are separated.

Further, the end of the first pad 14 on the main surface 15 a of the first semiconductor chip 15, for example, the top surface is exposed on the main surface 15 a, the side wall surface 15 b, and the non-mounting surface 12 c of the first semiconductor chip 15. Thus, for example, the insulating film 16 in which a passivation film and a protective film are sequentially provided is provided. Here, the passivation film is formed of, for example, a silicon oxide film (SiO ₂ ). Further, the protective film is formed of a low-hardness film material such as polyimide resin, for example. Therefore, the protective film causes an impact on the first semiconductor chip 15 during the manufacturing process and the sealing layer 22 and the semiconductor chip 15. Peeling due to stress between the two can be prevented.

  The first pads 14 are electrically connected individually to the solder balls (bumps) 24 that are external terminals for connection to the mounting substrate via the dedicated first wiring layer 18.

  Therefore, in the first wiring layer 18 in this configuration example, the solder ball 24 does not depend on the position of the first pad 14 and is shifted to a desired position on a substantially horizontal plane, that is, a shifted position above the first semiconductor chip 15. It can be placed in. Therefore, in this configuration example, the first wiring layer 18 functions as a rewiring layer in which the solder balls 24 can be rearranged at a position facing the non-mounting surface 12c (hereinafter, the first wiring layer 18 is referred to as the first wiring layer 18). Sometimes referred to as first redistribution layer).

  One end of the first wiring layer 18 in this configuration example is connected to the first pad 14, and the side wall surface 15 b of the inclined wall (side wall) 15 x of the first semiconductor chip 15 extends from the first pad 14 and is not mounted. Along the placement surface 12c, the cut surface extends so as to bend according to the height difference (step) between the main surface 15a of the first semiconductor chip 15 and the non-mounting surface 12c. The first wiring layer 18 is electrically connected to the solder ball 24 assigned as the connection destination of the first pad 14 via the post portion 20.

  In addition, on the upper surface of the main surface 15a, the side wall surface 15b, and the non-mounting surface 12c of the first semiconductor chip 15, so as to cover the insulating film 16, the first wiring layer 18 and the like, A sealing layer 22 made of epoxy resin or the like is formed so as to expose the top surface. The upper surface of the sealing layer 22 is a flat surface. A solder ball 24 serving as a bump for connection to a printed circuit board (not shown) or the like is formed on the post portion 20.

  Further, an output signal from the first semiconductor chip 15 in this configuration example is transmitted to a path from the first pad 14 to the solder ball 24 via the first wiring layer 18 and the post portion 20. Further, an input signal from the solder ball 24 is transmitted through a path opposite to the above.

  Next, a method for manufacturing the semiconductor device 10 will be described below with reference to FIGS.

  First, as the side wall surface forming step, a first main surface 15a on which the first pad 14 is formed, and a second main surface 15c facing the first main surface 15a and having a larger area than the first main surface. A mesa-type first semiconductor chip 15 is obtained by forming a side wall surface 15 b connecting the first main surface 15 a and the second main surface 15 c on the first semiconductor chip 15.

  Therefore, first, a semiconductor wafer 30 having a plurality of first semiconductor chips 15 ′ (chip size is about 7 mm × about 7 mm in length, for example) before being singulated is prepared. As shown in FIG. 2A, in the first semiconductor chip 15 ′ before singulation, the first pads 14 are arranged on the main surface with a predetermined interval (pitch), for example, 0.035 mm to 0.18 mm. It is formed every time. The back side of the wafer 30 is adhered and fixed with a wafer fixing tape 32 coated with an adhesive (not shown). In the drawing, for the sake of convenience, about two first semiconductor chips 15 ′ before separation are shown, but the present invention is not limited to this. Further, a scribe line (not shown) of about 0.08 mm is formed between adjacent first semiconductor chips 15 ′ before separation into pieces in the semiconductor wafer 30.

  Subsequently, as shown in FIG. 2B, the individual first semiconductor chips 15 are separated into pieces, that is, separated along the scribe line (not shown) by a blade (cutting tool) 19 or the like that rotates at high speed. . The cutting edge of the blade 19 used at this time has an angle (vertical angle) φ (for example, about 60 ° <θ <90 °) such that the cross-sectional shape of the tip is V-shaped. At this time, along with the formation of the groove 36 cut into a V shape, an inclined side wall surface 15b forming an acute angle θ (0 ° <θ <90 °) is formed on the side wall 15x of the first semiconductor chip 15 ′. . Thereafter, the adhesiveness of the adhesive is reduced by UV irradiation or the like, and the individual first semiconductor chips 15 are separated from the wafer fixing tape 32.

  Next, as a mounting step, the first semiconductor chip 15 having the side wall surface 15b formed thereon is formed with a third main surface 12a having a first region 12b and a second region 12c surrounding the first region, The semiconductor chip mounting portion 12 having the third main surface 12a and the fourth main surface 12i facing the third main surface 12a is mounted on the first region 12b.

  Specifically, as shown in FIG. 2C, each of the separated first semiconductor chips 15 is placed as a first region of the mounting surface 12 a that is the third main surface of the substrate 12. It mounts on the surface 12b at predetermined intervals. At this time, the space between the back surface 15c of the first semiconductor chip 15 and the mounting surface 12b is fixed by, for example, a dice bond agent (not shown).

  Next, as a first wiring layer forming step, the first semiconductor chip 15 is mounted along the first main surface 15a and the side wall surface 15b from the first pad 14 while being electrically connected to the first pad 14. A first wiring layer (first rewiring layer) 18 extending to the upper side of the non-mounting surface 12c, which is the second region around the first semiconductor chip 15, is formed on the surface 12a.

  Therefore, as shown in FIG. 3A, first, silicon is formed so that the top surface of the first pad 14 is exposed across the main surface 15a, the side wall surface 15b, and the non-mounting surface 12c of the first semiconductor chip 15. An insulating film 16 composed of a laminated film in which an oxide film and a polyimide film are sequentially laminated is formed.

  Since there is a height difference (step) between the main surface 15a of the first semiconductor chip 15 constituting the ground of the insulating film 16 and the non-mounting surface 12c, the insulating film 16 is formed corresponding to this step. Is done.

  Subsequently, the first wiring layer 18 made of copper is connected to the first pad 14 so that one end thereof is connected to the non-mounting surface 12c from the side wall surface 15b of the inclined wall (side wall) 15x on the insulating film 16. Then, patterning is performed by photolithography, sputtering, or the like so that the cut surface is bent and extended in accordance with the height difference between the main surface 15a and the non-mounting surface 12c. Since the first wiring layer 18 is formed by patterning, it is also referred to as a first wiring pattern.

  At this time, portions of the first wiring layer 18 located on the boundary between the main surface 15a and the side wall surface 15b and on the boundary between the side wall surface 15b and the non-mounting surface 12c (indicated by a broken line z in the figure). The width of the first wiring layer in a direction substantially perpendicular to the extending direction of the first wiring layer 18 (a direction perpendicular to the drawing sheet) is wider than the width of the other (remaining) portion of the first wiring layer. It is good to form like this.

  As a result, it is possible to reinforce the first wiring layer 18 on these boundaries that are weak against impact and stress concentration.

  Next, as an external terminal formation step, external terminals are formed on the upper surface of the non-mounting surface 12 c so as to be electrically connected via the first pads 14 and the first wiring layer 18.

  As shown in FIG. 3B, first, a corresponding post portion 20 made of copper is formed on the first wiring layer 18 extending on the surface of each insulating film 16 on the non-mounting surface 12c. It is formed by plating or the like. Further, gold (Au) or the like may be used in addition to copper for forming the post portion 20.

  Further, after the post portion 20 is formed, a thin oxide film may be formed on the side surface of the post portion 20 by thermal oxidation or the like. In this case, since the adhesion between the post part 20 and the sealing layer 22 is further improved, it is possible to further suppress the intrusion of moisture from the interface between the post part 20 and the sealing layer 22 described later.

  Subsequently, the sealing layer 22 is formed on the mounting surface 12a side of the substrate 12 on which the post portion 20 is formed by a transfer molding method using a sealing material made of an organic resin (epoxy resin or the like) until the post portion 20 is hidden. Form. Thereafter, the sealing layer 22 and the post portion 20 are polished by a grinder (polishing tool) or the like, and the top surface of all the post portions 20 is exposed to form a mounting surface for mounting external terminals. In addition, when forming the post part 20, if each of the post parts 20 can be formed at the same height in the vertical direction, a polishing process for forming a mounting surface for external terminals by a film molding method or the like is performed. It can be omitted.

  Thereafter, as shown in FIG. 3C, solder balls 24 as external terminals, which are bumps for connection to a printed circuit board (not shown), are reflow-formed on the exposed mounting surface for external terminals. To do. If necessary, a barrier metal layer or the like may be formed between the external terminal mounting surface and the solder ball 24. In this configuration example, the minimum interval (pitch) between the solder balls 24 that are external terminals can be expanded to, for example, 0.3 mm or more.

  Thereafter, each semiconductor device (package) 10 is cut out with a high-speed rotating blade (cutting tool) or the like (not shown) for normal scribing (see FIG. 1B).

  As is apparent from the above description, according to the semiconductor device and the manufacturing method thereof in this embodiment, the first semiconductor chip is mounted on the semiconductor chip mounting portion, so that the upper portion of the first semiconductor chip (that is, the fan-in portion). ) As well as in regions other than the upper side of the first semiconductor chip (that is, the fan-out portion) by the first wiring layer extending from the main surface of the first semiconductor chip to the side wall surface and the non-mounting surface. A structure (fan-out structure) in which external terminals are arranged can be realized.

  Therefore, it is possible to obtain a semiconductor device that can cope with an increase in the number of pins as compared with a normal WCSP.

  That is, according to the conventional semiconductor device, the normal WCSP chip size is undesirably increased only for the purpose of increasing the number of pins, and the number of chips collected per wafer has been reduced. According to the embodiment, unlike the conventional case, the semiconductor device can have a fan-out structure by the semiconductor chip mounting portion functioning as the expansion portion that allows the arrangement position of the external terminals to be expanded.

  As a result, it is possible to obtain a semiconductor device that can accommodate a large number of pins. For example, when the chip size is about 7 mm × about 7 mm and the external dimensions of the semiconductor chip mounting portion are about 10 mm × about 10 mm, For example, 312 pins can be arranged with a terminal pitch of 0.5 mm.

  In this embodiment, since the first pad and the solder ball are electrically connected via the first rewiring layer, the total signal wiring length is shortened as compared with the case where the WB method is adopted. be able to.

  As a result, for example, when transmitting a high-frequency signal, the attenuation of the signal can be effectively suppressed as compared with the WB method, and the characteristic impedance of the signal line and the impedance of the semiconductor chip can be easily matched. A semiconductor device having high-frequency characteristics superior to those of the prior art is obtained.

  In addition, it is not necessary to use an expensive substrate that has been previously processed through holes or the like, such as a WB BGA, so that the manufacturing cost of the semiconductor device can be reduced.

  In addition, if a disk-shaped silicon wafer is used as the substrate 12, an existing WCSP device manufacturing process can be applied. Therefore, since a new jig or the like for holding the substrate is unnecessary, the cost can be reduced.

<Second Embodiment>
With reference to FIGS. 4A and 4B, a semiconductor device 11 according to a second embodiment of the present invention will be described.

  The main differences between the second embodiment and the first embodiment are as follows. First, a through hole 38 having a conductor portion 39 that conducts electricity from the third main surface 12a to the fourth main surface 12i is formed as a through portion in the substrate 12 that is a semiconductor chip mounting portion, that is, the front and back of the substrate 12, In addition, the conductive portion 39 is electrically connected to the first wiring layer 18 and the substrate 12 includes a wiring portion 27 that traverses the region facing the first semiconductor chip 15. 27 is a point electrically connected to the first wiring layer 18. In addition, the same components as those already described in the first embodiment are denoted by the same reference numerals, and a specific description thereof may be omitted (hereinafter, each embodiment is also described). The same). In this configuration example, a double-sided substrate (such as a glass epoxy double-sided substrate) in which wiring is patterned on both surfaces of a base material constituting the substrate 12 with a conductor (here, copper (Cu) foil) is used as the substrate 12. A case will be described as an example.

  As shown in FIG. 4B, a through hole 38 is formed in the substrate 12, and a conductor portion (copper plating layer) 39 that allows conduction between the front and back of the substrate is formed on the entire inner wall of the through hole 38. Is formed. A first land 42 and a third pad 40 are respectively formed at both ends of the conductor portion 39 of the through hole 38. The first land 42 and the third pad 40 are formed on the surface of the substrate 12 using a copper foil.

  The conductor portion 39 of the through hole 38 is electrically connected to the first wiring layer 18 via the first land 42 exposed without being covered with the insulating layer 16. Further, the third pad 40 here is used, for example, as a pad for mounting a semiconductor device or a pad for mounting a passive element such as a coil or a capacitor when the semiconductor device is formed as a package stacked semiconductor device.

  Further, when a package stacked semiconductor device is constituted by the semiconductor device 11, the solder ball 24 of the semiconductor device 11 and the third pad 40 of the semiconductor device 11 having the same structure, for example, are bonded to each other. A plurality of layers may be stacked in the thickness direction of the semiconductor chip 15.

  Furthermore, in this embodiment, the substrate 12 is formed with a wiring portion 27 extending in a direction substantially orthogonal to the thickness direction of the substrate 12.

  For example, as shown in FIG. 4A, in the substrate 12, copper is arranged in such a manner that the substrate 12 is substantially orthogonal to the thickness direction of the substrate 12 and crosses a region portion facing the first semiconductor chip 15. A wiring portion 27 made of foil (not shown in FIG. 4B) is formed by patterning. The wiring portion 27 is electrically connected to the first wiring layer 18 via second pads 43 (only one is shown in FIG. 4B) located at both ends of the wiring portion 27. It is the structure connected to.

  In the configuration of the first embodiment, the solder ball 24 electrically connected to the first pad 14 has one end connected to the first pad 14, and the main surface 15 a and the side wall surface 15 b of the semiconductor chip 15. And the solder balls 24 that can be disposed above the first wiring layer 18 extending to the upper side of the non-mounting surface 12c (see FIG. 1A).

  Therefore, as shown in FIG. 4A, by using the substrate 12 on which the wiring portion 27 is patterned as a semiconductor chip mounting portion, any one of a plurality of solder balls can be applied to a certain first pad 14. When one solder ball is selected, the first wiring layer 18, the wiring portion 27, and the other first wiring layer 18 can be sequentially connected to the selected solder ball. The degree of freedom in routing can be further improved.

  Further, the output signal from the first semiconductor chip 15 in this configuration example is a path from the first pad 14 to the solder ball 24 via the first wiring layer 18 and the post portion 20, and from the first pad 14 to the first. A route from the first pad 14 to the first wiring layer through the wiring layer 18, the second pad 43, the wiring portion 27, the second pad 43, the first rewiring layer 18, and the post portion 20. 18, the first land 42, and the through hole 38 to be transmitted through at least one of the paths reaching the third pad 40. Further, input signals from the solder balls 24 and the third pads 40 are transmitted through a path opposite to the above. The transmission path is not limited to the above-described path, and can be formed as various wiring paths according to the purpose and design.

  In addition, the manufacturing method of the semiconductor device 11 of this embodiment has the same steps as the manufacturing steps described in the first embodiment, but differs in the following steps. That is, in the step of mounting the first semiconductor chip 15 on the substrate 12, the through holes 38 and the exposed first lands 42 and the second pads 43 are formed in advance on the substrate 12 at predetermined positions. Then, the first semiconductor chip 15 is placed and fixed on the substrate 12 via a dice bond agent or the like (not shown).

  Similarly to the step of forming the first wiring layer described in the first embodiment, first, the insulating film is exposed so that, for example, the top surfaces of the first pad 14, the first land 42, and the second pad 43 are exposed. 16 is formed. After the insulating film 16 is formed, the first wiring layer 18 is formed so that the first pad 14 is connected to the first land 42 or the second pad 43 whose connection relationship is designated.

  Thereafter, similarly to the first embodiment, an external terminal forming step is performed to obtain the semiconductor device 11. The through-hole 38 provided in the substrate 12 (here, glass epoxy double-sided substrate) is formed, for example, by forming a through-hole with a drill or the like in the substrate before patterning with a copper foil near the surface layer of the substrate. A copper plating layer (conductor portion) 39 is formed on the inner wall of the hole by a plating method or the like.

  As is clear from the above description, this embodiment can obtain the same effects as those of the first embodiment.

  Furthermore, in this embodiment, the first pad can be electrically connected to a desired external terminal as compared with the first embodiment by the wiring portion patterned on the substrate which is the semiconductor chip mounting portion, Therefore, the degree of freedom of wiring routing can be improved.

  Further, when the semiconductor device 11 is stacked to form a package stacked semiconductor device, a fan-in structure that has been difficult with the conventional WB package stacked semiconductor device is possible. In addition, the film thickness can be reduced.

<Third Embodiment>
A semiconductor device 50 according to a third embodiment of the present invention will be described with reference to FIGS.

  In this embodiment, the semiconductor chip mounting portion is the second semiconductor chip 44 having circuit elements, and the second semiconductor chip 44 is electrically connected to the first wiring layer 18 in the first embodiment. This is the main difference from this form.

  As shown in FIG. 5A, the planar shape of the second semiconductor chip 44 as the semiconductor chip mounting portion is a square. On the mounting surface 44a which is the third main surface of the second semiconductor chip 44, fourth pads 45 made of aluminum (Al) are arranged along the outer periphery of the second semiconductor chip 44 at predetermined intervals. The fourth pad 45 is electrically connected to the first wiring layer 18. The number and position of the fourth pads 45 are not limited to this.

  Further, the output signal from the first semiconductor chip 15 in this configuration example is a path from the first pad 14 to the solder ball 24 via the first wiring layer 18 and the post portion 20, and from the first pad 14. The data is transmitted via both or one of the routes reaching the second semiconductor chip 44 via the first wiring layer 18 and the fourth pad 45. In addition, input signals from the solder balls 24 and the second semiconductor chip 44 are transmitted through a path reverse to the above. The transmission path is not limited to the above, and can be formed as various wiring paths according to the purpose and design.

  Thus, in this configuration example, since the semiconductor chip mounting portion is the second semiconductor chip 44, the semiconductor device 50 has the first semiconductor chip 15 stacked on the mounting surface 44 b of the second semiconductor chip 44. Therefore, the degree of mounting can be increased.

  Further, in the manufacturing method of the semiconductor device 50 of this embodiment, the fourth pads 45 are formed at predetermined intervals, for example, 0.035 mm to 0.18 mm, as in the mounting process in the first embodiment. The first semiconductor chip 15 is placed and fixed on the second semiconductor chip 44 which is the semiconductor chip mounting portion via a dice bond agent (not shown) (FIG. 6A). Further, similarly to the first wiring layer forming step described in the first embodiment, the top surface of the first pad 14 and the top surface of the fourth pad 45 connected to the first wiring layer 18 are exposed. Thus, the insulating film 16 is formed. After forming the insulating film 16, the first wiring layer 18 is formed so as to be connected to the fourth pad 45 from the side wall surface 15b to the non-mounting surface 44c (FIG. 6B). In this configuration example, the connection between the fourth pad 45 and the first wiring layer 18 is designated in a one-to-one relationship.

  Thereafter, an external terminal formation step is performed in the same manner as in the first embodiment (FIG. 6C) to obtain the semiconductor device 50 (FIG. 5B).

  As is clear from the above description, this embodiment can obtain the same effects as those of the first embodiment.

  Further, in this embodiment, a substrate having a bonding post or the like as in the conventional WB type MCP is not required, and the height of the wire loop is taken into consideration when manufacturing the semiconductor device. It is not necessary.

  Therefore, according to the configuration of this embodiment, a semiconductor device having an MCP structure in which the outer dimensions of the second semiconductor chip 44 are substantially outer dimensions can be obtained, and the package size can be compared with a conventional WB type MCP or the like. Thus, a semiconductor device in which downsizing and thinning of the device are realized is obtained.

<Fourth embodiment>
A semiconductor device 60 according to the fourth embodiment of the present invention will be described with reference to FIG.

  In this embodiment, the second wiring layer 49 that passes between the first semiconductor chip 15 and the second semiconductor chip 44 is provided, and the second wiring layer 49 is electrically connected to the first wiring layer 18. This is the main difference from the third embodiment.

  More specifically, above the second semiconductor chip 44, the lower side of the first semiconductor chip 15 is arranged in a direction substantially perpendicular to the thickness direction of the second semiconductor chip 44. A second wiring layer 49 (hereinafter, the second wiring layer may be referred to as a second rewiring layer) is formed so as to cross the line. The second wiring layer 49 extends on the insulating film 21 provided on the mounting surface 44a which is the third main surface of the second semiconductor chip 44, and one end of the second wiring layer 49 is the first. The second semiconductor chip 44 and the other end are electrically connected to the first wiring layer 18 via the fifth pad 46 via the four pads 45.

  In the configuration of the third embodiment, the solder ball 24 electrically connected to the first pad 14 has one end connected to the first pad 14, and the main surface 15 a and the side wall surface 15 b of the semiconductor chip 15. And the solder balls 24 that can be disposed above the first wiring layer 18 that extends to the upper side of the non-mounting surface 44c (see FIG. 5A).

  Therefore, as shown in FIGS. 7A and 7B, by providing the second wiring layer 49, a plurality of one first pad 14 is provided with respect to a certain first pad 14 as compared with the third embodiment. When any one of the solder balls is selected, the first wiring layer 18, the second wiring layer 49, and the other first wiring layer 18 are sequentially connected to the selected solder ball. Therefore, the degree of freedom of wiring routing can be improved.

  In the manufacturing method of the semiconductor device 60 of this embodiment, in the mounting process described in the third embodiment, first, the top surface of the fourth pad 45 made of aluminum (Al) provided at a predetermined position is formed. An insulating film 21 is formed so as to be exposed. Subsequently, the second wiring layer 49 made of copper is patterned and formed over a position where one end thereof is connected to the fourth pad 45 and the other end is connected to the predetermined first wiring layer 18 in a later process. . Thereafter, in the same manner as in the mounting process of the third embodiment, the first semiconductor chip 15 is mounted on the mounting surface 44b of the second semiconductor chip 44 through a dice bond agent (not shown). Fix it. Further, in the same manner as the first wiring layer forming step described in the third embodiment, insulation is performed so that the top surface of the fifth pad 46 connected to the first wiring layer 18 of the second wiring layer 49 is exposed. After the film 16 is formed, the first wiring layer 18 connected to the fifth pad 46 is formed. Thereafter, an external terminal forming step is performed in the same manner as in the first embodiment, and the semiconductor device 60 is obtained.

  As is clear from the above description, this embodiment can provide the same effects as those of the third embodiment.

  Furthermore, since the second wiring layer 49 is provided in this embodiment, the first pad can be electrically connected to a desired external terminal as compared with the third embodiment. The degree of freedom of routing can be improved.

  As a result, an existing semiconductor chip having a circuit configuration that is difficult to be MCP can be used as it is because of the design position of the functional block and the pad arrangement, and it is not necessary to manufacture a new semiconductor chip.

<Fifth embodiment>
A semiconductor device 70 according to a fifth embodiment of the present invention will be described with reference to FIG.

  In this embodiment, the second semiconductor chip 44 that is a semiconductor chip mounting portion is formed with a through portion, for example, a through hole 52 having a conductor portion 54 for conducting the front and back of the second semiconductor chip 44. Thus, the point that the conductor portion 54 is electrically connected to the first wiring layer 18 is the main difference from the third embodiment. Note that this configuration example is also suitable for application to the fourth embodiment.

  As shown in FIGS. 8A and 8B, a through hole 52 is provided in the second semiconductor chip 44 which is a semiconductor chip mounting portion. An insulating film such as a silicon oxide film is provided on the inner wall surface of the through hole 52, and a conductor portion (copper, nickel (Ni), etc.) 54 is formed on the inner wall insulating film. The conductor portion 54 allows conduction between the front and back surfaces of the second semiconductor chip 44. Further, a second land 53 and a sixth pad 56 formed on the second semiconductor chip are respectively formed at both ends of the conductor portion 54 of the through hole 52 so as to be electrically connected thereto. .

  The top surface of the second land 53 is exposed without being covered with the insulating layer 16. Accordingly, the conductor portion 54 of the through hole 52 is electrically connected to the first wiring layer 18 via the second land 53. Further, the sixth pad 56 here is, for example, a semiconductor device mounting pad or a passive device mounting pad such as a coil or a capacitor when the semiconductor device is formed as a package stacked semiconductor device.

  Further, when the semiconductor device is a package stacked semiconductor device, the solder ball 24 of the semiconductor device 70 and, for example, the sixth pad 56 of the semiconductor device 70 having the same structure are joined to each other to form the first semiconductor chip. A plurality of layers may be stacked in the thickness direction of 15.

  Further, the output signal from the first semiconductor chip 15 in this configuration example is a path from the first pad 14 to the solder ball 24 via the first wiring layer 18 and the post portion 20, and from the first pad 14 to the first. A path reaching the second semiconductor chip 44 through the wiring layer 18 and the fourth pad 45, and a sixth pad 56 from the first pad 14 through the first wiring layer 18, the second land 53, and the through hole 52. It is transmitted via at least one of the routes leading to. Further, input signals from the solder ball 24, the second semiconductor chip 44, and the sixth pad 56 are transmitted through a path reverse to the above. The transmission path is not limited to the above-described path, and can be formed as various wiring paths according to the purpose and design.

  Further, the manufacturing method of the semiconductor device 70 of this embodiment is similar to the mounting process described in the third embodiment, and the through holes 52 and the exposed second lands 53 and the fourth pads 45 are exposed at predetermined positions. Is mounted and fixed on the mounting surface 44b of the second semiconductor chip 44 formed in advance via a dice bond agent (not shown).

  Similarly to the first wiring layer forming step described in the third embodiment, first, the insulating film 16 is formed so as to expose the surface of the second land 53, and then connected to each of the second lands 53. A first wiring layer 18 having a specified relationship is formed.

Thereafter, an external terminal forming step is performed in the same manner as in the first embodiment, and the semiconductor device 70 is obtained. The through hole provided in the second semiconductor chip 44 is formed by, for example, dry etching the through hole formation region to form a through hole, and the through hole is formed in a silicon oxide film (SiO ₂ ) or a silicon nitride film ( Insulating the inner wall with SiN) and filling with copper or the like.

  As is apparent from the above description, this embodiment can provide the same effects as those of the fourth embodiment.

  Furthermore, in this embodiment, when the semiconductor device 70 is stacked to form a package stacked semiconductor device, the number of stacked semiconductor chips per unit height can be increased more than in the second embodiment, so High-density mounting can be realized.

<Sixth Embodiment>
A semiconductor device 80 according to a sixth embodiment of the present invention will be described with reference to FIGS.

  As shown in FIG. 9A, on the main surface of the first semiconductor chip 82 included in the semiconductor device 80, the first pads 14 made of aluminum are arranged at predetermined intervals along the outer periphery of the first semiconductor chip 82. Has been placed.

  As shown in FIG. 9B, the first semiconductor chip 82 is placed and fixed on the mounting surface 83e of the substrate 83 as the support portion. Of the mounting surface 83e, a region where the first semiconductor chip 82 is actually mounted is a mounting surface 83f, and the other region is a non-mounting surface 83g. The first semiconductor chip 82 includes a back surface 82d that is the second main surface on the substrate 83 side, a main surface 82a that is the first main surface opposite to the back surface 82d, and an inclined side wall surface connected to the periphery of the main surface 82a. 82b, and the inclined side wall surface 82b and a vertical wall surface 82c perpendicular to the substrate mounting surface 83e formed continuously. The inclined side wall surface 82b is formed by obliquely chamfering a ridge with a wall surface orthogonal to the main surface 82a of the first semiconductor chip, and the remaining portion is a vertical wall surface 82c.

  The back surface 82d of the first semiconductor chip 82 and the mounting surface 83f of the substrate are fixed (adhered) by a dice bond agent or the like (not shown). Moreover, although the various board | substrates already demonstrated can be used for the board | substrate 83 as a support part of this structural example, what is necessary is just to perform the function as a support part.

  Furthermore, the non-mounting surface 83g of the substrate surrounds the side wall of the first semiconductor chip 82, and more specifically, for example, the first side surface of the inclined side wall surface 82b is exposed at least on the main surface 82a side. A frame-shaped portion 86 made of a photosensitive resin (photosensitive polyimide or the like) is provided so as to surround the first semiconductor chip 82 at a height reaching the inclined side wall surface 82b of the side wall 82x of the semiconductor chip 82.

  The top surface of the first pad 14 on the main surface of the first semiconductor chip 82 is exposed above the main surface 82a, the inclined sidewall surface 82b, and the non-mounting surface 83g of the first semiconductor chip 82. An insulating film 16 is provided. The first pad 14 includes a solder ball 24 constituting an external terminal for connection to the mounting substrate and a dedicated first wiring layer (also referred to as a first rewiring layer or a first wiring pattern) 18. Are electrically connected individually.

  More specifically, one end of the first wiring layer 18 in this configuration example is connected to the first pad 14, and on the inclined sidewall surface 82 b of the first semiconductor chip 82 and the third main surface of the frame-shaped portion 86. It extends so that the cut surface bends along the upper surface 86j according to the height difference between the main surface 82a and the third main surface 86j of the frame-shaped portion 86. The extending portion of the first wiring layer 18 is electrically connected to the first pad 14 via the post portion 20 and a solder ball 24 that is designated for electrical connection.

  In addition, on the upper side of the first semiconductor chip 82 and the frame-shaped portion 86, sealing with an epoxy resin or the like is performed so as to cover the insulating film 16, the first wiring layer 18 and the like and to expose the top surface of the post portion 20. A stop layer 22 is formed. The upper surface of the sealing layer 22 is a flat surface. A solder ball 24 serving as a bump for connection to a printed circuit board (not shown) or the like is formed on the post portion 20.

  In addition, an output signal from the first semiconductor chip 82 in this configuration example is transmitted to a path from each first pad 14 to the solder ball 24 via the first wiring layer 18 and the post portion 20. Further, an input signal from the solder ball 24 is transmitted through a path opposite to the above.

  Next, a method for manufacturing the semiconductor device 80 will be described below with reference to FIGS.

  First, as the inclined side wall surface forming step, the first main surface 82a on which the first pad 14 is formed, the second main surface 82d facing the first main surface 82a and having a larger area than the first main surface, and the first Chamfering the ridge portion between the first main surface 82a and the side wall surface 82c of the first semiconductor chip having the side wall surface 82c connecting the first and second main surfaces (82a, 82d) to form the inclined side wall surface 82b. To obtain a mesa-type first semiconductor chip 82.

  Therefore, first, a semiconductor wafer 81 having a plurality of first semiconductor chips 82 'before being singulated is prepared. As shown in FIG. 10A, in the first semiconductor chip 82 ′ before singulation, the first pads 14 are formed on the main surface at predetermined intervals, for example, 0.035 mm to 0.18 mm. Has been. The back side of the wafer 81 is bonded and fixed with a wafer fixing tape 32 coated with an adhesive (not shown). In the drawing, for the sake of convenience, about two first semiconductor chips 82 ′ before separation are shown, but the present invention is not limited to this. In addition, a scribe line (not shown) of about 0.08 mm is formed between adjacent first semiconductor chips 82 ′ before separation into adjacent semiconductor wafers 81.

  Subsequently, as shown in FIG. 10B, the edge of the first semiconductor chip 82 'before chamfering is chamfered with a blade (cutting tool) that rotates at high speed or the like. The cutting edge of the blade used at this time has an angle (vertical angle) φ (for example, about 60 ° <θ <90 °) such that the cross-sectional shape of the tip is V-shaped. Thereby, the inclined side wall surface 82b is formed by forming the groove 89 cut into a V shape. After the formation of the inclined side wall surface 82b, the individual first semiconductor chips 82 are separated into individual pieces, that is, separated by a normal scribing blade 79 or the like.

  Next, as a frame-shaped portion forming step, the support portion 83 has a third main surface 86j and a fourth main surface 86k opposite to the third main surface, and at least the first semiconductor chip on the inclined sidewall surface 82b. A frame-like portion 86 having an opening for exposing the surface region on the first main surface 82a side is formed so that the fourth main surface 86k and the support portion 83 are arranged to face each other.

  The frame-shaped portion 86 is formed on the substrate 83 as the support portion. At this time, as will be described later, the first semiconductor chip 82 is surrounded and inclined at the inner side of the frame, that is, in the opening portion, as will be described later. The side wall surface 82b is accommodated so as to be exposed at least.

  Therefore, as shown in FIG. 10C, the frame-shaped portion 86 is formed on the common substrate 83 by spin-coating a photosensitive resin material, and then formed by, for example, photolithography and curing processing. In addition, a high-precision printing method or the like can be applied to the formation of the frame-shaped portion 86. Of the substrate mounting surface 83e, the exposed surface of the substrate 83 surrounded by the frame-shaped portion 86 is a mounting surface 83f.

  Next, as a mounting step, the first semiconductor chip 82 is mounted on the support portion 83 by being disposed in the opening. Therefore, the first semiconductor chip 82 has a size that can be fitted into the frame-shaped portion 86 with substantially no gap.

  As shown in FIG. 11A, each of the separated first semiconductor chips 82 is placed on a predetermined position on the common substrate 83, here on the placement surface 83f. When the first semiconductor chip 82 is mounted on the mounting surface 83f, the side wall of the first semiconductor chip 82 is surrounded by the frame-shaped portion 86. At this time, the space between the back surface 82d of the first semiconductor chip 82 and the mounting surface 83f is fixed by, for example, a die bond agent or the like (not shown). In this configuration example, the first semiconductor chip 82 is placed on the placement surface 83f before the photosensitive resin constituting the frame-shaped portion 86 is completely cured (for example, during preliminary curing). The adhesion between the first semiconductor chip 82 and the photosensitive resin 86 can be further improved. As a result, generation of a gap (void) between the first semiconductor chip 82 and the photosensitive resin 86 can be suppressed, and an interface excellent in moisture resistance can be formed.

  Next, as a first wiring layer forming step, the frame-shaped portion 86 is electrically connected to the first pad 14 and from the first pad 14 along the first main surface 82a and the inclined side wall surface 82b. A first wiring layer 18 extending to the upper side of the main surface 86j that is the third main surface is formed.

  Therefore, as shown in FIG. 11B, first, for example, the top surface of the first pad 14 extends over the main surface 82a and the inclined sidewall surface 82b of the first semiconductor chip 82 and the main surface 86j of the frame-shaped portion 86. Then, an insulating film 16 composed of a laminated film in which a silicon oxide film and a polyimide film are sequentially laminated is formed.

  Since there is a height difference (step) between the main surface 82a of the first semiconductor chip 82 and the surface of the frame-shaped portion 86 constituting the ground of the insulating film 16, the insulating film is formed corresponding to this step. The

  Subsequently, the first wiring layer 18 made of copper is formed so that one end of the first wiring layer 18 is connected to the first pad 14 and on the insulating film 16 from the inclined sidewall surface 82b to the main surface 86j of the frame-shaped portion 86. The cut surface is bent and extended in accordance with the height difference between the main surface 82a and the third main surface 86j of the frame-shaped portion 86, and is formed by photolithography, sputtering, or the like.

  At this time, portions of the first wiring layer 18 located on the boundary between the main surface 82a and the side wall surface 82b of the semiconductor chip and on the boundary between the side wall surface 82b and the main surface 86j of the photosensitive resin (in the drawing, The width of a portion surrounded by a broken line z) in a direction substantially perpendicular to the extending direction of the first wiring layer 18 (a direction perpendicular to the drawing sheet) of the other (remaining) portions of the first wiring layer. It is good to form so that it may become wider than the said width | variety.

  As a result, it is possible to reinforce the first wiring layer 18 on these boundaries that are weak against impact and stress concentration.

  Next, as an external terminal formation step, the first wiring layer 18 is electrically connected to the upper side of the portion extending to the frame-shaped portion 86 via the first pad 14 and the first wiring layer 18. Form external terminals.

  First, a corresponding post portion 20 made of copper is formed on the first wiring layer 18 extending on the surface of each insulating film 16 on the frame-shaped portion 86 by photolithography, plating, or the like.

  Subsequently, a sealing layer 22 is formed on the mounting surface side of the substrate 83 on which the post portion 20 is formed by a transfer molding method using a sealing material made of an organic resin (epoxy resin or the like) until the post portion 20 is hidden. To do. Thereafter, the sealing layer 22 and the post portion 20 are polished by a grinder or the like, and the top surfaces of all the post portions 20 are exposed to form mounting surfaces of external terminals.

  Thereafter, solder balls 24 as external terminals, which are bumps for connection to a printed circuit board (not shown), are reflow formed on the exposed mounting surface for external terminals. In this configuration example, the minimum interval between the solder balls 24, which are external terminals, can be set to 0.3 mm or more, for example (FIG. 11C).

  After that, each semiconductor device (package) 80 is cut out with a normal blade or the like that rotates at high speed and does not chamfer (see FIG. 9B).

  As is clear from the above description, this embodiment can obtain the same effects as those of the first embodiment.

  Furthermore, in this embodiment, since the frame-shaped portion as described above is provided, a portion exposed from the frame-shaped portion of the side wall of the first semiconductor chip may be an inclined side wall surface. Therefore, in this embodiment, the wall surface other than the inclined side wall surface of the first semiconductor chip can be a vertical wall (vertical end surface).

  Therefore, since the depth of dicing can be made smaller than in the case of forming the inclined side wall surface by dicing reaching the back surface of the chip as in the first embodiment, the width of the wafer dicing line can be reduced. .

  As a result, the number of chips collected per wafer can be improved, and an increase in the product cost of the semiconductor device can be suppressed.

  In addition, since the amount of use of the V-shaped blade that is easily worn can be reduced, the life of the blade is longer than that of the first embodiment, and the cutting when the first semiconductor chip is separated into pieces is cut. You can save time.

<Seventh embodiment>
With reference to FIG. 12, a semiconductor device 90 according to a seventh embodiment of the present invention will be described.

  As shown in FIG. 12, the semiconductor device 90 of this embodiment is not provided with a substrate 83 as a support part, which is a main difference from the sixth embodiment.

  In addition, in the manufacturing method of the semiconductor device 90 of this embodiment, an adhesive having low adhesion is provided between the back surface 82d of the first semiconductor chip 82 and the mounting surface 83f in the mounting process described in the sixth embodiment. Fix by (not shown). As the low-adhesive adhesive, for example, a cured polyimide film or the like that has been subjected to ashing treatment using light plasma or introduction of hydrophobic groups using CF4 plasma treatment, or the like can be used.

  Then, after performing the external terminal formation step in the same manner as in the sixth embodiment, in this embodiment, a support portion removing step is performed in which the substrate 83 is peeled off by vacuum or the like to obtain the semiconductor device 90. .

  As is apparent from the above description, this embodiment can provide the same effects as those of the sixth embodiment.

  Further, in this embodiment, since the substrate 83 which is a support portion is not provided, the semiconductor device can be made thinner than the sixth embodiment.

  Further, since the adhesive as in the sixth embodiment is unnecessary, there is no concern about dimensional errors and chemical resistance due to thermal expansion and the like, and thus a highly reliable semiconductor device is obtained.

<Eighth Embodiment>
A semiconductor device 95 according to the eighth embodiment of the present invention will be described with reference to FIG.

  In this embodiment, a through hole 96 which is a through portion having a conductor portion 98 for conducting between the front and back of the photosensitive resin 86 is formed in the photosensitive resin 86 which is a frame-shaped portion, and The main difference from the seventh embodiment is that the conductor portion 98 is electrically connected to the first wiring layer 18.

  As shown in FIG. 13, a through hole 96 is formed in the photosensitive resin 86 that is a frame-shaped portion, and a conductor portion that allows conduction between the front and back of the photosensitive resin 86 on the entire inner wall of the through hole 96. (Copper plating layer) 98 is formed. A third land 97 and a seventh pad 99 made of copper are formed at both ends of the through hole 96, respectively.

  The conductor portion 98 of the through hole 96 is electrically connected to the first wiring layer 18 through the exposed third land 97, as in the case of the other embodiments described above. Further, the seventh pad 99 here is, for example, a semiconductor device mounting pad or a passive element mounting pad such as a coil or a capacitor when the semiconductor device is formed as a package stacked semiconductor device.

  Further, when a package stacked type semiconductor device is constituted by the semiconductor device 95, the solder ball 24 of the semiconductor device 95 and, for example, the seventh pad 99 of the semiconductor device 95 having the same structure are bonded to each other. A plurality of semiconductor chips 82 may be stacked in the thickness direction.

  Further, the output signal from the first semiconductor chip 82 in this configuration example is a path from the first pad 14 to the solder ball 24 via the first wiring layer 18 and the post portion 20, and from the first pad 14. The signal is transmitted through both or one of the routes reaching the seventh pad 99 via the first wiring layer 18, the third land 97, and the through hole 96. Further, input signals from the solder balls 24 and the seventh pad 99 are transmitted through a path reverse to the above.

  Further, in the manufacturing method of the semiconductor device 95 in this embodiment, the third semiconductor chip 82 is exposed to the through hole 96 at a predetermined position, as in the mounting process described in the seventh embodiment. The land 97 is placed and fixed at a position where the land 97 is surrounded by a pre-formed photosensitive resin 86 via an adhesive (not shown) having low adhesiveness. Similarly to the first wiring layer forming step described in the seventh embodiment, first, the insulating film 16 is formed so as to expose the top surfaces of the first pads 14 and the third lands 97, and then the first wiring layer forming step is performed. The first wiring layer 18 is formed so that the first pad 14 and the third land 97 for which the connection relationship between the first pad 14 is designated are connected. And after carrying out to an external terminal formation process similarly to 7th Embodiment, the support part removal process which peels and removes the board | substrate 83 with a vacuum etc. is performed. Thereafter, a seventh pad 99 is formed at a position corresponding to each through hole 96 to obtain the semiconductor device 95. In the formation of the through hole 96 in this configuration example, first, a through hole is formed in the photosensitive resin 86 by photolithography etching. Then, after coating the conductor portion 98 on the inner wall of the through hole by a printing method or the like, the photosensitive resin is cured, and the conductor portion 98 is formed on the cured resin by a plating method or the like. In this configuration example, the first semiconductor chip 82 may be placed before the photosensitive resin is completely cured. In this case, the adhesion between the first semiconductor chip 82 and the photosensitive resin 86 can be further improved, and an interface excellent in moisture resistance can be formed.

  As is clear from the above description, this embodiment can obtain the same effects as those of the seventh embodiment.

  Furthermore, when this semiconductor device is stacked to form a package stacked semiconductor device, a fan-in structure that is difficult with the conventional WB package stacked semiconductor device is possible. Thinning can be achieved.

  As mentioned above, this invention is not limited only to the combination of embodiment mentioned above. Therefore, the present invention can be applied by combining suitable conditions at any suitable stage.

  For example, in each of the above-described embodiments, the BGA type has been described. However, the present invention may be suitably applied to the LGA type.

  In each of the above-described embodiments, the semiconductor device having a fan-in / fan-out structure has been described. However, the semiconductor device may have only a fan-out structure depending on the purpose and design.

  As apparent from the above description, according to the present invention, external terminals are provided not only above the first semiconductor chip (ie, fan-in portion) but also in regions other than above the first semiconductor chip (ie, fan-out portion). The fan-out structure can be arranged, and the semiconductor device can cope with an increase in the number of pins as compared with a normal WCSP.

  Furthermore, since the electrode pads on the semiconductor chip and the external terminals are electrically connected via a wiring layer (also referred to as a rewiring layer), the total signal wiring length can be shortened as compared with the WB method. Therefore, the semiconductor device has excellent high frequency characteristics.

  In the semiconductor device of the present invention, the first main surface of the first semiconductor chip, the side wall surface, and the second region of the semiconductor chip mounting portion are exposed so that the first pad provided on the first main surface is exposed. And an insulating film including a protective film formed of a low-hardness film material. According to the semiconductor device of the present invention, the protective film included in the insulating film can prevent the impact on the first semiconductor chip during the manufacturing process and the peeling due to the stress between the sealing layer and the semiconductor chip.

1A is a schematic plan view showing a semiconductor device according to the first embodiment of the present invention, and FIG. 1B is a schematic cross-sectional view showing a part of the semiconductor device according to the first embodiment of the present invention. It is. (A)-(C) are schematic sectional drawings with which it uses for description of the manufacturing process of the semiconductor device of 1st Embodiment of this invention. (A)-(C) are schematic sectional drawings with which it uses for description of the manufacturing process of the semiconductor device of 1st Embodiment of this invention. (A) is a schematic plan view which shows the semiconductor device of 2nd Embodiment of this invention, (B) is schematic sectional drawing which shows a part of semiconductor device of 2nd Embodiment of this invention It is. (A) is a schematic plan view showing a semiconductor device according to a third embodiment of the present invention, and (B) is a schematic cross-sectional view showing a part of the semiconductor device according to the third embodiment of the present invention. It is. (A)-(C) are schematic sectional drawings with which it uses for description of the manufacturing process of the semiconductor device of the 3rd Embodiment of this invention. (A) is a schematic plan view which shows the semiconductor device of 4th Embodiment of this invention, (B) is schematic sectional drawing which shows a part of semiconductor device of 4th Embodiment of this invention It is. (A) is a schematic top view which shows the semiconductor device of 5th Embodiment of this invention, (B) is schematic sectional drawing which shows a part of semiconductor device of 5th Embodiment of this invention It is. (A) is a schematic top view which shows the semiconductor device of 6th Embodiment of this invention, (B) is schematic sectional drawing which shows a part of semiconductor device of 6th Embodiment of this invention It is. (A)-(C) are schematic sectional drawings with which it uses for description of the manufacturing process of the semiconductor device of 6th Embodiment of this invention. (A)-(C) are schematic sectional drawings with which it uses for description of the manufacturing process of the semiconductor device of 6th Embodiment of this invention. It is a schematic sectional drawing which shows a part of semiconductor device of 7th Embodiment of this invention. It is a schematic sectional drawing which shows a part of semiconductor device of 8th Embodiment of this invention.

Explanation of symbols

10, 11, 50, 60, 70, 80, 90, 95: Semiconductor device 12: Substrate (semiconductor chip mounting portion)
12a: Board mounting surface (third main surface)
12b: Substrate mounting surface (first region)
12c: Non-mounting surface of substrate (second region)
12i: Back surface of substrate (fourth main surface)
14: First pad 15, 82: First semiconductor chip 15a: Main surface of first semiconductor chip (first main surface)
15b: Side wall surface of the first semiconductor chip 15c: Back surface (second main surface) of the first semiconductor chip
15x: Side walls of the first semiconductor chip 15 ', 82': First semiconductor chip 16 and 21 before separation: Insulating film 18: First wiring layer (first rewiring layer)
19: Blade (with V-shaped blade)
20: Post part 22: Sealing layer 24: Solder ball (external terminal)
30, 81: Semiconductor wafer 32: Wafer fixing tape 36, 89: Groove 38, 52, 96: Through hole (through portion)
39, 54, 98: Conductor portion 40: Third pad 42: First land 43: Second pad 44: Second semiconductor chip 44a: Mounting surface (third main surface) of the second semiconductor chip
44b: placement surface (first region) of the second semiconductor chip
44c: Non-mounting surface (second region) of the second semiconductor chip
44i: Back surface (fourth main surface) of the second semiconductor chip
45: Fourth pad 46: Fifth pad 49: Second wiring layer (second rewiring layer)
53: Second land 56: Sixth pad 79: Blade (no V-shaped blade)
82a: main surface of first semiconductor chip (first main surface)
82b: inclined side wall surface of the first semiconductor chip 82c: vertical wall surface of the first semiconductor chip 82d: back surface (second main surface) of the first semiconductor chip
83: Substrate (support part)
83e: Substrate mounting surface 83f: Substrate mounting surface 83g: Non-substrate mounting surface 86: Photosensitive resin (frame-shaped portion)
86j: main surface of photosensitive resin (third main surface)
86k: Back surface of photosensitive resin (fourth main surface)
97: Third Land

Claims (11)

A first main surface having a plurality of first pads; a second main surface facing the first main surface and having a larger area than the first main surface; the first main surface and the second main surface; A first semiconductor chip having a side wall surface to be connected;
A semiconductor having a third main surface having a first region on which the first semiconductor chip is mounted and a second region surrounding the first region, and a fourth main surface facing the third main surface. A chip mounting portion;
A first external terminal provided on the first main surface of the first semiconductor chip;
A second external terminal provided on the second region of the semiconductor chip mounting portion;
A first wiring connecting the first pad and the first external terminal;
Connecting the first pad and the second external terminal, a second wiring provided over the first main surface, the side wall surface, and the second region;
A semiconductor device comprising:   2. The semiconductor device according to claim 1, wherein the semiconductor chip mounting portion includes a conductor portion penetrating from the third main surface to the fourth main surface, and the conductor portion is electrically connected to the second wiring. A semiconductor device characterized by being connected to the semiconductor device.   3. The semiconductor device according to claim 1, wherein the third main surface of the semiconductor chip mounting portion crosses the second main surface so as to face the second main surface of the first semiconductor chip. A wiring portion is provided, and the wiring portion is electrically connected to the second wiring, and the first pad is connected to the second external terminal via the second wiring and the wiring portion. A semiconductor device which is electrically connected.   4. The semiconductor device according to claim 1, wherein the semiconductor chip mounting portion is a second semiconductor chip having a second pad, and the second pad of the second semiconductor chip is the second wiring. A semiconductor device which is electrically connected to the semiconductor device.   3. The semiconductor device according to claim 1, wherein the semiconductor chip mounting portion is a second semiconductor chip, and the second main part of the first semiconductor chip is between the first semiconductor chip and the second semiconductor chip. A third wiring crossing the second main surface opposite to the surface; the third wiring being electrically connected to the second wiring; and the first pad being the second pad A semiconductor device, wherein the semiconductor device is electrically connected to the second external terminal through a wiring and the third wiring.   6. The semiconductor device according to claim 1, a post portion provided between the second wiring and the second external terminal, the second wiring, and the post portion. And a sealing layer provided on the side surface of the semiconductor device.   The semiconductor device according to claim 6, wherein an oxide film is formed on a side surface of the post portion embedded in the sealing layer in the post portion.   8. The semiconductor device according to claim 1, wherein a width of a portion of the second wiring located on a boundary between the first main surface and the side wall surface is the second wiring. A semiconductor device characterized in that it is formed wider than the remaining portion of the wiring.   A semiconductor device according to claim 2, wherein a plurality of the semiconductor devices are stacked in a thickness direction of the first semiconductor chip. 4. The semiconductor device according to claim 3, wherein the wiring portion is provided at a position crossing the second main surface with respect to the first pad together with the second wiring, and the first pad and the second pad. A semiconductor device characterized in that a path for electrically connecting the external terminal is formed. A first main surface having a plurality of first pads; a second main surface facing the first main surface and having a larger area than the first main surface; the first main surface and the second main surface; Preparing a first semiconductor chip having a side wall surface to be connected;
Mounting the first semiconductor chip on a semiconductor chip having a third main surface having a first region and a second region surrounding the first region, and a fourth main surface facing the third main surface Mounting on the first region of the portion;
A first wiring connected to the first pad and extending on the first main surface; and connected to the first pad; the first main surface; the side wall surface; And forming a second wiring formed to extend over the second region;
A first external terminal connected to the first wiring and formed on the first main surface of the first semiconductor chip, and connected to the second wiring and the second of the semiconductor chip mounting portion. Forming a second external terminal formed on the region of
A method for manufacturing a semiconductor device, comprising:

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