JP2008053628A - Solid-state imaging apparatus and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve sensitivity by reducing layer thickness from a photoelectric converter to an inner-layer lens, and to reduce manufacturing process steps in a CMOS-type solid-state imaging apparatus. <P>SOLUTION: The apparatus includes an imaging region where a plurality of pixels 50 are arranged, and multilayer Cu wiring 621 to 623 formed in an upper part of the plurality of pixels 50 via interlayer dielectrics 61, wherein each pixel 50 comprises a photoelectric conversion section PD and MOS transistors Tr1, Tr2. In each pixel, an inner-layer lens 64 is formed using a diffusion-preventing film 633 for the Cu wiring. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

The present invention relates to a solid-state imaging device incorporating an in-layer lens and a manufacturing method thereof.
In particular, the present invention relates to a solid-state imaging device including a conversion unit that converts a charge generated by photoelectric conversion into a pixel signal, that is, a solid-state imaging device including a plurality of pixels including a photoelectric conversion unit and a MOS transistor, For example, the present invention relates to a CMOS image sensor and a manufacturing method thereof.

  Here, the CMOS image sensor is an image sensor created by applying or partially using a CMOS process. Further, as a form of the solid-state imaging device, it may be one chip or a plurality of chips.

  A CMOS image sensor is known as a solid-state imaging device. FIG. 15 shows an example of the configuration (equivalent circuit) of the CMOS image sensor. The CMOS image sensor 1 includes two pixels 3 each including a photoelectric conversion unit that performs photoelectric conversion, a so-called photodiode 2 and a plurality of MOS transistors for selectively reading out the photodiode 2 on the same semiconductor substrate. The imaging region 4 is arranged in a dimensional manner. Further, peripheral circuits 5 and 6 for selecting pixels and outputting signals are provided around the imaging region 4 on the same semiconductor substrate.

  The pixel 3 includes a single photodiode 2 and a plurality of MOS transistors, in this example, three MOS transistors including a transfer transistor 8, a reset transistor 9, and an amplifying transistor 10. Further, as peripheral circuits, a pixel selection circuit (vertical scanning circuit) 5 and an output circuit (horizontal scanning / output circuit) 6 are configured using CMOS transistors. In addition, although not shown, the peripheral circuit is provided with a column signal processing circuit, a control circuit for generating a clock signal and a control signal, and the like.

  The photodiode 2 is connected to the source of the transfer transistor 8. A transfer wiring 11 is connected to the gate of the transfer delegating transistor 8. The drain of the transfer transistor 8 is connected to the source of the reset transistor 9 and the gate of the amplifying transistor 10 via a so-called floating diffusion FD between the drain of the transfer transistor 8 and the source of the reset transistor 9. Connected to. The gate of the reset transistor 9 is connected to the reset wiring 12. Further, the drain of the reset transistor 9 and the drain of the amplification transistor 10 are connected to a power supply wiring 13 for supplying power. The source of the amplifying transistor 10 is connected to the vertical signal line 14.

  In recent years, in the CMOS image sensor market that continues to expand rapidly, the demand for increasing the number of pixels and improving the basic characteristics has not stopped. In CMOS image sensors, by reducing the size of the pixels, the number of pixels in the same chip size is increased. On the other hand, the chip size is shrunk in the same number of pixels, and the gas for contributing to the increase in the number of pixels in the set and size reduction is high. .

  As one of the technologies for achieving the increase in the number of pixels, the Cu wiring process is used to achieve the increase in the number of pixels by forming fine pixels, and technical development for that purpose has been actively conducted. In the solid-state imaging device, various techniques have been proposed for improving problems unique to the Cu wiring process that occur when the Cu wiring process is used (see, for example, Patent Document 1).

  On the other hand, a configuration in which an in-layer lens is further provided in addition to the on-chip lens is known in order to increase the concentration of incident light and further improve the sensitivity. In the Cu wiring process, after forming a Cu wiring layer, in order to suppress Cu diffusion, a manufacturing method is generally used in which a diffusion prevention film made of, for example, a SiC film or a SiN film is formed. In a CMOS image sensor using a Cu wiring process, an intra-layer lens is formed by forming a new layer on a diffusion prevention film and processing the layer (Patent Document 2). reference).

  FIG. 14 shows an example of a CMOS image sensor having a conventional intralayer lens. The CMOS image sensor 21 includes a photodiode PD formed of an n-type charge storage region 23 and a p-type semiconductor region (p-type accumulation layer) 24 on the main surface of a semiconductor substrate 22. A MOS transistor is formed. In the figure, among the plurality of MOS transistors, a transfer transistor Tr1 and a reset transistor Tr2 are shown. The transfer transistor Tr1 includes an n-type semiconductor region 25 that becomes a floating diffusion FD, a photodiode PD, and a transfer gate electrode 26 formed through a gate insulating film. The reset transistor Tr2 includes an n-type semiconductor region 25 that becomes a floating diffusion FD, an n-type semiconductor region 27, and a reset gate electrode 28 formed through a gate insulating film. The unit pixel is separated from adjacent pixels in the element isolation region 29.

On the semiconductor substrate 22 on which the pixels are formed, a multilayer wiring made of Cu wiring 32 is formed via an interlayer insulating film 31 made of, for example, a SiO ₂ film. In this example, three layers of Cu wiring 32 are formed. On the Cu wiring 32 of each layer, a diffusion preventing film 33 made of, for example, a SiC film or a SiN film is formed in order to prevent diffusion of Cu. Here, the refractive index (n = 2.05) of, for example, the SiC film and the SiN film serving as the diffusion preventing film 33 is compared with the refractive index (n = 1.46) of, for example, the SiO ₂ film serving as the interlayer insulating film 31. Therefore, the incident light is reflected at the interface between the interlayer insulating film 31 and the diffusion prevention film 33, causing multiple interference and degrading the spectral characteristics of the image sensor. For this reason, the portion corresponding to the photodiode PD is removed from the diffusion prevention film 33 of each layer. Corresponding to the photodiode PD, an insulating film 34 made of the same SiO ₂ film as the interlayer insulating film 31 is formed including the portion from which the diffusion preventing film 33 has been removed.

The intralayer lens 36 is configured by forming a recess in the insulating film 34 made of this SiO ₂ film and forming a SiN film 37 so as to fill the recess.
Further, a color filter 39 is formed on the upper surface via a planarizing film 38 made of an SiN film, and an on-chip microlens 40 is formed on the color filter 39.

JP 2003-324189 A JP-A-2005-311015

  By the way, in the CMOS image sensor 21 having the conventional inner lens, as a method for forming the inner lens 36, as described above, the new layers (insulating films) 34, 36 are formed on the diffusion prevention film, The layers 34 and 36 are processed to form an in-layer lens. For this reason, there are problems in terms of complexity of manufacturing, cost, and characteristics such that the number of manufacturing steps increases, the layer thickness h1 from the photodiode PD to the inner lens 36 increases, and the sensitivity decreases.

  In view of the above, the present invention aims to improve the sensitivity by reducing the layer thickness from the photoelectric conversion portion to the inner lens, and to reduce the number of manufacturing steps, and to manufacture the same. A method is provided.

  A solid-state imaging device according to the present invention includes an imaging region in which a plurality of pixels including a photoelectric conversion unit and a MOS transistor are arranged, and a multilayer Cu wiring formed above the plurality of pixels via an interlayer insulating film. And an intralayer lens is formed using a diffusion preventing film for Cu wiring.

  In the solid-state imaging device of the present invention, since the inner lens is formed using the diffusion preventing film of Cu wiring, the layer thickness from the photoelectric conversion unit to the inner lens is reduced. Further, it is not necessary to separately provide a layer for constituting the in-layer lens.

  A method of manufacturing a solid-state imaging device according to the present invention includes a step of forming a plurality of pixels including a photoelectric conversion unit and a MOS transistor, and forming a Cu wiring via an interlayer insulating film above the plurality of pixels. A step of forming a diffusion prevention film having a required thickness on the wiring and a surface including a region corresponding to the photoelectric conversion unit, and forming an intralayer lens-shaped member on the diffusion prevention film, and performing an etch-back process, It has the process of forming the lens in a layer by a diffusion prevention film.

  According to the method for manufacturing a solid-state imaging device according to the present invention, a diffusion prevention film having a required thickness is formed in a region corresponding to a Cu wiring and a photoelectric conversion unit, and an in-layer lens-shaped member is formed thereon. In addition, since the inner lens is formed by the anti-diffusion film by performing the etch back process, the inner lens can be formed using the existing layer, and it is necessary to newly provide a layer for the inner lens. Absent. Since the inner lens is formed using the diffusion prevention film for the Cu wiring, the layer thickness from the photoelectric conversion portion to the inner lens can be reduced.

  According to the solid-state imaging device according to the present invention, the inner lens is formed by the diffusion preventing film of the Cu wiring, and the layer thickness from the photoelectric conversion unit to the inner lens is reduced, so that the incident light is further collected. Thus, the sensitivity can be further improved. Since it is not necessary to separately provide a layer constituting the in-layer lens, the number of manufacturing steps can be reduced.

  According to the method for manufacturing a solid-state imaging device according to the present invention, a solid-state imaging device having an in-layer lens can be manufactured by reducing the number of manufacturing steps. Further, since the inner lens is formed by reducing the layer thickness from the photoelectric conversion unit to the inner lens, it is possible to manufacture a solid-state imaging device excellent in collecting incident light.

  Embodiments of the present invention will be described below with reference to the drawings.

  The solid-state imaging device according to the embodiment of the present invention includes a CMOS image sensor provided with a pixel including one photodiode PD and three MOS transistors shown in FIG. 14 or one photodiode and a selection transistor. The present invention can be applied to a CMOS image sensor provided with a pixel from four MOS transistors to which is added, a CMOS image sensor in which a floating diffusion is shared by a plurality of pixels, and the like.

  FIG. 1 shows a first embodiment of a solid-state imaging device, a so-called CMOS image sensor according to the present invention. The solid-state imaging device 51 according to the present embodiment includes, for example, a first conductive type, for example, n-type charge storage region 53 and a second conductive type, for example, a p-type semiconductor region, on the main surface of a silicon semiconductor substrate 52. A photodiode PD serving as a photoelectric conversion unit including the so-called p-type accumulation layer 54 is formed. A plurality of MOS transistors are formed on the semiconductor substrate 52, and a unit pixel 50 is formed by the plurality of MOS transistors and the photodiode PD. The plurality of pixels 50 are two-dimensionally arranged to form an imaging region.

  FIG. 1 shows a transfer transistor Tr1 and a reset transistor Tr2 among a plurality of MOS transistors. The transfer transistor Tr1 includes an n-type semiconductor region 55 that becomes a floating diffusion FD, a photodiode PD, and a transfer gate electrode 56 formed through a gate insulating film therebetween. The reset transistor Tr2 includes an n-type semiconductor region 55 that becomes a floating diffusion FD, an n-type semiconductor region 57, and a reset gate electrode 58 formed through a gate insulating film. The pixel 50 is separated from adjacent pixels by an element isolation region 59 such as a selective oxide layer (LOCOS) or a trench isolation region.

On the semiconductor substrate 52 on which the pixels 50 are formed, a multilayer wiring made of Cu wiring 62 is formed via an interlayer insulating film 61 made of, for example, a SiO ₂ film. In this example, three layers of Cu wiring 62 [621, 622, 623] are formed. The Cu wiring 62 is formed by a so-called dual damascene method. On the Cu wiring 62 [621, 622, 623] of each layer, a diffusion preventing film 63 [631, 632, 633] for preventing the diffusion of Cu is formed. As the diffusion preventing film 63 of the Cu wiring 62, a SiC film or a SiN film is used.

  The floating diffusion FD serving as the drain of the transfer transistor Tr1 is connected to the required Cu wiring 621 in the first layer through the buried conductive member 60. The n-type semiconductor region 57 serving as the drain of the reset transistor Tr2 is connected to the required Cu wiring 621 in the first layer through the buried conductive member 60. A barrier film 65 is formed on the lower and side surfaces of each Cu wiring 62.

  In the present embodiment, the intralayer lens 64 is formed using the diffusion prevention film 63 particularly at a position corresponding to the photodiode PD. In this example, the inner lens 64 is formed using the uppermost diffusion prevention film 633. The in-layer lens 64 is formed of an upward convex lens in this example. Of the anti-diffusion film 63, except for the uppermost (third layer) anti-diffusion film 633 on which the inner lens 64 is formed, the other anti-diffusion films 631, 632 of the first and second layers are A portion corresponding to the photodiode PD is selectively removed in order to suppress multiple interference at the interface between the interlayer insulating film 61 and an interlayer insulating film 66 described later.

Further, a color filter 67 and an on-chip microlens 68 are formed on the color filter 67 via an interlayer insulating film 66 that becomes a planarizing film made of, for example, an SiO ₂ film so as to cover the inner lens 64.

3 to 7 show a method for manufacturing the solid-state imaging device 51 according to the first embodiment.
First, as shown in FIG. 3A, for example, a photodiode PD serving as a photoelectric conversion unit and a plurality of MOS transistors (in this example, only a transfer transistor Tr1 and a reset transistor Tr2 are shown) on the main surface side of a silicon semiconductor substrate 52. A plurality of pixels 50 are formed. That is, a photodiode PD comprising a first conductivity type, for example, n-type charge storage region 53 and a p-type accumulation layer 54 of the second conductivity type on the surface thereof is formed on the main surface of the semiconductor substrate 52. Further, an n-type semiconductor region 55 and an n-type semiconductor region 57 to be a floating diffusion FD are formed on the main surface side of the semiconductor substrate 52, and a gate insulating film is interposed between the photodiode PD and the n-type semiconductor region 55, for example. A transfer gate electrode 56 made of polycrystalline silicon is formed to form a transfer transistor Tr1, and a reset gate electrode 58 made of, for example, polycrystalline silicon is formed between the n-type semiconductor region 55 and the n-type semiconductor region 57 via a gate insulating film. Thus, the reset transistor Tr2 is formed. An element isolation region 59 is formed on the semiconductor substrate 52 so as to partition each pixel 50.

  Further, a first-layer Cu wiring 621 is formed on the semiconductor substrate 52 on which the pixels 50 are formed by using a dual damascene method through an interlayer insulating film 611 made of, for example, an SiO film. Before the formation of the Cu wiring 621, the conductive layer 60 is electrically connected to the floating diffusion FD and the n-type semiconductor region 57, and then connected to the Cu wiring 621. A barrier film 65 made of TaN is formed. The barrier film 65 becomes a Cu diffusion preventing film.

  Next, a first-layer Cu diffusion prevention film 631 is formed on the entire surface in contact with the upper surface of the first-layer Cu wiring 621 by, for example, a SiC film or a SiN film, and an interlayer insulating film 612 is formed on the diffusion-prevention film 631. Form. Further, a second-layer Cu wiring 622 covered with the barrier film 65 is formed in the interlayer insulating film 612 in the same manner as described above.

  Next, as shown in FIG. 3B, a second-layer Cu diffusion prevention film 632 is formed on the entire surface in contact with the upper surface of the second-layer Cu wiring 622.

  Next, as shown in FIG. 3C, through the resist mask (not shown), the diffusion prevention films 631 and 632 of the first layer and the second layer of the portions corresponding to the photodiode PD which is the light receiving unit. Are removed together with the interlayer insulating films 611 and 612 by etching. An opening 71 is formed by this etching removal.

Next, as shown in FIG. 4D, an interlayer insulating film 613 made of, for example, a SiO ₂ film is formed on the entire surface including the second-layer diffusion prevention film 632 so as to fill the opening 71.

  Next, as shown in FIG. 4E, the interlayer insulating film 613 is polished to a required film thickness by, for example, a CMP (Chemical Mechanical Polishing) method to flatten the surface.

  Next, as shown in FIG. 4F, a third-layer Cu wiring 623 covered with the barrier film 65 is formed in the interlayer insulating film 613 in the same manner as described above.

  Next, as shown in FIG. 5G, a third-layer Cu diffusion prevention film 633 is formed on the entire surface in contact with the upper surface of the third-layer Cu wiring 623. The third-layer diffusion prevention film 633 is formed to have a required thickness sufficient to form an in-layer lens. That is, the film thickness of the third layer diffusion prevention film 633 is made thicker than the film thicknesses of the other first layer and second layer diffusion prevention films 631 and 632.

  Next, as shown in FIG. 5H, a resist layer 72 to be an intra-layer lens-shaped member is selectively formed at a position corresponding to the photodiode PD on the third-layer diffusion prevention film 633. The resist layer 72 can be formed using a normal lithography technique.

  Next, as shown in FIG. 6I, the resist layer 72 is reflowed to form an in-layer lens-shaped member 73 made of the resist layer.

  Next, as shown in FIG. 6J, the third-layer diffusion prevention film 633 is etched back together with the inner-layer lens-shaped member 73 to form the inner lens 64 by the third-layer diffusion prevention film 633. . The film thickness of the diffusion preventive film 633 in the region other than the inner lens 64 is equal to the film thickness of the first and second diffusion preventive films 631 and 632.

Next, as shown in FIG. 7K, an interlayer insulating film 66 made of, for example, an SiO ₂ film is formed on the entire surface so as to cover the inner lens 64, and the surface is flattened by, eg, CMP. This interlayer insulating film 66 becomes a planarizing film.

  Next, as shown in FIG. 7J, a color filter 67 is formed on an interlayer insulating film 66 to be a planarizing film, and an on-chip microlens 68 is formed thereon, thereby obtaining a target solid-state imaging device 51.

  According to the solid-state imaging device 51 and the manufacturing method thereof according to the first embodiment described above, the inner lens 64 is formed using the diffusion prevention film 633 of the uppermost layer (third layer) of Cu wiring. The layer thickness h2 from the photodiode PD serving as the conversion unit to the in-layer lens 64 is lower than the layer thickness h1 of the conventional solid-state imaging device of FIG. Therefore, the light collection efficiency of incident light onto the photodiode PD is advantageous, and the sensitivity can be further improved. Further, since the inner lens 64 is formed using the existing diffusion prevention film 633, it is not necessary to separately form a layer for the inner lens, the number of manufacturing steps can be reduced, and the manufacturing can be simplified. be able to. As described above, this embodiment is advantageous in terms of characteristics (sensitivity), manufacturing, and cost as compared with the conventional structure of FIG.

Further, the portions on the light receiving portions (on the photodiode PD) of the first and second diffusion preventing films 631 and 632 other than the uppermost diffusion preventing film 633 forming the inner lens 64 are selectively used. Since it is removed, deterioration of spectral characteristics can be avoided.
Further, since the anti-diffusion film 633 for forming the in-layer lens 64 is formed thicker than the other anti-diffusion films 631, 632, the formation of the in-layer lens 64 is ensured and the film thicknesses of the other anti-diffusion films 631, 632 are secured. Since the thickness is made thinner, the overall layer thickness can be suppressed.

  FIG. 2 shows a second embodiment of a solid-state imaging device according to the present invention, a so-called CMOS image sensor. In FIG. 2, parts corresponding to those in FIG. As in FIG. 1, the solid-state imaging device 81 according to the present embodiment has a first conductivity type, for example, an n-type charge accumulation region 53 and a second conductivity type on the surface thereof, for example, on the main surface of a silicon semiconductor substrate 52. For example, a photodiode PD serving as a photoelectric conversion unit including a p-type semiconductor region (so-called p-type accumulation layer) 54 is formed. A plurality of MOS transistors are formed on the semiconductor substrate 52, and a unit pixel 50 is formed by the plurality of MOS transistors and the photodiode PD. The plurality of pixels 50 are two-dimensionally arranged to form an imaging region.

  In FIG. 2, as in FIG. 1, the transfer transistor Tr1 and the reset transistor Tr2 are shown among the plurality of MOS transistors. The transfer transistor Tr1 includes an n-type semiconductor region 55 that becomes a floating diffusion FD, a photodiode PD, and a transfer gate electrode 56 formed through a gate insulating film therebetween. The reset transistor Tr2 includes an n-type semiconductor region 55 that becomes a floating diffusion FD, an n-type semiconductor region 57, and a reset gate electrode 58 formed through a gate insulating film. The pixel 50 is separated from adjacent pixels by an element isolation region 59 such as a selective oxide layer (LOCOS) or a trench isolation region.

  On the semiconductor substrate 52 on which the pixels 50 are formed, a multilayer wiring made of Cu wiring 62 is formed via an interlayer insulating film 61 made of, for example, a SiO film. In this example, three layers of Cu wiring 62 [621, 622, 623] are formed. The Cu wiring 62 is formed by a so-called dual damascene method. On the Cu wiring 62 [621, 622, 623] of each layer, a diffusion preventing film 63 [631, 632, 633] for preventing the diffusion of Cu is formed. As the diffusion preventing film 63 of the Cu wiring 62, a SiC film or a SiN film is used.

  The floating diffusion FD serving as the drain of the transfer transistor Tr1 is connected to the required Cu wiring 621 in the first layer through the buried conductive member 60. The n-type semiconductor region 57 serving as the drain of the reset transistor Tr2 is connected to the required Cu wiring 621 in the first layer through the buried conductive member 60. A barrier film 65 is formed on the lower and side surfaces of each Cu wiring 62.

  In the second embodiment, the in-layer lens 64 is formed using the second-layer diffusion prevention film 632 particularly at a position corresponding to the photodiode PD. The in-layer lens 64 is formed of an upward convex lens in this example. In the diffusion prevention film 63, except for the second-layer diffusion prevention film 632 in which the intralayer lens 64 is formed, portions of the other diffusion prevention films 631 and 633 corresponding to the photodiode PD are the interlayer insulating film 61. In order to suppress multiple interference at the interface with an interlayer insulating film 66, which will be described later, it is selectively removed.

  Further, a color filter 67 and an on-chip microlens 68 are formed on the color filter 67 through an interlayer insulating film 66 that becomes a planarizing film made of, for example, an SiO film so as to cover the inner lens 64.

8 to 13 show a method for manufacturing the solid-state imaging device 81 according to the second embodiment.
First, as shown in FIG. 8A, for example, a photodiode PD serving as a photoelectric conversion portion and a plurality of MOS transistors (in this example, only a transfer transistor Tr1 and a reset transistor Tr2 are shown) on the main surface side of a silicon semiconductor substrate 52. A plurality of pixels 50 are formed. That is, a photodiode PD comprising a first conductivity type, for example, n-type charge storage region 53 and a p-type accumulation layer 54 of the second conductivity type on the surface thereof is formed on the main surface of the semiconductor substrate 52. Further, an n-type semiconductor region 55 and an n-type semiconductor region 57 to be a floating diffusion FD are formed on the main surface side of the semiconductor substrate 52, and a gate insulating film is interposed between the photodiode PD and the n-type semiconductor region 55, for example. A transfer gate electrode 56 made of polycrystalline silicon is formed to form a transfer transistor Tr1, and a reset gate electrode 58 made of, for example, polycrystalline silicon is formed between the n-type semiconductor region 55 and the n-type semiconductor region 57 via a gate insulating film. Thus, the reset transistor Tr2 is formed. An element isolation region 59 is formed on the semiconductor substrate 52 so as to partition each pixel 50.

Further, a first-layer Cu wiring 621 is formed on the semiconductor substrate 52 on which the pixels 50 are formed by using a dual damascene method via an interlayer insulating film 611 made of, for example, a SiO ₂ film. Before the formation of the Cu wiring 621, the conductive layer 60 is electrically connected to the floating diffusion FD and the n-type semiconductor region 57, and then connected to the Cu wiring 621. A barrier film 65 made of TaN is formed. The barrier film 65 becomes a Cu diffusion preventing film.

  Next, as shown in FIG. 8B, a first-layer Cu diffusion prevention film 631 made of, for example, a SiC film or a SiN film is formed on the entire surface in contact with the upper surface of the first-layer Cu wiring 621.

  Next, as shown in FIG. 8C, the first-layer diffusion prevention film 631 corresponding to the photodiode PD, which is the light receiving portion, together with the interlayer insulating film 611, through a resist mask (not shown). , Selectively removed by etching. By this etching removal, an opening 83 is formed.

  Next, as shown in FIG. 9D, an interlayer insulating film 612 made of, for example, a SiO film is formed on the entire surface including the first diffusion prevention film 631 so as to fill the opening 83.

  Next, as shown in FIG. 9E, the interlayer insulating film 612 is polished to a required film thickness by, for example, a CMP (Chemical Mechanical Polishing) method to flatten the surface.

  Next, as shown in FIG. 9F, a second-layer Cu wiring 622 covered with the barrier film 65 is formed in the interlayer insulating film 612 in the same manner as described above.

  Next, as shown in FIG. 10G, a second-layer Cu diffusion prevention film 632 is formed on the entire surface in contact with the upper surface of the second-layer Cu wiring 622. The second-layer diffusion prevention film 632 is formed to have a required thickness sufficient to form an in-layer lens. That is, the second layer diffusion prevention film 632 is formed to be thicker than the other first layer diffusion prevention films 631.

  Next, as shown in FIG. 10H, a resist layer 84 to be an in-layer lens-shaped member is selectively formed at a position corresponding to the photodiode PD on the second-layer diffusion prevention film 632. The resist layer 72 can be formed using a normal lithography technique.

  Next, as shown in FIG. 10I, the resist layer 84 is reflowed to form an in-layer lens-shaped member 85 using the resist layer.

  Next, as shown in FIG. 11J, the second layer diffusion prevention film 632 is etched back together with the inner layer lens-shaped member 85 to form the inner lens 64 by the second layer diffusion prevention film 632. . The film thickness of the diffusion prevention film 632 in a region other than the inner lens 64 is equal to the film thickness of the first layer diffusion prevention film 631.

Next, as shown in FIG. 11K, an interlayer insulating film 613 made of, for example, a SiO ₂ film is formed on the entire surface so as to cover the inner lens 64.

  Next, as shown in FIG. 11L, a third-layer Cu wiring 623 covered with the barrier film 65 is formed in the interlayer insulating film 613 in the same manner as described above.

  Next, as shown in FIG. 12M, a third-layer Cu diffusion prevention film 633 is formed on the entire surface in contact with the upper surface of the third-layer Cu wiring 623.

  Next, as shown in FIG. 12N, the third-layer diffusion prevention film 633 corresponding to the inner lens 64 is selectively formed together with the interlayer insulating film 613 through a resist mask (not shown). Etch away. An opening 86 is formed by this etching removal.

Next, as shown in FIG. 12O, an interlayer insulating film 66 to be a planarizing film made of, for example, an SiO ₂ film is formed on the entire surface including the third-layer diffusion prevention film 633 so as to fill the opening 86. To do.

  Next, as shown in FIG. 13P, the interlayer insulating film 66 is polished to a required film thickness by, for example, a CMP (Chemical Mechanical Polishing) method to flatten the surface.

  Next, as shown in FIG. 13Q, a color filter 67 is formed on the interlayer insulating film 66 to be a planarizing film, and an on-chip microlens 68 is formed thereon to obtain a target solid-state imaging device 81.

  According to the solid-state imaging device 81 and the manufacturing method thereof according to the second embodiment described above (the inner lens 64 is formed using the diffusion prevention film 632 of the second-layer Cu wiring, The layer thickness h3 from the photodiode PD to the inner lens 64 is further lower than the layer thickness h2 of the solid-state imaging device 51 of the first embodiment in Fig. 1. Accordingly, the incident light is collected on the photodiode PD. The light efficiency is advantageous and the sensitivity can be further improved, and since the inner lens 64 is formed using the existing diffusion prevention film 632, there is no need to separately form a layer for the inner lens, Thus, the number of manufacturing steps can be reduced, and the manufacturing can be simplified.As described above, this embodiment is advantageous in terms of characteristics (sensitivity), manufacturing, and cost compared to the conventional structure of FIG. Become.

Further, the portions on the light receiving portions (on the photodiode PD) of the first and third diffusion preventing films 631 and 633 other than the second diffusion preventing film 632 forming the inner lens 64 are selected. Therefore, it is possible to avoid deterioration of spectral characteristics.
Further, since the anti-diffusion film 632 for forming the in-layer lens 64 is formed thicker than the other anti-diffusion films 631 and 633, the formation of the in-layer lens 64 is ensured and the film thickness of the other anti-diffusion films 631 and 633. Since the thickness is made thinner, the overall layer thickness can be suppressed.

In the above example, the in-layer lens 64 is composed of an upward convex lens, but it can also be composed of a downward convex lens.
In the above example, the inner lens 64 is configured using the uppermost (third layer) anti-diffusion film 633 or the second anti-diffusion film 632, but the other three layers of the anti-diffusion film 63 [ 631, 632, 633] can be used to form an intralayer lens by using any two layers of diffusion preventing films. In this case, a two-stage inner lens is formed. In addition, the inner lens can be formed using all of the three layers of the diffusion preventing films 631, 632, and 633. In this case, a three-stage inner lens is formed.

  The solid-state imaging device and the manufacturing method thereof according to the present invention described above are suitable for application to a CMOS image sensor with a large number of pixels and a small size.

It is a block diagram of the principal part which shows 1st Embodiment of the solid-state imaging device concerning this invention. It is a block diagram of the principal part which shows 2nd Embodiment of the solid-state imaging device which concerns on this invention. 8A to 8C are manufacturing process diagrams (part 1) of the solid-state imaging device according to the first embodiment. DF are manufacturing process diagrams (part 2) of the solid-state imaging device according to the first embodiment; GH is a manufacturing process diagram (No. 3) of the solid-state imaging device according to the first embodiment; IJ is a manufacturing process diagram (part 4) of the solid-state imaging device according to the first embodiment; KL is a manufacturing process diagram (part 5) for the solid-state imaging device according to the first embodiment; FIGS. 8A to 8C are manufacturing process diagrams (part 1) of the solid-state imaging device according to the second embodiment. DF are manufacturing process diagrams (part 2) of the solid-state imaging device according to the second embodiment; GI is a manufacturing process diagram (part 3) for a solid-state imaging device according to the second embodiment; FIG. J to L are manufacturing process diagrams (part 4) of the solid-state imaging device according to the second embodiment. M to O are manufacturing process diagrams (part 5) of the solid-state imaging device according to the second embodiment. P to Q are manufacturing process diagrams (part 6) of the solid-state imaging device according to the second embodiment. It is a block diagram of the principal part which shows an example of the conventional solid-state imaging device. It is a schematic block diagram (equivalent circuit) of a CMOS image sensor.

Explanation of symbols

  50..Pixel, 51, 81..Solid-state imaging device, 52..Semiconductor substrate, 53..n-type charge storage region, 54..p-type semiconductor region, PD..photodiode, Tr1, Tr2..MOS transistor , 60 .. Embedded conductive member, 61 [611, 612, 613], 66 .. Interlayer insulating film, 621 to 623 .. Cu wiring, 631 to 633 .. Diffusion prevention film, 65 .. Barrier layer, 64. In-layer lens, 67 ... Color filter, 68 ... On-chip micro lens

Claims (7)

An imaging region in which a plurality of pixels including a photoelectric conversion unit and a MOS transistor are arranged;
A multilayer Cu wiring formed above the plurality of pixels via an interlayer insulating film;
A solid-state imaging device, wherein an intra-layer lens is formed using a diffusion preventing film for the Cu wiring. 2. The intra-layer lens is formed using a diffusion prevention film of a required layer or a diffusion prevention film of all layers among the diffusion prevention films of the multilayer Cu wiring. Solid-state imaging device. The solid-state imaging device according to claim 1, wherein the in-layer lens is formed of a downward convex lens. The solid-state imaging device according to claim 1, wherein the in-layer lens is formed of an upward convex lens. Forming a plurality of pixels including a photoelectric conversion unit and a MOS transistor;
Forming a Cu wiring over the plurality of pixels via an interlayer insulating film, and forming a diffusion prevention film having a required thickness on the Cu wiring and on a surface including a region corresponding to the photoelectric conversion unit; ,
A method of manufacturing a solid-state imaging device, comprising: forming an in-layer lens-shaped member on the diffusion prevention film and performing an etch-back process to form an in-layer lens by the diffusion prevention film. 6. The solid according to claim 5, further comprising a step of removing a diffusion prevention film of another layer that does not form the inner lens on a region corresponding to the photoelectric conversion unit before forming the inner lens. Manufacturing method of imaging apparatus. The method for manufacturing a solid-state imaging device according to claim 5, wherein the diffusion prevention film for forming the intralayer lens is formed thicker than other diffusion prevention films.

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