KR100840658B1 - CMOS Image Sensor and Method for Manufacturing the Same - Google Patents

Abstract

The present invention provides a semiconductor substrate including a gate, a metal wiring, or a plurality of devices in a logic region for processing predetermined optical information, a lower metal wiring connecting a pixel region and a logic region formed on the semiconductor substrate, and the logic region. A first contact formed in the via in contact with the lower metal wiring formed in the first wiring; a porous silicon thin film layer formed on the uppermost metal wiring formed in the pixel region; a plurality of photodiodes formed in the porous silicon thin film layer; A second contact formed in the plurality of vias connecting the uppermost metal wiring of the pixel region and the photodiode to the porous silicon thin film layer, a top insulating film formed on the photodiode, and a plurality of formed on the top insulating film Color filters and a plurality of micro formed respectively corresponding to the color filters Seeds containing's CMOS image sensor and a CMOS such relates to a method of manufacturing the image sensor.

Image sensor, photodiode, contact, porous silicon thin film layer

Description

CMOS Image Sensor and Method for Manufacturing the Same

1 is an exemplary view for explaining a method of manufacturing a conventional CMOS image sensor.

2 is a cross-sectional view illustrating a method of manufacturing a CMOS image sensor according to the present invention.

<Description of Major Symbols in Drawing>

A: pixel area

B: logic area

201: semiconductor substrate

202: gate

203: lower metal wiring

204: First contact

205: first metal wiring in the logic region

206: second metal wiring in the logic region

207: third metal wiring in the logic region

208: n-1 metal wiring in the logic region

209: n-th metal wiring in the logic region

210: Multiple metal wiring in the logic area

211: interlayer insulating film in the logic region

212: interlayer insulating film in the pixel region

213: first metal wiring in the pixel region

214: second metal wiring in the pixel region

215: third metal wiring in the pixel region

216: a plurality of metal wirings in the pixel region

217: porous silicon thin film layer

218 photodiode

219: second contact

220: top insulating layer

221 blue color filter

222: red color filter

223: Green Color Filter

224: Micro Lens

The present invention relates to a CMOS image sensor and a method of manufacturing the same, and more particularly, to a CMOS image sensor and a method of manufacturing the same that can improve the light receiving efficiency.

In general, an image sensor is a semiconductor device that converts an optical image into an electrical signal, and is largely a charge coupled device (CCD) and a complementary metal oxide silicon (CMOS) image sensor. It is divided into (Image Sensor). Here, a CCD is a device in which charge carriers are stored and transported in a capacitor while a metal-oxide-silicon (MOS) capacitor is in close proximity to each other, and a CMOS image sensor is a control circuit and a signal processing circuit. ) Is a device that adopts a switching method that makes MOS transistors as many pixels as the peripheral circuit using CMOS technology, and detects the output sequentially using them. Compared with CCDs, which are widely used as current image sensors, CMOS image sensors can be easily driven, implemented with various scanning methods, and integrated with signal processing circuits on a single chip. The use of CMOS technology reduces manufacturing costs, and power consumption is significantly lower than CCDs, making it widely used in a wide range of products.

On the other hand, the CMOS image sensor is composed of a light sensing portion for detecting light and a logic circuit portion for processing the detected light into an electrical signal to make data. Efforts have been made to increase the fill factor of the area of the photo-sensing part of the entire image sensor device to increase the sensitivity, but this is limited in areas where the logic circuit part cannot be removed. There is a limit to. Therefore, in order to increase the light sensitivity, a light condensing technology that changes the path of light incident to a region other than the light sensing portion and collects the light sensing portion has emerged. Such a technique is a microlens forming technique. In addition, the image sensor for implementing a color image is a color filter (Color filter) is sequentially arranged on the upper portion of the light sensing portion for generating and accumulating the optical charge by receiving light from the outside. The color filter array (CFA) may be composed of three color filters, a red filter, a green filter, and a blue filter, or three color filters of a yellow filter, a purple yellow filter, and a cyan filter. In addition, a microlens is used to increase the light sensitivity of the image sensor on the color filter array.

A method of manufacturing a conventional CMOS image sensor will be described with reference to FIG. 1.

As shown in FIG. 1, the pixel area A is an area in which a light receiving unit composed of a plurality of photodiodes 103 and the like is formed, and the logic area B is an area in which a general logic circuit for signal processing is mainly formed. . That is, a device isolation layer (not shown) may be locally formed on the silicon substrate 101 having a structure in which a high concentration of impurity regions and a plurality of epitaxial layers are stacked, and logic may be formed in the logic region B on the substrate 101. The gate 102 of the region is formed. In addition, the photodiode 103 is formed in the pixel region A by implanting predetermined ions into the substrate 101 through an ion implantation method.

Subsequently, a plurality of metal wirings 104, 105. 106, and 107 of the logic region B are disposed on the entire surface of the substrate 101 including the photodiode 103 of the pixel region A and the gate 102 of the logic region B. 108: 109, a plurality of interlayer insulating films 110, a plurality of metal wires 112, 113, 114: 115 of the pixel region A, and a plurality of interlayer insulating films 111 are formed.

Next, the interlayer insulating layer 116 is formed on the entire surface of the lower element layer including the plurality of metal wirings 115 and the plurality of interlayer insulating layers 111 of the pixel region formed by the above-described method and surrounds the color filter layer. In addition, a red color filter 117, a green color filter 118, and a blue color filter 119 are formed in the interlayer insulating layer 116 to pass light of each specific wavelength band. Subsequently, a planarization layer is formed on the color filter layer, and a convex shape having a predetermined curvature is formed on the planarization layer to form a micro lens 120 that transmits a corresponding color filter to condense light to the photodiode region. Herein, the microlens 120 has a curvature and a formation height determined in consideration of various conditions such as the focus of the collected light, mainly using a polymer-based resin, and is preferably deposited, patterned, and reflowed. It can be formed by treatment.

In the process of manufacturing CMOS image sensor in this way, the amount of light required by the multi-layered metal wiring and the interlayer insulation film between the microlens, the first point at which light is received, and the photodiode located on the silicon substrate, is transferred to the photodiode. Problems such as diffuse reflection caused by such a problem and light refraction due to different refractive indices between the multilayer insulating layers are caused before they are touched.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and the optical path is shortened to reduce the light reception efficiency and reduce the defective pixel due to the structural problem including the multilayer metal wiring of the CMOS image sensor and the insulating film therebetween. It is an object of the present invention to provide a CMOS image sensor and a method of manufacturing the same.

Another object of the present invention is to provide a CMOS image sensor and a method of manufacturing the same in which the size of a unit pixel is reduced as the optical path is shortened, so that a design rule can improve the high integration of a device.

The CMOS image sensor according to the present invention is a semiconductor substrate in which a gate, a metal wiring, or a plurality of elements of a logic region for processing predetermined optical information is formed, and a lower metal wiring connecting a pixel region and a logic region formed on the semiconductor substrate. And a first contact formed in a via in contact with a lower metal line formed in the logic region, a porous silicon thin film layer formed on the uppermost metal line formed in the pixel region, and a porous silicon thin film layer. A plurality of photodiodes, a second contact formed in the plurality of vias connecting the photodiode with the top metal wiring of the pixel region to the porous silicon thin film layer, a top insulating film formed over the photodiode, and the top A plurality of color filters formed on the insulating film and corresponding to the color filters, respectively It includes a plurality of microlenses that are generated.

In addition, the method for manufacturing a CMOS image sensor according to the present invention includes forming a gate, a metal wiring, or a plurality of devices in a logic region for processing predetermined optical information on a semiconductor substrate, a pixel region of the semiconductor substrate, Forming a lower metal interconnection connecting the logic region, forming a via in contact with the lower metal interconnection of the logic region, and forming a first contact in the via; Forming a porous silicon thin film layer on the uppermost metal wiring formed in the region, forming a plurality of photodiodes in the porous silicon thin film layer, forming a photoresist film on the porous silicon thin film layer, and then forming a top resistive metal in the pixel region. Forming a second contact in a plurality of vias connecting a wiring and the photodiode, and the photodiode It comprises the steps of forming a plurality of microlenses corresponding to the respective color filters forming a plurality of color filters on the phase and the top insulating film to form an insulating film on the top node.

Hereinafter, a CMOS image sensor and a method of manufacturing the same according to an embodiment of the present invention will be described with reference to FIG. 2.

Referring to FIG. 2, the CMOS image sensor forms a lower structure such as a gate 202 of a logic region for processing a predetermined optical information signal in a logic region B of a semiconductor substrate 201 for signal processing. General logic circuits can be constructed. Specifically, a predetermined metal is deposited on the silicon substrate 201 on which the above-described substructures, for example, metal lines, gates, or a plurality of elements are formed, and then selectively patterned to connect the pixel region A and the logic region B. The lower metal wiring 203 can be formed. Subsequently, an insulating film for insulation between the metal wires is formed and planarized on the lower metal wire 203. Thereafter, a photoresist film is formed on the insulating film, and the via may contact the lower metal wiring 203 of the logic region B through an etching process including a reactive ion etching (RIE) process. Form a first contact 204 in the via. In this case, the first contact 204 of the logic region B may be formed by filling a via hole by using chemical vapor deposition (CVD). In addition, the RIE method may be used to clean the surface of the lower metal wiring 203 that is in contact through the via. In addition, the first contact 204 of the logic region may be formed using a metal such as tungsten (W), aluminum (Al), copper (Cu), or the like.

Next, a metal wiring is deposited on the pixel region A and the logic region B on the insulating layer on which the first contact 204 of the logic region B is formed, and then selectively patterned to form the first metal wiring 213 of the pixel region. ) And the first metal wiring 205 of the logic region. In this case, the first metal wire 205 formed in the logic region B is connected to the lower metal wire 203 through the first contact 204 of the logic region. Subsequently, a plurality of interlayer insulating films 212 and 211 and a plurality of metal wirings 214 and 215: 216, 206 and 207 are formed on the first metal wirings of the pixel region A and the logic region B. FIG. That is, the metal wiring process of the pixel region A and the logic region B may proceed together until the metal wiring process of the pixel region A is completed. Thereafter, a process for forming the remaining metal wirings 208 and 209 of the logic region B is performed to complete the configuration of the logic region B. FIG.

Next, after the configuration of the logic region B is completed, the porous silicon thin film layer 217 is formed on the uppermost metal wiring of the pixel region A to form the photodiode 218 for implementing the image sensor. Herein, the porous silicon thin film layer 217 is formed by depositing single crystal silicon by CVD or the like and then electrolytically using hydrofluoric acid and hydrogen peroxide to selectively form a porous silicon wafer without applying an insulating film on the silicon wafer surface. It can be formed using a porous silicon forming method. The porous silicon thin film layer has an advantage of having various surface adsorption capacities, and may serve as a support for allowing the photodiode 218 and the microlens 224 to be disposed adjacent to each other in a subsequent process.

Next, an ion implantation and epitaxial process may be performed on the porous silicon thin film layer 217 formed as described above to form an impurity region having a P-type conductivity or an N-type conductivity. Thereafter, a process including an ion implantation method for forming P wells or N wells may be performed on the porous silicon thin film layer 217 to form a photodiode 218 that receives light to generate photocharges. In this case, before forming the photodiode 218, a plurality of device isolation layers (not shown) and a plurality of transistors (not shown) may be formed on the side surface of the photodiode 218.

Next, after the photoresist layer is selectively formed on the porous silicon thin film layer 217, a plurality of vias connected to the uppermost metal wiring of the pixel region are formed through an etching process including an RIE, and a second contact ( 219). The second contact 219 serves to send light information generated from the photodiode 218 that receives the light to the plurality of metal wires 216 of the pixel region A including the uppermost metal wire. In addition, the second contact 219 may be formed using a method of filling via holes through CVD in the same manner as the method of forming the first contact 204 described above, and the uppermost layer contacted through the via using RIE. The surface of the metal wiring can be cleaned. In this case, the second contact 219 may be formed using a metal including tungsten, aluminum copper, or the like.

Next, an uppermost insulating layer 220 is formed on the photodiode 218 to protect the color filter layer and is selectively etched to form a pattern. Thereafter, a color photosensitive film is coated and developed on the pattern to form a color filter layer in order of the blue color filter 221, the red color filter 222, and the green color filter 223. At this time, the color filter layer is planarized using a chemical mechanical polishing (CMP) method. Subsequently, a plurality of micro lenses 224 corresponding to each of the flattened color filter layers are formed. At this time, the micro lenses 224 and the color filter layers are formed without a gap. In addition, the micro lens 224 mainly uses a polymer-based resin, and may be formed by a process such as deposition, patterning, and reflow. In this method, since a plurality of metal wires are omitted on the photodiode 218, the light receiving sensitivity may be improved by reducing the distance between the photodiode and the microlens and dramatically reducing the optical path.

Although specific embodiments of the present invention have been described with reference to the drawings, this is intended to be easily understood by those skilled in the art and is not intended to limit the technical scope of the present invention. Therefore, the technical scope of the present invention is determined by the matters described in the claims, and the embodiments described with reference to the drawings may be modified or modified as much as possible within the technical spirit and scope of the present invention.

By shortening the optical path from the microlens to the photodiode, the present invention provides light due to different refractive indices between a diffuse reflection and a multilayer problem caused by a structural problem including a multilayer metal wiring and an insulating film therebetween. By eliminating the refraction phenomenon, the amount of light incident on the photodiode can be maximized, thereby forming a semiconductor device having greatly increased light receiving sensitivity of a unit pixel.

In addition, according to the present invention, as a device having such a short optical path is implemented, unit pixels may be reduced to realize a highly integrated device having a fine design rule, and color may be improved by minimizing light scattering to improve reliability of a semiconductor device. Can be.

Claims (10)

A semiconductor substrate on which a gate, a metal wiring, or a plurality of elements of a logic region for processing predetermined optical information are formed; A lower metal interconnection connecting the pixel region and the logic region formed on the semiconductor substrate; A first contact formed in a via in contact with a lower metal line formed in the logic region; A porous silicon thin film layer formed on the uppermost metal wiring formed in the pixel region; A plurality of photodiodes formed on the porous silicon thin film layer, A second contact formed in the plurality of vias connecting the uppermost metal wiring of the pixel region and the photodiode to the porous silicon thin film layer; An uppermost insulating film formed on the photodiode; A plurality of color filters formed on the uppermost insulating film, CMOS image sensor comprising a plurality of micro lenses each corresponding to the color filter. delete In claim 1, The porous silicon thin film layer includes a photodiode and a plurality of device isolation layers formed on the photodiode side of the CMOS image sensor. In claim 1, The porous silicon thin film layer is formed by depositing single crystal silicon by a CVD method, followed by electrolysis using hydrofluoric acid and hydrogen peroxide. In claim 1, And each of the photodiodes includes at least one of a blue color filter, a red color filter, and a green color filter. In claim 1, And the color filter layer and the micro lens are formed without a gap. Forming a gate, a metal wiring, or a plurality of devices in a logic region for processing predetermined optical information on the semiconductor substrate; Forming a lower metal wiring connecting the pixel region and the logic region of the semiconductor substrate; Forming a via in contact with the lower metal wiring of the logic region, and then forming a first contact in the via; Forming a porous silicon thin film layer on the uppermost metal wiring formed in the pixel region; Forming a plurality of photodiodes on the porous silicon thin film layer; Forming a photoresist film on the porous silicon thin film layer, and then forming a second contact in a plurality of vias connecting the uppermost metal wiring of the pixel region and the photodiode; Forming a top insulating film on the photodiode; Forming a plurality of color filters on the top insulating film; And forming a plurality of micro lenses corresponding to the color filters, respectively. In claim 7, The porous silicon thin film layer is a method of manufacturing a CMOS image sensor, characterized in that formed using an electrolysis method using hydrofluoric acid and hydrogen peroxide. delete In claim 7, The porous silicon thin film layer includes a photodiode and a plurality of device isolation layers formed on the side of the photodiode manufacturing method of the CMOS image sensor.

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