KR101412144B1 - Fabricating method of metal interconnection and fabricating method of image sensor using the same - Google Patents

Fabricating method of metal interconnection and fabricating method of image sensor using the same Download PDF

Info

Publication number
KR101412144B1
KR101412144B1 KR1020070121000A KR20070121000A KR101412144B1 KR 101412144 B1 KR101412144 B1 KR 101412144B1 KR 1020070121000 A KR1020070121000 A KR 1020070121000A KR 20070121000 A KR20070121000 A KR 20070121000A KR 101412144 B1 KR101412144 B1 KR 101412144B1
Authority
KR
South Korea
Prior art keywords
wiring
formed
substrate
interlayer insulating
insulating film
Prior art date
Application number
KR1020070121000A
Other languages
Korean (ko)
Other versions
KR20090054239A (en
Inventor
이정호
박영훈
정상일
양준석
신안철
정민영
Original Assignee
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 삼성전자 주식회사 filed Critical 삼성전자 주식회사
Priority to KR1020070121000A priority Critical patent/KR101412144B1/en
Publication of KR20090054239A publication Critical patent/KR20090054239A/en
Application granted granted Critical
Publication of KR101412144B1 publication Critical patent/KR101412144B1/en

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76825Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/14601Structural or functional details thereof
    • H01L27/14632Wafer-level processed structures
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/14601Structural or functional details thereof
    • H01L27/14636Interconnect structures
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/14683Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14687Wafer level processing

Abstract

A method of manufacturing a metal wiring and a method of manufacturing an image sensor using the same are provided. The method of manufacturing the metal wiring may include forming an interlayer insulating film on a substrate, forming a wiring forming region in the interlayer insulating film, forming a wiring forming region, then UV-treating the substrate, and forming a metal wiring in the wiring forming region .
Metal wiring, image sensor, plasma etching process, UV treatment

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a method of fabricating a metal wiring,

The present invention relates to a method of manufacturing a metal wiring and a method of manufacturing an image sensor using the same.

The image sensor converts the optical image into an electrical signal. 2. Description of the Related Art Recently, with the development of the computer industry and the communication industry, demand for image sensors with improved performance in various fields such as digital cameras, camcorders, personal communication systems (PCS), game devices,

In particular, the MOS image sensor can be implemented in a simple scanning system by a simple driving method. In addition, since the signal processing circuit can be integrated on a single chip, miniaturization of the product can be achieved, and the manufacturing cost can be reduced because the MOS process technology can be used in a compatible manner. Power consumption is also very low, making it easy to apply to products with limited battery capacity. Therefore, the use of MOS image sensors is rapidly increasing as high resolution can be implemented along with technology development.

The MOS image sensor includes a photoelectric conversion element which absorbs incident light and accumulates electric charge corresponding to the light quantity, and a multi-layered metal wiring for outputting the electric charge stored in each photoelectric conversion element. As the metal wiring, a copper wiring or an aluminum wiring is mainly used. As the MOS image sensor becomes finer, copper wiring which is easier to form resistivity and fine pattern than aluminum wiring is widely used.

However, when a copper wiring or an aluminum wiring is formed, a plasma etching process is used. Such a plasma etching process may cause various damages to the photoelectric conversion element. A defect in the photoelectric conversion element increases the dark level of the output signal.

A problem to be solved by the present invention is to provide a method of manufacturing a metal wiring which can heal defects by a plasma etching process.

Another object of the present invention is to provide a method of manufacturing an image sensor using the metal wiring manufacturing method.

The problems to be solved by the present invention are not limited to the above-mentioned problems, and other problems not mentioned can be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, an interlayer insulating film is formed on a substrate, a wiring forming region is formed in the interlayer insulating film, a wiring forming region is formed, And forming a metal wiring in the wiring formation area.

According to another aspect of the present invention, there is provided a method of manufacturing a metal wiring, including forming a metal film for wiring on a substrate, patterning the metal film for wiring, forming a metal interconnection on the interlayer insulating film, , And UV treatment of the substrate.

According to another aspect of the present invention, there is provided a method of manufacturing an image sensor including forming a photoelectric conversion element on a substrate, forming an interlayer insulating film on the substrate on which the photoelectric conversion element is formed, Forming a wiring formation region in an interlayer insulating film, forming a wiring formation region, and then performing a UV treatment on the substrate to form a metal wiring in the wiring formation region.

According to another aspect of the present invention, there is provided a method of manufacturing an image sensor, including forming a photoelectric conversion element on a substrate, forming a metal film for wiring on the substrate having the photoelectric conversion element formed thereon, Forming a metal wiring on the interlayer insulating film by patterning a metal film, forming a metal wiring, and then UV-treating the substrate.

Other specific details of the invention are included in the detailed description and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention and the manner of achieving them will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. Thus, in some embodiments, well known process steps, well-known structures, and well-known techniques are not specifically described to avoid an undue interpretation of the present invention.

It is to be understood that when an element or layer is referred to as being "on" or " on "of another element or layer, All included. On the other hand, a device being referred to as "directly on" or "directly above " indicates that no other device or layer is interposed in between. "And / or" include each and every combination of one or more of the mentioned items.

The terms spatially relative, "below", "beneath", "lower", "above", "upper" May be used to readily describe a device or a relationship of components to other devices or components. Spatially relative terms should be understood to include, in addition to the orientation shown in the drawings, terms that include different orientations of the device during use or operation. Like reference numerals refer to like elements throughout the specification.

Embodiments described herein will be described with reference to plan views and cross-sectional views, which are ideal schematics of the present invention. Thus, the shape of the illustrations may be modified by manufacturing techniques and / or tolerances. Accordingly, the embodiments of the present invention are not limited to the specific forms shown, but also include changes in the shapes that are generated according to the manufacturing process. Thus, the regions illustrated in the figures have schematic attributes, and the shapes of the regions illustrated in the figures are intended to illustrate specific types of regions of the elements and are not intended to limit the scope of the invention.

The terminology used herein is for the purpose of illustrating embodiments and is not intended to be limiting of the present invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. It is noted that the terms "comprises" and / or "comprising" used in the specification are intended to be inclusive in a manner similar to the components, steps, operations, and / Or additions. And "and / or" include each and any combination of one or more of the mentioned items. Like reference numerals refer to like elements throughout the following description.

1 is a flowchart illustrating a method of manufacturing a metal wiring according to a first embodiment of the present invention. FIGS. 2A to 2D are intermediate plan views illustrating a method of manufacturing the metal wiring of FIG. In FIGS. 2A to 2D, for example, dual damascene wiring is formed by way of example.

Referring to FIGS. 1 and 2A, a diffusion barrier layer 110 and an interlayer insulating layer 120 are sequentially formed on a lower metal wiring 100 formed on a substrate (S10).

Specifically, the diffusion barrier layer 110 serves to prevent diffusion of copper. In addition, the diffusion barrier layer 110 may serve as an etching stopper in the etching process. That is, when the interlayer insulating film 120 is etched to form a wiring formation region (for example, a trench and / or a via hole), it is used to prevent damage to the metal wiring 100 or to increase the precision of etching. For example, SiN, SiC, SiON, and SiCN may be used as the barrier insulating film 110, and the barrier insulating film 110 may be formed mainly by CVD (Chemical Vapor Deposition).

The interlayer insulating layer 120 may be formed of a material selected from the group consisting of PE-TEOS (Plasma Enhanced-Tetra Ethyl Ortho Silicate), PEOX (Plasma Enhanced Oxide), Fluoride Silicate Glass (FSG), Phosphor Silicate Glass (PSG), Borophosphosilicate Glass (BPSG) Glass) or a laminated film thereof. It can be formed mainly by the CVD method.

1 and 2B, a wiring formation region 130 is formed in the interlayer insulating film 120 (S20).

Specifically, the wiring formation region 130 defines a region where a metal wiring is to be formed. The wiring formation region 130 shown in FIG. 2B is a region for forming a dual damascene wiring and the wiring formation region 130 includes a via hole 132 and a trench 134. The shape of the via hole 132 and the trench 134 is not limited to the shape shown in FIG. 2B, but may be formed in a rounded corner, a vertical or horizontal direction.

For example, a via hole 132 may be formed in a predetermined region of the interlayer insulating film 120, and a trench 134 may be formed through the upper portion of the via hole 132. Alternatively, the trench 134 may be formed first and the via hole 132 later formed.

In the first embodiment of the present invention, the formation of the wiring formation region 130 (i.e., the via hole 132 and the trench 134) can be performed through the plasma etching process.

Referring to FIGS. 1 and 2C, the substrate is UV-processed 140 (S30).

More specifically, the plasma etching process used to form the wiring formation region 130 may cause various damage to the substrate. For example, these defects may be polar, and polar defects may act as a trap during transistor-based signaling. Therefore, malfunction of the semiconductor device may be induced.

In a first embodiment of the invention, the defects described above can be healed by UV treatment (140) the substrate. The UV treatment 140 may, for example, be conducted at 50 to 200 DEG C for 10 to 300 seconds, but is not limited thereto. In addition, the UV treatment 140 can be performed using a UV bake equipment, but is not limited thereto.

Referring to FIGS. 1 and 2D, a metal wiring 160 is formed in the wiring formation region 130 (S40).

More specifically, first, a barrier metal film 150 and a seed layer (not shown) are formed conformally along the profile of the interlayer insulating film 120. The barrier metal film 150 suppresses the diffusion of the metal wiring 160. That is, the copper to be used as the metal wiring 160 may be a material used in the manufacture of integrated circuits, such as Si, SiO 2 Because the diffusion coefficient is large. When copper is diffused into an insulating film such as SiO 2 , the insulating film becomes conductive and the insulating characteristics are deteriorated. The barrier metal film 150 does not react with copper or a copper alloy or uses a high fusion point metal such as Ti, Ta, W, Ru, TiN, TaN, WN, TiZrN, TiSiN , it is possible to TaAlN, TaSiN, TaSi 2, TiW, etc., and combinations thereof, stacked films thereof. The barrier metal film 150 may be formed using a method such as PVD, ALD, or CVD. The seed layer (not shown) can be formed mainly using the PVD method.

Then, a conductive layer (not shown) is formed to be sufficiently thick so as to fill the interconnection forming region 130 on the interlayer insulating film 120. The conductive layer may be formed using an electroplating method, an electroless plating method, an MOCVD (Metal Organic Chemical Vapor Deposition) method, or the like, which has excellent embedding characteristics.

Then, the conductive layer and the barrier metal film 150 are planarized so that the upper surface of the interlayer insulating film 120 is exposed. The conductive layer thus planarized becomes a metal wiring 160 (dual damascene wiring in Fig. 2D). In order to form a flat surface, a part of the conductive layer and a part of the barrier metal film 150 may be nonselectively removed. For example, the planar surface can be formed through a CMP process using a non-selective slurry. Here, the non-selective slurry may use a silica abrasive material capable of removing the different kinds of layers at the same rate. On the other hand, the flat surface may be formed by a non-selective plasma etching process. Alternatively, a planarized surface may be formed on each of the conductive layer and the barrier metal film 150 through a selective planarization process.

Although FIGS. 2A to 2D illustrate the formation of a dual damascene wiring for convenience of explanation, the present invention is not limited thereto. That is, the present invention can be applied to forming a single damascene wiring and also to forming a contact or a via. That is, after the wiring formation region for forming the single damascene wiring is formed, the UV treatment can be performed. Alternatively, a UV treatment can be performed after forming a contact hole or a via hole.

3 is a flow chart for forming a metal wiring manufacturing method according to a second embodiment of the present invention.

Referring to FIG. 3, the method of manufacturing a metal wiring according to the second embodiment of the present invention differs from the first embodiment of the present invention in that a wiring formation region is formed (S20) (S30 to S39). For example, the UV treatment may be performed three times, four times, five times, or the like.

The reason why the UV treatment is performed many times as described above is as follows. The amount of defects that can be healed during one UV treatment is predetermined. In other words, the amount of defects to be healed does not increase even if the processing time is increased during one UV treatment. Therefore, it is possible to increase the amount of defects that can be healed by performing the UV treatment a plurality of times.

On the other hand, each of the multiple UV treatments may proceed for the same process time at the same process temperature. Alternatively, each of the multiple UV treatments may be conducted for the same process time at different process temperatures.

4 is a flowchart illustrating a method of manufacturing a metal wiring according to a third embodiment of the present invention. 5A to 5C are intermediate diagrams for explaining a method of manufacturing the metal wiring of FIG.

Referring to FIGS. 4 and 5A, an interlayer insulating film 120 is formed on a lower metal wiring 100 formed on a substrate. A via 170 is formed in a part of the interlayer insulating film 120 to contact the metal interconnection 100 at the bottom. A wiring metal film 180a is formed on the interlayer insulating film 120 in which the via 170 is formed (S50). Here, the wiring metal film 180a may be an aluminum film.

4 and 5B, a metal wiring 180 (that is, aluminum wiring) is formed on the interlayer insulating film 120 by patterning the wiring metal film 180a (S60). Here, the patterning of the wiring metal film 180a can be performed through a plasma etching process.

Referring to FIGS. 4 and 5C, the substrate is UV-processed 190 (S70). As described above, the plasma etching process used for patterning the wiring metal film 180a can cause various defects on the substrate, and the defects can be healed by UV treatment (190) the substrate. The UV treatment 190 may be performed, for example, at 50 to 200 占 폚 for 10 seconds to 300 seconds, but is not limited thereto. In addition, the UV treatment 190 can be performed using a UV bake equipment, but is not limited thereto.

6 is a flow chart for forming a metal wiring manufacturing method according to a fourth embodiment of the present invention.

Referring to FIG. 6, a method of manufacturing a metal wiring according to a fourth embodiment of the present invention is different from the second embodiment of the present invention in that a metal wiring is formed (S60) (S70 to S79). For example, the UV treatment may be performed three times, four times, five times, or the like. The reason why the UV treatment is performed a plurality of times in this manner is that the amount of defects that can be healed during one UV treatment is set to a predetermined value. On the other hand, each of the multiple UV treatments may proceed for the same process time at the same process temperature. Alternatively, each of the multiple UV treatments may be conducted for the same process time at different process temperatures.

Hereinafter, a manufacturing method of an image sensor using the metal wiring manufacturing method described with reference to FIGS. 1 to 6 will be described with reference to FIGS. 7 to 10C. FIG.

7 is a block diagram of an image sensor in accordance with embodiments of the present invention.

7, an image sensor according to embodiments of the present invention includes an active pixel sensor (APS) array 210 in which pixels including photoelectric conversion elements are arranged in a two-dimensional manner, a timing generator 220 A row decoder 230, a row driver 240, a correlated double sampler (CDS) 250, an analog to digital converter (ADC) 260, A latch 270, a column decoder 280, and the like.

The APS array 210 includes a plurality of unit pixels arranged two-dimensionally. The plurality of unit pixels serve to convert the optical image into an electrical output signal. The APS array 210 is driven by receiving a plurality of drive signals, such as a row selection signal, a reset signal, and a charge transfer signal, from the row driver 240. The converted electrical output signal is also provided to the correlated dual sampler 250 through a vertical signal line.

The timing generator 220 provides a timing signal and a control signal to the row decoder 230 and the column decoder 280.

The row driver 240 provides a plurality of driving signals to the active pixel sensor array 210 for driving a plurality of unit pixels according to the decoded result in the row decoder 230. Generally, when unit pixels are arranged in a matrix form, a driving signal is provided for each row.

The correlated dual sampler 250 receives and holds and samples the output signal formed on the active pixel sensor array 210 via the vertical signal line. That is, a specific noise level and a signal level by the output signal are sampled double, and a difference level corresponding to the difference between the noise level and the signal level is output.

The analog-to-digital converter 260 converts the analog signal corresponding to the difference level into a digital signal and outputs the digital signal.

The latch unit 270 latches the digital signal and the latched signal is sequentially output to the image signal processing unit (not shown) according to the decoding result in the column decoder 280.

8 is an equivalent circuit diagram of the APS array of Fig.

Referring to FIG. 7, the pixels P are arranged in a matrix form to constitute the APS array 210. Each pixel P includes a photoelectric conversion element 211, a floating diffusion region 213, a charge transfer element 215, a drive element 217, a reset element 218, and a selection element 219. (I, j + 1), P (i, j + 2), P (i, j + 3), ...) .

The photoelectric conversion element 211 absorbs the incident light and accumulates the electric charge corresponding to the light amount. As the photoelectric conversion element 211, a photodiode, a phototransistor, a photogate, a pinned photodiode, or a combination thereof can be applied, and a photodiode is illustrated in the figure.

Each photoelectric conversion element 211 is coupled to each charge transfer element 215 that transfers the accumulated charge to the floating diffusion region 213. [ A floating diffusion region (FD) 213 is a region for converting a charge to a voltage, and has a parasitic capacitance, so that charges are stored cumulatively.

The drive element 217 illustrated in the source follower amplifier amplifies a change in the electrical potential of the floating diffusion region 213 that receives the charge accumulated in each photoelectric converter 211 and outputs it to the output line Vout .

The reset element 218 periodically resets the floating diffusion region 213. The reset element 218 may be composed of one MOS transistor driven by a bias provided by a reset line RX (i) for applying a predetermined bias (i.e., a reset signal). When the reset element 218 is turned on by the bias provided by the reset line RX (i), a predetermined electric potential, e.g., the power source voltage VDD, provided to the drain of the reset element 218 is applied to the floating diffusion region 213).

The selection element 219 serves to select a pixel P to be read in units of rows. The selection element 219 may be composed of one MOS transistor driven by a bias (i.e., a row selection signal) provided by the row selection line SEL (i). When the select element 219 is turned on by the bias provided by the row select line SEL (i), a predetermined electrical potential, e.g., the power supply voltage VDD, provided to the drain of the select element 219 is applied to the drive element 217, respectively.

A transfer line TX (i) for applying a bias to the charge transfer element 215, a reset line RX (i) for applying a bias to the reset element 218, a row for applying a bias to the selection element 219 The selection lines SEL (i) may be arranged extending substantially in parallel with each other in the row direction.

FIGS. 9A to 9G are intermediate steps for explaining a manufacturing method of an image sensor using the method of manufacturing copper wiring according to the first and second embodiments of the present invention. 9A to 9G show the photoelectric conversion element and the elements disposed in the periphery thereof as the center for convenience of explanation.

First, referring to FIG. 9A, a plurality of pixels are formed in a substrate 310.

Specifically, an element isolation region 312 such as STI (Shallow Trench Isolation) or DTI (Deep Trench Isolation) is formed on a substrate 310 to define an active region on the substrate 310. The substrate 310 may be of a first conductivity type (e.g., P-type) and may extend an epitaxial layer of a first conductivity type on the substrate 310 although not shown in the figure.

Then, a photoelectric conversion element 320, a floating diffusion region 340, and a plurality of transistors are formed in the substrate 310. Here, the plurality of transistors may correspond to a charge transfer element 330, a driver element (not shown), a reset element (not shown), and a selection element (not shown). In FIG. 9A, a pinned photodiode is shown as an example of the photoelectric conversion element 320. FIG. That is, the photoelectric conversion element 320 may include an impurity region 322 of a second conductivity type (for example, N type) and an impurity region 324 of a first conductivity type (for example, P type) have.

Referring to FIG. 9B, an interlayer insulating layer 351 is formed on a substrate 310 on which a plurality of pixels are formed.

Then, a contact hole 391 exposing the floating diffusion region 340 is formed.

Subsequently, a barrier metal film 381 is conformally formed on the side surfaces and the bottom surface of the contact hole 391 and on the upper surface of the interlayer insulating film 351. The barrier metal film 381 is not reacted with copper or a copper alloy or, and it uses a melting point materials (high fusion point metal), for example, Ti, Ta, W, Ru, TiN, TaN, WN, TiZrN, TiSiN, TaAlN, TaSiN, TaSi 2, TiW, and combinations thereof, A laminated film thereof, or the like.

Next, a conductive layer is formed by depositing copper, titanium, tungsten, or the like on the barrier metal film 381 so as to fill the contact hole 391, and a conductive layer and a barrier metal film (not shown) are formed to expose the upper surface of the interlayer insulating film 351 The contact 371 is completed. When using titanium or tungsten for the contact 371, the barrier metal film 381 may not be used.

Next, a diffusion preventing film 361 and an interlayer insulating film 352 are formed. The diffusion barrier layer 361 serves to prevent diffusion of copper and serves as an etching stopper in the etching process.

Then, a wiring formation region 392 is formed in the interlayer insulating film 352 by using a plasma etching process. The wiring formation region 392 shown in FIG. 9B is a region for forming a single damascene wiring.

Subsequently, the substrate 310 is subjected to a UV treatment (410). As described above, when the wiring formation region 392 is formed through the plasma etching process, various kinds of damage may occur. For example, the stress applied to the photoelectric conversion element 320 may be changed, and the surface of the photoelectric conversion element 320, the boundary between the element isolation region 312 and the substrate 310, A charge may be generated at the boundary of the charge pump 330 or the like.

These defects can increase the dark level of the output signal. The pixel provides an output signal through the output line Vout, which can be divided into a signal level and a dark level. That is, the signal level means the voltage value corresponding to the charge generated through the photoelectric conversion, and the dark level means the charge generated by the method other than the photoelectric conversion (for example, the charge generated by the heat and the charge due to the other offset) &Quot; Therefore, such defects must be healed.

These defects can be healed by UV treatment 410 of the substrate. Particularly, the charge generated on the surface of the photoelectric conversion element 320, the boundary between the element isolation region 312 and the substrate 310, and the boundary between the substrate 310 and the charge transfer element 330 can be removed . Therefore, the dark level of the output signal output from the pixel can be reduced.

The UV treatment 410 may be performed, for example, at 50 to 200 DEG C for 10 to 300 seconds, but is not limited thereto. In addition, the UV treatment 410 may be performed using a UV bake equipment, but is not limited thereto.

In addition, the UV treatment 410 may be performed a plurality of times.

Referring to Fig. 9C, a barrier metal film 382 and a metal wiring 372 (i.e., a single damascene wiring) are formed in the wiring formation region 392. [ Here, the metal wiring 372 may be a copper wiring.

9D, a diffusion prevention film 362 and an interlayer insulating film 353 are formed on an interlayer insulating film 352 in which a metal wiring 372 is formed.

Then, a wiring formation region 395 for forming a dual damascene wiring is formed in the interlayer insulating film 353. The wiring formation region 395 includes a via hole 393 and a trench 394. For example, a via hole 393 may be formed first in a predetermined region of the interlayer insulating film 395, and a trench 394 may be formed through the upper portion of the via hole 393. Alternatively, the trench 394 may be formed first and the via hole 393 formed later. The formation of the wiring formation region 395 (i.e., the via hole 393 and the trench 394) can be formed through the plasma etching process.

Subsequently, the substrate is subjected to UV treatment (420). By performing the UV treatment (420) on the substrate, defects generated by the plasma etching process can be removed.

Referring to FIG. 9E, a barrier metal film 383 and a metal wiring 373 (i.e., dual damascene wiring) are formed in the wiring formation region 395. Here, the metal wiring 373 may be a copper wiring.

Referring to FIG. 9F, a diffusion prevention film 363 and an interlayer insulating film 354 are formed on the interlayer insulating film 353 in which the metal wiring 373 is formed, as described in FIGS. 9D and 9F.

Then, a wiring formation region 398 including a via hole 396 and a trench 397 is formed in the interlayer insulating film 354.

Subsequently, the substrate is subjected to UV treatment.

Then, a barrier metal film 384 and a metal wiring 374 (that is, a dual damascene wiring) are formed in the wiring formation region 398. Then,

Next, a diffusion prevention film 364 is formed.

9G, a cavity is formed on the photoelectric conversion element 320 through a multilayer interlayer insulating film 351, 352, 353, 354, a multilayered diffusion preventing film 361, 362, 363, 364, ) 326 are formed.

Specifically, since the silicon nitride film used as the diffusion preventing films 361, 362, 363, and 364 has a low transmittance to light, incident light can be prevented from reaching the photoelectric conversion element 320. Therefore, in order to remove the multilayer interlayer insulating films 351, 352, 353, and 354 and the multilayered diffusion preventing films 361, 362, 363, and 364 formed on the photoelectric conversion elements 320, a cavity 326 is formed do. By forming the cavity 326, the amount of incident light reaching the photoelectric conversion element 320 can be increased and the photosensitivity can be increased.

The cavity 326 can be formed by removing a part of the interlayer insulating film 351 as shown in FIG. 9G, but the present invention is not limited thereto. In addition, the cavity 326 may have inclined sidewalls and a flat bottom as shown in Figure 9G, but is not limited thereto. For example, the sidewalls of the cavity 326 may not be inclined and the bottom of the cavity 326 may not be planar (i. E. May have a concave or convex shape).

The cavity 326 is then filled with a light transmitting material 327.

The light transmitting material 327 may be, for example, an organic polymer compound, for example, a fluorine-based polymer having a cyclic structure of Cytop (TM), or a PMMA-based polymer, but is not limited thereto. Further, the cavity 326 may be filled with the light transmitting material 327 using a spin coating method, but the present invention is not limited thereto.

Next, a color filter 328 is formed on the light transmitting material 327, and then a microlens 329 is formed at a position corresponding to the photoelectric conversion element 320 on the color filler 328.

FIGS. 10A to 10C are intermediate steps for explaining a method of manufacturing an image sensor using the method of manufacturing a copper wiring according to the third and fourth embodiments of the present invention.

10A, a wiring metal film 510a is formed on the interlayer insulating film 351 on which the contact 371 is formed. The wiring metal film 510a may be an aluminum film.

Referring to FIG. 10B, the metal film for wiring 510a is patterned to form a metal wiring 510 (that is, aluminum wiring) on the interlayer insulating film 351.

Referring to FIG. 10C, the substrate is UV treated (610). As described above, the plasma etching process used for patterning the wiring metal film 510a can cause various defects on the substrate, and the defects described above can be healed by UV treatment (610) the substrate. In particular, the UV treatment removes the charge generated on the surface of the photoelectric conversion element 320, the boundary between the element isolation region 312 and the substrate 310, the boundary between the substrate 310 and the charge transfer element 330, . In addition, the UV treatment 610 may be performed a plurality of times.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, You will understand. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

1 is a flowchart illustrating a method of manufacturing a metal wiring according to a first embodiment of the present invention.

FIGS. 2A to 2D are intermediate plan views illustrating a method of manufacturing the metal wiring of FIG.

3 is a flow chart for forming a metal wiring manufacturing method according to a second embodiment of the present invention.

4 is a flowchart illustrating a method of manufacturing a metal wiring according to a third embodiment of the present invention.

5A to 5C are intermediate diagrams for explaining a method of manufacturing the metal wiring of FIG.

6 is a flow chart for forming a metal wiring manufacturing method according to a fourth embodiment of the present invention.

7 is a block diagram of an image sensor in accordance with embodiments of the present invention.

8 is an equivalent circuit diagram of the APS array of Fig.

FIGS. 9A to 9G are intermediate steps for explaining a manufacturing method of an image sensor using the method of manufacturing copper wiring according to the first and second embodiments of the present invention.

FIGS. 10A to 10C are intermediate views for explaining a method of manufacturing an image sensor using the copper wiring manufacturing method according to the third and fourth embodiments of the present invention.

 DESCRIPTION OF THE REFERENCE NUMERALS (S)

120: interlayer insulating film 130: wiring formation region

132: via hole 134: trench

140: UV treatment 150: barrier metal film

160: metal wiring

Claims (20)

  1. An interlayer insulating film is formed on a substrate,
    A wiring formation region is formed in the interlayer insulating film by using a plasma etching process,
    After the formation of the wiring formation region, the substrate is subjected to UV treatment so as to heal the defects of the substrate generated by the plasma etching process,
    And forming a metal wiring in the wiring formation area.
  2. The method according to claim 1,
    Wherein the UV treatment is performed a plurality of times.
  3. The method according to claim 1,
    Wherein the UV treatment is performed at 50 to 200 DEG C for 10 to 300 seconds.
  4. delete
  5. The method according to claim 1,
    Wherein the wiring formation region includes at least one of a single damascene wiring formation region, a dual damascene wiring region, a contact hole, and a via hole.
  6. The method according to claim 1,
    Wherein the metal wiring is a copper wiring.
  7. A wiring metal film is formed on an interlayer insulating film on a substrate,
    Patterning the wiring metal film using a plasma etching process to form a metal wiring on the interlayer insulating film,
    And after forming the metal wiring, UV-treating the substrate to heal the defects of the substrate generated by the plasma etching process.
  8. delete
  9. delete
  10. delete
  11. 8. The method of claim 7,
    Wherein the metal wiring is an aluminum wiring.
  12. A photoelectric conversion element is formed on a substrate,
    An interlayer insulating film is formed on a substrate on which the photoelectric conversion element is formed,
    A wiring forming region is formed in the interlayer insulating film by using a plasma etching process,
    After the formation of the wiring formation region, the substrate is subjected to UV treatment so as to heal the defects of the substrate generated by the plasma etching process,
    And forming a metal wiring in the wiring formation region.
  13. delete
  14. delete
  15. delete
  16. delete
  17. A photoelectric conversion element is formed on a substrate,
    An interlayer insulating film is formed on a substrate on which the photoelectric conversion element is formed,
    Forming a wiring metal film on the interlayer insulating film,
    Patterning the wiring metal film using a plasma etching process to form a metal wiring on the interlayer insulating film,
    And after forming the metal wiring, UV-treating the substrate to heal the defects of the substrate generated by the plasma etching process.
  18. delete
  19. delete
  20. delete
KR1020070121000A 2007-11-26 2007-11-26 Fabricating method of metal interconnection and fabricating method of image sensor using the same KR101412144B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020070121000A KR101412144B1 (en) 2007-11-26 2007-11-26 Fabricating method of metal interconnection and fabricating method of image sensor using the same

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
KR1020070121000A KR101412144B1 (en) 2007-11-26 2007-11-26 Fabricating method of metal interconnection and fabricating method of image sensor using the same
US12/274,040 US8026171B2 (en) 2007-11-26 2008-11-19 Method of fabricating metal interconnection and method of fabricating image sensor using the same
US13/206,703 US8338295B2 (en) 2007-11-26 2011-08-10 Method of fabricating metal interconnection and method of fabricating image sensor using the same

Publications (2)

Publication Number Publication Date
KR20090054239A KR20090054239A (en) 2009-05-29
KR101412144B1 true KR101412144B1 (en) 2014-06-26

Family

ID=40670106

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020070121000A KR101412144B1 (en) 2007-11-26 2007-11-26 Fabricating method of metal interconnection and fabricating method of image sensor using the same

Country Status (2)

Country Link
US (2) US8026171B2 (en)
KR (1) KR101412144B1 (en)

Families Citing this family (65)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101478189B1 (en) * 2007-11-19 2015-01-02 삼성전자주식회사 Fabricating method of image sensor
US10378106B2 (en) 2008-11-14 2019-08-13 Asm Ip Holding B.V. Method of forming insulation film by modified PEALD
US9394608B2 (en) 2009-04-06 2016-07-19 Asm America, Inc. Semiconductor processing reactor and components thereof
JP5304536B2 (en) * 2009-08-24 2013-10-02 ソニー株式会社 Semiconductor device
US10364496B2 (en) 2011-06-27 2019-07-30 Asm Ip Holding B.V. Dual section module having shared and unshared mass flow controllers
US9112090B2 (en) 2012-01-31 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. UV radiation recovery of image sensor
US9659799B2 (en) 2012-08-28 2017-05-23 Asm Ip Holding B.V. Systems and methods for dynamic semiconductor process scheduling
US9484191B2 (en) 2013-03-08 2016-11-01 Asm Ip Holding B.V. Pulsed remote plasma method and system
US9589770B2 (en) 2013-03-08 2017-03-07 Asm Ip Holding B.V. Method and systems for in-situ formation of intermediate reactive species
US9240412B2 (en) 2013-09-27 2016-01-19 Asm Ip Holding B.V. Semiconductor structure and device and methods of forming same using selective epitaxial process
US9368448B2 (en) * 2013-12-20 2016-06-14 Applied Materials, Inc. Metal-containing films as dielectric capping barrier for advanced interconnects
US10167557B2 (en) 2014-03-18 2019-01-01 Asm Ip Holding B.V. Gas distribution system, reactor including the system, and methods of using the same
KR20160022087A (en) 2014-08-19 2016-02-29 삼성전자주식회사 Unit pixel for image sensor and pixel array comprising the same
US9657845B2 (en) 2014-10-07 2017-05-23 Asm Ip Holding B.V. Variable conductance gas distribution apparatus and method
KR20160076208A (en) 2014-12-22 2016-06-30 에이에스엠 아이피 홀딩 비.브이. Semiconductor device and manufacuring method thereof
US10529542B2 (en) 2015-03-11 2020-01-07 Asm Ip Holdings B.V. Cross-flow reactor and method
US10276355B2 (en) 2015-03-12 2019-04-30 Asm Ip Holding B.V. Multi-zone reactor, system including the reactor, and method of using the same
US10458018B2 (en) 2015-06-26 2019-10-29 Asm Ip Holding B.V. Structures including metal carbide material, devices including the structures, and methods of forming same
US9923003B2 (en) 2015-06-30 2018-03-20 Microsoft Technology Licensing, Llc CMOS image sensor with a reduced likelihood of an induced electric field in the epitaxial layer
US10600673B2 (en) 2015-07-07 2020-03-24 Asm Ip Holding B.V. Magnetic susceptor to baseplate seal
US9960072B2 (en) 2015-09-29 2018-05-01 Asm Ip Holding B.V. Variable adjustment for precise matching of multiple chamber cavity housings
US10322384B2 (en) 2015-11-09 2019-06-18 Asm Ip Holding B.V. Counter flow mixer for process chamber
US10468251B2 (en) 2016-02-19 2019-11-05 Asm Ip Holding B.V. Method for forming spacers using silicon nitride film for spacer-defined multiple patterning
US10529554B2 (en) 2016-02-19 2020-01-07 Asm Ip Holding B.V. Method for forming silicon nitride film selectively on sidewalls or flat surfaces of trenches
US10501866B2 (en) 2016-03-09 2019-12-10 Asm Ip Holding B.V. Gas distribution apparatus for improved film uniformity in an epitaxial system
US10343920B2 (en) 2016-03-18 2019-07-09 Asm Ip Holding B.V. Aligned carbon nanotubes
US9892913B2 (en) 2016-03-24 2018-02-13 Asm Ip Holding B.V. Radial and thickness control via biased multi-port injection settings
US10367080B2 (en) 2016-05-02 2019-07-30 Asm Ip Holding B.V. Method of forming a germanium oxynitride film
KR20170129475A (en) 2016-05-17 2017-11-27 에이에스엠 아이피 홀딩 비.브이. Method of forming metal interconnection and method of fabricating semiconductor device using the same
US10388509B2 (en) 2016-06-28 2019-08-20 Asm Ip Holding B.V. Formation of epitaxial layers via dislocation filtering
US10612137B2 (en) 2016-07-08 2020-04-07 Asm Ip Holdings B.V. Organic reactants for atomic layer deposition
US9859151B1 (en) 2016-07-08 2018-01-02 Asm Ip Holding B.V. Selective film deposition method to form air gaps
KR20180012727A (en) 2016-07-27 2018-02-06 에이에스엠 아이피 홀딩 비.브이. Method of processing a substrate
US10395919B2 (en) 2016-07-28 2019-08-27 Asm Ip Holding B.V. Method and apparatus for filling a gap
US10410943B2 (en) 2016-10-13 2019-09-10 Asm Ip Holding B.V. Method for passivating a surface of a semiconductor and related systems
US10643826B2 (en) 2016-10-26 2020-05-05 Asm Ip Holdings B.V. Methods for thermally calibrating reaction chambers
US10435790B2 (en) 2016-11-01 2019-10-08 Asm Ip Holding B.V. Method of subatmospheric plasma-enhanced ALD using capacitively coupled electrodes with narrow gap
US10229833B2 (en) 2016-11-01 2019-03-12 Asm Ip Holding B.V. Methods for forming a transition metal nitride film on a substrate by atomic layer deposition and related semiconductor device structures
US10643904B2 (en) 2016-11-01 2020-05-05 Asm Ip Holdings B.V. Methods for forming a semiconductor device and related semiconductor device structures
US10134757B2 (en) 2016-11-07 2018-11-20 Asm Ip Holding B.V. Method of processing a substrate and a device manufactured by using the method
US10340135B2 (en) 2016-11-28 2019-07-02 Asm Ip Holding B.V. Method of topologically restricted plasma-enhanced cyclic deposition of silicon or metal nitride
US10269558B2 (en) 2016-12-22 2019-04-23 Asm Ip Holding B.V. Method of forming a structure on a substrate
US10468261B2 (en) 2017-02-15 2019-11-05 Asm Ip Holding B.V. Methods for forming a metallic film on a substrate by cyclical deposition and related semiconductor device structures
US10283353B2 (en) 2017-03-29 2019-05-07 Asm Ip Holding B.V. Method of reforming insulating film deposited on substrate with recess pattern
US10529563B2 (en) 2017-03-29 2020-01-07 Asm Ip Holdings B.V. Method for forming doped metal oxide films on a substrate by cyclical deposition and related semiconductor device structures
US10103040B1 (en) 2017-03-31 2018-10-16 Asm Ip Holding B.V. Apparatus and method for manufacturing a semiconductor device
US10446393B2 (en) 2017-05-08 2019-10-15 Asm Ip Holding B.V. Methods for forming silicon-containing epitaxial layers and related semiconductor device structures
US10504742B2 (en) 2017-05-31 2019-12-10 Asm Ip Holding B.V. Method of atomic layer etching using hydrogen plasma
US10541333B2 (en) 2017-07-19 2020-01-21 Asm Ip Holding B.V. Method for depositing a group IV semiconductor and related semiconductor device structures
US10312055B2 (en) 2017-07-26 2019-06-04 Asm Ip Holding B.V. Method of depositing film by PEALD using negative bias
US10590535B2 (en) 2017-07-26 2020-03-17 Asm Ip Holdings B.V. Chemical treatment, deposition and/or infiltration apparatus and method for using the same
US10605530B2 (en) 2017-07-26 2020-03-31 Asm Ip Holding B.V. Assembly of a liner and a flange for a vertical furnace as well as the liner and the vertical furnace
US10249524B2 (en) 2017-08-09 2019-04-02 Asm Ip Holding B.V. Cassette holder assembly for a substrate cassette and holding member for use in such assembly
US10607895B2 (en) 2017-09-18 2020-03-31 Asm Ip Holdings B.V. Method for forming a semiconductor device structure comprising a gate fill metal
US10403504B2 (en) 2017-10-05 2019-09-03 Asm Ip Holding B.V. Method for selectively depositing a metallic film on a substrate
US10319588B2 (en) 2017-10-10 2019-06-11 Asm Ip Holding B.V. Method for depositing a metal chalcogenide on a substrate by cyclical deposition
US10290508B1 (en) 2017-12-05 2019-05-14 Asm Ip Holding B.V. Method for forming vertical spacers for spacer-defined patterning
US10535516B2 (en) 2018-02-01 2020-01-14 Asm Ip Holdings B.V. Method for depositing a semiconductor structure on a surface of a substrate and related semiconductor structures
USD880437S1 (en) 2018-02-01 2020-04-07 Asm Ip Holding B.V. Gas supply plate for semiconductor manufacturing apparatus
US10510536B2 (en) 2018-03-29 2019-12-17 Asm Ip Holding B.V. Method of depositing a co-doped polysilicon film on a surface of a substrate within a reaction chamber
US10612136B2 (en) 2018-06-29 2020-04-07 ASM IP Holding, B.V. Temperature-controlled flange and reactor system including same
US10388513B1 (en) 2018-07-03 2019-08-20 Asm Ip Holding B.V. Method for depositing silicon-free carbon-containing film as gap-fill layer by pulse plasma-assisted deposition
US10483099B1 (en) 2018-07-26 2019-11-19 Asm Ip Holding B.V. Method for forming thermally stable organosilicon polymer film
US10381219B1 (en) 2018-10-25 2019-08-13 Asm Ip Holding B.V. Methods for forming a silicon nitride film
US10559458B1 (en) 2018-11-26 2020-02-11 Asm Ip Holding B.V. Method of forming oxynitride film

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030093721A (en) * 2002-06-05 2003-12-11 삼성전자주식회사 Method for Patterning Inter-Metal Dielectric Layer
US20060189133A1 (en) * 2005-02-22 2006-08-24 International Business Machines Corporation Reliable BEOL integration process with direct CMP of porous SiCOH dielectric
WO2007032563A1 (en) 2005-09-16 2007-03-22 Nec Corporation Wiring structure and semiconductor device and production methods thereof
KR20070036532A (en) * 2005-09-29 2007-04-03 매그나칩 반도체 유한회사 Method for manufacturing cmos image sensor

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020034309A (en) 2000-10-31 2002-05-09 박종섭 Method for etching using plasma in semiconductor device
US7335600B2 (en) * 2003-05-01 2008-02-26 United Microelectronics Corp. Method for removing photoresist
KR100499174B1 (en) * 2003-06-17 2005-07-01 삼성전자주식회사 Image device
US7351656B2 (en) * 2005-01-21 2008-04-01 Kabushiki Kaihsa Toshiba Semiconductor device having oxidized metal film and manufacture method of the same
KR100653715B1 (en) * 2005-06-17 2006-11-28 삼성전자주식회사 Semiconductor devices including a topmost metal layer with at least one opening and methods of fabricating the same
US7314828B2 (en) * 2005-07-19 2008-01-01 Taiwan Semiconductor Manufacturing Company, Ltd. Repairing method for low-k dielectric materials
KR20070071045A (en) 2005-12-29 2007-07-04 매그나칩 반도체 유한회사 Method for forming metal line in semiconductor device and method for manufacturing semiconductor device using the same
US20080242118A1 (en) * 2007-03-29 2008-10-02 International Business Machines Corporation Methods for forming dense dielectric layer over porous dielectrics

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030093721A (en) * 2002-06-05 2003-12-11 삼성전자주식회사 Method for Patterning Inter-Metal Dielectric Layer
US20060189133A1 (en) * 2005-02-22 2006-08-24 International Business Machines Corporation Reliable BEOL integration process with direct CMP of porous SiCOH dielectric
WO2007032563A1 (en) 2005-09-16 2007-03-22 Nec Corporation Wiring structure and semiconductor device and production methods thereof
KR20070036532A (en) * 2005-09-29 2007-04-03 매그나칩 반도체 유한회사 Method for manufacturing cmos image sensor

Also Published As

Publication number Publication date
US20110294288A1 (en) 2011-12-01
US20090137111A1 (en) 2009-05-28
KR20090054239A (en) 2009-05-29
US8026171B2 (en) 2011-09-27
US8338295B2 (en) 2012-12-25

Similar Documents

Publication Publication Date Title
US10403670B2 (en) Semiconductor device and method of manufacturing the same, and electronic apparatus
US9911778B2 (en) Semiconductor device, fabrication method for a semiconductor device and electronic apparatus
US9530811B2 (en) Elevated photodiode with a stacked scheme
US10431546B2 (en) Manufacturing method for semiconductor device and semiconductor device
US10249674B2 (en) Semiconductor device and electronic apparatus including a semiconductor device having bonded sensor and logic substrates
US10121814B2 (en) Solid-state imaging device, manufacturing method thereof, and electronic apparatus
US10438985B2 (en) Semiconductor device, manufacturing method thereof, and electronic apparatus
US9257326B2 (en) Method of making backside illuminated image sensors
US8772072B2 (en) Backside illuminated image sensor
JP6259418B2 (en) Back-illuminated image sensor device integrated vertically
US8895349B2 (en) Backside illuminated image sensor having capacitor on pixel region
US20160284755A1 (en) Semiconductor apparatus
KR101899595B1 (en) Solid-state imaging device, manufacturing method of solid-state imaging device, and electronic equipment
TWI599025B (en) Semiconductor image sensor device and method for manufacturing the same
US9941321B2 (en) Semiconductor device and method of manufacturing semiconductor device
JP5730530B2 (en) Image sensor
US8564135B2 (en) Backside illuminated sensor and manufacturing method thereof
US10453886B2 (en) Semiconductor apparatus, method of manufacturing semiconductor apparatus, method of designing semiconductor apparatus, and electronic apparatus
TWI517375B (en) Semiconductor device and manufacturing of the same
TWI407554B (en) Solid-state imaging device, method of fabricating solid-state imaging device, and camera
US9368545B2 (en) Elevated photodiodes with crosstalk isolation
US9093348B2 (en) Method of manufacturing semiconductor device, semiconductor device, and electronic apparatus
KR100687102B1 (en) Image sensor and method of manufacturing the same
EP2361440B1 (en) Backside illuminated image sensor
US7745250B2 (en) Image sensor and method for manufacturing the same

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant