JP2008042827A - Solid-state imaging element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that power consumption tends to increase as a driving signal for charge transfer increases, since a CCD transfer path for accumulating and transferring image information (electric charges) is added to a normal CCD type solid-state imaging element. <P>SOLUTION: The solid-state imaging element has a pixel section with matrix-like light reception units comprising a plurality of light receiving elements which generate electric signals corresponding to light intensities of received light beams, amplifying parts which amplify output signals of the light receiving elements, a plurality of storage parts which store the electric signals amplified by the amplifiers, and a signal output part which reads the electric signals out of the plurality of storage parts. Differences between the electric signals from the light receiving elements 1 and a reference electric signal are defined as outputs. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device, and more particularly to a technique for performing high-speed imaging.

High speed for analysis of (a) vehicle crash test, (b) product drop test / strength test, (c) combustion state of internal combustion engine, (d) phenomena in the field of physical chemistry such as chemical reaction, etc. A camera is used.
In this regard, in Patent Document 1, as a CCD type imaging device capable of high-speed shooting, a plurality of charge storage elements are arranged around each photoelectric conversion element, and writing to the charge storage elements is performed at the time of writing. It can be realized.

FIG. 8 shows a solid-state imaging device described in Patent Document 1. First, operations during continuous overwriting will be described. Image information (charge) generated by the photodiode 230a is collected in the charge collection well 231a, transferred from the input gate 232a to the CCD transfer path 233a, and transferred downward on the CCD transfer path 233a. The charge transfer on the CCD transfer path 233a is performed by standard 23-phase driving. The CCD transfer path 233a is not parallel to the vertical line 240 connecting the input gate 232a and the input gate 232b of the lower pixel, but is inclined to the left in FIG. Because of this inclination, the CCD transfer path 233b that exits from the input gate 232b of the lower pixel can be incorporated in the light receiving surface. The CCD transfer path 233a linearly extends diagonally downward for a distance of 6 pixels. A drain gate 235a and a drain 236a are provided at the lowermost end. After the image information is transferred on the CCD transfer path 233a, the image information is discharged out of the device from the drain 236a. As will be described later, the drain gate 235a is used in combination with the read gate.
JP 2000-165750 A

However, the technique described in Patent Document 1 adds a CCD transfer path for accumulating and transferring image information (charges) to a normal CCD solid-state imaging device, so that the charge transfer drive signal increases and is consumed. Power tends to increase.
The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a MOS type solid-state imaging device that does not significantly increase power consumption and that can perform high-quality high-speed shooting. .

  In order to achieve the above object, a solid-state imaging device of the present invention includes a plurality of light receiving elements that generate electrical signals according to received light intensity, and a plurality of light signals that store the electrical signals and noise signals from the light receiving elements. A solid-state imaging device that constitutes a light receiving unit in which pixel units including a storage unit are arranged in a matrix, and obtains a differential signal between an electrical signal (hereinafter referred to as a light receiving signal) from the light receiving device and a noise signal.

According to the solid-state imaging device of the present invention, a differential signal between a received light signal and a noise signal can be obtained, high-quality high-speed shooting is possible, transfer operation as in Patent Document 1 is unnecessary, and high-speed without increasing power consumption. Shooting is possible.
The solid-state imaging device of the present invention has a difference circuit between the light receiving element in the pixel unit and the storage unit, and after obtaining the difference signal of the light reception signal and the noise signal by the difference circuit, the storage unit To accumulate.

According to the solid-state imaging device of the present invention, a difference signal between a received light signal and a noise signal can be obtained by a difference circuit, and high-quality high-speed shooting with less noise can be performed.
In the solid-state imaging device of the present invention, the storage unit in the pixel unit has a difference function between a light reception signal and a noise signal.
According to the solid-state imaging device of the present invention, a difference signal between a received light signal and a noise signal is obtained in the storage unit, and high-quality high-speed shooting with less noise is possible. Also, the difference circuit can be omitted. As a result, the space of the difference circuit omitted can be used to increase the area of the light receiving element, thereby contributing to improvement in sensitivity. Further, since the space can be omitted, the chip size can be reduced.

According to the solid-state imaging device of the present invention, the amplification unit is provided after the light receiving element in the pixel unit.
According to the solid-state imaging device of the present invention, since the light reception signal and the noise signal are amplified, an output signal having a large S / N can be obtained, and high-quality high-speed shooting with less noise can be performed.
The solid-state imaging device according to the present invention includes an output circuit unit that reads the received light signal and the noise signal accumulated in the storage unit, and includes an amplification unit in the previous stage of the output circuit unit.

According to the solid-state imaging device of the present invention, accumulated charges are held when reading from the storage unit, so that an output signal with a large S / N can be obtained without a decrease in output, and high-quality high-speed shooting with less noise is possible. It becomes.
In the solid-state imaging device of the present invention, the difference circuit holds a voltage difference between the noise signal and the first reference signal in a holding unit, and applies a voltage level of the light reception signal to the voltage difference, or the light reception A voltage difference between the element and the first reference signal is held in a holding unit, and a voltage level of the noise signal is applied to the voltage difference to obtain a difference between the noise signal and the light reception signal.

According to the solid-state imaging device of the present invention, it is possible to realize driving for obtaining a difference signal between a light reception signal and a reference signal by a difference circuit.
In the solid-state imaging device of the present invention, the storage unit has a capacitor, the light receiving signal is accumulated in the light receiving element side terminal of the capacitor, and the second reference signal is accumulated in the terminal opposite to the light receiving element side terminal. Applying a noise signal from the light receiving element side terminal, or accumulating the noise signal in the light receiving element side terminal of the capacitor and storing a second reference signal in a terminal opposite to the light receiving element side terminal, By applying a light reception signal from the element side terminal, a differential voltage between the light reception signal and the noise signal is obtained.

According to the solid-state imaging device of the present invention, it is possible to realize driving for obtaining a difference signal between the light reception signal and the reference signal in the storage unit.
The solid-state imaging device of the present invention includes the storage unit on which the light reception signal and the noise signal are written and read out on the same side.
According to the solid-state imaging device of the present invention, a storage unit can be realized with a simple circuit configuration by configuring a capacitor in parallel between the light receiving element unit and the output circuit unit.

According to the solid-state imaging device of the present invention, the storage unit is provided on a side where writing and reading of the light reception signal and the noise signal are different.
According to the solid-state imaging device of the present invention, the differential circuit can be omitted because the storage unit has a differential function by configuring a capacitor in series between the light receiving element unit and the output circuit unit. As a result, the space of the difference circuit omitted can be used to increase the area of the light receiving element, thereby contributing to improvement in sensitivity. Further, since the space can be omitted, the chip size can be reduced.

  Note that the present invention can be realized not only as such a solid-state image sensor but also as a camera capable of high-speed shooting with less noise including such a solid-state image sensor.

  According to the solid-state imaging device of the present invention, it is possible to realize a MOS type solid-state imaging device that does not significantly increase power consumption and can perform high-quality high-speed shooting.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(Embodiment 1)
A solid-state imaging device according to Embodiment 1 of the present invention will be described with reference to the drawings.
FIG. 1 is a diagram illustrating a schematic configuration of a solid-state imaging device.
In FIG. 1, 1 is a light receiving element, 2 is a transfer MOS transistor for transferring the charge of the light receiving element 1, 3 is a gate of the transfer MOS transistor 2, 4 is a reset MOS transistor, and 5 is a gate of the reset MOS transistor 4. The drain of the transistor 4 is set to a desired voltage VR.

The MOS transistor 6 and the MOS transistor 7 form a source follower. The drain of the MOS transistor 6 is connected to the power supply VDD, and the source is connected to the drain of the MOS transistor 7. A bias voltage is supplied to the gate 8 of the MOS transistor 7.
Reference numeral 20 is a MOS transistor, 21 is a gate of the MOS transistor 20, 22 is a capacitor, 23 and 24 are MOS transistors that form a source follower, and 25 is an output node. A bias voltage is supplied to the gate 26 of the MOS transistor 24.

  Reference numeral 9 denotes a MOS transistor, and reference numeral 10 denotes a gate light reception signal of the MOS transistor 9, which is turned on when a noise signal is stored in the storage unit and is turned off when a light reception signal and a noise signal are read. 11 is a MOS transistor, 12 is a gate of the MOS transistor 11, and a drain of the MOS transistor 11 is set to a desired voltage VB. The source of the MOS transistor 11 is connected to the source of the MOS transistor 9 and the gate of the MOS transistor 13 (referred to as point M). By turning on the MOS transistor 11, the point M is set to VB.

The MOS transistors 13 and 14 form a source follower, the drain of the MOS transistor 13 is connected to the power supply VDD, and the source is connected to the drain of the MOS transistor 14. A bias voltage is supplied to the gate 15 of the MOS transistor 14.
A connection point between the source follower of the MOS transistor 13 and the drain of the MOS transistor 14 is an output node 16 at the output. A storage unit is connected to point M.

  Reference numerals 17-1, 17-2, 17-3, 17-4, 17-n in the storage section are MOS transistors, their drains are connected to the M point, and the sources are capacitors 19-1, 19-2, 19-, respectively. 3, 19-4, 19-n. Reference numerals 18-1, 18-2, 18-3, 18-4, and 18-n denote gates of the MOS transistors 17-1, 17-2, 17-3, 17-4, and 17-n, respectively.

  The other terminals of the capacitors 19-1, 19-2, 19-3, 19-4, 19-n are grounded. With this configuration, high-speed shooting of n frames is possible. Further, the capacitor C0 connected to the point M is a stray capacitance. A difference signal between a light reception signal and a noise signal obtained by a difference circuit composed of a capacitor 22 and a MOS transistor 20 is accumulated in the storage unit 19. Thereafter, a differential signal is output to the output node 16 by a source follower composed of the MOS transistors 13 and 14.

Hereinafter, the operation of the solid-state imaging device of the first embodiment will be described. FIG. 2 is a timing chart of the solid-state imaging device according to the first embodiment.
In the figure, period A is a period for accumulating the received light signal in the storage unit, and period B is a period for reading the received light signal accumulated in the storage unit.
Reference numeral 30 denotes a signal applied to the gate 10 of the MOS transistor 9. In the period A in which the received light signal is accumulated in the storage unit, the HIGH level is applied to make it conductive, and in the reading period B, the LOW level is applied to make it non-conductive.

31 is a signal to be applied to the gate 12 of the MOS transistor 11, and in the accumulation period A, the LOW level is applied to make the circuit non-passable, and in the reading period B, the HIGH level is applied in the periods t7, t9, t11 and the M point. The potential is initialized (set to VB level).
A signal 32 is applied to the gate 5 of the MOS transistor 4, and a HIGH level is applied during periods t1, t3, and t5 to initialize the gate of the MOS transistor 6 (set to the VR level).

A signal 33 is applied to the gate 3 of the MOS transistor 2, and a HIGH level is applied during the periods t 2, t 4 and t 6 to transfer the charge of the light receiving element to the gate of the MOS transistor 6.
A signal 34 is applied to the gate 21 of the MOS transistor 20, and a HIGH level is applied during the periods t1, t3, and t5 to set the terminal voltage of the capacitor 22 to VREF.

Reference numeral 35 denotes a signal applied to the gate 18-1 of the MOS transistor 17-1 of the memory unit. A HIGH level is applied in the periods t2 and t8, and the difference signal is accumulated in the capacitor 19-1 in the period t2, and in the period t8. Read the signal of the capacitor 19-1.
A signal 36 is applied to the gate 18-2 of the MOS transistor 17-2 of the memory unit. A HIGH level is applied during the periods t4 and t10, and the difference signal is accumulated in the capacitor 19-2 during the period t4. Read the signal of the capacitor 19-2.

Reference numeral 37 denotes a signal applied to the gate 18-n of the MOS transistor 17-n of the memory unit. A HIGH level is applied during the periods t6 and t12, and the difference signal is accumulated in the capacitor 19-n during the period t6. Read the signal of the capacitor 19-n.
The operation will be described below with reference to FIGS.
In the period t1, the MOS transistors 4, 20, and 9 are turned on, and the initialization level (VR) is applied to the terminal of the capacitor 22 through the source follower (potential VRSF). The other terminal of the capacitor 22 is at the VREF potential because the MOS transistor 20 is conductive. Therefore, the capacity 22 stores the difference between VREF and VRSF. Further, (VREF−Vt drop) is output to the output node 25 of the source follower.

  In the period t2, the MOS transistors 2, 9, 17-1 are conductive. The operation of transferring the charge of the light receiving element 1 to the gate 6 of the MOS transistor through the MOS transistor 2 is performed. If the gate potential of the MOS transistor 6 drops by ΔV due to charge transfer from the light receiving element 1, the output of the source follower formed by the MOS transistors 6 and 7 will drop by ΔV1 (Vt drop of ΔV). Since the difference between VREF and VRSF is stored in the capacitor 22, the gate of the MOS transistor 23 is decreased by ΔV1, and the output node 25 is further decreased (by Vt of ΔV).

The potential change of the output node 25 is (VREF− (Vt drop)) in the period t1, and (VREF− (Vt drop) − (Vt drop of ΔV1)) in the period t2.
Here, the output node 25 changes in the difference between the reference voltage and the signal voltage (Vt drop of ΔV1). Since the MOS transistors 9 and 17-1 are also conductive during the period t2, (VREF− (Vt drop) − (Vt drop of ΔV1)) is recorded in the capacitor 19-1.

Similarly, in the periods t3 and t4 and the periods t5 and t6, the above differential voltage is recorded from the capacitors 17-2 to 17-n.
Next, since the MOS transistor 11 becomes conductive in the period t7, the level at the point M is set to VB.
In the period t8, the MOS transistor 17-1 of the storage unit is turned on, so that the differential voltage accumulated in the capacitor 19-1 is generated at the point M by dividing the voltage between the capacitor 19-1 and the stray capacitor C0. 14 is output to the output node 16 via the source follower constituted by 14.

Similarly, in the period t9, the MOS transistor 11 becomes conductive again, so that the level at the point M is set to VB.
In the period t10, the MOS transistor 17-2 of the storage unit is turned on, so that a differential voltage accumulated in the capacitor 19-2 is generated at a point M between the capacitor 19-2 and the stray capacitor C0. 14 is output to the output node 16 via the source follower constituted by 14. Similarly, in the period t11, the MOS transistor 11 becomes conductive again, so that the level at the point M is set to VB. During the period t12, the MOS transistor 17-n of the storage unit is turned on, so that the differential voltage stored in the capacitor 19-n is generated at the M point by the divided voltage of the capacitor 19-n and the floating capacitor C0. 14 is output to the output node 16 via the source follower constituted by 14.

As described above, n capacitors of the storage unit in the pixel unit are provided, and the light reception signal from the light receiving element can be photographed at high speed with a high-quality image with low noise at a high speed of 10,000 frame rates or more. In the description, an amplifying unit composed of the MOS transistors 6 and 7 is used, but the same effect can be obtained even without this amplifying unit.
(Embodiment 2)
A solid-state imaging device according to Embodiment 2 of the present invention will be described with reference to the drawings.

In FIG. 3, the source follower formed by the MOS transistors 23 and 24 of the first embodiment is changed to an inverter, and the terminal of the capacitor 22 connected to the gate of the MOS transistor 23 is connected to the gate of the MOS transistor 24. The MOS transistor 20 is connected to the gate of the MOS transistor 24 and the output node 25.
Hereinafter, the operation of the solid-state imaging device of the second embodiment will be described. In the second embodiment, the timing is the same as in FIG. 2, and the application of the HIGH level in the periods t1, t3, and t5 with the signal applied to the gate 21 of the MOS transistor 20 at 34 is the same.
However, it differs from the first embodiment in that the operating point of the inverter is set by short-circuiting the drain and gate of the MOS transistor 24 in terms of operation.

In a period t1, a reference signal is output from the source follower, the MOS transistor 20 is turned on, the gate and drain of the MOS transistor 24 are short-circuited, and the operating point is set.
When the light reception signal is output to the source follower during the period t2, the differential voltage between the reference signal and the light reception signal is amplified by the inverter via the capacitor 22 and accumulated in the storage unit capacitor 17. The difference from the first embodiment is that the differential voltage between the reference signal and the received light signal is amplified and stored in the storage unit capacity.

FIG. 4 is a functional block diagram showing the configuration of the solid-state imaging device according to the first and second embodiments.
50-1-1 to 50-LM are pixels in FIG. 1, and are arranged in an L × M matrix. The output node 16 of each pixel is connected to a MOS transistor 51, and the MOS transistor 51 is connected to a common vertical signal line 52. The common vertical signal line 52 is connected to the common signal line 55 via the MOS transistor 54 in each column. Reference numeral 56 denotes a vertical scanning circuit, and an output 57 is connected to the gate of the MOS transistor 51. Reference numeral 58 denotes a horizontal scanning circuit, and an output 59 is connected to the gate of the MOS transistor 54.

  The operation will be described below with reference to FIG. When the output 57-1 of the vertical scanning circuit is output, the MOS transistor 51 becomes conductive, and the signal of the output node 16 of the pixels 50-1-1 to 50-L-1 is transmitted to the common vertical signal line 52. Reference numeral 58 denotes a horizontal scanning circuit. When the output is applied to the output line 59, the MOS transistor 54 is turned on and is output to the common signal line 55 in time series. This operation is repeated until t10 and t12.

Next, when the output 57-2 of the vertical scanning circuit is applied, the light reception signals of the pixels 50-1-2 to 50-L-2 are output to the common signal line 55. Finally, the pixels 50-1-M to 50-LM are repeated, and L × M pixels, n frames of light reception signals are obtained at high speed.
As described above, n capacitors of the storage unit in the pixel unit are provided, noise is generated by generating a difference signal between the reference signal and the received light signal at a high speed of 10,000 frame rates or more and storing the received light signal from the light receiving element in the storage unit. High-speed images can be taken with high-quality images with little. In the description, an amplifying unit composed of the MOS transistors 6 and 7 is used, but the same effect can be obtained even without this amplifying unit.
(Embodiment 3)
A solid-state imaging device according to Embodiment 3 of the present invention will be described with reference to the drawings.

FIG. 5 is a diagram illustrating a schematic configuration of the solid-state imaging device.
In FIG. 5, 1 is the light receiving element, 2 is the transfer MOS transistor for transferring the charge of the light receiving element 1, 3 is the gate of the transfer MOS transistor 2, 4 is the reset MOS transistor, and 5 is the gate of the reset MOS transistor 4. The drain of the transistor 4 is set to a desired voltage VR.

The MOS transistor 6 and the MOS transistor 7 form a source follower. The drain of the MOS transistor 6 is connected to the power supply VDD, and the source is connected to the drain of the MOS transistor 7. A bias voltage is supplied to the gate 8 of the MOS transistor 7. The output of the source follower is connected to the output node M.
The MOS transistor 13 and the MOS transistor 14 form an inverter, the gate of the MOS transistor 13 is connected to the drain, and the source is connected to the drain of the MOS transistor 14. A connection point between the source of the MOS transistor 13 and the drain of the MOS transistor 14 is an output and an output node 16.

  A MOS transistor 61 is connected to the output node 16 and the gate of the MOS transistor 14. 62 is a gate of the MOS transistor 61, and C0 is a stray capacitance. The drains of the MOS transistors 17-1, 17-2, 17-n are connected to the output node M of the source follower. The sources of the MOS transistors 17-1, 17-2, and 17-n are connected to capacitors 19-1, 19-2, and 19-n, respectively. The drains of the MOS transistors 60-1, 60-2, 60-n are respectively connected to the capacitors 19-1, 19-2, 19-n, and the sources are respectively connected to the N points.

  Reference numeral 18-1 denotes a common gate terminal for the MOS transistors 17-1 and 60-1. Similarly, 18-2 is a common gate terminal of the MOS transistors 17-2 and 60-2, and 18-n is a common gate terminal of the MOS transistors 17-n and 60-n. The N point is connected to the drain of the MOS transistor 61 and the gate of the MOS transistor 14.

A light receiving signal is applied to the light receiving element side of the capacitor 19, and an operating point voltage of the inverter is applied to the inverter side constituted by the MOS transistors 13 and 14, and the light receiving signal and the operating point voltage are held in the capacitor 19. Thereafter, by applying a noise signal to the light receiving element side, a difference between the light receiving element and the noise signal is obtained and output to the output node 16.
Hereinafter, the operation of the solid-state imaging device of the present embodiment will be described. FIG. 6 is a timing chart of the solid-state imaging device according to the third embodiment.

In the figure, period A is a period for accumulating the received light signal in the storage unit, and period B is a period for reading the received light signal accumulated in the storage unit.
Reference numeral 70 denotes a signal applied to the gate 62 of the MOS transistor 61. The HIGH level is applied during the period A in which the received light signal is accumulated in the storage unit, and the conductive state is established.
Reference numeral 71 denotes a signal applied to the gate 5 of the MOS transistor 4. In the accumulation period A, the LOW level is applied to make the circuit non-passable, and in the reading period B, the HIGH level is applied to initialize the potential at the point M (VB Level).

A signal 72 is applied to the gate 3 of the MOS transistor 2, and a HIGH level is applied during the periods t 1, t 2, and t 3 to transfer the charge of the light receiving element to the gate of the MOS transistor 6.
A signal 73 is applied to the gate terminal 18-1, and a HIGH level is applied during periods t1 and t4 to store and read the received light signal in the capacitor 19-1.

A signal 74 is applied to the gate terminal 18-2, and a HIGH level is applied during periods t2 and t5 to store and read the received light signal in the capacitor 19-2.
A signal 75 is applied to the gate terminal 18-n. A HIGH level is applied during periods t3 and t6 to store and read the received light signal in the capacitor 19-n. In the period A, the MOS transistor 61 becomes conductive, so that an operating point where the input and output of the inverter constituted by the MOS transistors 13 and 14 are equal is set, and the voltage value (V0) is set to the MOS transistors 60-1, 60-2, 60-. to n.

In the period t1, since the MOS transistors 61, 2, 17-1, and 60-1 are turned on, the light reception signal is supplied to the capacitor 19-1 via the source follower composed of the MOS transistors 6 and 7 (VP1). ) Is transmitted. That is, the (VP1-V0) value is accumulated and held in the capacitor 19-1.
In the period t2, the MOS transistors 61, 2, 17-2, 60-2 are turned on, so that the light reception signal is supplied to the capacitor 19-2 via the source follower constituted by the MOS transistors 6, 7 (VP2). ) Is transmitted. That is, the (VP2-V0) value is accumulated and held in the capacitor 19-2.

In the period t3, the MOS transistors 61, 2, 17-n, and 60-n are turned on, so that the light reception signal is sent to the capacitor 19-n via the source follower constituted by the MOS transistors 6 and 7 (VPn) corresponding to the light reception signal. ) Is transmitted. That is, the (VPn−V0) value is accumulated and held in the capacitor 19-n.
In the period t4, the MOS transistors 4, 61, 17-1, and 60-1 are turned on, and the MOS transistor 61 is turned off. At this time, the reference potential is applied from the MOS 17-1 to the terminal on the M point side of the capacitor 19-1. This voltage is set to (VR0). Accordingly, the M point side potential of the capacitor 19-1 changes from VP1 to VR0. In general, since VR0> VP1, the potential at the point N of the capacitor 19-1 increases from V0 by (VR0-VP1). This corresponds to the light reception signal, which is input to the inverter formed by the MOS transistors 13 and 14, and an output is generated at the output node 16.

  Similarly, in the period t5, the MOS transistors 4, 61, 17-2, 60-2 are turned on, and the MOS transistor 61 is turned off. At this time, the reference potential is applied from the MOS 17-2 to the terminal on the M point side of the capacitor 19-2. This voltage is set to (VR0). Therefore, the M point side potential of the capacitor 19-2 changes from VP2 to VR0. In general, since VR0> VP2, the potential at the N-point side of the capacitor 19-2 increases from V0 by (VR0-VP2). This corresponds to the light reception signal, which is input to the inverter formed by the MOS transistors 13 and 14, and an output is generated at the output node 16.

  Similarly, in the period t6, the MOS transistors 4, 61, 17-n, 60-n are turned on, and the MOS transistor 61 is turned off. At this time, the reference potential is applied from the MOS 17-n to the terminal on the M point side of the capacitor 19-n. This voltage is set to (VR0). Therefore, the M point side potential of the capacitor 19-n changes from VPn to VR0. In general, since VR0> VPn, the N-point side potential of the capacitor 19-n increases from V0 by (VR0-VPn). This corresponds to the light reception signal, which is input to the inverter formed by the MOS transistors 13 and 14, and an output is generated at the output node 16.

  The operation will be described below with reference to FIG. When the output 57-1 of the vertical scanning circuit is output, the MOS transistor 51 becomes conductive, and the signal of the output node 16 of the pixels 90-1-1 to 90-L-1 is transmitted to the common vertical signal line 52. Reference numeral 58 denotes a horizontal scanning circuit. When the output is applied to the output line 59, the MOS transistor 54 is turned on and is output to the common signal line 55 in time series.

This operation is repeated until t10 and t12. Next, when the output 57-2 of the vertical scanning circuit is applied, the light reception signals of the pixels 90-1-2 to 90-L-2 are output to the common signal line 55. Finally, the pixels 90-1-M to 90-LM are repeated, and L × M pixels, n-frame light reception signals are obtained at high speed.
As described above, n capacitors of the storage unit in the pixel unit are provided, and the light reception signal from the light receiving element is generated at a high speed of 10,000 frame rates or more, and the reference signal and the light reception signal are generated in the storage unit, thereby reducing noise. High-speed shooting with high quality images. In the description, an amplifying unit composed of the MOS transistors 6 and 7 is used, but the same effect can be obtained even without this amplifying unit.

  By creating a camera using the solid-state imaging device according to Embodiments 1 to 3 of the present invention, high-speed shooting can be performed with a high-quality image with less noise.

  The solid-state imaging device according to the present invention is useful because high-speed shooting is possible with low power consumption.

1 is a diagram showing a schematic configuration of a solid-state imaging element according to Embodiment 1 of the present invention. FIG. 3 is a timing diagram of the solid-state imaging element according to Embodiment 1 of the present invention. The figure which shows schematic structure of the solid-state image sensor which concerns on Embodiment 1, 2 of this invention. The figure which shows the solid-state image sensor of the matrix arrangement | positioning which concerns on Embodiment 2 of this invention. FIG. 5 is a diagram illustrating a schematic configuration of a solid-state imaging element according to a third embodiment of the present invention. FIG. 9 is a timing diagram of a solid-state imaging element according to Embodiment 3 of the present invention. The figure which shows the solid-state image sensor of the matrix arrangement | positioning which concerns on Embodiment 3 of this invention. The figure of the solid-state image sensor of patent documents 1.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Light receiving element 2 Transfer MOS transistor 3 Gate of transfer MOS transistor 2 4 Reset MOS transistor 5 Gate of reset MOS transistor 6 MOS transistor 7 MOS transistor 8 Gate of MOS transistor 7 9 MOS transistor 10 Gate of MOS transistor 9 MOS transistor 12 MOS transistor Gate of transistor 11 MOS transistor 14 MOS transistor 15 Gate 16 of MOS transistor 14 Output node 17 MOS transistor 18 Gate of MOS transistor 17 Capacitance 20 MOS transistor 21 Gate 22 of MOS transistor 20 Capacitance 23 MOS transistor 24 MOS transistor 25 Output node 26 Gate of MOS transistor 24 30 MOS transistor A signal 31 applied to the gate 10 of the MOS transistor 11 A signal 32 applied to the gate 12 of the MOS transistor 11 A signal 33 applied to the gate 5 of the MOS transistor 4 A signal 34 applied to the gate 3 of the MOS transistor 2 applied to the gate 21 of the MOS transistor 20 A signal 35 applied to the gate 18-1 of the MOS transistor 17-1 in the storage unit A signal 37 applied to the gate 18-2 in the MOS transistor 17-2 in the storage unit The gate 18 of the MOS transistor 17-n in the storage unit Signal applied to -n 50 Pixel 60 MOS transistor 61 MOS transistor 62 Gate 63 of MOS transistor 61 Capacitance 64 MOS transistor 65 Gate 70 of MOS transistor 64 Signal 71 applied to gate 62 of MOS transistor 61 MOS transistor 4 Signal 72 applied to gate 5 of MOS transistor 2 Signal 73 applied to gate 3 of MOS transistor 2 Signal 74 applied to gate terminal 18-1 Signal 75 applied to gate terminal 18-2 Signal 90 applied to gate terminal 18-n Pixel

Claims (10)

  A light receiving section in which a plurality of light receiving elements that generate electrical signals according to received light intensity and a plurality of storage sections that store the electrical signals and noise signals from the light receiving elements are arranged in a matrix is configured. What is claimed is: 1. A solid-state image pickup device that obtains a differential signal between an electric signal (hereinafter referred to as a light-receiving signal) from the light-receiving element and a noise signal.    A difference circuit is provided between the light receiving element in the pixel portion and the storage portion, and after the difference signal between the light reception signal and the noise signal is obtained by the difference circuit, the difference circuit stores the difference signal in the storage portion. The solid-state imaging device according to claim 1.   The solid-state imaging device according to claim 1, wherein the storage unit in the pixel unit has a difference function between a light reception signal and a noise signal.    4. The solid-state imaging device according to claim 1, further comprising an amplifying unit downstream of the light receiving element in the pixel unit. 5.   4. The solid-state imaging device according to claim 1, further comprising: an output circuit unit that reads the light reception signal and the noise signal accumulated in the storage unit, and an amplification unit disposed in front of the output circuit unit. 5.   The difference circuit holds a voltage difference between the noise signal and the first reference signal in a holding unit, and applies a voltage level of the light receiving signal to the voltage difference, or between the light receiving element and the first reference signal. 3. The solid-state imaging device according to claim 2, wherein a difference between the noise signal and the light reception signal is obtained by holding a voltage difference in a holding unit and applying a voltage level of the noise signal to the voltage difference.   The storage unit has a capacitor, and after storing the light reception signal in a light receiving element side terminal of the capacitor and a second reference signal in a terminal opposite to the light receiving element side terminal, a noise signal is transmitted from the light receiving element side terminal. Or the noise signal is accumulated in the light receiving element side terminal of the capacitor, and the second reference signal is accumulated in the terminal opposite to the light receiving element side terminal, and then the light receiving signal is applied from the light receiving element side terminal. The solid-state imaging device according to claim 3, wherein a differential voltage between the light reception signal and the noise signal is obtained.   The solid-state imaging device according to any one of claims 1 to 2, and 4 to 6, further comprising the storage unit on which writing and reading of the light reception signal and the noise signal are on the same side.   8. The solid-state imaging device according to claim 1, further comprising the storage unit on a side where writing and reading of the light reception signal and the noise signal are different. 9.   A camera using the solid-state imaging device according to claim 1.

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