JP4858480B2 - Solid-state imaging device - Google Patents

Description

  The present invention relates to a solid-state imaging device in which a plurality of unit pixels are arranged, and a signal from each unit pixel can be arbitrarily selected and read by address control.

  An amplification type solid-state imaging device (APS; also called Active Pixel Sensor / gain cell), which is a kind of XY address type solid-state imaging device, is an active device (MOS transistor) such as a MOS structure in order to give the pixel itself an amplification function. ) To form a pixel. That is, signal charges (photoelectrons) accumulated in a photodiode which is a photoelectric conversion element are amplified by the active element and read out as image information.

  In this type of XY address type solid-state imaging device, for example, a plurality of pixel transistors are arranged in a two-dimensional matrix to form a pixel unit, and a signal charge corresponding to incident light for each line (row) or each pixel. Accumulation is started, and a current or voltage signal based on the accumulated signal charge is sequentially read out from each pixel by addressing.

  In this type of XY address type solid-state imaging device, for example, a large number of pixel transistors are arranged in a matrix, and accumulation of signal charges corresponding to incident light is started for each line (row) or for each pixel. A current or voltage signal based on the accumulated signal charge is sequentially read out from each pixel by addressing (see, for example, Patent Documents 1 to 4). For example, in the VGA format having about 300,000 pixels, 30 images per second that appear to be a smooth moving image to the human eye are output at an output rate of 12 MHz.

JP 11-239299 A Japanese Patent Laid-Open No. 2001-069408 JP 2001-298748 A JP 2003-031785 A

  On the other hand, in recent years, it has been considered to output an image of 30 sheets / second using, for example, an imaging device having an extremely large number of pixels. In a specific case, an image of 30 sheets / second is output from a solid-state imaging device having 3 million pixels or 30 million pixels. Even when the number of pixels is not very large, it is necessary to output 100 to 10000 images per second when time resolution is required, such as an automobile collision experiment or a ball impact moment of a baseball batter. is there.

  Here, as a method of satisfying the above-described requirements at a low data rate, it is conceivable to increase the number of output terminals, prepare hundreds of output terminals, and output in parallel.

  However, this increases the number of output terminals, which increases the area of the solid-state imaging device (increasing costs), increases the number of input terminals in the next stage, makes mounting difficult, and reduces the size of the camera. Various problems may arise, such as being difficult to synchronize a large number of output signals, and being difficult to output at a high clock due to synchronization problems.

  As a method for improving such a problem, it is conceivable to increase the reading speed. In this case, for example, in order to output 30 images / second from a solid-state imaging device having 3 million pixels or 30 million pixels, the operations are 120 MHz and 1.2 GHz, respectively. Further, even when a time resolution is required such as outputting 100 to 10000 images per second, it is effective to increase the reading speed.

  However, simply increasing the reading speed may cause an increase in power consumption, noise, or unnecessary radiation.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a solid-state imaging device capable of speeding up output while solving at least one problem of power consumption, noise, and unnecessary radiation. And

A solid-state imaging device according to the present invention includes a pixel unit that outputs an analog pixel signal corresponding to a signal charge generated by a charge generation unit that generates a signal charge, and a pixel signal output from the pixel unit as digital data. An AD conversion unit for converting into pixel data, a high-speed clock generation unit for generating a high-speed clock that is a pulse having a higher frequency than a basic clock that is a basic pulse corresponding to a drive pulse for driving the pixel unit, and a high-speed and a data output unit for outputting to the outside to convert the parallel format of the pixel data converted by the AD conversion unit by using a high-speed clock clock generator has generated the output data of a serial format, one pixel of the output data The boundary data indicating the minute break is output as data having a frequency lower than that of the high-speed clock .

  The inventions described in the dependent claims define further advantageous specific examples of the solid-state imaging device according to the present invention.

  For example, the high-speed clock generation unit is preferably arranged in the vicinity where output data is output to the outside. The generated high-speed clock may be output from a terminal different from the output data terminal.

  Preferably, the output data is output to the outside after being converted into serial format data using a high-speed clock. In this case, boundary data indicating a delimiter for all the bits of the pixel data converted by the AD conversion unit, that is, a delimiter of the word may be output from a terminal different from the terminal for output data.

  According to the present invention, the high-speed clock generation unit generates a high-speed clock having a higher frequency than the basic clock that is the basis of various transfer pulses and synchronization signals that drive the pixel unit, and uses this high-speed clock. Then, predetermined output data based on the pixel data converted by the AD conversion unit is output to the outside.

  Accordingly, an output side circuit that outputs predetermined output data based on pixel data to the outside can be operated at a high frequency while operating an input side circuit such as a pixel unit or an AD conversion unit at a low frequency. For this reason, as a whole device, an increase in power consumption can be suppressed as compared to operating all circuit systems at high speed. In addition, since the routing of high-frequency signal lines can be reduced, noise and unnecessary radiation can be suppressed. Thereby, a small, inexpensive and highly reliable imaging device (for example, a camera for taking a still image or a moving image) can be manufactured.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following description, a case where the present invention is applied to a CMOS image sensor which is an example of an XY address type solid-state imaging device will be described. The CMOS image sensor will be described on the assumption that all pixels are made of NMOS.

<Configuration of solid-state imaging device>
FIG. 1 is a schematic configuration diagram of a CMOS solid-state imaging device according to an embodiment of the present invention. FIG. 2 is a diagram for explaining an example of a device arrangement form of the clock converter and the output circuit. FIG. 3 is a timing chart showing an example of the data output method.

  The solid-state imaging device 1 is applied as an electronic still camera that can capture a color image. For example, in a still image capturing mode, a mode for sequentially reading all pixels is set.

  The solid-state imaging device 1 has a pixel unit in which a plurality of pixels including a light receiving element (an example of a charge generation unit) that outputs a signal corresponding to an incident light amount is arranged in rows and columns (that is, in a two-dimensional matrix form). The signal output from each pixel is a voltage signal, and is a column type in which a CDS (Correlated Double Sampling) processing function unit, a digital conversion unit, and the like are provided for each column.

  That is, as shown in FIG. 1, the solid-state imaging device 1 includes a pixel unit (imaging unit) 10 in which a plurality of unit pixels 3 are arranged in rows and columns, and a drive control unit 7 provided outside the pixel unit 10. And a column processing unit 26. The drive control unit 7 is an example of a horizontal scanning circuit 12, a vertical scanning circuit 14, a communication / timing generation unit 20, and a high-speed clock generation unit, and has a clock frequency faster than the input clock frequency. And a clock conversion unit 21 for generating the pulse.

  In FIG. 1, some of the rows and columns are omitted for the sake of simplicity, but in reality, tens to thousands of pixels are arranged in each row and each column. Further, as other components of the drive control unit 7, a horizontal scanning circuit 12, a vertical scanning circuit 14, and a communication / timing generation unit 20 are provided. Each element of these drive control units 7 is formed integrally with a pixel unit 10 in a semiconductor region such as single crystal silicon using a technique similar to a semiconductor integrated circuit manufacturing technique, and is a solid-state imaging which is an example of a semiconductor system It is configured as an element (imaging device).

  The unit pixel 3 includes a vertical scanning circuit 14 for vertical column selection via a vertical control line 15, a column processing unit 26 provided with a column AD circuit for each column via a vertical signal line 19, Each is connected. Here, the vertical control line 15 indicates all the wiring that enters the pixel from the vertical scanning circuit 14.

  The horizontal scanning circuit 12 and the vertical scanning circuit 14 include a decoder as will be described later, and start a shift operation (scanning) in response to a drive pulse given from the communication / timing generation unit 20. . Therefore, the vertical control line 15 includes various pulse signals (for example, a reset pulse RST, a transfer pulse TRF, a DRN control pulse DRN, etc.) for driving the unit pixel 3.

  Although not shown, the communication / timing generation unit 20 includes a functional block of a timing generator TG (an example of a read address control device) that supplies a clock signal necessary for the operation of each unit and a pulse signal at a predetermined timing, an input clock, an operation mode, and the like. And a functional block of a communication interface that outputs data including information of the solid-state imaging device 1. For example, the horizontal address signal is output to the horizontal decoder 12a and the vertical address signal is output to the vertical decoder 14a, and each decoder 12a, 14a receives it and selects a corresponding row or column.

  Further, in the communication / timing generation unit 20 of the present embodiment, the clock CLK1 having the same frequency as the input clock (master clock) CLK0 input via the terminal 5a, a clock obtained by dividing the clock CLK1, or a low speed obtained by further dividing the clock. Are supplied to each part in the device, for example, the horizontal scanning circuit 12, the vertical scanning circuit 14, the column processing unit 26, or the output circuit 28, other than the signal processing system (near the output) near the output terminal 5c. Hereinafter, the clocks divided by two and the clocks having a frequency lower than that are collectively referred to as a low-speed clock CLK2.

  The vertical scanning circuit 14 selects a row of the pixel portion and supplies a necessary pulse to the row. For example, a pulse is applied to the control line for the vertical decoder 14a that defines the vertical readout row (selects the row of the pixel unit 10) and the unit pixel 3 on the readout address (in the row direction) defined by the vertical decoder 14a. And a vertical drive circuit 14b for supplying and driving. Note that the vertical decoder 14a selects a row for electronic shutter, in addition to a row from which a signal is read.

  The horizontal scanning circuit 12 sequentially selects the column AD circuits of the column processing unit 26 in synchronization with the low-speed clock, and guides the signal to the horizontal signal line 18. For example, the horizontal decoder 12a (which selects individual column circuits in the column processing unit 26) that defines the readout column in the horizontal direction, and each signal of the column processing unit 26 according to the readout address that is defined by the horizontal decoder 12a. And a horizontal drive circuit 12 b leading to the horizontal signal line 18. For example, if the number of horizontal signal lines 18 is n (n is a positive integer) handled by the column AD circuit, for example 10 (= n), 10 horizontal signal lines 18 are arranged corresponding to the number of bits.

<Clock converter>
The clock converter 21 includes a multiplier circuit that generates a pulse having a clock frequency faster than the input clock frequency. The clock conversion unit 21 receives the low-speed clock CLK2 from the communication / timing generation unit 20, and generates a clock having a frequency twice or more higher based on the low-speed clock CLK2. Hereinafter, all clocks having a frequency two times higher than that of the low-speed clock CLK2 are collectively referred to as a high-speed clock. Here, in particular, a reference child CLK3 is attached and referred to as a high-speed clock CLK3. The clock conversion unit 21 supplies the low-speed clock CLK2 received from the communication / timing generation unit 20 and the high-speed clock CLK3 generated by itself to the output circuit 28 which is an example of the data output unit.

  Here, the high-speed clock CLK3 has a frequency that is at least twice as high as that of the low-speed clock CLK2, but is not limited to an integer multiple and may be other than an integer multiple. However, it is preferably an integer multiple from the viewpoint of easy connection of data.

The frequency of the high-speed clock CLK3 may be changed according to a command from the outside via the communication / timing generation unit 20 having a communication function with the outside. In this case, the frequency switching command P3 may be automatically switched according to an operation mode such as a still image shooting mode, a moving image shooting mode, or an addition reading mode. For example, the communication / timing generation unit 20 receives an operation mode instruction from the central control unit outside the device, and issues a frequency switching command P3 to the clock conversion unit 21 in conjunction with the operation mode. It is preferable to switch the frequency of the high-speed clock CLK3 to be generated.

  Alternatively, the frequency switching command P3 issued from the central control unit outside the device to the clock conversion unit 21 is notified independently of the operation mode (effectively directly), and automatically switched according to this notification. You may be made to do. Even in this case, in the configuration of the present embodiment, the communication / timing generation unit 20 is provided with a communication function with the outside, so that the frequency switching command P3 is sent to the clock conversion unit 21 via the communication / timing generation unit 20. Notify However, the present invention is not limited to this configuration, and the clock conversion unit 21 may have a communication function with the outside by providing the clock conversion unit 21 with a communication function with the outside.

  The clock converter 21 may be provided in a TG block (not shown) of the communication / timing generator 20, but the clock converter 21 and the wiring of the high-speed clock CLK3 coming out of the clock converter 21 are noise sources. Therefore, it is preferable to place the clock converter 21 and the output circuit 28, which are individually designed, adjacent to each other and placed on the output side of the device. In this case, as shown in FIG. 2 (A), it is preferable that the region edge of each part is partitioned into a substantially rectangular shape so that they are adjacent to each other without a gap.

  It is more desirable to design the device so that the clock converter 21 and the output circuit 28 are integrated and placed on the output side as one block. For example, as shown in FIG. 2 (B), each part is intricate, and it is not possible to determine the edge of the area between the two. The advantage that wiring between various signals can be obtained with the shortest distance is obtained.

  As the multiplication circuit of the clock converter 21, a k1 multiplication circuit may be provided when k1 is a multiple of the frequency of the low-speed clock CLK2, and various known circuits can be used. For example, the PLL frequency using a PLL (Phase Lock Loop) as shown in the prior art of Japanese Patent Publication No. 2003-8435, the prior art of Japanese Patent No. 3360667, paragraphs 6, 7 and FIG. Synthesizer circuit technology can be used. If the PLL method is used, the high-speed clock CLK3 can be phase-locked with the low-speed clock CLK2. Further, the circuit technology described in the related art of Japanese Patent No. 3366223 can be used, for example, without being limited to using the PLL.

  Also described in “Description of frequency multiplier, [online], [Search June 20, 2003], Internet <URL: http://www.nakaco.co.jp/technical/Freq%20multiplier.pdf” As described above, a circuit technique in which amplification is repeated using a band-pass filter may be used. If this method is used, all frequencies over the multiplied high-speed clock CLK3 can be covered based on the low-speed clock CLK2 as the source oscillation. In addition, a high-speed clock with less noise and relatively high purity can be obtained as compared with a method of multiplying by a PLL circuit.

  In the solid-state imaging device 1 having such a configuration, the pixel signal output from the unit pixel 3 is supplied to the column AD circuit of the column processing unit 26 via the vertical signal line 19 for each vertical column. Each column AD circuit of the column processing unit 26 receives a pixel signal for one column and processes the signal. For example, based on two sample pulses such as the sample pulse SHP and the sample pulse SHD given from the communication / timing generation unit 20, a voltage mode pixel signal input via the vertical signal line 19 is immediately after the pixel reset. A process for obtaining a difference between the signal level (noise level) and the signal level is performed. As a result, noise signal components called fixed pattern noise (FPN) and reset noise are removed. Note that an AGC (Auto Gain Control) circuit having a signal amplifying function or the like may be provided in the same semiconductor region as the column processing unit 26 as required after the column processing unit 26.

  Each column AD circuit has an ADC (Analog Digital Converter) circuit that converts a processed analog signal into 10-bit digital data using, for example, a low-speed clock CLK2. The digitized pixel data is transmitted to the horizontal signal line 18 via a horizontal selection switch (not shown) driven by a horizontal selection signal from the horizontal scanning circuit 12 and further input to the output circuit 28. Note that 10 bits is an example, and other bit numbers such as less than 10 bits (for example, 8 bits) and more than 10 bits (for example, 14 bits) may be used.

  Here, the AD conversion function is provided for each column circuit so that the data is converted into digital data for each vertical column. However, the AD conversion function is not limited to the column circuit portion, and may be provided in other locations. For example, a configuration may be employed in which each pixel in the pixel unit is provided individually (provided in large numbers), or the pixel signal is output in analog to the horizontal signal line 18, and then AD conversion is performed and passed to the output circuit 28. It is good also as a structure.

  Regardless of the configuration, pixel signals are sequentially output for each vertical column for each row from the pixel unit 10 in which light receiving elements as charge generation units are arranged in a matrix. Then, one image corresponding to the pixel unit 10 in which the light receiving elements are arranged in a matrix, that is, a frame image, is shown as a set of pixel signals of the entire pixel unit 10.

<First example of output circuit>
Here, the output circuit 28 of the first example uses the low-speed clock CLK2 and the high-speed clock CLK3 supplied from the clock conversion unit 21, the clock CLK1 from the communication / timing generation unit 20, and other pulse signals P1 to generate a horizontal signal. The pixel data D0 from the line 18 is buffered and output to the outside as video (imaging) data D1. As will be described later, for example, black level adjustment, column variation correction, signal amplification, color-related processing, signal compression processing, and the like may be performed and then output as video data D1.

  When outputting data based on the high-speed clock CLK3, the output circuit 28 first takes in pixel data (for example, 10 bits) from the column processing unit 26 as parallel data in synchronization with the low-speed clock CLK2, and thereafter, FIG. As shown, it is converted into serial format data in synchronization with only one of the rising edge and falling edge of the high-speed clock CLK3 (the rising edge in the figure) and output. As a circuit configuration for converting parallel data into serial data (hereinafter referred to as “Parisiri conversion”), a known parallel-serial conversion circuit can be used. Further, as described later, a configuration similar to that of the switching unit 284 can be used.

  Here, as the frequency of the high-speed clock CLK3, pixel data D0 indicated by n bits / parallel is output from each column AD circuit of the column processing unit 26 and taken into the signal processing unit 282 for each cycle of the low-speed clock CLK2. If this is the case, the frequency must be sufficient to convert this into serial format data within the same period. Specifically, it is necessary to be at least the number of bits, that is, n (in this example, n = 10) times the low-speed clock CLK2. Since it is not necessary to make it unnecessarily high, it is assumed here that the frequency of the high-speed clock CLK3 is 10 times the frequency of the low-speed clock CLK2, as shown in each diagram of FIG.

  The output circuit 28 not only has a function of outputting the video data D1 from the output terminal 5c to the outside, but also outputs a high-speed clock CLK3 generated by the clock converter 21 from a terminal different from the data terminal. It is good to give the function of the part. For example, the bit data of the imaging data D0 or the video data D1 is sequentially output from the terminal 5c as serial data in synchronization with the rising edge, and the high-speed clock CLK3 used at this time is output from the terminal 5d. At this time, the high-speed clock CLK3 is output in consideration of the delay with the video data D1. Taking the delay into account means that the data switching position of each bit of the video data D1 in the serial format and the respective edges of the high-speed clock CLK3 are maintained in a fixed relationship (for example, substantially the same position). means. The same applies hereinafter.

  In this way, by using the low frequency as the input clock CLK0, the operation of the pixel unit 10 and the column processing unit 26 is operated at a low speed, and only the output circuit 28 side is operated at a high speed, so that the circuit unit that operates at a high speed can be minimized. Thus, the power consumption can be reduced. Further, the connection from the pre-stage circuit or IC (integrated circuit) for supplying the input clock CLK0 to the solid-state imaging device 1 is facilitated.

  In addition, in the present embodiment, the clock conversion unit 21 is disposed in the vicinity of the output circuit 28 that performs the function of the parallel-serial conversion that requires the high-speed clock CLK3, and the high-speed clock CLK3 is generated in the vicinity of the output circuit 28. Therefore, it is possible to prevent the influence of noise on the operation of the pixel unit 10 and the column processing unit 26 without drawing a high-speed pulse line. Further, since the high-speed pulse line can be kept near the output circuit 28 without routing the high-speed pulse line, the problem of unnecessary radiation can be suppressed. For example, it is possible to reduce unnecessary radiation from entering the video data D1 and becoming noise.

  According to the CMOS sensor type solid-state imaging device 1 having such a configuration, the pixel unit and the column circuit are operated at a low frequency, and then the output unit side performs parallel-serial conversion using a high-speed clock to the output unit. Can be operated at high speed with few terminals. As a result, an increase in power consumption of the entire apparatus can be suppressed and noise can be suppressed. In addition, since the external clock input to the imaging device has a low frequency, loss from the previous stage to the CMOS sensor and unnecessary radiation can be suppressed. Thereby, a small, inexpensive and highly reliable camera (moving image, still image) can be made.

  For example, a solid-state image pickup device of VGA (about 300,000 pixels) class is operated at an input clock frequency of 24 MHz, other than the output circuit 28 at 12 MHz or 24 MHz (low speed clock), and a high speed clock of 120 MHz from the single output terminal 5c of the output circuit 28. With CLK3, 10-bit video data D1 can be serially output at a frame rate of 30 fps (frame / s).

  Since most of the imaging devices operate at 12 MHz, the power consumption is hardly affected even at an output rate of 120 MHz. In general, a solid-state imaging device is a very precise analog circuit that cares about noise of 1 mV or less, and in particular, the pixel feels light, and the photoelectrically converted charge is held in the pixel for a certain period of time and then output. However, about 300,000 for the VGA class and millions for the megapixel must be in that order. The severity is the same for the column processing unit 26, and the number is as small as several hundred to several thousand compared to the number of pixels, but the same.

  Therefore, the pixel unit 10 and the column processing unit 26 need to reduce frequency characteristics as much as possible to reduce white noise and operate at a frequency as low as possible to suppress unevenness due to location such as pulse delay. Moreover, as image information to be output, an image of several hundred thousand to several million pixels × 10 bits must be output at several tens to several thousand images / second. In addition, to be installed in small devices such as mobile phones and PDAs (Personal Digital Assistants), we want to make it as small and cheap as possible, so that the number of output terminals is reduced and the burden of connection to the next-stage LSI is reduced. There is a request to do.

  Here, the solid-state imaging device communicates with the outside for switching or checking the output mode, but the amount of data is sufficiently small relative to the output data. In such a solid-state imaging device, the configuration of the present embodiment is such that the input clock is received at a low frequency, the pixel unit 10 and the column processing unit 26 are operated at a low frequency, and only the output circuit 28 is operated at a high frequency. It is valid.

  The high-speed clock CLK3 is output from a terminal (5d in this example) that is different from the data output terminal (5c in this example) while taking into account the delay with the video data D1 as well as the video data D1, so that the outside of the device On the data receiving side, the video data D1 can be taken in synchronization with the high-speed clock CLK3, and an error can be prevented.

  As described above, when the high-speed clock CLK3 is output together with the video data D1, the specifications for the jitter of the high-speed clock CLK3 are relaxed. Therefore, the PLL can be made small. However, in order to avoid the influence of jitter, it is preferable not to use the high-speed clock CLK3 for a portion that handles an analog signal, for example, the pixel unit 10 or the column processing unit 26.

  Note that the video data D1 and the high-speed clock are effectively obtained by adopting a data format in which the clock is embedded in the data (for example, as a synchronization signal) as in the technology used in the field of communication. CLK3 can also be output from a common terminal. By doing so, interface terminals and wiring can be reduced.

  In addition to outputting the high-speed clock CLK3, as shown in FIG. 3B, the video data D1 and the terminals 5c and 5d of the high-speed clock CLK3 are separated from one terminal 5e by one pixel. The boundary data P2 may be output as data having a frequency lower than that of the high-speed clock CLK3. For example, in this example, a clock having the same frequency as the low-speed clock CLK2 indicating the start or end of the 10-bit video data D1 may be output as the boundary data P2.

  This is because if the data is output in the serial format, if the receiving side cannot correctly recognize the data delimiter for one pixel, it cannot be reproduced correctly. If the data rate is several tens of MHz as in the prior art, the possibility of making a mistake is small, but the higher the speed, the more complicated it becomes. To prevent the mistake, it is better to have identification information. That is, if the frequency is low, even if the boundary data P2 is not used, it is possible to ensure a certain degree of tracking on the receiving side, so that one pixel in the serial data can be correctly recognized. Due to instability and the like, there is an increased possibility of missing a break for one pixel. In addition, once a mistake is made, it is carried over to the subsequent pixel data, and the influence is great. Therefore, the effect of using the boundary data P2 having a frequency lower than that of the high-speed clock CLK3 is high.

  The boundary data P2 may be generated by any of the TG block of the communication / timing generation unit 20, the clock conversion unit 21, or a signal processing unit 282 described later, for example. Further, in FIG. 3B, the duty (= high period / 1 period) is 50%, and the data is practically opposite in polarity to the low-speed clock CLK2, but not limited to this, the data is shown in FIG. 3C. As such, the duty may be changed to other than 50%.

<Modification of First Example of Output Circuit>
FIG. 4 is a circuit block diagram showing a modification of the first configuration example of the output circuit. Here, only the vicinity of the output buffer is shown. FIG. 5 is a timing chart showing a data output method in this modification. This modified example is characterized in that n-bit serial output data and high-speed clock CLK3 are differentially output from two output terminals.

  For this reason, as shown in FIG. 5, the output buffer 286 of the output circuit 28 is n (10 in this example) video data expressed in the serial format generated by the switching unit 284 that functions as a parallel-serial conversion unit. Based on D1, it has a function of a differential conversion section for converting into differential format data composed of forward video data D1P having the same polarity as the video data D1 and inverted video data D1N having the reverse polarity. The output buffer 286 having the function of the differential converter has an output terminal 5cP for outputting the normal video data D1P to the outside and an output terminal 5cN for outputting the inverted video data D1N to the outside. As a differential output of the normal video data D1P and the reverse video data D1N, the corresponding two output terminals 5cP and 5cN are individually output to the outside.

  Similarly, an output buffer 288 different from the output buffer 286 has a differential format consisting of a forward high-speed clock CLK3P having the same polarity as the high-speed clock CLK3 received via the switching unit 284 and an inverted high-speed clock CLK3N having the reverse polarity. It has the function of a differential converter that converts data. The output buffer 288 has an output terminal 5dP for outputting the normal high speed clock CLK3P to the outside and an output terminal 5dN for outputting the inverted high speed clock CLK3N to the outside. The output buffer 288 adds the high-speed clock CLK3 input via the switching unit 284 to the high-speed clock CLK3 in consideration of the delay with the video data D1, and the inverted high-speed clock CLK3N with the inverted video data D1N. In consideration of this delay, differential outputs of the high-speed clock CLK3 and the inverted high-speed clock CLK3N are individually output to the outside from the corresponding two output terminals 5dP and 5dN.

  In this way, when data is output at a high-speed clock frequency, as shown in FIG. 3, as shown in FIG. 5, in addition to the method of outputting using only one of the rising edge and falling edge of the high-speed clock, Both the rising and falling edges of the high-speed clock CLK3 can be used. By doing so, it is possible to output at a substantially double frequency (double output rate). Conversely, when the same output rate is used, the frequency of the high-speed clock CLK3 can be halved.

  In this way, each differential output is output from a terminal (5dP, 5dN in this example) different from the data output terminal (5cP, 5cN in this example) while taking into account the delay with the video data D1P, D1N. As a result, on the data receiving side outside the device, the video data D1P and D1N can be taken in synchronization with the corresponding high-speed clocks CLK3P and CLK3N for any of the differential outputs, and errors can be prevented.

<Second Example of Output Circuit>
FIG. 6 is a circuit block diagram showing a second configuration example of the output circuit. FIG. 7 is a circuit block diagram showing a modification of the output circuit of the second example. Here, FIG. 6 shows application to a differential output format, and FIG. 7 shows application to a single output format. FIG. 8 is a diagram for explaining the effect of improving unnecessary radiation by the output circuit 28 of the second example.

  The output circuit 28 of the second example shown in FIG. 6 is characterized in that a digital signal processing unit is taken in and a differential output is used. On the other hand, the modification of the second example shown in FIG. 7 is the same as the second example in that the digital signal processing unit is incorporated therein. This is different from the second example. This will be specifically described below.

  The output circuit 28 of the second example shown in FIG. 6 includes a signal processing unit 282 that performs digital signal processing on 10-bit digital data D0 input from the horizontal signal line 18, a switching unit 284, an output buffer 286, and the like. 288.

  Predetermined data is input to the signal processing unit 282 from the TG block of the communication / timing generation unit 20, and the low-speed clock CLK 2 is input from the clock conversion unit 21. The switching unit 284 receives the high-speed clock CLK3 from the clock conversion unit 21.

  The signal processing unit 282 takes in the pixel data D0 in parallel from the ten horizontal signal lines 18 in synchronization with the low-speed clock CLK2. This is the same as the output circuit 28 of the first example. The signal processing unit 282 performs black level adjustment, column variation correction, signal amplification, color-related processing, or signal compression processing on the captured data D0, for example, using the same low-speed clock CLK2. Then, the processed 10-bit data D1 is input to different input terminals of the switching unit 284 for each bit.

  The switching unit 284 includes a multiplexer (multi-input-1 output changeover switch; details are omitted), and each of a plurality of input terminals 284a of the multiplexer includes a signal from the signal processing unit 282. Data in parallel format is input individually. In addition, any one of the data input to the plurality of input terminals 284a is selected and output from the output terminal 284b. The high-speed clock CLK3 from the clock converter 21 is input to the control terminal 284c of the multiplexer as a switching command. By using the multiplexer having such a configuration as the parallel-serial conversion function unit, parallel-serial conversion can be realized with a simple circuit configuration.

  Using the high-speed clock CLK3 as a switching command, the switching unit 284 having such a configuration selects one bit from 10-bit data input from another terminal according to a predetermined order and outputs it from the output terminal 284b. Thus, the parallel data is converted into serial format data (hereinafter also referred to as parallel-serial conversion). Then, the video data D1 after the parallel-serial conversion is guided to the data output buffer 286. In addition, the switching unit 284 guides the high-speed clock CLK3 used at the time of the parallel-serial conversion to the clock output buffer 288.

  The output buffers 286 and 288 have a function of a differential conversion unit as in the modification of the first example. For example, the output buffer 286 outputs the normal video data D1P and the reverse video data D1N as differential outputs to the outside individually from the corresponding two output terminals 5cP and 5cN. Similarly, the output buffer 288 takes into account the delay with the video data D1 for the high-speed clock CLK3, and takes into account the delay with the inverted video data D1N for the inverted high-speed clock CLK3N. As a differential output of CLK3N, the corresponding two output terminals 5dP and 5dN are individually output to the outside.

  For example, as in the first example, when a VGA (about 300,000 pixels) class solid-state imaging device is operated at an input clock frequency of 24 MHz and other than the output circuit 28 at 12 MHz or 24 MHz (low speed clock), 2 of the output circuit 28 The 10-bit video data D1 can be output serially at a frame rate of 30 fps (frame / s) with a high-speed clock CLK3 of 120 MHz from the two differential output terminals 5cP and 5cN.

  Note that the modification of the second example shown in FIG. 7 is different only in that the output buffers 286 and 288 are single outputs, and therefore the description of the circuit configuration and the operation thereof will be omitted.

  In the output circuit 28 of the second example shown in FIG. 6, as in the first example, the data input to the output circuit 28 is performed in synchronization with the low speed clock CLK2, while the output of the video data D1 is the high speed clock CLK3. It is done synchronously. Further, the high-speed clock is also output as in the first example. Therefore, although there is a difference between single output and differential output, the output circuit 28 of the second example can basically enjoy the same effect as the first example described above.

  In addition, the output circuit 28 of the second example shown in FIG. 6 can enjoy a unique effect due to the differential output. That is, the higher the speed, the more likely abnormal components such as blunting and ringing occur in the pulse waveform, and only one of the single outputs is directly affected. On the other hand, by using the differential output, it becomes possible to reproduce the waveform using both of the differential outputs, so that the noise resistance is improved. This applies not only to the data D1 but also to the high-speed clock CLK3. Therefore, the second example adopting the differential output format has a configuration capable of handling a higher frequency than the configuration of the first example. Conversely, it can be said that the configuration of the first example adopting the single output format can be used as long as the frequency is medium.

  In the configuration of the second example, a mechanism (LVDS; Low Voltage Differential Signaling) that adopts a differential interface in the current mode can be used. This is advantageous for noise resistance and unwanted radiation problems. For example, when a single output current mode interface is adopted as in the configuration of the first example or the modification of the second example shown in FIG. 7, as shown in FIG. Since current flows back and forth between the next-stage circuit and the next-stage IC on the receiving side (the timing is not simultaneous), an electromagnetic field that causes unnecessary radiation is generated each time, and the peripheral circuit or solid-state imaging device 1 is generated. Affects the outside.

  On the other hand, when the current mode interface is used with the differential output using the normal data P and the inverted data N as in the configuration of the second example, as shown in FIG. Although current flows back and forth between a certain output circuit 28 and the next stage circuit or next stage IC on the receiving side, the timing is always the same, and the directions of the generated electromagnetic fields are opposite to each other. Therefore, the electromagnetic fields generated by both of them cancel each other, and it may be considered that the electromagnetic fields that cause unnecessary radiation are not generated. In order to further enhance such an effect, it is preferable to adopt an interface between the output amplifier 28 and an external circuit by bringing two differential output lines close to each other. For this purpose, for example, a connection line having a twisted pair line shape is preferably used.

<Third example of output circuit>
FIG. 9 is a circuit block diagram showing a third configuration example of the output circuit. FIG. 10 is a circuit block diagram showing a modification of the output circuit of the third example. Here, FIG. 10 shows application to a differential output format, and FIG. 11 shows application to a single output format. FIG. 11 is a timing chart showing a data output method in the third example and its modification.

  Here, as in the second example, the output circuit 28 of the third example shown in FIG. 9 takes in the digital signal processing unit and makes it a differential output, and m (m is the m in the column processing unit 26). It is characterized in that n (where n is a positive integer) bits of data corresponding to two or more positive integer) columns can be output simultaneously. On the other hand, the modification of the third example shown in FIG. 10 can simultaneously output the data for m columns in the column processing unit 26 and the point that the digital signal processing unit is incorporated and the differential output is used. However, the third example is different from the third example in that the single output is used as in the modification of the second example. This will be specifically described below.

  Here, as a specific example, there is an example in which there are 40 horizontal signal lines 18 so that data for 10 (= n) bit column AD circuits 4 (= m) columns can be output simultaneously. Show. In this case, a total of 40-bit pixel data D0 is signal-processed by the signal processing unit 282, and is input to the switching unit 284 as four 10-bit data.

  Similarly to the second example, the switching unit 284 includes a multiplexer (not shown), and uses m high-speed clocks CLK4 that are m times as fast as the low-speed clocks CLK2. Are converted into serial format data (hereinafter also referred to as parallel-serial conversion).

  In this example, when the switching unit 284 of the output circuit 28 outputs data based on the high-speed clock CLK4, as shown in FIG. 11, only one of the rising edge and the falling edge of the high-speed clock CLK4 (the rising edge in the figure). In synchronization with the edge), four pieces of data for each bit are converted into serial data. Then, for every 0th to 9th bits, the data D1 after the parallel-serial conversion is led to the output buffers 286-0 to 286-9 for the respective bits. In addition, the switching unit 284 guides the high-speed clock CLK4 used at the time of the parallel-serial conversion to the clock output buffer 288.

  The output buffers 286-0 to 286-9 output from the corresponding two output terminals 5cP and 5cN as differential outputs of the video data D1 and the inverted video data D1N based on the input pixel data D1 of each bit. . Similarly, an output buffer 288 different from the output buffer 286 has two corresponding output terminals 5dP as differential outputs of the high-speed clock CLK4 and the inverted high-speed clock CLK4N with a delay based on the input high-speed clock CLK4. , 5dN.

  Note that the modification of the third example shown in FIG. 10 differs only in that the output buffers 286-0 to 286-9, 288 are single outputs, and therefore the description of the circuit configuration and its operation is omitted.

  Thus, even when the output circuit 28 is configured to handle data for m vertical columns, that is, data corresponding to a plurality of pixels, the signal processing unit 282 that receives data corresponding to a plurality of pixels first performs low speed processing. A plurality of pixels (four pixels in the previous example) are processed in parallel using the clock CLK2, and the data output from the signal processing unit 282 is m times the frequency of the low-speed clock CLK2 in the switching unit 284. If the high-speed clock CLK4 is used to select signals corresponding to one pixel in order and output them at high speed, the function part of the parallel-serial conversion, which is the part that speeds up the output data, is placed in the immediate vicinity of the data output ( In the previous example, it can be arranged in the switching unit 284 and the output buffers 286-0 to 286-9, 288). Therefore, even if it is set as the 3rd example and its modification, the same effect as the composition of the 1st example and the 2nd example can be enjoyed.

<Combination of second and third examples of output circuit>
12 and 13 are circuit block diagrams showing a configuration in which the above-described second and third configuration examples of the output circuit are combined. In any configuration, two stages of switching units 284a and 284b are provided as functional parts for converting to serial format data, but the roles of FIGS. 12 and 13 are different. Both FIG. 12 and FIG. 13 have a differential output configuration as in the second and third configuration examples, but a single output as in the modification examples of the second and third configuration examples. It may be output. This will be specifically described below.

  In the configuration example of FIG. 12, similarly to the third configuration example, first, the switching unit 284a uses the high-speed clock CLK4 to convert the data for m columns into serial-format data for each bit, and thereafter the switching unit. The second configuration example is applied at 284b using the high-speed clock CLK5, and this n-bit parallel data is further converted into serial data. The high-speed clock CLK5 used when the switching unit 284b converts n-bit parallel data into serial-format data is n times the high-speed clock CLK4, that is, m × n times the low-speed clock CLK2. Then, 4 × 10 = 40 times.

  On the other hand, in the configuration example of FIG. 13, first, the second configuration example is applied, and the switching unit 284a uses the high-speed clock CLK3 to serially convert n-bit parallel data for every m columns in the column processing unit 26. This is characterized in that the data is converted into data in the format, and then the third configuration example is applied using the high-speed clock CLK6 in the switching unit 284b to further convert the data for m columns into data in the serial format. The high-speed clock CLK6 used when the switching unit 284b converts m columns of data into serial format data is m times the high-speed clock CLK3, that is, n × m times the low-speed clock CLK2. Then, 10 × 4 = 40 times.

  By adopting such a configuration, even when the output circuit 28 is configured so as to collectively handle data for m vertical columns, all m data that is originally parallel is converted into a serial format. By converting to data and outputting the data, the number of data output terminals can be reduced as compared with the third and modified examples. Further, the function part of the parallel-serial conversion, which is a part for speeding up the output data, can be arranged in the immediate vicinity of the data output (in the previous example, the switching unit 284 and the output buffers 286-0 to 286-9, 288). By doing so, it is possible to enjoy the same effects as the configurations of the first to third examples or the modifications thereof.

<Fourth example of output circuit>
FIG. 14 is a circuit block diagram showing a fourth configuration example of the output circuit 28, where (A) shows an application to a differential output format, and (B) shows an application to a single output format. In the fourth example, the signal processing unit 282 of the second example is slightly changed. Similar changes can be made to the signal processing unit 282 of the third example.

  Here, in the signal processing unit 282 of the second example and the third example, the digital signal processing is performed using the low-speed clock CLK2, but the output circuit 28 of the fourth example is 2 than the low-speed clock CLK2. The difference is that signal processing is performed using a clock having a frequency that is at least twice as high and less than half the frequency of the high-speed clock CLK3 (not necessarily one, but also collectively referred to as a medium-speed clock CLK7). In this case, as shown in the drawing, the signal processing unit 282 may include a functional part that performs predetermined processing using not only the medium speed clock CLK7 but also the low speed clock CLK2. The medium speed clock CLK7 also has a frequency more than twice that of the low speed clock CLK2, and is an example of the high speed clock of the present invention.

  The medium speed clock CLK7 is preferably generated by the clock converter 21. That is, it is assumed that the clock conversion unit 21 generates clocks with different frequencies (CLK3 and CLK5 in this example) that are higher in frequency than the low-speed clock CLK2. As described above, the technique for generating a plurality of frequency clocks having a frequency higher than that of the low-speed clock CLK2 by the single clock conversion unit 21 is based on various known circuits as in the case of generating the single high-speed clock CLK3. A mechanism of a multiplier circuit can be used. For example, when k1 and k2 are multiples of the frequency of the low-speed clock CLK2, a k1 multiplication circuit and a k2 multiplication circuit may be provided. Here, explanation of the specific mechanism is omitted.

  Here, the contents of the signal processing using the low-speed clock CLK2 in the signal processing unit 282 include simple addition / subtraction / multiplication / division for each pixel signal such as digital gain control and vertical stripe correction. On the other hand, the contents of the signal processing using the medium-speed clock CLK7 may require a lot of calculations while referring to the signals of a plurality of pixels, such as color-related processing and compression processing.

When a digital signal processing circuit that operates with the high-speed clock CLK3 is provided in the imaging device, the power consumption of the device increases. On the other hand, when such a digital signal processing circuit is not provided in the device, a similar circuit is provided outside the device. In this case, the power consumption of the entire camera apparatus hardly differs depending on whether the digital signal processing circuit is provided inside the device or outside the device. Rather, there are cases where processing efficiency is better when processing is performed in a device having a strong connection with pixel signals. The fourth example can meet such a demand.

  However, in such a case, it is better to provide a digital signal processing circuit that operates with the high-speed clock CLK3 in the imaging device.However, when the heat generation of the digital signal processing unit in the same chip increases, Since the shading increases, signal processing in the imaging device is not performed here for the processing target range that is not inconvenient even if the medium speed clock CLK7 having a frequency equal to or lower than 1/2 of the high speed clock CLK3 is used. It is assumed that the data is taken into the unit 282.

  That is, in the configuration of the fourth example, even in the signal processing unit 282 other than the final circuit portion (in this example, the output buffers 286 and 288) from which data is output, a clock (in this example) having a higher frequency than the low-speed clock CLK2. Then, the medium speed clock CLK7) is used. Here, the range up to the medium speed clock CLK7 whose frequency is lower than that of the high-speed clock CLK3 is used, but the high-speed clock CLK3 in the frequency range shown in each of the above configuration examples or a frequency higher than this high-speed clock CLK3. This does not exclude the use of the clock in the signal processing unit 282.

<Fifth example of output circuit>
FIG. 15 is a circuit block diagram showing a fifth configuration example of the output circuit. Here, only the vicinity of the output buffer for the differential output method is shown. FIG. 16 is a circuit block diagram showing a configuration example of a strobe data generation unit used in the fifth example. Here, only one of the differential outputs is shown. FIG. 17 is a timing chart showing the data output method in the fifth example. The fifth example is characterized in that strobe data STB capable of reproducing a clock is output by taking an exclusive OR with n-bit output data expressed in a serial format.

  The strobe data STB is used instead of the high-speed clock CLK3. That is, the strobe data STB is output from the terminal 5d. Here, the strobe data STB is a data signal that is inverted at a timing at which the video data D1 is not inverted.

The strobe data STB is generated by the signal processing unit 282 or the switching unit 284 before the output buffer 290. This is output to the outside through an output buffer 290 similar to the output buffer 286. For example, when the signal after serializing provision of strobe signal generation unit, as an example, a result good circuit configuration as shown in FIG. 16.

  In the strobe signal generation unit 300, the parallel-converted data is delayed by one clock with the high-speed clock CLK3 by the D flip-flop 312, and exclusive-OR circuit (NXOR) 314 takes the exclusive OR, The strobe data STB can be generated by putting it in the flip-flop 316.

  At this time, the flip-flop 312 and the T flip-flop 316 (falling edge synchronization) prevent the malfunction of the edge of the high-speed clock CLK3 to be used as shown in the figure. The half clock delay is adjusted by passing serial data through the D flip-flop 306 (falling edge synchronization).

  Then, the serial data and the strobe data STB are passed through D flip-flops 308 (rising edge synchronization) and 318 (falling edge synchronization) that operate at different edges, thereby matching the phases of the two.

  The normal rotation data D1P and STBP output from the normal rotation terminals Q of the D flip-flops 308 and 318 are output to the outside from the normal rotation terminals 5cP and 5dP via the output buffers 286 and 290, respectively. , 318 and the inverted data D1N and STBN output from the inverting terminals 5cN and 5dN via the output buffers 286 and 290, respectively.

  As can be seen from FIG. 5, when the high-speed clock CLK3 is normally output, the timing at which both the high-speed clock CLK3 and the video data D1 are simultaneously inverted may occur. When both are inverted simultaneously, the load applied to the device output is both, and the timing is not constant because it depends on the video data D1.

  On the other hand, if the strobe data STB is used, as can be seen from FIG. 17, either one of the video data D1P and the strobe data STBP or only one of the video data D1N and the strobe data STBN is inverted. The load on the device output at each clock timing is only one load and is constant. Further, by taking an exclusive OR of the strobe data STB and the video data D1, the high-speed clock CLK3 can be reproduced by a circuit block provided at the rear stage of the output circuit 28 or the next stage IC.

  Although the application to the differential output method has been described here, the video data D1 and the strobe data STB are each modified to a configuration that uses only one of normal rotation and inversion, and the first example and Similarly, a single output can be supported.

<Sixth example of output circuit>
FIG. 18 is a circuit block diagram showing a sixth configuration example of the output circuit. Here, only the vicinity of the output buffer for the single output method is shown. FIG. 19 is a timing chart showing the data output method in the sixth example. The sixth example is characterized in that the frequency of the high-speed clock is secured to be equal to or higher than the output of pixel data, and other information is output with the margin.

  For example, as shown in FIGS. 3A and 3B, in each of the above-described examples, the parallel processing is performed within the same period as one cycle of the low-speed clock CLK2 in which the signal processing unit 282 takes in pixel data indicated by 10 bits / parallel. The high-speed clock CLK3 having a frequency several times the number of bits of the low-speed clock CLK2 is used.

  On the other hand, in this sixth example, as shown in FIG. 19, by setting the frequency to be higher than the number of bits, the number of bits for representing the data for one pixel in serial format data (this number) In the example, 10 bits) or more is secured as a data allocation part. In this example, a high-speed clock CLK8 having a frequency 16 times that of the low-speed clock CLK2 is used, thereby securing 16 bits as a whole for each unit. Then, for each unit of the data allocation portion, desired data other than the pixel data is allocated to a margin portion (hereinafter referred to as an additional data portion, which is 6 bits in this example) excluding the number of bits of one pixel. That is, the additional data is substantially embedded for each pixel data.

  For example, the frequency of the high-speed clock is further increased from that of the high-speed clock CLK3, and information other than information derived from the pixels is output. If the data rate is several tens of MHz as in the prior art, the possibility of making a mistake is small, but the higher the speed, the more complicated it becomes. To prevent the mistake, it is better to have identification information.

  The boundary data P2 output from the output buffer 292 is allocated for each unit (16 bits in this example) of the video data D1. The duty may be 50% as shown in FIG. 19 and may be data having a polarity opposite to that of the low-speed clock CLK2, or the duty may be changed to other than 50% as shown in FIG.

  As desired data to be allocated to the additional data portion secured for 6 bits, for example, in the serial output method, data indicating the start or end of a line (that is, data indicating switching of lines) P4, or indicating the start or end of a frame. Data (that is, data indicating frame switching) P5 or the like can be considered. For example, as shown in FIG. 18, the switching unit 284 acquires not only the bit data of the video data D1 but also the data P4 and P5 from the signal processing unit 282. Then, the switching unit 284 embeds the data P4 and P5 as additional data for each pixel data by collecting the bit data of one pixel and the data P4 and P5 into serial data using the high-speed clock CLK8.

  Conventionally, the beginning of a row or the beginning of a frame is input from the outside of the solid-state imaging device, and the signal of the solid-state imaging device is output in synchronization with it, but in the configuration of this embodiment, the frequency of output data is high, It is difficult to synchronize these. Therefore, it is preferable to output data indicating the beginning of a row or the beginning of a frame from the solid-state imaging device. At this time, if different terminals are used, the number of terminals is increased. In this way, output can be performed using the same terminal, and the number of terminals is not increased.

  As another example, when the solid-state imaging device 1 is for color imaging as in the present embodiment, for example, the color filter array changes between an even number column and an odd number column. Thus, it is conceivable to assign identification information indicating which color separation filter (color component) the pixel corresponds to. Further, when performing decimation readout, information indicating how many pixels the decimation operation is skipped and whether or not addition is performed may be assigned. These signals serve as error checks for read mistakes that are likely to occur with high-speed output. In this way, it is possible to check for an error in speeding up without increasing the number of terminals.

  In any case, if the frequency is increased, there is an increased possibility of mistakes in row switching, frame switching, color filter arrangement, and the like due to instability of data reproduction. In addition, once a mistake is made, it is carried over to the subsequent data, and normal images cannot be reproduced, so the effect is great.Therefore, switching between rows and frames, or data indicating a color filter is used as pixel data. The effect of embedding each is high.

  Although the boundary data P2 is also output here, the boundary data P2 may not be used. Here, each data is synchronized with the falling edge of the high-speed clock CLK8. However, the data may be synchronized with the rising edge. In addition, the application to the single output method has been described. However, each of the video data D1 and the strobe data STB is modified to a configuration that uses both normal rotation and inversion, so that the modified example of the first example and other configurations are used. Similar to the example, it can support differential output.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. Various changes or improvements can be added to the above-described embodiment without departing from the gist of the invention, and embodiments to which such changes or improvements are added are also included in the technical scope of the present invention.

  Further, the above embodiments do not limit the invention according to the claims (claims), and all combinations of features described in the embodiments are not necessarily essential to the solution means of the invention. Absent. The embodiments described above include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. Even if some constituent requirements are deleted from all the constituent requirements shown in the embodiment, as long as an effect is obtained, a configuration from which these some constituent requirements are deleted can be extracted as an invention.

  For example, in the above-described embodiment, even when a high-speed clock is used, a portion where high-speed data is output from the imaging device (that is, a circuit portion using the high-speed clock) so that noise and unnecessary radiation can be suppressed. The configuration in which the clock conversion unit 21 is disposed in the vicinity of the pole (the output circuit 28 in the previous example) has been shown. However, for example, if attention is paid only to power consumption and noise and unnecessary radiation need not be considered, The place where the symbol is arranged may be another place. For example, the communication / timing generation unit 20 may be arranged near the communication / timing generation unit 20 or may be integrated with the communication / timing generation unit 20.

  In addition, as an example of using the high-speed clock only in the output side circuit, an example in which the entire one pixel or one pixel and additional data are serialized is shown. However, the present invention is not limited to this. Any configuration may be used as long as output based on the output data is output to the outside with fewer terminals than the number of bits of the AD-converted digital data. For example, a part of one pixel may be converted to serial data, for example, serial data corresponding to 2 bits of the s-th bit and 2s-1 bit. Even in this case, there is an advantage that the output side circuit can be output at high speed with fewer terminals than when all bits are simply output as parallel data.

  In addition, as an example of using the high-speed clock only in the output side circuit, an example of converting to serial data has been shown. However, the use form of the high-speed clock is not limited to serial data. For example, it can be used for motion extraction or compression processing that requires many calculations at high speed.

  In addition, when switching the frequency of the high-speed clock by the frequency switching command P3 from the outside, when the clock converter 21 is configured to generate a plurality of high-speed clocks, a configuration capable of notifying a switching instruction for each frequency, do it.

  In addition, as an example of a solid-state imaging device that can arbitrarily read out signals from individual unit pixels by address control, a CMOS sensor including a pixel portion that generates signal charges by receiving light is shown as an example. However, the generation of signal charges is not limited to light, and can be applied to electromagnetic waves such as infrared rays, ultraviolet rays, or X-rays in general, and a large number of pixels that receive the electromagnetic waves and output an analog signal corresponding to the amount are arranged. The items described in the above embodiment can be applied to an imaging apparatus including a pixel portion.

1 is a schematic configuration diagram of a CMOS solid-state imaging device according to an embodiment of the present invention. It is a figure explaining an example of the device arrangement | positioning form of a clock converter and an output circuit. It is a timing chart which shows an example of a data output system. FIG. 6 is a circuit block diagram showing a modification of the first configuration example of the output circuit. It is a timing chart which shows the data output system in the modification of the 1st example. It is a circuit block diagram which shows the 2nd structural example of an output circuit. It is a circuit block diagram which shows the modification of the output circuit of a 2nd example. It is a figure explaining the improvement effect of the unnecessary radiation by the output circuit of the 2nd example. It is a circuit block diagram which shows the 3rd structural example of an output circuit. It is a circuit block diagram which shows the modification of the output circuit of a 3rd example. It is a timing chart which shows the data output system in the 3rd example and its modification. It is a circuit block diagram which shows the structural example which combined the structural example of the 2nd and 3rd output circuit. It is a circuit block diagram which shows the other structural example which combined the structural example of the 2nd and 3rd output circuit. It is a circuit block diagram which shows the 4th structural example of an output circuit. FIG. 10 is a circuit block diagram showing a modification of the fifth configuration example of the output circuit. It is a circuit block diagram which shows one structural example of the strobe signal generation part used for the 5th example. It is a timing chart which shows the data output system in the 5th example. It is a circuit block diagram which shows the 6th structural example of an output circuit. It is a timing chart which shows the data output system in the 6th example.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Solid-state imaging device, 3 ... Unit pixel, 7 ... Drive control part, 10 ... Pixel part, 12 ... Horizontal scanning circuit, 14 ... Vertical scanning circuit, 15 ... Vertical control line, 18 ... Horizontal signal line, 19 ... Vertical signal Line 20, communication / timing generation unit 21 clock conversion unit 21 26 column processing unit 28 output circuit 282 signal processing unit 284 switching unit 286 288 290 292 output buffer 300: Strobe signal generator

Claims (14)

A pixel unit that has a charge generation unit that generates a signal charge and outputs an analog pixel signal corresponding to the signal charge generated by the charge generation unit;
An AD converter that converts the pixel signal output from the pixel unit into pixel data that is digital data;
A high-speed clock generation unit that generates a high-speed clock that is a pulse having a higher frequency than a basic clock that is a basic pulse corresponding to a drive pulse that drives the pixel unit;
Based on the high-speed clock generated by the high-speed clock generation unit, a data output unit that converts parallel-format pixel data converted into digital data by the AD conversion unit into serial-format output data and outputs the data to the outside Prepared ,
Boundary data indicating a delimiter for one pixel of the output data is output as data having a lower frequency than the high-speed clock.
Solid-state image sensor. The data output unit, based on both edges of rising and falling of the high-speed clock the high speed clock generator has generated, you outputting the output data to the outside
The solid-state imaging device according to 請 Motomeko 1. The high-speed clock generator, k times the basic clock (k is a positive integer of 2 or more) that generates said high-speed clock having a higher frequency
The solid-state imaging device according to 請 Motomeko 1. The high-speed clock generator, that generates the high-speed clock (the k of 2 or more positive integer) k times the basic clock has a higher frequency, and synchronized with the basic clock
The solid-state imaging device according to 請 Motomeko 1. Wherein the high-speed clock generator and the data output unit, in a state where the portion partitioning the both intricate substantially that are disposed on the semiconductor substrate of the solid-state imaging device
The solid-state imaging device according to 請 Motomeko 1. Wherein the high-speed clock generator and the data output unit, that is disposed on the semiconductor substrate of the solid-state imaging device in close proximity region periphery defining the respective
The solid-state imaging device according to 請 Motomeko 1. Having a communication unit that communicates with an external control unit,
The high-speed clock generating unit, based on the frequency switching instruction received the communication unit, Ru switches the frequency of the high-speed clock
The solid-state imaging device according to 請 Motomeko 1. The data output unit, the high-speed clock the high speed clock generator has generated, that have a high-speed clock output unit to be outputted from another terminal and the terminal for outputting the output data to the outside
The solid-state imaging device according to 請 Motomeko 1. The high-speed clock generation unit generates the high-speed clock having a frequency high enough to collectively output the pixel data and additional data that is other information related to the pixel data,
Wherein the data output unit uses the high-speed clock the high speed clock generator has generated, processed and outputted based on the previous SL parallel format of the pixel data and the additional data and the predetermined rule
The solid-state imaging device according to 請 Motomeko 1. The data output unit, using said high-speed the high-speed clock clock generator has generated, and outputs previous SL is converted into data in serial form are collectively and parallel form of the pixel data and the additional data
The solid-state imaging device according to 請 Motomeko 9. The pixel unit has a plurality of the charge generation units in a matrix and outputs the pixel signal for each column for each row.
The additional data, Ru Ah with data indicating the Ri switching of the row
The solid-state imaging device according to 請 Motomeko 10. The pixel unit has a plurality of the charge generation units in a matrix and outputs the pixel signal for each column for each row.
The additional data, the charge generation unit corresponding to the pixel portion arranged in a matrix, Ru Ah with data indicating the Ri switching of frame image is an image for one sheet
The solid-state imaging device according to 請 Motomeko 10. The data output unit includes a differential conversion unit that converts the n-bit data expressed in the received parallel format into differential data composed of forward data having the same polarity and inverted data having the reverse polarity. Have a bit,
Each of the differential conversion unit of the n bits is that having a two output terminals for outputting the forward data and said inverted data to the respective individual external
The solid-state imaging device according to 請 Motomeko 1. The data output unit converts the high-speed clock generated by the high-speed clock generation unit into a differential clock composed of a normal high-speed clock having the same polarity as that of the high-speed clock and an inverted high-speed clock having a reverse polarity, and outputs the clock to the outside Part
In addition to the two data output terminals provided for each of the n bits, the high-speed clock output unit includes two clocks for individually outputting the normal high-speed clock and the reverse high-speed clock to the outside. that having a output terminal
The solid-state imaging device according to 請 Motomeko 13.

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