JP2013197866A - Solid-state imaging device, driving method, and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable suppression of power consumption of an image sensor.SOLUTION: A solid-state image sensor has a pixel area in which a plurality of pixels are arranged in a two-dimensional matrix form, and a plurality of vertical signal lines provided corresponding to a pixel column in the pixel area, and comprises: a reference counter that is provided for each block with a predetermined number of vertical signal lines among the plurality of vertical signal lines as a unit; a difference counter that is provided corresponding to each of the vertical signal lines in the block; and a pixel signal generation unit that generates a digitized pixel signal by adding a count value of the reference counter and a count value of the difference counter.

Description

  The present technology relates to an individual imaging device, a driving method, and an electronic device, and more particularly, to an individual imaging device, a driving method, and an electronic device that can suppress power consumption of an image sensor.

  In recent years, CMOS image sensors have been widely used as image sensors.

  Conventionally, in a CMOS image sensor, a column ADC (Analog-to-Digital Converter) is often used. The column ADC is an AD conversion circuit provided for each column of pixels arranged in a two-dimensional matrix in the pixel array of the CMOS image sensor.

  In the column ADC, a comparator that compares an analog signal obtained from a pixel in a selected row with a reference voltage is provided for each vertical signal line provided corresponding to a pixel column arranged in the pixel array. A counter that counts the clock in response to the output of the comparator and a memory that holds the count value are provided.

  As a result, for example, clock pulses until the magnitude relationship between the analog signal obtained from the pixel in the selected row and the reference voltage is inverted are counted, held as digital data, and output as a pixel signal. .

  The analog signal output from each pixel is converted into an N-bit digital signal by the ADC configured as described above (see, for example, Patent Document 1).

JP-A-2005-278135

  However, since the conventional column ADC needs to be provided with a counter for each vertical signal line, power for driving these counters is also required.

  The conventional column ADC tends to increase the power consumption of the entire CMOS image sensor because the counters of each column operate simultaneously at the same time. For example, if the number of pixel columns in the pixel array is 1000, when relatively high illuminance light is received by the entire light receiving surface, 1000 counters continue to count for a long time at the same time. Will increase.

  The present technology is disclosed in view of such a situation, and enables the power consumption of the image sensor to be suppressed.

  A first aspect of the present technology includes a pixel region in which a plurality of pixels are arranged in a two-dimensional matrix, and a plurality of vertical signal lines provided corresponding to the pixel columns of the pixel region. A reference counter provided for each block having a predetermined number of vertical signal lines as a unit, a difference counter provided corresponding to each of the vertical signal lines in the block, and the reference counter And a pixel signal generation unit that generates a digitized pixel signal by adding the count value of the difference counter and the count value of the difference counter.

  A comparison unit that is provided corresponding to each of the plurality of vertical signal lines and compares a voltage value output from each of the plurality of pixels with a reference voltage; and a clock pulse according to an output from the comparison unit And a counter clock control unit that supplies the reference counter to one of the reference counter of the block or the plurality of difference counters in the block.

  A comparator that is provided corresponding to each of the plurality of vertical signal lines and compares a voltage value output from each of the plurality of pixels with a reference voltage; and the reference counter has a predetermined count In the period, until one of the comparison units corresponding to each of the vertical signal lines in the block detects that the magnitude relationship between the voltage value output from the pixel and the reference voltage has been determined. A clock pulse is counted during a reference period, and each of the difference counters outputs a voltage output from the pixel by each of the other comparison units in the block after the reference period in a predetermined count period. Clock pulses can be counted during a difference period until it is detected that the magnitude relationship between the value and the reference voltage is determined.

  A reference memory for storing count values by the reference counter of the block, a plurality of difference memories for storing count values by the plurality of difference counters in the block, and data stored in the reference memory for the pixels The pixel signal generation further comprises: a reference bus composed of one signal line for transferring to the signal generating unit; and a differential bus consisting of a plurality of signal lines for transferring data stored in the difference memory The unit may include a buffer for storing data transferred serially via the reference bus.

  In parallel with the period in which each of the data stored in the difference memory in the block is transferred in parallel via the difference bus, the data transferred as the count value by the reference counter of the immediately following block is the reference It can be transferred serially via the bus.

  A first aspect of the present technology includes a pixel region in which a plurality of pixels are arranged in a two-dimensional matrix, and a plurality of vertical signal lines provided corresponding to the pixel columns of the pixel region. A reference counter provided for each block having a predetermined number of vertical signal lines as a unit, and a differential counter provided corresponding to each of the vertical signal lines in the block. In the driving method, a digitized pixel signal is generated by adding a count value of the reference counter and a count value of the difference counter by a signal generation unit.

  A second aspect of the present technology includes a pixel region in which a plurality of pixels are arranged in a two-dimensional matrix, and a plurality of vertical signal lines provided corresponding to the pixel columns of the pixel region, A reference counter provided for each block having a predetermined number of vertical signal lines as a unit, a difference counter provided corresponding to each of the vertical signal lines in the block, and the reference counter And a pixel signal generation unit that generates a digitized pixel signal by adding the count value of the difference counter and the count value of the difference counter.

  In the first aspect and the second aspect of the present technology, a predetermined number of the plurality of vertical signal lines provided corresponding to the pixel columns in the pixel region in which the plurality of pixels are arranged in a two-dimensional matrix form. It is digitized by adding the count value of the reference counter provided for each block with the vertical signal line as a unit and the count value of the difference counter provided for each of the vertical signal lines in the block. A pixel signal is generated.

  According to the present technology, power consumption of the image sensor can be suppressed.

It is a block diagram which shows the structural example of the solid-state image sensor to which this technique is applied. It is a figure explaining the detailed structure of a CNT clock control part. It is a figure explaining another detailed structure of a CNT clock control part. It is a block diagram which shows another structural example of the solid-state image sensor to which this technique is applied. FIG. 5 is a block diagram illustrating an internal configuration example of a signal processing unit in FIG. 4. 6 is a timing chart illustrating data transfer timing on a signal line connected to the signal processing unit illustrated in FIG. 5. It is a block diagram showing an example of composition of an imaging device as electronic equipment to which this art is applied.

  Hereinafter, embodiments of the technology disclosed herein will be described with reference to the drawings.

  FIG. 1 is a block diagram illustrating a configuration example of a solid-state imaging device to which the present technology is applied. The solid-state imaging device 10 shown in the figure is configured as a CMOS image sensor, for example.

  The CMOS image sensor 10 shown in FIG. 1 includes a pixel array 11, a column ADC 12, a vertical scanning circuit 13, a horizontal scanning circuit 14, a timing control circuit 15, DACs 16, SA 17, and a signal processing unit 18.

  In the pixel array 11, a plurality of unit pixels 2 are arranged in a two-dimensional matrix. For example, unit pixels 2 are arranged in n rows and m columns, and in FIG. 1, the unit pixels 2 are described by small squares. Each unit pixel 2 arranged in the pixel array 11 receives light and performs photoelectric conversion, thereby outputting a voltage value corresponding to the amount of received light.

  A vertical signal line is provided corresponding to each column of unit pixels 2 arranged in a matrix in the pixel array 11. In the example of FIG. 1, vertical signal lines 21-1 to 21-m are provided corresponding to each column of the unit pixels 2.

  The column ADC 12 is internally divided into a plurality of blocks. In this example, it is assumed that the inside of the column ADC 12 is divided into p blocks. In FIG. 1, blocks 30-1 and 30-p are described by rectangular dotted lines, and the description of other blocks is omitted, but the respective blocks are configured in the same manner.

  The blocks 30-1 to 30-p are provided corresponding to q vertical signal lines, respectively.

  The block 30-1 is provided with comparators 31-1-1 to 31-1-q. The comparators 31-1-1 through 31-1-q compare the analog signal voltage supplied via the vertical signal lines 21-1 through 21-q with the reference voltage supplied from the DAC 16, respectively. To do.

  The outputs of the comparators 31-1-1 through 31-1-q have initial values of “H”, and the analog signal voltages supplied via the vertical signal lines 21-1 through 21-q When the magnitude relationship of the reference voltage supplied from the DAC 16 is inverted, the reference voltage changes to “L”.

  The block 30-1 is provided with a CNT clock control unit 32-1. The CNT clock control unit 32-1 switches the supply destination of the clock signal supplied from the timing control circuit 15 based on the outputs of the comparators 31-1-1 to 31-1-q. That is, the CNT clock control unit 32-1 supplies the clock signal supplied from the timing control circuit 15 to any one of the difference CNT 33-1-1 to the difference CNT 33-1-q or the reference CNT 36-1. Switch.

  Details of the CNT clock control unit 32-1 will be described later.

  Each of the difference CNT 33-1-1 to the difference CNT 33-1-q counts pulses of the clock signal supplied from the CNT clock control unit 32-1.

  The reference CNT 36-1 counts pulses of the clock signal supplied from the CNT clock control unit 32-1.

  The block 30-1 includes adders 34-1-1 to 34-1-q. The adders 34-1-1 to 34-1-q add the count values of the reference CNT 36-1 and the count values of the difference CNT 33-1-1 to the difference CNT 33-1-q. Yes. For example, when the counting of the reference CNT 36-1 is finished and the counting of each of the difference CNT 33-1-1 to the difference CNT 33-1-q is finished, both count values are added.

  The memories 35-1-1 to 35-1-q store the added values output from the adders 34-1-1 to 34-1-q, respectively. The memories 35-1-1 to 35-1-q update and store the addition values output from the adders 34-1-1 to 34-1-q at the timing when the switches are connected.

  Although not shown here, the block 30-2 on the right side of the block 30-1 includes comparators 31-2-1 to 31-1-q... Memory 35-2-1. Thru / or memory 35-2-q. The block 30-p is provided with comparators 31-p-1 to 31-pq... Memory 35-p-1 to memory 35-pq.

  FIG. 2 is a diagram illustrating a detailed configuration of the CNT clock control unit 32-1.

  As shown in FIG. 2, the outputs of the comparators 31-1-1 to 31-1-q are input to the OR gate 41-1 via the inverter. In this case, when all the outputs of the comparators 31-1-1 to 31-1-q are “H”, the output of the OR gate 41-1 becomes “L”, and the comparators 31-1-1 to 31-31. When any of the outputs of -1-q is “L”, the output of the OR gate 41-1 becomes “H”. In other words, the OR gate 41-1 does not change until the magnitude relationship between the voltage of the analog signal supplied via the vertical signal line 21-1 to the vertical signal line 21-q and the reference voltage supplied from the DAC 16 is inverted. The output becomes “L”.

  The output of the OR gate 41-1 is supplied as an enable signal for the reference CNT 36-1. The reference CNT 36-1 counts pulses of the clock signal (CLK) only during a period when the enable signal is “L”.

  The output of the OR gate 41-1 is input to the AND gate 42-1 together with the clock signal. Therefore, during the period when the output of the OR gate 41-1 is “H”, the pulse of the clock signal is supplied to the difference CNT33-1-1 to the difference CNT33-1-q via the AND gate 42-1. On the other hand, during the period when the output of the OR gate 41-1 is “L”, the pulse of the clock signal is not supplied to the difference CNT33-1-1 to the difference CNT33-1-q via the AND gate 42-1.

  That is, with the configuration of FIG. 2, any one of the magnitude relationships between the voltage of the analog signal supplied via the vertical signal line 21-1 to the vertical signal line 21-q and the reference voltage supplied from the DAC 16 is reversed. During the period, the reference CNT 36-1 counts pulses of the clock signal. During this time, the difference CNT 33-1-1 to the difference CNT 33-1-q do not count clock signal pulses.

  On the other hand, if one of the magnitude relationships between the voltage of the analog signal supplied via the vertical signal line 21-1 to the vertical signal line 21-q and the reference voltage supplied from the DAC 16 is inverted, the difference CNT33-1-1 to Each of the differences CNT33-1-q counts the pulses of the clock signal. During this time, the reference CNT 36-1 does not count clock signal pulses.

  As described above, the count of the clock signal pulse until the magnitude relationship between the voltage of the analog signal supplied via the vertical signal line in the block 30-1 and the reference voltage is inverted is determined by the reference CNT 36-1. Done. By doing in this way, it becomes possible to reduce a power consumption compared with the case where count operation is simultaneously performed by all the difference CNT33-1-1 thru | or difference CNT33-1-q.

  In addition, the pulse count of the clock signal after the magnitude relationship between the voltage of the analog signal supplied via the vertical signal line in the block 30-1 and the reference voltage is inverted is the difference CNT33-1-1 to the difference CNT33. -1-q. Then, each of the count values of the difference CNT 33-1-1 to the difference CNT 33-1-q and the count value of the reference CNT 36-1 are added by the adder 34-1-1 to the adder 34-1-q. . By doing so, it is possible to correctly AD convert the analog signal output from each unit pixel.

  The reference CNT 36-1 and the difference CNT 33-1-1 to the difference CNT 33-1-q count pulses of the clock signal in a predetermined count period (so-called P-phase period or D-phase period). It is made like that.

  Note that the CNT clock control unit 32-1 is controlled by inverting the polarity of the outputs of the comparators 31-1-1 to 31-1-q shown in FIG. 2 and inverting the clock enable polarity of each difference CNT. It is also possible to configure as shown in FIG.

  FIG. 3 is a diagram for explaining another detailed configuration of the CNT clock control unit 32-1. In other words, the CNT clock control unit can be configured as shown in FIG. 3 without providing an inverter as in the CNT clock control unit shown in FIG.

  Here, the configuration in the block 30-1 has been described in detail, but the blocks 30-2 to 30-p are configured similarly.

  Returning to FIG. 1, the vertical scanning circuit 13 includes, for example, a shift register, selects a pixel drive wiring, applies a pulse for driving a unit pixel connected to the selected pixel drive wiring, To drive the unit pixel. That is, the vertical scanning circuit 13 selectively scans each unit pixel arranged in the pixel array 11 sequentially in the vertical direction in units of rows.

  The horizontal scanning circuit 14 is composed of, for example, a shift register, and sequentially selects horizontal memories 35-1-1 to 35-pq by sequentially outputting horizontal scanning pulses, and the pixel signals are converted into sense amplifiers. (SA) 17 to output to the signal processing unit 18.

  The signal processing unit 18 performs predetermined processing on the pixel signals supplied from the memories 35-1-1 to 35-pq, generates image data, and outputs the image data. Yes.

  The timing control circuit 15 outputs a pixel driving pulse for driving each unit pixel arranged in the pixel array 11, thereby controlling the vertical scanning circuit 13 and the horizontal scanning circuit 14. The timing control circuit 15 generates a clock signal and supplies it to the column ADC 12.

  Since the CMOS image sensor 10 to which the present technology is applied is configured as described above, power consumption can be reduced as described above. In particular, the column ADC 12 is divided into blocks 30-1 to 30-p, and the reference CNT 36-1 to the reference CNT 36-p are provided for each block. Can be used.

  Usually, the intensity of light received by adjacent unit pixels is often almost the same, and a counting operation is performed by each difference CNT by forming a block by combining a plurality of adjacent unit pixels. Time can be shortened. That is, it can be said that the power saving effect is higher as the time ratio in which the counting operation by the reference CNT is performed becomes longer than the counting operation by each difference CNT.

  FIG. 4 is a block diagram illustrating another configuration example of the solid-state imaging element to which the present technology is applied. The solid-state imaging device 10 shown in the figure is configured as a CMOS image sensor, for example.

  FIG. 4 is a diagram corresponding to FIG. 1, and each part corresponding to FIG. 1 is denoted by the same reference numeral. 4 includes a pixel array 11, a column ADC 12, a vertical scanning circuit 13, a horizontal scanning circuit 14, a timing control circuit 15, DACs 16, SA17, and a signal processing unit 18, as in FIG. It is configured.

  In the configuration of FIG. 4, unlike the case of FIG. 1, the adder 34-1-34-1-q is not provided in the column ADC. In the configuration of FIG. 4, unlike the case of FIG. 1, the reference CNT 36-1 is connected to the memory 35-1-0 via the switch, and the difference CNT 33-1-1 to the difference CNT 33-1-q are changed. The switches are connected to the memories 35-1-1 to 35-1-q through switches.

  When the CMOS image sensor 10 is configured as shown in FIG. 4, each of the count values of the difference CNT 33-1-1 to the difference CNT 33-1-q and the count value of the reference CNT 36-1 is added to the signal processing unit 18. Done in

  That is, each of the count values of the difference CNT 33-1-1 to the difference CNT 33-1-q is transferred to the signal processing unit 18 via the difference CNT data transfer bus 51. Further, the count value of the reference CNT 36-1 is transferred to the signal processing unit 18 via the reference CNT data transfer bus 52. Then, inside the signal processing unit 18, both count values are added in advance to obtain a pixel signal, and predetermined processing is performed on the pixel signal to generate image data.

  FIG. 5 is a block diagram illustrating an internal configuration example of the signal processing unit 18 when the CMOS image sensor 10 is configured as illustrated in FIG. 4. In this example, a buffer 61, an addition processing unit 62, and a normal signal processing unit 63 are provided inside the signal processing unit 18.

  The differential CNT data transfer bus 51 is configured to transfer bit strings in parallel. The differential CNT data transfer bus 51 has, for example, k signal lines corresponding to each bit of the k-bit count value stored in each of the memories 35-1-1 to 35-1-q, and a sense amplifier 17 is connected to the addition processing unit 62 of the signal processing unit 18.

  The reference CNT data transfer bus 52 is configured to serially transfer a bit string. The reference CNT data transfer bus 52 transfers, for example, the s-bit count value stored in the memory 35-1-0 by one signal line, and the buffer 61 of the signal processing unit 18 is passed through the sense amplifier 17. Connected to. The buffer 61 accumulates s bits of data transferred via the reference CNT data transfer bus 52, and supplies the data to the addition processing unit 62 via s signal lines corresponding to each bit of the data.

  The addition processing unit 62 adds the data supplied via the sense amplifier 17 and the data supplied from the buffer 61. The data added by the addition processing unit 62 is supplied to the normal signal processing unit 63 as pixel signal data having a predetermined number of bits.

  The normal signal processing unit 63 performs predetermined processing on the pixel signal data supplied from the addition processing unit 62 to generate image data.

  FIG. 6 is a timing chart for explaining the data transfer timing on the signal line connected to the signal processing unit 18 shown in FIG. In the figure, the horizontal axis represents time, and the data of the first bit signal line to the kth bit signal line of the differential CNT data transfer bus 51 are shown in order from the top in the vertical direction. Data on the signal line of the reference CNT data transfer bus 52 is shown.

  In FIG. 6, a frame 101 indicated by a dotted line represents a first block data transfer period, and a frame 102 indicated by a dotted line represents a second block data transfer period. Here, the first block data transfer period is, for example, a period for transferring data stored in the memories 35-1-1 to 35-1-q included in the block 30-1 of FIG. Is done. Further, the second block data transfer period is, for example, a period for transferring data stored in the memory 35-2-1 to 35-2-q included in the block 30-2.

  In the first block data transfer period, first, s-bit data is transferred serially on the signal line of the reference CNT data transfer bus 52. As described above, the data transferred through the reference CNT data transfer bus 52 is accumulated in the buffer 61 and supplied to the addition processing unit 62.

  When the transfer of the s-bit data on the signal line of the reference CNT data transfer bus 52 is completed, the data of the first bit signal line to the data of the k-th bit signal line of the differential CNT data transfer bus 51 are transferred in parallel. Is done. On the signal line of the differential CNT data transfer bus 51, for example, k-bit data stored in the memory 35-1-1 is transferred, and then k-bit data stored in the memory 35-1-2 is transferred. Thereafter, k-bit data stored in the memory 35-1-q is transferred. In FIG. 6, the data stored in the memory 35-1-1, the memory 35-1-2, the memory 35-1-3,. Shown as column 3,... Column q.

  The addition processing unit 62 converts the data stored in the buffer 61 in advance into k-bit data corresponding to column 1, k-bit data corresponding to column 2, k-bit data corresponding to column 3,. Add to each of k-bit data corresponding to column q.

  That is, since the data accumulated in the buffer 61 in the first block data transfer period is a count value by the reference CNT 36-1, the count value of the difference CNT 33-1-1 (k-bit data corresponding to the column 1) ). Also, the count value based on the reference CNT 36-1 (data accumulated in the buffer 61 in the first block data transfer period) is set to the count value of the difference CNT 33-1-2 (k-bit data corresponding to the column 2). Is also added. In this way, the count value based on the reference CNT 36-1 is added to the count values of the difference CNT 33-1-1 to the difference CNT 33-1-q.

  Also in the second block data transfer period, s-bit data is first transferred serially on the signal line of the reference CNT data transfer bus 52. However, as shown in FIG. 6, in the first block data transfer period, before the data transfer of the differential CNT data transfer bus 51 ends, the reference CNT data transfer bus in the second block data transfer period. 52 data transfer has started. That is, when the data transfer of the differential CNT data transfer bus 51 is completed in the first block data transfer period, the data transfer of the reference CNT data transfer bus 52 in the second block data transfer period is also completed. Yes.

  As described above, the data transferred via the reference CNT data transfer bus 52 is accumulated in the buffer 61. As shown in FIG. 6, by transferring the data of the reference CNT data transfer bus 52 in parallel with the transfer of the data of the differential CNT data transfer bus 51 of the immediately preceding block, so to speak, the count value by the reference CNT 36-1 Can be read ahead.

  By doing in this way, the addition process in the addition process part 62 can be performed more efficiently, and the processing speed of the CMOS image sensor 10 can be increased.

  Further, as described above, the differential CNT data transfer bus 51 is configured by a plurality of signal lines corresponding to each of a plurality of bits, and the reference CNT data transfer bus 52 is configured by a single signal line. It is also possible to reduce the total number of signal lines compared to the configuration. For example, each difference CNT provided in the column ADC to which the present technology is applied only needs to count the clock pulse after the counting by the reference CNT is completed. It can be expressed by a smaller number of bits than the count value by the counter. Therefore, by appropriately designing the reference CNT, difference CNT, memory, etc., the number of bits of data stored in each memory can be reduced, and as a result, the total number of signal lines can be reduced. .

  Of course, in the case of the configuration of FIG. 4 as well, in the same way as in the case of FIG.

  In addition, this technique is not restricted to application to a solid-state image sensor like a CMOS image sensor, for example. That is, the present technology is applied to an image capturing unit (photoelectric conversion unit) such as an imaging device such as a digital still camera or a video camera, a portable terminal device having an imaging function, or a copying machine using a solid-state imaging device as an image reading unit. The present invention can be applied to all electronic devices using a solid-state image sensor. The solid-state image sensor may be formed as a single chip, or may be a form in which a plurality of chips are stacked or adjacent to each other, or the image pickup unit and the signal processing unit or optical system are packaged together. It may be in the form of a module having a captured imaging function.

  FIG. 7 is a block diagram illustrating a configuration example of an imaging apparatus as an electronic apparatus to which the present technology is applied.

  An imaging apparatus 600 in FIG. 7 includes an optical unit 601 including a lens group, a solid-state imaging device (imaging device) 602 that employs each configuration of the pixel 2 described above, and a DSP circuit 603 that is a camera signal processing circuit. The imaging apparatus 600 also includes a frame memory 604, a display unit 605, a recording unit 606, an operation unit 607, and a power supply unit 608. The DSP circuit 603, the frame memory 604, the display unit 605, the recording unit 606, the operation unit 607, and the power supply unit 608 are connected to each other via a bus line 609.

  The optical unit 601 captures incident light (image light) from a subject and forms an image on the imaging surface of the solid-state imaging device 602. The solid-state imaging device 602 converts the amount of incident light imaged on the imaging surface by the optical unit 601 into an electrical signal for each pixel and outputs the electrical signal as a pixel signal. As the solid-state imaging device 602, a solid-state imaging device such as the CMOS image sensor 10 according to the above-described embodiment, that is, a solid-state imaging device capable of realizing imaging without distortion by global exposure can be used.

  The display unit 605 includes a panel type display device such as a liquid crystal panel or an organic EL (Electro Luminescence) panel, and displays a moving image or a still image captured by the solid-state image sensor 602. The recording unit 606 records a moving image or a still image captured by the solid-state imaging device 602 on a recording medium such as a video tape or a DVD (Digital Versatile Disk).

  The operation unit 607 issues operation commands for various functions of the imaging apparatus 600 under the operation of the user. The power supply unit 608 appropriately supplies various power sources serving as operation power sources for the DSP circuit 603, the frame memory 604, the display unit 605, the recording unit 606, and the operation unit 607 to these supply targets.

  As described above, by using the CMOS image sensor 10 according to the above-described embodiment as the solid-state imaging device 602, the second pixel signal can be extracted without performing signal addition. Since the reset noise can be accurately removed also when extracting the pixel signal, the captured image is captured by the imaging device 600 such as a video camera, a digital still camera, or a camera module for a mobile device such as a mobile phone. Image quality can be improved.

  In the above-described embodiment, the case where the present invention is applied to a CMOS image sensor in which unit pixels that detect signal charges corresponding to the amount of visible light as physical quantities are arranged in a matrix has been described as an example. However, the present technology is not limited to application to a CMOS image sensor, and can be applied to all column-type solid-state imaging devices in which a column processing unit is arranged for each pixel column of a pixel array unit.

  In addition, the present technology is not limited to application to a solid-state imaging device that senses the distribution of the amount of incident light of visible light and captures it as an image. Applicable to imaging devices and, in a broad sense, solid-state imaging devices (physical quantity distribution detection devices) such as fingerprint detection sensors that detect the distribution of other physical quantities such as pressure and capacitance and capture images as images. is there.

  Note that the series of processes described above in this specification includes processes that are performed in parallel or individually even if they are not necessarily processed in time series, as well as processes that are performed in time series in the order described. Is also included.

  The embodiments of the present technology are not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present technology.

  In addition, this technique can also take the following structures.

(1)
A pixel region in which a plurality of pixels are arranged in a two-dimensional matrix, and a plurality of vertical signal lines provided corresponding to the pixel columns of the pixel region;
A reference counter provided for each block having a predetermined number of vertical signal lines as a unit among the plurality of vertical signal lines;
A differential counter provided corresponding to each of the vertical signal lines in the block;
A solid-state imaging device comprising: a pixel signal generation unit that generates a digitized pixel signal by adding the count value of the reference counter and the count value of the difference counter.
(2)
A comparison unit that is provided corresponding to each of the plurality of vertical signal lines and compares a voltage value output from each of the plurality of pixels with a reference voltage;
The counter clock control unit that further supplies a clock pulse to either the reference counter of the block or the plurality of difference counters in the block according to an output from the comparison unit. Individual image sensor.
(3)
A comparator that is provided corresponding to each of the plurality of vertical signal lines and compares a voltage value output from each of the plurality of pixels with a reference voltage;
The reference counter has a magnitude relationship between a voltage value output from the pixel and a reference voltage by one of the comparators corresponding to each of the vertical signal lines in the block in a predetermined count period. Count clock pulses for a reference period until it is detected that
Each of the difference counters determines the magnitude relationship between the voltage value output from the pixel and the reference voltage by each of the other comparison units in the block after the reference period in a predetermined count period. The individual image pickup device according to (1) or (2), wherein a clock pulse is counted during a difference period until it is detected.
(4)
A reference memory for storing count values by the reference counter of the block, and a plurality of difference memories for respectively storing count values by the plurality of difference counters in the block;
It consists of a reference bus consisting of one signal line for transferring data stored in the reference memory to the pixel signal generator, and a plurality of signal lines for transferring data stored in the difference memory A differential bus,
The pixel signal generator is
The solid-state imaging device according to any one of (1) to (3), further including a buffer that stores data transferred serially via the reference bus.
(5)
In parallel with the period in which each of the data stored in the difference memory in the block is transferred in parallel via the difference bus, the data transferred as the count value by the reference counter of the immediately following block is the reference The individual imaging device according to (4), which is transferred serially via a bus.
(6)
A pixel region in which a plurality of pixels are arranged in a two-dimensional matrix, and a plurality of vertical signal lines provided corresponding to the pixel columns of the pixel region;
A reference counter provided for each block having a predetermined number of vertical signal lines as a unit among the plurality of vertical signal lines;
A differential counter provided corresponding to each of the vertical signal lines in the block,
A driving method in which a pixel signal generation unit generates a digitized pixel signal by adding the count value of the reference counter and the count value of the difference counter.
(7)
A pixel region in which a plurality of pixels are arranged in a two-dimensional matrix, and a plurality of vertical signal lines provided corresponding to the pixel columns of the pixel region;
A reference counter provided for each block having a predetermined number of vertical signal lines as a unit among the plurality of vertical signal lines;
A differential counter provided corresponding to each of the vertical signal lines in the block;
An electronic apparatus comprising an individual imaging device having a pixel signal generation unit that generates a digitized pixel signal by adding the count value of the reference counter and the count value of the difference counter.

  10 CMOS image sensor, 11 pixel array, 12 column ADC, 13 vertical scanning circuit, 14 horizontal scanning circuit, 15 timing control circuit, 16 DAC, 18 signal processing unit, 30-1 block, 30-p block, 31-1- 1 to 31-1-q comparator, 32-1 CNT clock control unit, 33-1-1 to 33-1-q differential CNT, 34-1-1 to 34-1-q adder, 35-1-1 Thru 35-1-q memory, 51 differential CNT data transfer bus, 52 reference CNT data transfer bus, 600 imaging device, 602 individual imaging device

Claims (7)

A pixel region in which a plurality of pixels are arranged in a two-dimensional matrix, and a plurality of vertical signal lines provided corresponding to the pixel columns of the pixel region;
A reference counter provided for each block having a predetermined number of vertical signal lines as a unit among the plurality of vertical signal lines;
A differential counter provided corresponding to each of the vertical signal lines in the block;
A solid-state imaging device comprising: a pixel signal generation unit that generates a digitized pixel signal by adding the count value of the reference counter and the count value of the difference counter. A comparison unit that is provided corresponding to each of the plurality of vertical signal lines and compares a voltage value output from each of the plurality of pixels with a reference voltage;
2. The counter clock controller according to claim 1, further comprising: a counter clock controller that supplies a clock pulse to either the reference counter of the block or a plurality of the differential counters in the block according to an output from the comparator. Individual image sensor. A comparator that is provided corresponding to each of the plurality of vertical signal lines and compares a voltage value output from each of the plurality of pixels with a reference voltage;
The reference counter has a magnitude relationship between a voltage value output from the pixel and a reference voltage by one of the comparators corresponding to each of the vertical signal lines in the block in a predetermined count period. Count clock pulses for a reference period until it is detected that
Each of the difference counters determines the magnitude relationship between the voltage value output from the pixel and the reference voltage by each of the other comparison units in the block after the reference period in a predetermined count period. The solid-state imaging device according to claim 1, wherein clock pulses are counted during a difference period until it is detected. A reference memory for storing count values by the reference counter of the block, and a plurality of difference memories for respectively storing count values by the plurality of difference counters in the block;
It consists of a reference bus consisting of one signal line for transferring data stored in the reference memory to the pixel signal generator, and a plurality of signal lines for transferring data stored in the difference memory A differential bus,
The pixel signal generator is
The solid-state imaging device according to claim 1, further comprising a buffer that accumulates data serially transferred via the reference bus. In parallel with the period in which each of the data stored in the difference memory in the block is transferred in parallel via the difference bus, the data transferred as the count value by the reference counter of the immediately following block is the reference The solid-state image sensor according to claim 4, which is serially transferred via a bus. A pixel region in which a plurality of pixels are arranged in a two-dimensional matrix, and a plurality of vertical signal lines provided corresponding to the pixel columns of the pixel region;
A reference counter provided for each block having a predetermined number of vertical signal lines as a unit among the plurality of vertical signal lines;
A differential counter provided corresponding to each of the vertical signal lines in the block,
A driving method in which a pixel signal generation unit generates a digitized pixel signal by adding the count value of the reference counter and the count value of the difference counter. A pixel region in which a plurality of pixels are arranged in a two-dimensional matrix, and a plurality of vertical signal lines provided corresponding to the pixel columns of the pixel region;
A reference counter provided for each block having a predetermined number of vertical signal lines as a unit among the plurality of vertical signal lines;
A differential counter provided corresponding to each of the vertical signal lines in the block;
An electronic apparatus comprising an individual imaging device having a pixel signal generation unit that generates a digitized pixel signal by adding the count value of the reference counter and the count value of the difference counter.

Images