JP2008040723A - Memory controller, flash memory system using memory controller and control method of flash memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide address management for converting the LBN of logical blocks included in the same logical zone to the PBA of physical blocks included in a physical zone comprising the physical blocks inside the same plane. <P>SOLUTION: A PBA' in which a PZIBN is connected below a PZN is generated and the PBA' is converted to the PBA. When the number of the physical blocks included in each physical zone is M (M=2<SP>n</SP>), in the conversion processing, the (n+1)-th bit from the last of the PBA' is moved to the least significant bit. Since the (n+1)-th bit from the last of the PBA' corresponds to the least significant bit of the PZN, by moving the (n+1)-th bit from the last to the least significant bit, the physical zone for the PZN having the even number of bits is constituted of the physical blocks within the plane #0 and the physical zone for the PZN having the odd number of bits is constituted of the physical blocks within the plane #1. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a memory controller, a flash memory system including the memory controller, and a flash memory control method. More specifically, the present invention relates to a memory controller that controls access to a flash memory having a two-plane writing function, a flash memory system including the memory controller, and a flash memory control method.

  In recent years, flash memories have been widely adopted as semiconductor memories used in memory systems such as memory cards and silicon disks. A flash memory is a kind of nonvolatile memory. Data stored in the flash memory is required to be retained even when power is not supplied.

  By the way, the flash memory used in the apparatus as described above includes a page that is a unit of reading and writing and a block that is a unit of erasing processing including a plurality of pages. In addition, since data cannot be overwritten in this flash memory, in order to write new data different from this to a page in which data has already been written, once the data already written is erased, new data is written. A process of writing is required.

  However, as described above, erasure is processed in units of blocks. Therefore, when data of a page to which new data is written is erased, data of all pages of a block including the page is erased. Therefore, when data written on a certain page is rewritten, the process of writing the data of all the pages of the block including the page to be rewritten to the empty block and erasing the original block is performed.

  In the processing as described above, since the data after rewriting is written in a block different from the block before rewriting, the block in the flash memory changes every time data is rewritten. Therefore, the correspondence relationship between the block supplied from the host system to which the flash memory system is mounted and the block in the flash memory changes every time data is rewritten.

  In order to manage the correspondence that changes each time data is rewritten as described above, Patent Document 1 creates an address conversion table that shows the correspondence between the logical address supplied from the host system and the physical address in the flash memory. ing.

  In addition, flash memories are widely used as storage media for information devices (host systems) such as digital still cameras. As the data handled by such information devices has increased in capacity, the storage capacity of flash memory has also increased.

  In order to smoothly manage the storage area of the flash memory having a large capacity as described above, Patent Document 2 uses a technique of dividing the storage area into a plurality of zones.

[Address space of flash memory system]
FIG. 6 is a diagram schematically showing the structure of the address space of the flash memory. The address conversion table and zone division will be specifically described with reference to FIG.

  The address space on the host system side is managed by an LBA (Logical Block Address) that is a serial number assigned to an area divided in units of sectors (512 bytes) as shown in FIG. Further, a group of a plurality of sectors is called a logical block, and a group of a plurality of logical blocks is called a logical zone. Further, as shown in FIG. 6B, the serial numbers assigned to the logical blocks are called logical block numbers (LBN), and the serial numbers assigned to the logical zones are called logical zone numbers (LZN). In addition, a serial number in each logical zone of a logical block included in each logical zone is called a logical zone block number (LZIBN). On the other hand, as shown in FIG. 6C, each physical block is assigned a unique physical block address (PBA). Further, a physical zone is constituted by a plurality of physical blocks, and a unique physical zone number (PZN) is assigned to each physical zone. A serial number in each physical zone of a physical block included in each physical zone is called an intra-physical zone block number (PZIBN).

  In addition, one physical zone is allocated to each logical zone, and data corresponding to each logical block included in the logical zone is written to a physical block included in the physical zone allocated to the logical zone. Therefore, the number of sectors included in one logical block is set according to the number of sector areas included in one physical block. However, when one logical block is assigned to a plurality of physical blocks, the plurality of physical blocks are regarded as one physical block, and the number of sectors included in one logical block is set.

  In the example shown in FIG. 6, since a flash memory in which one physical block is composed of 256 sector areas is assumed, 256 sectors correspond to one logical block. Therefore, the logical zone of LZN # 0 configured with 500 logical blocks of LBN # 0 to # 499 corresponds to the 128000 sector area of LBA # 0 to # 127999. Similarly, the logical zone of LZN # 1 corresponds to the 128000 sector area of LBA # 128000 to # 255999, the logical zone of LZN # 2 corresponds to the 128000 sector area of LBA # 256000 to # 383999, The logical zone of LZN # 3 corresponds to the 128000 sector area of LBA # 3840000 to # 511999.

  In addition, the logical zone of LZN # 0 configured with 500 logical blocks of LBN # 0 to # 499 is allocated to the physical zone of PZN # 0 configured with 512 physical blocks of PBA # 0 to # 511. It has been. Similarly, the logical zone of LZN # 1 is assigned to the physical zone of PZN # 1, the logical zone of LZN # 2 is assigned to the physical zone of PZN # 2, and the logical zone of LZN # 3 is assigned to PZN #. Assigned to three physical zones. Here, the reason why the number of physical blocks included in the physical zone is larger than the number of logical blocks included in the logical zone is that new data and old data corresponding to the same logical block coexist in different physical blocks. This is a case in which a case where a defective block in which data cannot be normally written is generated.

[Flash memory address conversion]
FIG. 7 is a diagram conceptually showing address conversion of the flash memory. The conversion from the address space on the host system side to the address space of the flash memory, that is, the conversion from LBN to PBA will be described with reference to FIG.
(S71) LZN and LZIBN are obtained from LBN. When the number of logical blocks included in each logical zone is N, LZN corresponds to the quotient when LBN is divided by N, and LZIBN corresponds to the remainder when LBN is divided by N.
(S721) LZN is converted to PZN (PZN corresponding to LZN is obtained). Since LZN and PZN correspond to each other, PZN has the same value as LZN.
(S722) LZIBN is converted to PZIBN (PZIBN corresponding to LZIBN is obtained). By referring to the address conversion table, PZIBN corresponding to LZIBN can be obtained. Alternatively, in the case of the writing process, when the PZIBN corresponding to LZIBN does not exist in the address translation table, the PZIBN of the free physical block is assigned as PZIBN corresponding to LZIBN.

FIG. 7B is a diagram showing an example of the configuration of the address conversion table, and the address conversion table is created for each zone. In this example, the left side shows the logical block LZIBN, and the right side shows the physical block PZIBN. The logical block of LZIBN # 0 corresponds to the physical block of PZIBN # 22, the logical block of LZIBN # 1 corresponds to the physical block of PZIBN # 12, and the logical block of LZIBN # 2 corresponds to the physical block of PZIBN # 6.
(S73) PBA is obtained from PZIBN and PZN. PBA is obtained by connecting PZIBN to the lower side of PZN as shown in FIG.

[2-plane flash memory]
2. Description of the Related Art A two-plane flash memory having two planes each composed of a memory cell array composed of a plurality of memory cells and a register for accessing the memory cell array is known (for example, see Non-Patent Document 1). ). Also in the case of the two-plane flash memory, the memory cell array is divided into physical blocks that are units of erasing processing, and the physical blocks are divided into pages that are processing units of writing or reading.

  As in the example shown in FIG. 8, the two-plane flash memory is composed of plane # 0 and plane # 1, and PBA numbers are alternately allocated to the physical blocks of plane # 0 and plane # 1. . For example, plane # 0 includes 2048 physical blocks up to PBA # 4094 in the order of PBA # 0, # 2, and # 4, and plane # 1 has up to PBA # 4095 in the order of PBA # 1, # 3, and # 5. It has 2048 physical blocks.

  Each physical block of the 2-plane flash memory is composed of 64 pages as shown in FIG. 9A, and 64 page numbers from # 0 to # 63 are assigned to each page. Further, as shown in FIG. 9B, each page includes a user area and a redundant area. The user area is an area of 4 sectors (512 bytes × 4 = 2048 bytes) for storing data given from the host system, and the redundant area stores additional information such as an error correction code corresponding to the data of the user area. This is a 64-byte area. Register # 0 and register # 1 shown in FIG. 8 are read from the user area (2048 bytes) and redundant area (64 bytes) of each page, or read from the user area (2048 bytes) and redundant area (64 bytes). This is a storage area for temporarily storing data.

  The two-plane flash memory can use a writing method called two-plane writing when writing data written in the registers # 0 and # 1 in FIG. 8 to the flash memory. In this two-plane writing, data is written to a pair of preset physical blocks (physical block in plane # 0 and physical block in plane # 1). When one logical block is assigned to the pair of physical blocks, 512-sector data (sectors # 0 to # 511) included in the logical block is written to a page in the pair of physical blocks. That is, sectors # 0 to # 3 are assigned to page number # 0 of plane # 0, sectors # 4 to # 7 are assigned to page number # 0 of plane # 1, and sectors # 8 to # 11 are assigned to page number # of plane # 0. 1, sectors # 12 to # 15 are written in the order of page number # 1 of plane # 1, sectors # 504 to # 507 are written to page number # 63 of plane # 0, and sectors # 508 to # 511 are written to plane # 1. It is written in page number # 63 of # 1.

  The two-plane flash memory can use a normal writing method when writing data written in the register # 0 and the register # 1 in FIG. 8 to the flash memory. That is, it can be written separately for each plane. In the 2-plane flash memory, the physical block in plane # 0 and the physical block in plane # 1 are alternately assigned PBA numbers, so when physical blocks are assigned to each physical zone in the PBA order, A physical block in plane # 0 and a physical block in plane # 1 are included in the same physical zone. As shown in FIG. 10, PZN # 0 and PZIBN # 0 correspond to PBA # 0 of plane # 0, and PZN # 0 and PZIBN # 1 correspond to PBA # 1 of plane # 1. Similarly, PZN # 1 and PZIBN # 1022 correspond to PBA # 2046 of plane # 0, and PZN # 1 and PZIBN # 1023 correspond to PBA # 2047 of plane # 1. This conversion is calculated as shown in FIG. For example, since PZN # 1 is “0001” in binary number and PZIBN # 1022 is “11 1111 1110” in binary number, PBA # becomes “0001 11 1111 1110” in binary number and is 2046 in decimal number. become.

  Next, a timing chart of normal writing and 2-plane writing will be described. In normal writing, as shown in the timing chart of FIG. 11A, an input command IC for instructing data writing to the register for the plane # 0 or the plane # 1, the write destination address AD, and the write data DT And a write command PC instructing writing from the register to the memory cell array are sequentially supplied to the flash memory. Here, in the flash memory of Non-Patent Document 1, a busy time of 200 μs occurs after the write command PC is supplied, and the data written in the register is written into the memory cell array during this busy time.

  On the other hand, in 2-plane writing, as shown in the timing chart of FIG. 11B, an input command IC, a write destination address AD and write data DT, and a dummy write command DPC are supplied to the plane # 0. Thereafter, a dummy input command DIC, a write destination address AD and write data DT, and a write command PC are supplied to the plane # 1. In this two-plane writing, after the dummy write command DPC is supplied, a dummy busy time is generated for 0.5 μsec. However, the write command PC supplies data written to the plane # 0 register and the plane # 1 register. Are simultaneously written in the flash memory. The busy time that occurs at the time of writing is the same as the busy time that occurs at the time of writing to either plane # 0 or plane # 1, which is 200 μsec. That is, in 2-plane writing, the amount of data written to the flash memory is equivalent to two registers, but the busy time that occurs in this writing process is almost the same as the busy time (200 μsec) that occurs in normal writing (0 (5 μ + 200 μ = 200.5 μsec), high-speed writing can be realized.

[Free block search]
When PZIBN corresponding to LZIBN does not exist in the address conversion table, and when a page in which data is written is rewritten, it is necessary to search for an empty block. The empty block search will be specifically described below.

  FIG. 12 is a diagram illustrating an example of a configuration of an empty block search table. A process for searching for an empty block will be described with reference to FIG. The free block search table shown in FIG. 12 is a table showing the usage status of physical blocks in the physical zone of the flash memory, and is created for each physical zone.

  This empty block search table is composed of 128 bytes (1024 bits) of data, and indicates the use status of physical blocks included in the physical zone by the logical value of each bit. In this empty block search table, the logical value “1” indicates that it is an empty block, and the logical value “0” indicates that it is not an empty block. That is, the logical value “1” indicates that the physical block corresponding to the bit is in a state where no data is written (erased state), and the logical value “0” indicates the physical block corresponding to the bit. The block indicates a state where data is written or a bad block.

  In FIG. 12, 128-byte data indicating the use status of 1024 physical blocks is displayed with a line feed for each byte. Here, the top row indicates the usage status of the physical blocks PZIBN # 0 to # 7. Similarly, the second row indicates the usage status of the physical blocks PZIBN # 8 to # 15, and the third row indicates the usage status of the physical blocks PZIBN # 16 to # 23. The bottom row shows the usage status of the physical blocks PZIBN # 1016 to # 1023. In addition, physical blocks are allocated to 1-byte data in each row in the order of PZIBN from the lower bit side. Therefore, the least significant bit of the top row indicates the usage status of the physical block of PZIBN # 0, and the most significant bit of the bottom row indicates the usage status of the physical block of PZIBN # 1023.

  When searching for an empty block, 1-byte data of each row is read in order from the upper row, and when the read data is not 0 (binary number display: 0000 0000), the data is stored in the shift register. Write, shift shift register in lower direction. The number of bits from the lower order is determined to be “1” depending on how many times the carry has occurred. For example, if 0001 1000 (binary number display) in the fourth row is written to the shift register and the shift register is shifted in the lower direction, a carry occurs in four shifts, so the fourth bit from the lower side The corresponding physical block of PZIBN # 27 is detected as an empty block.

  In the next empty block search, the search is started from the fifth bit from the lower side of the fourth row. When the search starts from the fifth bit from the lower side in this way, a mask process is performed so that the lower 4 bits of the data to be set become “0” before setting the data in the shift register. .

  When data is written in the empty block detected using the above-described empty block search table, the bit on the empty block search table corresponding to the physical block is rewritten from “1” to “0”. In the address conversion table, PZIBN having a correspondence relationship with LZIBN of the logical block corresponding to the written data is rewritten to PZIBN of the write destination physical block. The logical block LZIBN corresponding to the written data is written in the redundant area 26 of the physical block in which the data is written.

  As described above, the empty block search searches only empty blocks included in the same physical zone. In the two-plane flash memory, PBA numbers are assigned alternately, so that there are cases where an empty block in plane # 0 is detected and an empty block in plane # 1 is searched.

JP 2001-243110 A JP 2005-018490 A Samsung Electronics, “K9XXG08UXM”, [online], [searched July 13, 2006], Internet (URL: http://www.samsung.com/Products/Semiconductor/NANDFlash/SLC_LargeBlock/16Gbit/K9WAG08U1M/ds_k9revgux08 (pdf)

  As described above, two-plane writing can be written at a higher speed than normal writing. However, 2-plane writing can be performed only on a pair of physical blocks in which PBA # 2n and PBA # 2n + 1 (n is an integer of 0 or more) are combined. In order to perform 2-plane writing, it is necessary to allocate one logical block to the pair of physical blocks. For this reason, the creation of an address translation table that enables two-plane writing requires more processing than the creation of an address translation table for normal writing. Furthermore, when one of the pair of physical blocks becomes a defective block, only normal writing can be performed on the other physical block. Therefore, it is necessary to separately manage blocks that can only be written normally.

  For the reasons described above, there is a demand for performing normal writing on the two-plane flash memory.

  However, in the 2-plane flash memory, the PBA number is alternately assigned to each plane. Therefore, when an empty block is detected by the prior art empty block search process when data is rewritten, the data before rewriting is stored. In some cases, the stored physical block and the empty block to which the rewritten data is written become a physical block in a different plane. In such a case, after rewriting the storage data that is not to be rewritten in the physical block in which the data before rewriting is stored, by copying back processing (processing for copying data copied from the memory cell array to the register to another memory cell array) Unable to write empty block to write data. In other words, since the copyback processing can be performed only within the same plane, in such a case, it is necessary to read out the storage data that is not the target of rewriting from the two-plane flash memory and rewrite it, and it takes time to rewrite data. There is a problem that it takes.

  The present invention relates to a memory controller capable of providing address management such that a physical block included in each physical zone is composed of physical blocks in the same plane, a flash memory system including the memory controller, and control of the flash memory It aims to provide a method.

  In order to achieve the above object, a memory controller for controlling access to a flash memory having a two-plane write function, wherein the memory controller manages a storage area of the flash memory by dividing it into a plurality of physical zones. A zone management means for managing a logical zone that is an area of logical addresses to be allocated to the address, an address management means for managing a correspondence relationship between a logical address area included in the logical zone and a storage area included in the physical zone, and The means is a means for managing so that the area of the logical address included in the same logical zone is allocated to a physical zone configured by physical blocks in the same plane.

  In addition, the address management means determines the temporary physical block address based on the physical zone number that is a serial number assigned to the physical zone and the block number in the physical zone that is the serial number in the physical zone of the physical block included in the physical zone. The address generation means for generating the address, and the address conversion means for converting the temporary physical block address generated by the address generation means into the physical block address of the physical block included in the physical zone configured by the physical blocks in the same plane. It is also preferable.

In addition, when the number of physical blocks included in the physical zone is 2 ⁿ , the address conversion unit moves the bit of the (n + 1) th bit from the lower order when the temporary physical block address is displayed in bits to the least significant bit. Accordingly, it is also preferable that the temporary physical block address is converted into a physical block address.

  In addition, the address management means uses the physical zone number, which is a serial number assigned to the physical zone, and the physical zone block number, which is the serial number within the physical zone, of the physical block included in the physical zone. Physical block address generating means for generating a physical block address of a physical block included in a physical zone composed of blocks, and the physical block address generating means includes the first bit from the lower order when the physical zone number is displayed in bits. It is also preferable that the physical block address is generated by inserting a bit when the block number in the physical zone is displayed in bits between the second bits.

  In order to achieve the above object, a flash memory system according to the present invention includes any one of the memory controllers and a flash memory.

  In order to achieve the above object, a flash memory control method for controlling access to a flash memory having a two-plane write function, which divides a storage area of a flash memory into a plurality of physical zones and allocates the physical zones In a flash memory control method for managing a logical zone which is a logical address area, a logical zone including a logical address area to be accessed is determined, and a serial number assigned to a physical zone assigned to the logical zone is determined. Physical zone number identification step for obtaining a physical zone number, and physical zone block number identification step for obtaining a physical zone block number that is a serial number in the physical zone of a physical block corresponding to the logical address area to be accessed And physical zone number and physical zone block Includes a physical block address generation step for generating a physical block address of a physical block corresponding to the area of the logical address to be accessed based on the number, and in the physical block address generation step, the physical zone number is displayed in bits. A physical block address is generated by inserting a bit when the block number in the physical zone is displayed between the first bit and the second bit from the lower side.

  According to the present invention, address management is performed such that a logical address area included in the same logical zone is allocated to a physical address area included in a physical zone configured by physical blocks in the same plane. When such address management is performed, a physical block in which data before rewriting is stored and a free block in which data after rewriting is written do not become physical blocks in different planes. Therefore, a combination of a physical block in which data before rewriting is stored and a physical block in which data after rewriting is written cannot be subjected to copy back processing is prevented.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram schematically showing the flash memory system 1. As shown in FIG. 1, the flash memory system 1 includes a flash memory 2 (2-plane flash memory) and a memory controller 3 that controls the flash memory 2.

  The flash memory system 1 is connected to the host system 4 via the external bus 13. The host system 4 includes a CPU (Central Processing Unit) for controlling the entire operation of the host system 4, a companion chip for transferring information to and from the flash memory system 1, and the like. The host system 4 may be various information processing apparatuses such as a personal computer and a digital still camera that process various types of information such as characters, sounds, and image information.

[Description of flash memory 2]
The flash memory 2 is a non-volatile memory and includes a register and a memory cell array. The flash memory 2 performs data copying between the register and the memory cell array to write or read data.

  The memory cell array includes a plurality of memory cell groups and word lines. Each memory cell group includes a plurality of memory cells connected in series. The word line is for selecting a specific memory cell in the memory cell group. Data is copied between the selected memory cell and the register via the word line, that is, data is copied from the register to the selected memory cell, or data is copied from the selected memory cell to the register. .

  A memory cell constituting the memory cell array is constituted by a MOS transistor having two gates. Here, the upper gate and the lower gate are referred to as a control gate and a floating gate, respectively. By injecting charges (electrons) into the floating gate or discharging charges (electrons) from the floating gate, data can be obtained. Is written or data is erased.

  Since the floating gate is surrounded by an insulator, the injected electrons are held for a long period of time. Note that, when electrons are injected into the floating gate, a high voltage at which the control gate is on the high potential side is applied between the control gate and the floating gate. Further, when electrons are discharged from the floating gate, a high voltage at which the control gate becomes a low potential side is applied between the control gate and the floating gate.

  Here, a state where electrons are injected into the floating gate is a write state, which corresponds to a logical value “0”. The state in which electrons are discharged from the floating gate is an erased state, which corresponds to a logical value “1”.

  Next, FIG. 2 shows an address space of the flash memory 2 composed of two planes (plane # 0 and plane # 1). The address space of the flash memory 2 (2-plane flash memory) is composed of “page”, “block (physical block)”, and “plane”.

  A page is a processing unit in a data read operation and a data write operation performed in a general flash memory. The physical block is a processing unit in the data erasing operation performed in the flash memory, and is composed of a plurality of pages.

  In the flash memory 2 (2-plane flash memory) shown in FIG. 2, one page is composed of a user area 25 of 4 sectors (512 × 4 bytes) and a redundant area 26 of 64 bytes (16 × 4 bytes). One physical block is composed of 64 pages.

  PBAs are alternately allocated to the physical blocks in the plane # 0 and the plane # 1. For example, even PBAs # 0, # 2, and # 4 are assigned to physical blocks in the plane # 0 in this order, and PBAs # 1, # 3, and # 5 are assigned to physical blocks in the plane # 1. An odd number of PBAs are allocated in order.

  Each page includes a user area 25 and a redundant area 26. The user area 25 is an area for storing user data supplied from the host system 4. The redundant area 26 is an area for storing additional data such as ECC (Error Correcting Code), logical address information, and block status (flag).

  The ECC is data for detecting and correcting an error included in the data stored in the user area 25.

  The logical address information is information for specifying a logical block corresponding to the data when the data is stored in the physical block.

  Accordingly, since the logical address information is not written in the erased physical block, the physical block including the redundant area 26 is determined by determining whether or not the logical address information is stored in the redundant area 26. It is possible to determine whether or not valid data is stored. That is, when logical address information is not stored in the redundant area 26, it can be determined that valid data is not stored in the physical block.

  The block status (flag) is a flag indicating whether the block is good or bad. A block in which data cannot be normally written is determined as a defective block, and a block status (flag) indicating a defective block is written in the redundant area 26.

  Such a flash memory 2 receives data, address information, internal commands, and the like from the controller 3 and performs various processes such as a data read process, a write process, a block erase process, and a transfer process.

  Here, the internal command is a command for the controller 3 to instruct the flash memory 2 to execute processing, and the flash memory 2 operates in accordance with the internal command given from the controller 3. In contrast, the external command is a command for the host system 4 to instruct the flash memory system 1 to execute processing.

[Description of controller 3]
As shown in FIG. 1, the controller 3 includes a microprocessor 6, a host interface block 7, a work area 8, a buffer 9, a flash memory interface block 10, an ECC block 11, and a ROM (Read Only Memory) 12. And. The controller 3 constituted by these functional blocks is integrated on one semiconductor chip. Each functional block will be described below.

  The microprocessor 6 controls the overall operation of the controller 3 in accordance with a program stored in the ROM 12. For example, the microprocessor 6 reads a command set defining various processes from the ROM 12, supplies the command set to the flash memory interface block 10, and causes the flash memory interface block 10 to execute processes. The host interface block 7 exchanges data, address information, status information, external commands, and the like with the host system 4. Data or the like supplied from the host system 4 to the flash memory system 1 is taken into the flash memory system 1 (for example, the buffer 9) using the host interface block 7 as an entrance. Data supplied from the flash memory system 1 to the host system 4 is supplied to the host system 4 through the host interface block 7 as an exit.

  A work area 8 shown in FIG. 1 is a work area in which data necessary for controlling the flash memory 2 is temporarily stored, and includes a plurality of SRAM (Static Random Access Memory) cells.

  The buffer 9 temporarily stores data read from the flash memory 2 and data to be written to the flash memory 2. That is, data read from the flash memory 2 is held in the buffer 9 until the host system 4 can receive the data, and data to be written to the flash memory 2 is stored until the flash memory 2 becomes writable. It is held in the buffer 9.

  The flash memory interface block 10 exchanges data, address information, status information, internal commands, and the like with the flash memory 2 via the internal bus 14.

  The flash memory interface block 10 supplies an internal command, address information, and the like to the flash memory 2 based on a command set read from the ROM 12, thereby causing the flash memory 2 to read and write.

  The ECC block 11 generates an ECC added to data to be written to the flash memory 2 and detects and corrects an error included in the read data based on the ECC added to the data read from the flash memory 2.

  The ROM 12 is a non-volatile storage element that stores a program that defines a processing procedure performed by the microprocessor 6. Specifically, the ROM 12 stores a program that defines a processing procedure such as creation of an address conversion table, for example.

  The address conversion table is created on the work area 8. This address conversion table stores the correspondence between the corresponding logical zone, the block number LZIBN in the logical zone in the physical zone, and the block number PZIBN in the physical zone.

[Address management of the present invention]
First, functions necessary for the address management means of the present invention will be described. As described above, the empty block search searches only for empty blocks included in the same physical zone. Therefore, in order to ensure that the physical block in which the data before rewriting is stored and the free block in which the data after rewriting is written always become a physical block in the same plane, the physical blocks included in the same physical zone are: It suffices to have only physical blocks in the same plane. Note that logical blocks included in the same logical zone are allocated to physical blocks included in the same physical zone.

  Therefore, the address management means of the present invention converts the logical block number into a physical block address so that logical blocks included in the same logical zone are allocated to physical blocks in the same plane. The address management means of the present invention will be described in detail below.

FIG. 3 is a diagram conceptually showing address conversion in the first embodiment of the present invention. The conversion from LBN to PBA in this embodiment will be described with reference to FIG.
(S31) LZN and LZIBN are obtained from LBN. When the number of logical blocks included in each logical zone is N, LZN corresponds to the quotient when LBN is divided by N, and LZIBN corresponds to the remainder when LBN is divided by N.
(S321) LZN is converted to PZN (PZN corresponding to LZN is obtained). When the same numbers of LZN and PZN are made to correspond to each other, PZN has the same value as LZN.
(S322) LZIBN is converted to PZIBN (PZIBN corresponding to LZIBN is obtained). PZIBN corresponding to LZIBN can be obtained by referring to the address conversion table showing the correspondence between LZIBN and PZIBN. Alternatively, in the case of the writing process, when the PZIBN corresponding to LZIBN does not exist in the address translation table, the PZIBN of the free physical block is assigned as PZIBN corresponding to LZIBN.
(S33) PBA ′ (provisional physical block address) is generated from PZIBN and PZN. When the number of physical blocks included in each physical zone is a power of 2, PZN and PZIBN are displayed in bits, and PZ ′ is obtained by connecting PZIBN to the lower side of PZN. That is, when the number of physical blocks included in each physical zone is M (M = 2 ⁿ ), PZN is multiplied by M, and PZIBN is added to the result. The host interface block 7 supplies the PBA ′ thus obtained to the flash memory interface block 10.
(S34) Convert PBA 'to PBA. In this conversion, the bit of the (n + 1) th bit from the lower order side when PBA ′ is displayed in bits is moved to the least significant bit. Here, when the number of physical blocks included in each physical zone is M (M = 2 ⁿ ), the bit length of PZIBN (# 0 to # M−1) is n, and the (n + 1) th bit from the lower side. Corresponds to the least significant bit of PZN. Therefore, by performing a bit operation to move the (n + 1) -th bit from the lower order side to the least significant bit, the physical zone with an even number of PZN is composed of physical blocks in the plane # 0, and the odd number of PZN is an odd number. The physical zone is composed of physical blocks in the plane # 1.

  By the conversion of S34, the object of the present invention of converting the LBN in the same physical zone into the PBA of the physical block included in the physical zone configured with the physical blocks in the same plane is realized. The flash memory interface block 10 supplies the flash memory 2 with address information and internal commands based on the PBA, thereby causing the flash memory 2 to perform reading or writing.

  FIG. 5 is a diagram illustrating an example of a logical address space, a physical address space, and an address conversion table in the embodiment of the present invention. A specific example of the address conversion unit of the first embodiment of the present invention will be described with reference to FIG.

  FIG. 5A shows a logical address space. In this example, the number of logical blocks included in each logical zone is 1000. Therefore, LZIBN is 0-999. FIG. 5B shows a physical address space. In this example, the number of physical blocks included in each physical zone is 1024. Therefore, PZIBN is 0-1023. Further, since this is a physical address space of the two-plane flash memory, PZN # 0 and PZN # 2 are physical blocks in the plane # 0, and PZN # 1 and PZN # 3 are physical blocks in the plane # 1. FIG. 5C shows an address conversion table. An address conversion table is created for each zone. The first address conversion table is an address conversion table for zone # 0 (an address conversion table indicating the correspondence between the logical blocks included in the logical zone of LZN # 0 and the physical blocks included in the physical zone of PZN # 0). The second address conversion table is an address conversion table for zone # 1 (an address indicating the correspondence between the logical blocks included in the logical zone of LZN # 1 and the physical blocks included in the physical zone of PZN # 1) Conversion table), and so on.

  First, the case of converting LBN # 2000 will be described. In S31, LZN # 2 and LZIBN # 0 are obtained from LBN # 2000 (2000/1000 = 2 remainder 0). In S321, LZN # 2 is converted to PZN # 2. In S322, LZIBN # 0 is converted to PZIBN # 1021 by the address conversion table. In S33, PBA '# 3069 is generated based on PZN # 2 and PZIBN # 1021 (2 * 1024 + 1021). In S34, PBA '# 3069 is converted to PBA # 4090.

  The conversion is performed as follows in accordance with FIG. When PBA '# 3069 is expressed in binary, it becomes “1011 1111 1101”, and by moving the 11th bit from the lower side to the least significant bit, “1111 1111 1010” and 4090 in decimal are obtained.

  Next, the case of converting LBN # 2001 will be described. In S31, LZN # 2 and LZIBN # 1 are obtained from LBN # 2001 (2001/1000 = 2 remainder 1). In S321, LZN # 2 is converted to PZN # 2. In S322, LZIBN # 1 is converted to PZIBN # 1023 by the address conversion table. In S33, PBA '# 3071 is generated based on PZN # 2 and PZIBN # 1023 (2 * 1024 + 1023). In S34, PBA '# 3071 is converted to PBA # 4094.

  As described above, LBN # 2000 and LBN # 2001 in LZN # 2 are converted into PBA # 4090 and PBA # 4092 of the same PZN # 2, respectively. As described above, in the address conversion process of this embodiment, the LBN of the logical block included in the same logical zone is converted into the PBA of the physical block included in the same physical zone. Since each physical zone is composed of physical blocks in the same plane, as a result, LBAs of logical blocks included in the same logical zone are converted to PBAs of physical blocks included in the same plane.

In the first embodiment of the present invention, S31 to S33 shown in FIG. 3A are generally performed address conversion processes. S34 is a newly added process. When the number of physical blocks included in each physical zone is M (M = 2 ⁿ ), the bit operation (S34) for moving the (n + 1) th bit from the lower side of PBA ′ to the least significant bit is as follows. Alternatively, a logic circuit may be used.

FIG. 4 is a diagram conceptually showing address conversion in the second exemplary embodiment of the present invention. The conversion from LBN to PBA in this embodiment will be described with reference to FIG.
(S41), (S421), and (S422) are the same conversion contents as (S31), (S321), and (S322), respectively. Therefore, details are omitted.
(S43) PBA is generated from PZIBN and PZN. Here, as shown in FIG. 4B, a bit indicating PZIBN is inserted between the first bit and the second bit from the lower side of PZN. That is, when the number of physical blocks included in each physical zone is M (M = 2 ⁿ ), n bits indicating PZIBN are inserted between the first and second bits from the lower side of PZN. . For example, when the number of physical blocks included in each physical zone is 1024, 10 bits when PZIBN is displayed in bits are inserted between the first bit and the second bit from the lower side of PZN.

  The object of the present invention is realized by converting the LBN in the same physical zone into the PBA of the physical block included in the physical zone configured by the physical blocks in the same plane by the conversion in S43. The flash memory interface block 10 supplies the flash memory 2 with address information and internal commands based on the PBA, thereby causing the flash memory 2 to perform reading or writing.

  A specific example of the address conversion unit of the second exemplary embodiment of the present invention will be described with reference to FIG. Note that PBA ′ in FIG. 5 is not used in this embodiment.

  First, the case of converting LBN # 2000 will be described. In S41, LZN # 2 and LZIBN # 0 are obtained from LBN # 2000 (2000/1000 = 2 remainder 0). In S421, LZN # 2 is converted to PZN # 2. In S422, LZIBN # 0 is converted to PZIBN # 1021 by the address conversion table. In S43, PBA # 4090 is generated based on PZN # 2 and PZIBN # 1021.

  The generation process of S43 is performed as follows according to FIG. When PZN # 2 is expressed in binary, it becomes “0010”. When PZIBN # 1021 is expressed in binary, it becomes “11 1111 1101”. By concatenating bits “001” other than the lower 1 bit of PZN # 2, all bits “11 1111 1101” of PZIBN # 1021, and the lower 1 bit “0” of PZN # 2, “00 1111 1111 1010” is obtained. Expressed in decimal, it is 4090.

  Next, the case of converting LBN # 2001 will be described. In S41, LZN # 2 and LZIBN # 1 are obtained from LBN # 2001 (2001/1000 = 2 remainder 1). In S421, LZN # 2 is converted to PZN # 2. In S422, LZIBN # 1 is converted to PZIBN # 1023 by the address conversion table. In S43, PBA # 4094 is generated based on PZN # 2 and PZIBN # 1023.

  As described above, LBN # 2000 and LBN # 2001 in LZN # 2 are converted into PBA # 4090 and PBA # 4094 of the same PZN # 2, respectively. As described above, the address conversion process of this embodiment also converts the LBN of the logical block included in the same logical zone into the PBA of the physical block included in the same physical zone. Since the same physical zone is composed of physical blocks in the same plane, as a result, the LBN of the logical block included in the same logical zone is converted to the PBA of the physical block included in the same plane.

  In the second embodiment of the present invention, the conversions S41, S421, and S422 are generally performed address conversion processes. This is a process in which the conversion S43 is changed. As described above, in the second embodiment of the present invention, when generating PBA from PZIBN and PZN, a bit indicating PZIBN is inserted between the first and second bits from the lower side of PZN. The object of the invention is realized.

  The number of logical blocks in each logical zone is not limited to 1000. Similarly, the number of physical blocks in each physical zone is not limited to 1024. Each value may be freely set as long as the number of logical blocks ≦ the number of physical blocks. Further, the number of bits of PBA is not limited to 14 bits.

  In the above embodiment, the number of planes is two. However, the number of planes is not limited to two, and may be an even number.

  As described above, in the address management of the present invention, the LBN of the logical block included in the same logical zone is converted into the PBA of the physical block included in the physical zone configured with the physical blocks in the same plane. Therefore, the physical block in which the data before rewriting is stored and the empty block in which the data after rewriting is written do not become physical blocks in different planes.

  Moreover, all the embodiment described above shows the present invention exemplarily, and does not limit the present invention, and the present invention can be implemented in other various modifications and changes. Therefore, the scope of the present invention is defined only by the claims and their equivalents.

1 is a block diagram schematically showing a flash memory system in an embodiment of the present invention. FIG. FIG. 3 is a diagram schematically showing a structure of an address space of a two-plane flash memory in an embodiment of the present invention. It is a figure which shows notionally the address conversion in the 1st Embodiment of this invention. It is a figure which shows notionally the address conversion in the 2nd Embodiment of this invention. It is a figure which shows an example of the logical address space in the embodiment of this invention, a physical address space, and an address conversion table. It is a figure which shows roughly the structure of the address space of flash memory. It is a figure which shows notionally the address conversion of a flash memory. It is a figure which shows roughly the structure of the physical address space of 2 plane flash memory. (A) is a figure which shows roughly the relationship between the physical block and page of 2 plane flash memory. (B) is a diagram schematically showing a relationship between a page of a two-plane flash memory, a user area, and a redundant area. It is a figure which shows roughly the relationship between the block in a zone in the case of performing normal writing with respect to 2 plane flash memory, and a physical block. (A) is a figure which shows the time chart in the case of performing normal writing with respect to flash memory. (B) is a diagram showing a time chart when performing two-plane writing to a two-plane flash memory. It is a figure which shows an example of a structure of an empty block search table.

Explanation of symbols

1 Flash memory system 2 Flash memory 3 Controller 4 Host system 6 Microprocessor 7 Host interface block 8 Work area 9 Buffer 10 Flash memory interface block 11 ECC block 12 ROM
13 External bus 14 Internal bus 25 User area 26 Redundant area

Claims (6)

A memory controller for controlling access to a flash memory having a two-plane writing function,
In a memory controller that manages the storage area of the flash memory divided into a plurality of physical zones,
Zone management means for managing a logical zone that is an area of a logical address assigned to the physical zone;
An address management means for managing a correspondence relationship between a logical address area included in the logical zone and a storage area included in the physical zone;
The memory controller according to claim 1, wherein the address management means is a means for managing so that an area of a logical address included in the same logical zone is allocated to the physical zone composed of physical blocks in the same plane. The address management means is
An address for generating a temporary physical block address based on a physical zone number that is a serial number assigned to the physical zone and a block number in the physical zone that is a serial number in the physical zone of a physical block included in the physical zone Generating means;
An address conversion unit that converts the temporary physical block address generated by the address generation unit into a physical block address of a physical block included in the physical zone configured by physical blocks in the same plane is provided. The memory controller according to claim 1. The address conversion means is
When the number of physical blocks included in the physical zone is ²ⁿ ,
The temporary physical block address is converted into the physical block address by moving the bit of the (n + 1) th bit from the lower order side when the temporary physical block address is displayed in bits to the least significant bit. Item 3. The memory controller according to Item 2. Based on the physical zone number that is the serial number assigned to the physical zone and the block number in the physical zone that is the serial number within the physical zone of the physical block included in the physical zone, the address management means Physical block address generating means for generating physical block addresses of physical blocks included in the physical zone composed of physical blocks of
The physical block address generation means inserts a bit when the physical zone block number is displayed in bits between the first and second bits from the lower side when the physical zone number is displayed in bits. The memory controller according to claim 1, wherein the physical block address is generated.   5. A flash memory system comprising: the memory controller according to claim 1; and a flash memory having a two-plane write function. A flash memory control method for controlling access to a flash memory having a two-plane writing function,
In the flash memory control method for dividing a storage area of the flash memory into a plurality of physical zones and managing a logical zone that is an area of a logical address assigned to the physical zone,
A physical zone number specifying step of determining the logical zone including the area of the logical address to be accessed and obtaining a physical zone number that is a serial number assigned to the physical zone assigned to the logical zone;
A physical zone block number specifying step for obtaining a physical zone block number that is a serial number within the physical zone of a physical block corresponding to the area of the logical address to be accessed;
Based on the physical zone number and the block number in the physical zone, including a physical block address generation step of generating a physical block address of a physical block corresponding to the area of the logical address to be accessed,
In the physical block address generation step, by inserting the bit when the block number in the physical zone is displayed in bits between the first and second bits from the lower side when the physical zone number is displayed in bits. A method for controlling a flash memory, wherein the physical block address is generated.

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