JP2008040406A - Plasma display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a plasma display device capable of displaying an image by using a power source for a data electrode whose power supply amount is suppressed. <P>SOLUTION: The plasma display device includes a data electrode driving circuit 52, the power source 57 for the data electrode which supplies electric power to the data electrode driving circuit 52, an image signal processing circuit 51 which converts an image signal into image data by subfields, and an image converting circuit 62 which predicts the power consumption of the data electrode driving circuit 52 based upon the image data from the image signal processing circuit 51, and converts the image data into image data reducing the power consumption of the data electrode driving circuit 52 when the predicted value exceeds a prediction threshold. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a plasma display device used for a wall-mounted television or a large monitor.

  A plasma display panel (hereinafter abbreviated as “panel”), which is a typical image display device having a large number of pixels arranged in a plane, has a large number of discharges as pixels between a front substrate and a rear substrate that are opposed to each other. A cell is formed. In the front substrate, a plurality of display electrode pairs including a pair of scan electrodes and sustain electrodes are formed in parallel on the front glass substrate, and a dielectric layer and a protective layer are formed so as to cover the display electrode pairs. Yes. The back substrate has a plurality of parallel data electrodes on the back glass substrate, a dielectric layer so as to cover them, and a plurality of barrier ribs in parallel with the data electrodes formed on the back surface glass substrate. A phosphor layer is formed on the side walls of the barrier ribs. Then, the front substrate and the rear substrate are disposed opposite to each other so that the display electrode pair and the data electrode are three-dimensionally crossed and sealed, and a discharge gas is sealed in the internal discharge space. Here, a discharge cell is formed at a portion where the display electrode pair and the data electrode face each other. In the panel having such a configuration, ultraviolet light is generated by gas discharge in each discharge cell, and phosphors of RGB colors are excited and emitted by the ultraviolet light to perform color display.

  The subfield method is used as a method for driving the panel. In this method, one field period is divided into a plurality of subfields, and each discharge cell emits light or does not emit light in each subfield. Each subfield has an initialization period, an address period, and a sustain period. In the initializing period, initializing discharge is performed in the discharge cells, and wall charges necessary for the subsequent address operation are formed. In the address period, a scan pulse is sequentially applied to the scan electrodes, an address pulse corresponding to an image signal to be displayed is applied to the data electrodes, and an address discharge is selectively generated between the scan electrodes and the data electrodes. Selective wall charge formation is performed. In the subsequent sustain period, a predetermined number of sustain pulses corresponding to the display luminance to be emitted is applied between the scan electrode and the sustain electrode, and the discharge cells in which the wall charges are formed by the address discharge are selectively discharged to emit light. Let The ratio of display luminance for each subfield is referred to as “luminance weight”.

  The means for driving the panel includes a scan electrode drive circuit for driving the scan electrodes, a sustain electrode drive circuit for driving the sustain electrodes, and a data electrode drive circuit for driving the data electrodes. The circuit applies the required drive waveform to each electrode. Here, when viewed from the data electrode drive circuit side, each data electrode is a capacitive load having a combined capacity of the adjacent data electrode, scan electrode, and sustain electrode. Therefore, in order to apply a drive waveform to each data electrode, this capacity must be charged and discharged. The power consumption of the data electrode driving circuit is not only the discharge accompanying the address discharge, but rather the ratio of the power consumption accompanying the charging / discharging of the capacity of the data electrode is large. This charge / discharge current largely depends on the image signal to be displayed. For example, when the address pulse is not applied to all the data electrodes, the charge / discharge current is 0, so that the power consumption is minimized. Similarly, when the address pulse is applied to all the data electrodes, the charge / discharge current is 0, so the power consumption is small. However, when an address pulse is randomly applied to the data electrodes, the charge / discharge current increases, and the power consumption of the data electrode drive circuit also increases.

Since the power consumption of the data electrode driving circuit varies greatly depending on the image signal in this way, the power supply for the data electrode that supplies power to the data electrode driving circuit has the maximum power consumption of the data electrode driving circuit. However, it has been designed to have a sufficiently large power supply capability so that a normal write operation can be performed. However, as panels increase in screen size and resolution, the maximum value of power consumption becomes much larger than the power consumption during normal image display so that power can be supplied even in such cases. Designing a power supply for the data electrode was not economical. In view of this, a driving method has been proposed that reduces power consumption by sacrificing image display performance to some extent for an image with high power consumption. For example, Patent Document 1 discloses a plasma display device that predicts a temperature increase due to an increase in power consumption of a data electrode driving circuit based on an image signal and converts the predicted image signal into an image signal that suppresses the temperature increase of the data electrode driving circuit. .
JP 2002-149109 A

  However, in order to accurately predict the power consumption of the data electrode driving circuit based on the image signal and to control it to be equal to or less than the predetermined power consumption, a large amount of signal processing must be performed in real time. It was not practical, for example, the circuit scale of the signal processing unit became too large. Conversely, if the power consumption is predicted within a range where the circuit scale does not become too large, it is necessary to design the data electrode power supply with a margin to absorb the prediction error, and the data electrode power supply cannot be made too small. there were.

  The present invention has been made in view of the above problems, and an object thereof is to provide a plasma display device capable of displaying an image using a power supply for a data electrode with a reduced power supply amount.

  The present invention has a panel in which discharge cells are formed at intersections between display electrode pairs and data electrodes, and one field period of an image signal is divided into a plurality of subfields so that the discharge cells emit or do not emit light for each subfield. And a data electrode driving circuit for driving data electrodes for each subfield, a data electrode power source for supplying power to the data electrode driving circuit, and an image signal for each subfield. The image signal processing circuit that converts the image data to indicate light emission or non-light emission of the discharge cell, and the power consumption of the data electrode driving circuit are predicted based on the image data from the image signal processing circuit, and the predicted value predicted An image conversion circuit that converts image data into image data with low power consumption of the data electrode drive circuit when a threshold value is exceeded. And said that there were pictures. With this configuration, it is possible to provide a plasma display device capable of displaying an image using a data electrode power source with a reduced power supply amount.

  The plasma display device of the present invention also includes a power detection circuit for detecting the power supplied to the power supply for the data electrode, and a data electrode drive circuit in a predetermined subfield when the power detected by the power detection circuit exceeds a power threshold. It is desirable to provide a write control circuit that stops the operation.

  Also, the image conversion circuit of the plasma display device of the present invention converts the image data of the subfield with the smaller luminance weight into the image data with the lower power consumption of the data electrode driving circuit in order, and the write control circuit has the subfield with the smaller luminance weight. It is desirable that the operation of the data electrode driving circuit is stopped in order from the address period.

  Further, it is desirable that the detection response speed of the power detection circuit of the plasma display device of the present invention is faster than the predicted response speed of the power prediction circuit. With these configurations, it is possible to provide a plasma display device that does not significantly impair image display quality.

  ADVANTAGE OF THE INVENTION According to this invention, it becomes possible to provide the plasma display apparatus which can display an image using the power supply for data electrodes which suppressed the electric power supply amount.

  Hereinafter, a plasma display device according to an embodiment of the present invention will be described with reference to the drawings.

(Embodiment)
FIG. 1 is an exploded perspective view showing a main part of a panel used in the embodiment of the present invention. The panel 10 is configured such that a glass front substrate 21 and a rear substrate 31 are arranged to face each other and a discharge space is formed therebetween. On the front substrate 21, a plurality of scanning electrodes 22 and sustaining electrodes 23 constituting the display electrode pair 28 are formed in parallel with each other. A dielectric layer 24 is formed so as to cover the scan electrodes 22 and the sustain electrodes 23, and a protective layer 25 is formed on the dielectric layer 24. A plurality of data electrodes 32 are formed on the back substrate 31, and a dielectric layer 33 is formed so as to cover the data electrodes 32. On the dielectric layer 33, a grid-like partition wall 34 is provided. A phosphor layer 35 is provided on the surface of the dielectric layer 33 and the side surfaces of the partition walls 34. The front substrate 21 and the rear substrate 31 are arranged to face each other in the direction in which the scan electrode 22 and the sustain electrode 23 intersect with the data electrode 32, and in the discharge space formed therebetween, for example, neon And a mixed gas of xenon. Note that the structure of the panel 10 is not limited to the above-described structure, and for example, the panel 10 may include a stripe-shaped partition wall.

  FIG. 2 is an electrode array diagram of panel 10 in accordance with the exemplary embodiment of the present invention. 1. n scan electrodes SC1 to SCn (scan electrode 22 in FIG. 1) and n sustain electrodes SU1 to SUn (sustain electrode 23 in FIG. 1) that are long in the row direction are arranged, and m data electrodes are long in the column direction. D1 to Dm (data electrodes 32 in FIG. 1) are arranged. A discharge cell is formed at a portion where a pair of scan electrode SCi and sustain electrode SUi (i = 1 to n) and one data electrode Dj (j = 1 to m) intersect, and the discharge cell is in the discharge space. M × n are formed.

  Next, a driving voltage waveform for driving the panel 10 will be described. In the present embodiment, one field is divided into ten subfields (first SF, second SF,..., Tenth SF), and each subfield is (1, 2, 3, 6, 11, 18, The description will be made assuming that the luminance weights are 30, 44, 60, and 80). Here, a subfield with a small luminance weight is called a lower subfield, and a subfield with a large luminance weight is called an upper subfield. As described above, in the present embodiment, the subfields set later are set so as to be higher-order subfields having higher luminance weights. However, in the present invention, the number of subfields and the luminance weight of each subfield are not limited to the above values.

  FIG. 3 is a diagram showing drive voltage waveforms applied to the respective electrodes of panel 10 in accordance with the exemplary embodiment of the present invention.

  In the initializing period, first, in the first half, the data electrodes D1 to Dm and the sustain electrodes SU1 to SUn are held at 0 (V), and the discharge starts from the voltage Vi1 which is lower than the discharge start voltage with respect to the scan electrodes SC1 to SCn. A ramp voltage that gradually increases toward the voltage Vi2 exceeding the voltage is applied. Then, weak initializing discharge is caused in all the discharge cells, and wall voltages are accumulated on scan electrodes SC1 to SCn, sustain electrodes SU1 to SUn, and data electrodes D1 to Dm. Here, the wall voltage on the electrode refers to a voltage generated by wall charges accumulated on the dielectric layer covering the electrode, the phosphor layer, or the like.

  Subsequently, in the second half of the initialization period, sustain electrodes SU1 to SUn are maintained at voltage Ve1, and a ramp voltage that gradually decreases from voltage Vi3 to voltage Vi4 is applied to scan electrodes SC1 to SCn. Then, a weak initializing discharge is caused again in all the discharge cells, and the wall voltages on scan electrodes SC1 to SCn, sustain electrodes SU1 to SUn, and data electrodes D1 to Dm are adjusted to values suitable for the address operation.

  In some of the subfields constituting one field, the first half of the initializing period may be omitted. In this case, the discharge cells that have been subjected to the sustain discharge in the immediately preceding subfield may be omitted. An initialization operation is selectively performed. FIG. 3 shows drive waveforms for performing the initialization operation having the first half and the second half in the initialization period of the first SF, and performing the initialization operation having only the second half in the initialization period of the subfield after the second SF.

  In the address period, voltage Ve2 is applied to sustain electrodes SU1 to SUn. The address pulse voltage Vd is applied to the data electrode Dk (k = 1 to m) of the discharge cell that should emit light in the first row among the data electrodes D1 to Dm, and the scan pulse voltage Va is applied to the scan electrode SC1 in the first row. Is applied. Then, an address discharge occurs between data electrode Dk and scan electrode SC1 and between sustain electrode SU1 and scan electrode SC1, and a positive wall voltage is generated on scan electrode SC1 and a negative voltage is applied on sustain electrode SU1. Wall voltage is accumulated. In this way, the address operation is performed in which the address discharge is caused in the discharge cells to emit light in the first row and the wall voltage is accumulated on each electrode. On the other hand, no address discharge occurs at the intersection between the data electrode Dh (h ≠ k) to which the address pulse voltage Vd is not applied and the scan electrode SC1. The above address operation is sequentially performed until the discharge cell in the nth row, and the address period ends.

  The data electrodes D1 to Dm are driven by the data electrode drive circuit described later as described above, but each data electrode Dj is a capacitive load when viewed from the data electrode drive circuit. Therefore, during the address period, the capacitance must be charged and discharged each time the voltage applied to each data electrode is changed from the ground potential 0 (V) to the address pulse voltage Vd or from the address pulse voltage Vd to the ground potential 0 (V). I must. If the number of times of charging / discharging is large, the power consumption of the data electrode driving circuit also increases.

  In the subsequent sustain period, sustain electrodes SU1 to SUn are returned to 0 (V), and sustain pulse voltage Vs is applied to scan electrodes SC1 to SCn. In the discharge cell that has caused the address discharge at this time, the voltage between scan electrode SCi and sustain electrode SUi is the sustain pulse voltage Vs plus the wall voltage on scan electrode SCi and sustain electrode SUi. Exceeding the discharge start voltage. A sustain discharge occurs between scan electrode SCi and sustain electrode SUi, and light is emitted. At this time, a negative wall voltage is accumulated on scan electrode SCi, and a positive wall voltage is accumulated on sustain electrode SUi. Subsequently, scan electrodes SC1 to SCn are returned to 0 (V), and sustain pulse voltage Vs is applied to sustain electrodes SU1 to SUn. Then, in the discharge cell in which the sustain discharge has occurred, since the voltage between sustain electrode SUi and scan electrode SCi exceeds the discharge start voltage, a sustain discharge occurs again between sustain electrode SUi and scan electrode SCi, and the sustain cell is maintained. Negative wall voltage is accumulated on electrode SUi, and positive wall voltage is accumulated on scan electrode SCi. Similarly, the sustain discharge continues in the discharge cells that have caused the address discharge in the address period by applying the number of sustain pulses proportional to the luminance weight to scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn. Done. Note that the sustain discharge does not occur in the discharge cells that did not cause the address discharge in the address period, and the wall voltage at the end of the initialization period is maintained. Thus, the maintenance operation in the maintenance period is completed.

  Also in the subsequent second to tenth SFs, the initialization period and the writing period are the same as those of the first SF, and the sustain period is the same as the sustain period of the first SF except for the number of sustain pulses. In this way, each discharge cell is controlled to emit light or not emit light for each subfield, and image display is performed by combining the luminance weights of the subfields.

  FIG. 4 is a circuit block diagram of plasma display device 1 in accordance with the exemplary embodiment of the present invention. The plasma display device 1 includes a panel 10, an image signal processing circuit 51, a data electrode driving circuit 52, a scan electrode driving circuit 53, a sustain electrode driving circuit 54, a timing generation circuit 55, a data electrode power supply 57, a power detection circuit 58, writing A control circuit 59, a power prediction circuit 61, and an image conversion circuit 62 are provided.

  The timing generation circuit 55 generates various timing signals for controlling the operation of each circuit block based on the horizontal synchronization signal H and the vertical synchronization signal V, and supplies them to the respective circuit blocks. Scan electrode drive circuit 53 applies the drive voltage waveform shown in FIG. 3 to each of scan electrodes SC1 to SCn based on the timing signal, and sustain electrode drive circuit 54 shows the drive voltage waveform shown in FIG. 3 based on the timing signal. Is applied to sustain electrodes SU1 to SUn.

  The image signal processing circuit 51 converts the input image signal sig into image data indicating light emission or non-light emission of the discharge cell for each subfield. The power prediction circuit 61 predicts the power consumption of the data electrode driving circuit 52 based on the image data for each subfield output from the image signal processing circuit 51. The image conversion circuit 62 converts the image data for each subfield into image data with low power consumption of the data electrode driving circuit 52 based on the predicted value of the power prediction circuit 61. The data electrode driving circuit 52 converts the image data for each subfield into signals corresponding to the data electrodes D1 to Dm, and drives the data electrodes D1 to Dm.

  The data electrode power source 57 is a power source that supplies necessary power to the data electrode driving circuit 52. The power detection circuit 58 detects the power supplied from the data electrode power source 57. The write control circuit 59 controls the write operation of the data electrode drive circuit 52 for each subfield based on the output of the power detection circuit 58.

  Here, the power detection circuit 58, the write control circuit 59, and the data electrode drive circuit 52 constitute feedback type control means for reducing the power of the data electrode drive circuit 52. That is, when the power detection circuit 58 detects the supply power of the data electrode power source 57 and the detected power exceeds the power threshold value, the write operation of the data electrode drive circuit 52 is started from the lower subfield with a small luminance weight. Stop in order. Hereinafter, this control means is abbreviated as “first power reduction means”.

  Further, the power prediction circuit 61 and the image conversion circuit 62 constitute feed-forward control means for reducing the power of the data electrode drive circuit 52. That is, when the power prediction circuit 61 predicts the power of the data electrode driving circuit 52 based on the image data and the predicted value exceeds the prediction threshold, the image conversion circuit 62 converts the image data into the power consumption of the data electrode driving circuit 52. Convert to small image data. Hereinafter, this control means is abbreviated as “second power reduction means”.

  As described above, the present embodiment includes two control means for reducing the power consumption of the data electrode drive circuit 52, that is, a first power reduction means and a second power reduction means.

  Before describing the two control means, first, an operation in which the image signal processing circuit 51 converts the input image signal sig into image data indicating light emission / non-light emission for each subfield will be described. For the sake of simplicity, the red, green, and blue image signals are simply referred to as image signals without being distinguished, and the image signals are assumed to be digital signals having a minimum value of “0” and a maximum value of “255”. To do. FIG. 5 is a diagram showing the relationship between the image signal of the plasma display apparatus and the image data for each subfield in the embodiment of the present invention. In this way, the relationship indicating in which subfield the discharge cell emits light with respect to the input image signal is hereinafter abbreviated as “coding”. In FIG. 5, the numerical value shown in the leftmost column indicates the value of the image signal, and the right side indicates whether or not the discharge cell is caused to emit light in each subfield when displaying the corresponding luminance. “0” indicates no light emission, and “1” indicates light emission. For example, when the image signal “1” is input, the discharge cell is caused to emit light only by the first SF having the luminance weight 1 to display the luminance “1”, and when the image signal “7” is input. The discharge cells are caused to emit light by the first SF with the luminance weight 1 and the fourth SF with the luminance weight 6 to display the luminance of “7”. Further, when the image signal “14” is input, the discharge cell is caused to emit light by the first SF having the luminance weights 1 and 2 and the second SF having the luminance weight 11 and the luminance “14” is displayed. In addition, when displaying the luminance “3”, there are a method of causing the discharge cells to emit light with the first SF and the second SF and a method of causing only the third SF to emit light. Selects a coding to be lit in a subfield having a luminance weight as small as possible. That is, when the luminance “3” is displayed, the discharge cells are caused to emit light by the first SF and the second SF. Note that a circuit for converting an image signal as described above into image data can be realized by using a data conversion table using a ROM or the like.

  Next, details of the first power reduction means will be described. First, the data electrode power source 57 will be described. FIG. 6 is a circuit diagram of data electrode power source 57 of the plasma display device in accordance with the exemplary embodiment of the present invention. The data electrode power source 57 includes a DC power source 100 configured by a switching power source and a DC-DC converter 110 that is a stabilization circuit. The DC-DC converter 110 in the present embodiment is a step-down chopper converter that includes a switching element 112, a diode 114, an inductor 116, a smoothing capacitor 118, and a control unit 200. The control unit 200 includes an oscillation circuit 202 and a flip-flop 204. The flip-flop 204 generates a signal for on / off control of the switching element based on a clock output from the oscillation circuit 202. The control unit 200 also includes a comparator 206 for controlling the conduction time of the switching element 112 so that the output of the output voltage detection unit 120 is constant. Further, based on the output of the current detection circuit 122 that detects the current flowing through the switching element 112, the control unit 200 controls the comparator 208 and the OR gate 210 to limit the conduction time of the switching element 112 when the current exceeds a predetermined value. It has. This current limitation is so-called pulse-by-pulse control that operates every clock cycle.

  Therefore, while the power consumption is small, the output voltage of the data electrode power source 57 is constant. However, when the power consumption increases, the above-described current limit starts to operate, and the output voltage decreases as the current flowing through the load increases. Indicates.

  FIG. 7A is a diagram showing the relationship between the supply current of the data electrode power source 57 and the output voltage of the plasma display device in accordance with the exemplary embodiment of the present invention. In the data electrode power source 57 in the present embodiment, the output voltage is almost constant at 72 (V) until the supply current is 2.2 (A), but when the supply current exceeds 2.2 (A), the current is It is designed so that the voltage decreases slightly as the voltage increases. When the supply current exceeds 3.5 (A), the power supply capability of the power supply is exceeded and the output voltage rapidly decreases.

  The power detection circuit 58 detects the supply power of the data electrode power source 57. The power detection circuit 58 may be configured to detect the supply power itself of the data electrode power source 57 and output a power value, but may be configured to detect a value correlated with power, such as a voltage value or a current value. In the present embodiment, an increase in power supply is detected by detecting a decrease in output voltage. That is, the output voltage of the data electrode power source 57 is compared with a voltage threshold value, and a detection signal indicating whether the output voltage of the data electrode power source 57 is equal to or higher than the voltage threshold value is output. FIG. 8 is a circuit diagram of power detection circuit 58 of the plasma display device in accordance with the exemplary embodiment of the present invention. The power detection circuit 58 includes a comparator 304 that compares the output voltage of the data electrode power source 57 and the first voltage threshold 302, and a comparator that compares the output voltage of the data electrode power source 57 and the second voltage threshold 306. 308. The first voltage threshold 302 is, for example, 65 (V), and the second voltage threshold 306 is, for example, 70 (V). FIG. 7B is a diagram showing the relationship between the supply current of the data electrode power source 57 and the detection signal of the power detection circuit 58 of the plasma display device according to the embodiment of the present invention. As described above, when the output voltage of the data electrode power source 57 becomes the second voltage threshold value 306 or less, the second detection signal becomes “H”, and when the output voltage becomes the first voltage threshold value 302 or less, the first detection signal also becomes “ H ".

  The write control circuit 59 controls the data electrode drive circuit 52 based on the detection signal from the power detection circuit 58. In the present embodiment, every time the first detection signal changes from “L” to “H”, the address operation of the data electrode driving circuit 52 is stopped in order from the address period of the lower subfield with the smaller luminance weight. Each time the second detection signal changes from “H” to “L”, the operation stop is canceled in order from the subfield having the largest luminance weight among the subfields in which the write operation is stopped. is doing.

  For example, as can be seen from FIG. 5, when the writing operation in the first SF is stopped, the luminance of the image signal “1” becomes “0”, and the luminance “1” cannot be displayed. Similarly, luminance “4”, “7”, “10”,... Cannot be displayed. However, since no write operation is performed in the first SF, power consumption can be reduced accordingly. When the writing operation in the second SF in addition to the first SF is stopped, the luminance “2”, “5”, “8”,. In this way, when the number of subfields not performing the write operation is increased, the number of luminances that can be displayed is reduced, but the power consumption for the write operation can be reduced.

  The stop of the writing operation as described above may be realized by fixing the corresponding bit of the image data indicating light emission / non-light emission for each subfield to “0”, but in the present embodiment, Control is performed using an enable terminal of a data driver IC used in the data electrode driving circuit 52.

  In this way, the first power reduction means directly detects the power of the data electrode power source 57, detects that the power has increased and is likely to exceed the power supply capability of the data electrode power source 57, The power of the data electrode driving circuit 52 is forcibly reduced. Therefore, it is not necessary to provide a sufficient margin for the power supply amount of the data electrode power source 57, and a power supply design with a minimum supply power is possible. However, since the subfield writing operation is forcibly stopped, the display quality may be noticeably deteriorated depending on the image.

  Next, the details of the second power reduction means will be described. The power prediction circuit 61 predicts the power consumption of the data electrode driving circuit 52 based on the image data for each subfield. As described above, since the data electrode 32 is a capacitive load when viewed from the data electrode drive circuit 52, the voltage of the data electrode 32 is charged and discharged when the voltage applied to the data electrode 32 changes frequently. Power consumption increases. For example, when an address pulse is applied to a discharge cell having an even-numbered scan electrode SCp (p = even) and no address pulse is applied to a discharge cell having an odd-numbered scan electrode SC (p + 1), the corresponding data electrode Dj In this case, voltage Vd and 0 (V) are alternately applied to increase power consumption. In addition, when the adjacent data electrodes D (j−1) and D (j + 1) apply the voltages Vd and 0 (V) alternately in opposite phases, the power consumption is further increased. Conversely, when no address pulse is applied to all the discharge cells, the power consumption is minimized, and when the address pulse is applied to all the discharge cells, the power consumption is small. In normal image display, the power consumption of the data electrode drive circuit 52 varies according to the image signal. If the number of changes in the voltage applied to the data electrode is large, the power consumption of the data electrode driving circuit 52 also increases. Therefore, by summing the number of voltage changes for each data electrode and calculating the sum for each subfield, a value highly correlated with the power consumption of the data electrode drive circuit 52 is obtained.

  In the present invention, the power consumption of the data electrode driving circuit 52 is predicted as follows. First, the image data of the target pixel is compared with the image data of the upper, lower, left and right pixels. When the image data of the upper and lower pixels is different from the image data of the target pixel, the predicted value 2 is added to each. Also, when the image data of the left and right pixels is different from the image data of the target pixel, the predicted value 1 is added to each. FIG. 9 is a diagram for explaining the operation of the power prediction circuit 61 of the plasma display device in accordance with the exemplary embodiment of the present invention. In the example of FIG. 9A, since the image data of the pixel above the target pixel is different from the image data of the target pixel, the predicted value “2”, and the image data of the pixel to the left of the target pixel is the image data of the target pixel. Since they are different, the predicted value is “1”, and the total predicted value of the target pixel is “3”. In the example shown in FIG. 9B, since the image data of all the pixels on the top, bottom, left, and right adjacent to the target pixel is different from the image data of the target pixel, the predicted value is “2” + “2” + “1 ”+“ 1 ”=“ 6 ”. In this way, the predicted values of all the pixels are obtained for each subfield and summed, and the predicted values for each subfield are summed for one field. The value obtained in this way may be used as the power predicted value. However, in the present embodiment, in order to average this value temporally, the sum of one field is further cumulatively added for a plurality of fields. It is used as Therefore, the response speed of the power prediction circuit 61 is slower than the response speed of the power detection circuit 58.

  The image conversion circuit 62 converts the image data into image data in which the power consumption of the data electrode driving circuit 52 is reduced when the predicted power value exceeds a predetermined prediction threshold value. FIG. 10 is a circuit block diagram showing the configuration of the image conversion circuit 62 of the plasma display device in the present embodiment. The image conversion circuit 62 includes an addition circuit 621, delay circuits 622 and 623, a comparison circuit 624, and a lower subfield data conversion circuit (hereinafter abbreviated as “lower SF conversion circuit”) 625.

  The adding circuit 621 adds the error data output from the lower SF conversion circuit 625 to the image data. The delay circuit 622 delays the image data by a time of 1H (one horizontal scanning period) and outputs the image data delayed by 1H. The delay circuit 623 further delays the image data delayed by 1H by a time of 1H and outputs image data delayed by 2H.

  The lower SF conversion circuit 625 compares the image data delayed by 2H with the image data delayed by 1H. When the image data delayed by 2H is larger than the image data delayed by 1H by a predetermined threshold or more, the lower SF conversion circuit 625 The data of the lower subfield is replaced with the data of the lower subfield of the image data delayed by 1H. At this time, the difference between the image data before replacement and the image data after replacement is output to the adder circuit 621 as error data. The number of lower subfields for replacing data is controlled depending on the output of the comparison circuit 624.

  The comparison circuit 624 compares the power prediction value with a plurality of prediction threshold values, and determines the number of lower subfields in which the lower SF conversion circuit 625 performs image data replacement. For example, when the power prediction value is less than the smallest prediction threshold, the image data is not replaced. When the power prediction value is equal to or greater than the smallest prediction threshold, the number of lower subfields for data replacement is “1”, that is, replacement is performed with the first SF. When the power prediction value is equal to or larger than the next smallest prediction threshold value after the smallest prediction threshold value, the number of lower subfields for data replacement is “2”, that is, the first SF and the second SF are replaced. . Hereinafter, as the predicted power value increases, the number of lower subfields for data replacement is increased.

  11 and 12 are schematic diagrams for explaining the operation of the image conversion circuit 62 of the plasma display device according to the embodiment of the present invention, and show an example of the image signal sig. The numerical value in FIG. 11A indicates the luminance of each pixel, and is an image including a checkered pattern with luminances “2” and “10”. Referring to the coding table shown in FIG. 5, the image data for the first SF is shown in FIG. 11 (b), the image data for the second SF is shown in FIG. 11 (c), the image data for the third SF is shown in FIG. It can be seen that the image data for 4SF is as shown in FIG. Then, the writing patterns of the first SF to the fourth SF also have a checkered pattern, and if the writing operation is performed as it is, the power consumption of the data electrode driving circuit 52 becomes large. However, in the present embodiment, the image conversion circuit 62 converts the image data into image data in which the power consumption of the data electrode driving circuit 52 is reduced. For the description of the operation, the pixels shown in FIG. 11 are called the first row, the second row,... From the top, and the first column, the second column,. It is also assumed that the number of lower subfields for data replacement is two. The operation in the first column will be described below.

  First, the lower SF conversion circuit 625 compares the image data “2” in the first row with the image data “10” in the second row. Then, since the image data on the first line is smaller, the image data “2” on the first line is output as it is. Next, the image data “10” in the second row is compared with the image data “2” in the third row. Then, since the image data in the third row is smaller, each of the first SF and second SF data of the image data “10” in the second row is changed to each of the first SF and second SF data of the image data “2” in the third row. Replace with As a result, the image data “10” in the second row is replaced with “11”. This replacement causes an error “−1”, which is added to the image data “10” in the fourth row by the adder circuit 621. That is, the image data in the fourth row is “9”. Next, the lower SF conversion circuit 625 compares the image data “2” in the third row with the image data “9” in the fourth row. Then, since the image data on the third row is smaller, the image data “2” on the third row is output as it is. Next, the image data “9” in the fourth row is compared with the image data “2” in the fifth row. Then, since the image data in the fifth row is smaller, each of the first SF and second SF data in the image data “9” in the fourth row is changed to each of the first SF and second SF data in the image data “2” in the third row. Replace with As a result, the image data “9” in the second row is replaced with “8”. This replacement causes an error “−1”, and this error is added to the image data of the sixth row by the addition circuit 621.

  By performing such an operation on all the pixels, the image conversion circuit 62 converts the image data shown in FIG. 11A into the image data shown in FIG. The image data for the first SF, the second SF, the third SF, and the fourth SF are shown in FIGS. 12 (b), 12 (c), 12 (d), and 12 (e), respectively. It can be seen that the image data has been converted into small image data.

  In addition, since the image conversion circuit 62 adds the error accompanying the conversion to the image data in the lower row, the average luminance value in the converted area can be maintained. In the above description, the lower SF conversion circuit 625 has been described as replacing the data in the lower subfield regardless of the difference between the image data delayed by 1H and the image data delayed by 2H. However, if data replacement is performed only in a region where the difference between the image data delayed by 1H and the image data delayed by 2H is large, the replacement of the data is difficult to be visually recognized in such a region. Is not greatly impaired.

  The comparison circuit 624 has eight prediction threshold values in the present embodiment, and outputs “1” as the number of the lower subfields described above when the first prediction threshold value is exceeded. When the value is exceeded, “2” is output as the number of lower subfields. Similarly, when the nth prediction threshold is exceeded, “n” is output as the number of lower subfields.

  As described above, the second power reduction unit predicts the power consumption of the data electrode driving circuit 52 and converts the image data into image data with low power consumption. Although the predicted power value obtained by the power prediction circuit 61 does not accurately represent the actual power, the power of the data electrode driving circuit 52 can be reduced by a relatively simple method. Further, the image conversion circuit 62 converts the image data so as not to impair the image display quality as much as possible.

  Next, detailed operations of the first power reduction unit and the second power reduction unit will be described. FIGS. 13 and 14 are diagrams showing an example of the operation of the plasma display device according to the embodiment of the present invention. FIG. 13 shows the data electrode power supply 57 when the power consumption of the data electrode drive circuit 52 changes slowly. It is a figure which shows an example of the change of supplied electric power and an output voltage. When the image signal sig changes and the prediction value of the power prediction circuit 61 increases to exceed the first prediction threshold, the image conversion circuit 62 replaces the first SF of the image data, and the power consumption of the data electrode driving circuit 52 Decreases (time t11 in FIG. 13). When the image signal sig further changes and the prediction value of the power prediction circuit 61 increases to exceed the second prediction threshold, the image conversion circuit 62 replaces the first SF and the second SF of the image data, and the data electrode drive circuit The power consumption of 52 further decreases (time t12 in FIG. 13). As described above, when the power consumption of the data electrode driving circuit 52 changes slowly, the second power reduction unit operates to suppress the power consumption of the data electrode driving circuit 52. However, the power consumption reduction effect of the image conversion circuit 62 is not so great, the power consumption of the data electrode drive circuit 52 is further increased, and the output voltage of the data electrode power source 57 is less than the first voltage threshold. When the detection circuit 58 detects, the write control circuit 59 stops the first SF write operation of the data electrode drive circuit 52 (time t13 in FIG. 13).

  Since the second power reduction unit operates without depending on the operation of the first power reduction unit, as shown in FIG. 13, the image signal sig further changes, and the predicted value of the power prediction circuit 61 increases and the second power reduction unit increases. When the prediction threshold value of 3 is exceeded, the image conversion circuit 62 replaces the third SF in addition to the first SF and the second SF of the image data, and the power consumption of the data electrode driving circuit 52 decreases (time t14 in FIG. 13). Conversely, when the power detection circuit 58 detects that the power consumption of the data electrode drive circuit 52 has decreased and the output voltage of the data electrode power source 57 has become equal to or higher than the second voltage threshold value, the write control circuit 59 The write prohibition of the first SF of the data electrode driving circuit 52 is released (time t15 in FIG. 13). Further, when the image signal sig changes and the prediction value of the power prediction circuit 61 decreases and falls below the third prediction threshold, the image conversion circuit 62 returns the replacement of the image data to only the first SF and the second SF (FIG. 13 time t16).

  As described above, when the power consumption of the data electrode driving circuit 52 changes slowly, the second power reduction unit operates to suppress the power consumption of the data electrode driving circuit 52. If the power consumption of the data electrode drive circuit 52 may increase beyond the power supplied to the data electrode power source 57, the first power reduction means is activated to force the data electrode drive circuit 52 to Reduce power consumption.

  On the other hand, when the power consumption of the data electrode driving circuit 52 suddenly increases, as shown in FIG. 14, the power detection circuit indicates that the output voltage of the data electrode power source 57 is less than the first voltage threshold value. 58 detects. Then, the write control circuit 59 stops the write operation in the first SF of the data electrode drive circuit 52. As a result, the power consumption of the data electrode driving circuit 52 decreases, and the output voltage of the data electrode power source 57 increases. However, if the output voltage of the data electrode power source 57 does not return to the first voltage threshold value or higher, the write control circuit 59 stops the write operation not only in the first SF but also in the second SF. As described above, when the power detection circuit 58 detects that the output voltage of the data electrode power source 57 is less than the first voltage threshold value, the first power reduction means operates, and the data electrode power source 57 quickly Until the output voltage becomes equal to or higher than the first voltage threshold value, the address operation of the data electrode driving circuit 52 is stopped in order from the subfield with the smallest luminance weight (time t21 in FIG. 14).

  Thereafter, the second power reduction unit starts operating with a slight delay, independently of the operation of the first power reduction unit. That is, the predicted value of the power prediction circuit 61 exceeds the first prediction threshold value, and the image conversion circuit 62 replaces the first SF of the image data to reduce the power consumption of the data electrode driving circuit 52 (time t22 in FIG. 14). ). At this time, if the output voltage of the data electrode power supply 57 becomes equal to or higher than the second voltage threshold, the write control circuit 59 cancels the write prohibition of the second SF of the data electrode drive circuit 52 (time t23 in FIG. 14).

  The power prediction circuit 61 operates regardless of the operation of the first power reduction unit, and the predicted value exceeds the second predicted threshold value. Then, the image conversion circuit 62 replaces the first SF and the second SF of the image data, and the power consumption of the data electrode driving circuit is reduced (time t24 in FIG. 14). At this time, if the output voltage of the data electrode power supply 57 becomes equal to or higher than the second voltage threshold value, the write control circuit 59 also cancels the write prohibition of the first SF of the data electrode drive circuit 52 (time t25 in FIG. 14).

  Furthermore, when the predicted value of the power prediction circuit 61 increases to a value corresponding to the image signal sig and exceeds the third prediction threshold, the image conversion circuit 62 replaces the first SF, the second SF, and the third SF of the image data, The power consumption of the data electrode drive circuit 52 decreases (time t26 in FIG. 14).

  Since the detection response speed of the power detection circuit 58 in the present embodiment is faster than the prediction response speed of the power prediction circuit 61, when the power consumption of the data electrode driving circuit 52 increases rapidly in this way, first, The power reduction means operates quickly, and the address operation of the data electrode driving circuit 52 is stopped in order from the subfield with the smallest luminance weight until the output voltage of the data electrode power source 57 becomes equal to or higher than the first voltage threshold value. Then, the second power reduction means operates to convert the image signal processing circuit 51 into an image signal with low power consumption of the data electrode driving circuit 52. At the same time, the first power reduction means operates so as to restart the address operation of the data electrode drive circuit 52.

  As described above, in the present embodiment, the power consumption of the data electrode driving circuit 52 is suppressed by using the first power reduction unit and the second power reduction unit, so that the data display quality is not greatly deteriorated. The design can suppress the power supply amount of the electrode power source 57.

  In the present embodiment, in order to stably operate the first power reduction means that is feedback type control, the power detection circuit 58 is provided with hysteresis characteristics using two voltage thresholds. . However, the present invention is not limited to this. For example, even if the power detection circuit 58 has only one voltage threshold value, it is possible to perform stable power reduction by associating operations of two power reduction means.

  FIG. 15 is a diagram showing an example of the operation of the plasma display device according to another embodiment of the present invention. The power detection circuit 58 compares the output voltage of the data electrode power source 57 with the voltage threshold value, and when the output voltage becomes lower than the voltage threshold value, the write control circuit 59 performs the write operation of the data electrode drive circuit 52. Increase the number of subfields to stop. Then, the power consumption of the data electrode drive circuit 52 decreases and the output voltage of the data electrode power source 57 rises. When the voltage at this time becomes higher than the voltage threshold, the write control circuit 59 stops the write operation. Reduce the number of fields. Then, the power consumption of the data electrode driving circuit 52 increases again, the output voltage of the data electrode power supply 57 becomes lower than the voltage threshold value, and the writing control circuit 59 stops the writing operation of the data electrode driving circuit 52. Increase the number of. As shown in FIG. 15, when the number of subfields for stopping the write operation of the data electrode driving circuit 52 is repeatedly increased and decreased, the write control circuit 59 once sets the number of subfields for which the write operation is stopped. Control not to decrease. Then, when the output voltage of the data electrode power source 57 is higher than the voltage threshold value and the predicted value of the power prediction circuit 61 is decreased by a predetermined value or more, the number of subfields for stopping the write operation is decreased. Thus, the power reduction means can be stably operated.

  The number of subfields for stopping the write operation of the data electrode drive circuit 52 can be increased or decreased by monitoring the output of the power detection circuit 58 using a microcomputer or the like without providing a dedicated circuit. Then, by supplying the result and the output of the power prediction circuit 61 to the write control circuit 59, the above-described control becomes possible.

  In the present embodiment, the data electrode power source is described as being a DC-DC converter that performs pulse-by-pulse control, but the present invention is not limited to this. If the power supply has a characteristic that the output voltage decreases as the supply power increases, the supply power can be known by detecting the voltage.

  Further, the specific numerical values used in the present embodiment are merely examples, and it is desirable to appropriately set the values appropriately according to the characteristics of the panel, the specifications of the plasma display device, and the like.

  Since the plasma display device of the present invention can display an image using a power supply for data electrodes with a reduced power supply, it is useful as a display device used for a wall-mounted television or a large monitor.

The disassembled perspective view which shows the principal part of the panel used for embodiment of this invention. Electrode arrangement of the panel The figure which shows the drive voltage waveform impressed to each electrode of the panel Circuit block diagram of plasma display device in accordance with exemplary embodiment of the present invention The figure which shows the relationship between the image signal of the plasma display apparatus, and the image data for every subfield Circuit diagram of power supply for data electrode of the plasma display device The figure which shows the relationship between the supply current of the power supply for data electrodes of the plasma display apparatus, an output voltage, and the output signal of a power detection circuit Circuit diagram of power detection circuit of plasma display device The figure for demonstrating operation | movement of the electric power prediction circuit of the plasma display apparatus Circuit block diagram showing the configuration of the image conversion circuit of the plasma display device Schematic diagram for explaining the operation of the image conversion circuit of the plasma display device Schematic diagram for explaining the operation of the image conversion circuit of the plasma display device The figure which shows an example of operation | movement of the plasma display apparatus The figure which shows an example of operation | movement of the plasma display apparatus The figure which shows an example of operation | movement of the plasma display apparatus in other embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Plasma display apparatus 10 Panel 22 Scan electrode 23 Sustain electrode 28 Display electrode pair 32 Data electrode 51 Image signal processing circuit 52 Data electrode drive circuit 53 Scan electrode drive circuit 54 Sustain electrode drive circuit 55 Timing generation circuit 57 Data electrode power supply 58 Electric power Detection circuit 59 Write control circuit 61 Power prediction circuit 62 Image conversion circuit 100 DC power supply 110 DC-DC converter 112 Switching element 114 Diode 116 Inductor 118 Smoothing capacitor 120 Output voltage detection unit 122 Current detection circuit 200 Control unit 302 First voltage threshold Value 304, 308 Comparator 306 Second voltage threshold 621 Adder circuit 622, 623 Delay circuit 624 Comparison circuit 625 Lower SF conversion circuit

Claims (4)

A plasma display panel having discharge cells formed at intersections between display electrode pairs and data electrodes, wherein one field period of an image signal is divided into a plurality of subfields, and the discharge cells are caused to emit or not emit light for each subfield. A plasma display device for displaying an image,
A data electrode driving circuit for driving the data electrode for each subfield;
A data electrode power supply for supplying power to the data electrode drive circuit;
An image signal processing circuit for converting the image signal into image data indicating light emission or non-light emission of the discharge cell for each subfield;
The power consumption of the data electrode driving circuit is predicted based on the image data from the image signal processing circuit, and when the predicted value exceeds the prediction threshold, the image data is consumed by the data electrode driving circuit. A plasma display device comprising: an image conversion circuit for converting image data with low power. A power detection circuit for detecting supply power of the data electrode power supply;
2. The plasma according to claim 1, further comprising an address control circuit that stops the operation of the data electrode driving circuit in a predetermined subfield when the power detected by the power detection circuit exceeds a power threshold value. Display device. The image conversion circuit sequentially converts the image data of the subfield with small luminance weight into image data with low power consumption of the data electrode driving circuit,
3. The plasma display device according to claim 2, wherein the address control circuit is configured to stop the operation of the data electrode driving circuit in order from an address period of a subfield with a small luminance weight. The plasma display apparatus of claim 2, wherein a detection response speed of the power detection circuit is faster than a predicted response speed of the power prediction circuit.

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