JP2008039946A - Image display - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve an image quality by suppressing signal potential fluctuations. <P>SOLUTION: The horizontal drive circuit 3 supplies signal voltages matching the image data to each signal line SL at every horizontal cycle. The vertical drive circuit 4 applies control signals WS to the scanning lines WS at every horizontal cycle and selects the pixels 2 on the corresponding lines. The selected pixels 2 change their gradations by the applied signal voltages. A complementary capacitor Csub is connected to each signal line SL to prevent the signal voltages supplied to the signal lines SL from fluctuating by the operation of the horizontal drive circuit 3 or pixels 2. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an active matrix image display apparatus. More specifically, the present invention relates to a technique for improving the image quality of an image display device.

An active matrix type image display device includes a scanning line arranged in a row, a signal line arranged in a column, a pixel that is arranged at a portion where each signal line and the scanning line intersect, and whose gradation changes, It consists of a horizontal drive circuit connected to the signal line and a vertical drive circuit connected to each scanning line. The horizontal drive circuit supplies a signal voltage corresponding to the image data to each signal line every predetermined horizontal period (1H). The vertical drive circuit selects a pixel in a corresponding row by applying a control signal to one scanning line for each horizontal period. The selected pixel changes its gradation in accordance with the signal voltage supplied to the signal line, thereby displaying an image. Typically, each pixel has a light emitting element, and the luminance gradation of the light emitting element changes according to the signal voltage. An image display apparatus having such a configuration is described in, for example, the following Patent Documents 1 to 5.
JP 2003-255856 A JP 2003-271095 A JP 2004-133240 A JP 2004-029791 A JP 2004-093682 A

  The luminance gradation of each pixel is determined by the signal voltage supplied to the signal line. However, the signal potential of the signal line is not always stable and fluctuates under the influence of the operation on the pixel side or the horizontal drive circuit side. The fluctuation of the signal potential varies and adversely affects the image quality, which is a problem to be solved.

  In view of the above-described problems of the conventional technology, an object of the present invention is to improve image quality by suppressing fluctuations in signal potential. In order to achieve this purpose, the following measures were taken. That is, according to the present invention, the scanning lines arranged in rows, the signal lines arranged in columns, the pixels having gradations that are arranged at the intersections of the signal lines and the scanning lines, and the signal lines are arranged. The horizontal driving circuit includes a horizontal driving circuit to be connected and a vertical driving circuit to be connected to each scanning line. The horizontal driving circuit supplies a signal voltage corresponding to image data to each signal line every predetermined horizontal period, and the vertical driving circuit. The circuit applies a control signal to one scanning line every horizontal period to select a pixel in the corresponding row, and the gradation of the selected pixel changes according to the signal voltage supplied to the signal line. A complementary capacitance is connected to each signal line, and the signal voltage supplied to the signal line fluctuates under the influence of the operation on the horizontal drive circuit side or the pixel side. It is characterized by suppressing.

  In one aspect, the horizontal drive circuit is connected to each signal line via a horizontal switch, and opens and closes the horizontal switch for each horizontal period to supply a signal voltage to each signal line. Then, fluctuation of the signal voltage caused by the opening / closing operation of the horizontal switch is suppressed. In another aspect, the pixel includes a sampling switch and a pixel capacitor, the sampling switch is connected between the signal line and the pixel capacitor, and the horizontal driving circuit is configured to output each signal in the horizontal cycle. After supplying the signal voltage to the line, each signal line is electrically disconnected from the horizontal driving circuit, and then the vertical driving circuit outputs the control signal to select the pixel in the corresponding row, and The sampling switch of the pixel is turned on in response to the control signal, performs a write operation that takes in the signal voltage from the signal line and holds it in the pixel capacitor, and the complementary capacitor has the signal voltage generated during the write operation of the sampling switch. Suppress fluctuations. In another aspect, the pixel includes a sampling switch and a correction circuit, and the sampling switch is turned on in response to a control signal to acquire a signal voltage from the signal line, and the correction circuit A signal voltage correction operation is performed, and the complementary capacitor suppresses signal voltage fluctuation caused by the correction operation.

  In the image display device according to the present invention, in addition to the wiring capacitance, a complementary capacitance is actively connected to each signal line. This complementary capacitance can increase the resistance of the signal line to noise. Thus, a phenomenon in which the potential of the signal line fluctuates due to the influence of the operation on the horizontal drive circuit side or the pixel side can be suppressed. Since variations in signal potential are reduced, image quality can be improved.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a schematic plan view showing an example of a general active matrix image display device, and particularly shows an image display device adopting a line sequential drive system. As shown in the figure, this image display device is composed of a flat panel 0 as a whole. On the flat panel 0, the pixel array 1, the selector 3, and the scanner 4 are integrally formed. The panel 0 has a connection terminal 11 and is connected to an external system. The panel 0 is supplied with signals necessary for the operation of the panel 0 such as image data data, a clock signal VCK, and an enable signal ENB from an external system.

  The pixel array 1 includes scanning lines WS arranged in rows, signal lines SL arranged in columns, and pixels 2 having gradations that are arranged and change at portions where the signal lines SL and the scanning lines WS intersect. It consists of

  The selector 3 constitutes a horizontal drive circuit and is connected to each signal line SL. On the other hand, the scanner 4 forms a vertical drive circuit and is connected to each scanning line WS. The selector 3 supplies a signal voltage Vsig corresponding to the image data data to each signal line SL every horizontal period (1H). The scanner 4 selects the pixel 2 in the corresponding row by applying the control signal V to one scanning line WS for each horizontal period. The gradation of the selected pixel 2 changes according to the signal voltage Vsig supplied to the signal line SL. In the figure, the control signal supplied to the n-th scanning line WS is represented by V (n). A signal voltage supplied to the green pixel is represented by Vsig_G. In particular, the signal voltage supplied to the signal line SL in the nth column is represented by Vsig_G (n).

  Each pixel 2 includes a sampling transistor Tr1, a drive transistor Trd, and a light emitting element EL. The gate of the sampling transistor Tr1 is connected to the corresponding scanning line WS, the source is connected to the corresponding signal line SL, and the gate is connected to the gate of the corresponding drive transistor Trd. The drain of the drive transistor Trd is connected to the power supply line Vcc, and the source is connected to the anode of the light emitting element EL. The cathode of the light emitting element EL is connected to the ground potential Vcath.

  FIG. 2 is a circuit diagram showing a connection relationship between the selector 3 and the pixel array 1. On the pixel array 1 side, one trio is composed of three RGB pixels, which are arranged in order. On the other hand, the scanner 3 has three horizontal switches HSW arranged corresponding to one pixel trio. Among the set of three horizontal switches HSW, the left HSW is controlled to be turned on / off by the gate signals sel1 and xsel1. Image data data (n) is supplied to the input side of the HSW, and the output side is connected to the signal line SL. When the HSW is turned on in response to the gate signals sel1 and xsel1, the image data data (n) is supplied to the signal line SL on the output side. At this time, the potential of the signal line is Vsig-R (n). Note that R represents a signal potential assigned to the red pixel. Similarly, the central HSW samples the image data data (n) and supplies Vsig_G (n) to the corresponding signal line. The right HSW also takes in the image data data (n) and supplies the signal voltage Vsig_B (n) to the corresponding signal line SL. B represents a signal voltage supplied to the red pixel. In the figure, for easy understanding, the image data data and the signal voltage Vsig are simply expressed as the same voltage signal. For convenience of explanation, in this specification, the signal voltage before being supplied to the signal line is represented by data, and the voltage signal after being supplied to the signal line is represented by Vsig. Therefore, Vsig represents the actual signal potential of the signal line SL and varies depending on various factors. On the other hand, data is supplied from a source driver (not shown) and is a stable voltage signal.

  FIG. 3 is a timing chart for explaining the operation of the line-sequential image display apparatus shown in FIGS. The scanner 4 is composed of a shift register and operates every horizontal period (1H) in accordance with a clock signal VCK and an enable signal ENB supplied from an external system, and also a start signal (not shown) supplied from the external system. Are sequentially rolled to output a shift signal vsr (n). The scanner 4 further includes an output stage gate circuit, which processes the shift signal vsr (n) with the enable signal ENB and outputs a final control signal V (n) to each scanning line WS.

  On the other hand, the source driver supplies the selector 3 with image data data time-divided into RGB for each horizontal period. In the selector 3, the gate signal sel1 becomes high level when dataR is input, and the HSWs corresponding to the R pixels in the horizontal switch HSW are opened simultaneously. As a result, dataR is written to each R pixel in the selected row all at once. Subsequently, at the timing when dataG is input, the gate signal sel2 becomes high level, the horizontal switches HSW corresponding to the G pixels are simultaneously turned on, and dataG is supplied to the corresponding signal line SL. Subsequently, at the timing when dataB is input from the source driver, the gate signal sel3 becomes high level, the HSWs corresponding to the B pixels are simultaneously turned on, and the dataB is sampled on the corresponding signal line SL.

  FIG. 4 is a schematic circuit diagram showing another example of an active matrix image display device, and particularly shows an analog dot sequential image display device. The difference from the selector line sequential image display apparatus shown in FIG. 1 is that an H scanner 3 a is used instead of the selector 3. In contrast to this, the scanner 4 is particularly described as a V scanner. The H scanner 3a constitutes a horizontal drive circuit, and the V scanner 4 constitutes a vertical drive circuit.

  FIG. 5 is a circuit diagram showing a connection relationship between the H scanner 3 a and the pixel array 1. The H scanner 3a has a set of three horizontal switches HSW corresponding to a trio of RGB 3 pixels. The horizontal scanner 3a further includes a shift register SR for sequentially turning on and off a set of three HSWs. The shift register SR operates in response to a clock signal HCK supplied from an external system, and outputs a control signal H (n) for each stage in order to control on / off of the corresponding HSW.

  Of the set of three HSWs, the left HSW is supplied with the image data dataR on the input side, and the output side is connected to the signal line SL assigned to the R pixel. The left HSW samples the signal voltage dataR and supplies it to the corresponding signal line SL. The potential at this time is represented by Vsig_R (n). Similarly, the central HSW samples dataG and sets the potential of the corresponding signal line SL to Vsig_G (n). The right HSW takes in dataB and sets the potential of the corresponding signal line to Vsig_B (n).

  FIG. 6 is a timing chart for explaining the operation of the V scanner and the H scanner shown in FIGS. The V scanner 4 operates according to VCK and ENB, and sequentially outputs control signals V (n−1), V (n), and V (n + 1) to the corresponding scanning line WS. As a result, pixels for one row are sequentially selected in one horizontal cycle.

  On the other hand, the H scanner 3a operates in response to the clock signal HCK and sequentially outputs horizontal control signals H (1), H (2), H (3). As a result, the horizontal switch HSW is turned on dot-sequentially, dataB, R, and G are supplied to the corresponding signal lines SL dot-sequentially, and further written sequentially to the pixels in the selected row. As is clear from the above description, the selector line sequential image display device writes signal voltages all at once in a row. For this reason, a source driver is required separately. The source driver can have a COG or COF configuration outside the panel 0. Alternatively, a source driver can be incorporated in the panel 0. On the other hand, an analog dot sequential image display apparatus uses an H scanner instead of a selector, and sequentially writes signal voltages to pixels in a selected row within each horizontal period. That is, it is a type that performs drawing by R / G / B analog input. Here, in both the selector line sequential method and the analog dot sequential method, a data line for supplying image data data and a signal line branched from the data line are connected by a horizontal switch HSW. Although the on / off timing of the HSW is different, other operations are the same for the selector line sequential and the analog dot sequential.

  There are roughly three factors that cause fluctuations in the signal voltage Vsig supplied from the data line to the signal line through the horizontal switch HSW. FIG. 7 is a schematic diagram showing the first factor. As shown in the figure, a data line for supplying image data data is connected to a signal line SL via an HSW. The potential of the signal line SL is represented by Vsig, and the wiring capacitance is represented by Csig. HSW is ON / OFF controlled by gate signals hsw and xhsw having opposite polarities. In the case of the selector line sequential method described above, the gate signal hsw is sel (n). In the case of the analog dot sequential method, the gate signal hsw is given as H (n). The HSW is usually composed of a CMoS transistor, and has a parasitic capacitance Chsw between the gate and the drain.

  On the other hand, the pixel 2 is basically composed of a sampling transistor Tr1, a drive transistor Trd, and a light emitting element EL. The normal pixel 2 includes a correction circuit 2a in order to eliminate the influence of variations in threshold voltage and mobility of the drive transistor Trd.

  In the first factor illustrated in FIG. 7, the jump from the HSW gate signals hsw and xhsw affects the signal potential Vsig of the signal line SL. Ideally, the potential defined by data (data potential) and the signal line potential Vsig must be equal. However, actually, there is a jump from the gate signal of HSW, and Vsig deviates from the data potential by ΔVh as shown in the figure. The fluctuation amount of jumping into the signal line SL is given by ΔVh = Vhsw × Chsw / (Chsw + Csig). Here, Vhsw is the amplitude of the gate signal hsw. The variation ΔVh due to the jump is the sum of the jumps from both CMoS transistors constituting the HSW. The variation ΔVh due to the jumping varies for each signal line SL, which causes image quality deterioration.

  FIG. 8 is a schematic diagram showing a second variation factor of Vsig. As shown on the left side of this schematic diagram, the data line is connected to the signal line SL via the HSW. A pixel 2 is connected to the signal line SL. After the data voltage data is written to the signal line SL, the HSW is turned off with the gate signals hsw = LO and xhsw = HI. On the other hand, on the pixel 2 side, the control signal supplied to the scanning line WS becomes HI, the sampling transistor Tr1 is turned on, Vsig is taken in from the signal line SL, and is supplied to the gate G of the drive transistor Trd. The drive transistor Trd causes a drive current to flow from the source S to the light emitting element EL according to Vsig. At this time, the correction circuit 2a corrects the captured signal potential Vsig in order to correct variations in threshold voltage and mobility of the drive transistor Trd. Due to this relationship, the potential of the source S of the drive transistor Trd varies.

  The right side of FIG. 8 is an equivalent circuit diagram of the configuration shown on the left side of FIG. As shown in the figure, HSW is OFF and the sampling transistor Tr1 is expressed by ON resistance. The correction circuit 2a is schematically represented by a simple storage capacitor Cs. The storage capacitor Cs is connected between the gate G and the source S of the drive transistor Trd. The signal potential Vsig written to the signal line SL is held in the holding capacitor Cs via the sampling transistor Tr1, and the gate G of the drive transistor Trd is fixed to a predetermined potential VG0. Ideally, this gate potential VG0 should be maintained as it is. However, the node S of the drive transistor Trd may rise due to the operation of the correction circuit 2a. Under this influence, the node G of the drive transistor Trd rises by ΔVs. This increase in ΔVs affects the signal line SL via the on-resistance of the sampling transistor Tr1. The influence on the signal line is ΔVs = Vs × Cs / (Cs + Csig). Vs is the fluctuation of the node S that appears during the correction operation.

  FIG. 9 is a schematic diagram showing a third variation factor of the signal potential Vsig. As shown on the left side of this schematic diagram, the data line for supplying data data is connected to the signal line SL via the HSW. A pixel 2 is connected to the signal line SL. The pixel 2 includes a pixel capacitor Cg in addition to the sampling transistor Tr1, the drive transistor Trd, and the light emitting element EL. This pixel capacitance Cg is for taking in and holding the signal potential Vsig via the sampling transistor Tr1 that is turned on.

  A timing chart of this configuration is shown on the lower right side of FIG. First, the gate signal HSW becomes high level, the HSW is turned on, and the data voltage Vdata is taken into the signal line SL. As a result, the signal potential Vsig of the signal line becomes equal to the data voltage Vdata. At this time, the node G of the drive transistor Trd is at a predetermined potential VG0. Thereafter, the control signal supplied to the scanning line WS becomes high level, and the sampling transistor Tr1 is turned on. As a result, the signal potential Vsig is sampled from the signal line SL, and the determined potential of the node G becomes VG. Ideally, the definite potential VG of the node G should be equal to Vsig, but changes by ΔVG due to capacitive coupling of the wiring capacitance Csig and the pixel capacitance Cg. The determined potential of the node G changed from the ideal state is given by VG = (Csig · Vdata + Cg · Vg0) / (Csig + Cg). Here, VG0 is an initial voltage of the node G.

  FIG. 10 is a schematic diagram showing a main part of the image display apparatus according to the present invention. As shown in the figure, the image display device according to the present invention is provided with a complementary capacitance Csub in addition to the wiring capacitance Csig of the signal line SL itself. The complementary capacitor Csub increases the resistance to noise of the signal line SL, and the signal potential Vsig written from the data line to the signal line SL via the horizontal switch HSW can be stably maintained. By connecting the complementary capacitor Csub to the signal line SL, the signal voltage Vsig supplied to the signal line SL varies under the influence of the operation on the horizontal drive circuit side including the horizontal switch HSW or the pixel 2 side including the correction circuit 2a. To suppress the phenomenon.

By adding the complementary capacitance Csub, the fluctuation due to the jump from the gate pulse of the horizontal switch HSW described above is expressed as follows.
ΔVh = Vhsw × Chsw / ((Chsw + (Csig + Csub))
By adding Csub, the denominator Csig becomes Csig + Csub. By making Csig + Csub sufficiently larger than the parasitic capacitance Chsw of the horizontal switch HSW, the variation ΔVh can be brought close to zero. In practice, the capacitance of Csub may be designed so that Csig + Csub is 5 times or more of Chsw.

Further, the fluctuation due to the rise of the node S on the pixel circuit 2 side is expressed as follows.
ΔVs = Vs × Cs / ((Cs + (Csig + Csub))
In this case as well, the variation ΔVs can be brought close to 0 by setting Csig + Csub to be larger than the holding capacitor Cs on the correction circuit 2a side. Practically, the capacitance of Csub may be set so that the sum of Csig and Csub is 5 times or more with respect to the holding capacitor Cs.

The definite potential of the gate node when there is capacitive coupling is expressed by the following equation.
VG = ((Csig + Csub) .Vdata + Cs.VG0)) /
((Csig + Csub) + Cg))
Here, by taking Csig + Csub to be larger than the pixel capacitance Cg, the term of Cg in the numerator and denominator of the above equation can be ignored. As a result, VG = Vdata is obtained, and the influence of capacitive coupling can be suppressed, and the potential VG of the gate node can be made substantially the value of the data voltage Vdata. In this way, in order to maintain the gate node potential VG substantially equal to Vdata, the value of Csub may be set so that the sum of Csig and Csub is 5 times or more than Cg.

  As described above, in the image display device according to the present invention, the scanning lines WS arranged in rows, the signal lines SL arranged in columns, and the signal lines SL and the scanning lines WS intersect each other. The pixel 2 is arranged in a portion and changes in gradation, a horizontal driving circuit 3 connected to each signal line, and a vertical driving circuit 4 connected to each scanning line WS. The horizontal drive circuit 3 supplies a signal voltage Vsig corresponding to the image data data to each signal line SL every predetermined horizontal period (1H). The vertical drive circuit 4 applies the control signal WS to one scanning line WS for each horizontal period, and selects the pixels 2 in the corresponding row. Note that in this specification, the scanning lines WS and their control signals are denoted by the same reference numerals in order to simplify the notation. . The gradation of the selected pixel 2 changes according to the signal voltage Vsig supplied to the signal line SL.

  As a feature of the present invention, a complementary capacitor Csub is connected to the signal line SL, and the signal voltage Vsig supplied to the signal line SL varies due to the influence of the operation on the horizontal drive circuit 4 side or the pixel 2 side. Suppress. For example, the horizontal drive circuit 3 is connected to each signal line SL via a horizontal switch HSW, and supplies the signal voltage Vsig to each signal line SL by opening and closing the horizontal switch HSW every horizontal period. The complementary capacitor Csub suppresses the fluctuation ΔVh of the signal voltage Vsig caused by the opening / closing operation of the horizontal switch HSW.

  In one aspect, the pixel 2 includes a sampling transistor Tr1 serving as a sampling switch and a pixel capacitor Cg. The sampling transistor Tr1 is connected between the signal line SL and the pixel capacitor Cg. The horizontal driving circuit 3 supplies the signal voltage Vsig to each signal line SL in the horizontal period, and then electrically disconnects each signal line SL from the horizontal driving circuit 3. Thereafter, the vertical drive circuit 4 outputs a control signal WS to select the pixels 2 in the corresponding row. The sampling transistor Tr1 of the pixel 2 in the selected row is turned on in response to the control signal WS, and performs a writing operation of taking in the signal voltage Vsig from the signal line SL and holding it in the pixel capacitor Cg. The complementary capacitor Csub suppresses the fluctuation ΔVG of the signal voltage Vsig that occurs during the write operation of the sampling transistor Tr1.

  In another aspect, the pixel 2 includes a sampling transistor Tr1 and a correction circuit 2a that form a sampling switch. The sampling transistor Tr1 is turned on according to the control signal WS and takes in the signal voltage Vsig from the signal line SL. The correction circuit 2a performs a correction operation on the captured signal voltage Vsig. The complementary capacitor Csub can suppress the fluctuation ΔVs of the signal voltage Vsig caused by this correction operation.

  FIG. 11 is a schematic diagram corresponding to the circuit configuration and device structure of the image display apparatus according to the present invention. In terms of circuit, in the present image display device, the data line is connected to the signal line SL via the horizontal switch HSW. The pixel 2 and the complementary capacitor Csub are connected to the signal line SL. The pixel 2 basically includes a transistor Tr such as a sampling transistor Tr1 or a drive transistor Trd and a light emitting element EL.

  The right side of FIG. 11 is a schematic diagram showing device structures of the transistor Tr and the light emitting element EL. In this embodiment, the transistor Tr and the light emitting element EL are formed of thin film elements. Specifically, after a transistor Tr of a thin film element is formed on an insulating substrate such as glass, a light emitting element EL of the same thin film element is formed thereon via an insulating film. As shown in the drawing, the light-emitting element EL is composed of a cathode and an anode, and an insulating film is disposed between the cathode and the anode. The light emitting element EL has a diode structure, and for example, an organic electroluminescence material is used as the light emitting material. On the other hand, the transistor Tr is a thin film transistor (TFT) having polysilicon (PS) as an element region. The source electrode and drain electrode of the TFT are made of metallic aluminum (Al). A polysilicon film (PS) serving as a TFT element region is formed under the insulating film. Further below, metal molybdenum (Mo) is formed as a gate electrode of the TFT through an insulating film. The signal line SL is usually made of a metal aluminum layer or a metal molybdenum layer having a low wiring resistance. With such a multilayer structure, the complementary capacitor Csub is formed together with the transistor Tr and the like using an insulating film as a dielectric.

  FIG. 12 is a schematic cross-sectional view showing an embodiment of the complementary capacitor. In this embodiment, the signal line SL is made of metal aluminum wiring. The floating cathode layer (Cathode) and the metal molybdenum layer (Mo) are brought to the same potential by making contact with the aluminum wiring. On the other hand, the floating anode layer (Anode) and the polysilicon layer (PS) are suspended at a fixed potential. With this configuration, the first complementary capacitor Csub1 is formed between the cathode and the anode, the second complementary capacitor Csub2 is formed between the anode and the aluminum wire, and between the aluminum wire and the polycrystalline silicon film PS. A third complementary capacitor Csub3 is formed, and finally a fourth complementary capacitor Csub4 is formed between the polycrystalline silicon film PS and the metal molybdenum film (Mo). The total complementary capacitance Csub is the sum of Csub1, Csub2, Csub3 and Csub4, and a large capacitance value is obtained.

  FIG. 13 is a schematic cross-sectional view showing another embodiment of the complementary capacitor. In this embodiment, a metal molybdenum film is used for the signal line SL. In this case, the floating cathode and aluminum wiring are brought to the same potential by contacting the molybdenum wiring. The floating Anode and the polycrystalline silicon film PS are suspended at a fixed potential. With this configuration, the complementary capacitors Csub1 to Csub4 can be formed by using the insulating film of each layer as a dielectric.

  FIG. 14 is a schematic diagram showing another embodiment of the complementary capacity. Basically, the capacitance value of the complementary capacitance Csub may be determined according to the size required in design. Practically, this embodiment is preferable. In this embodiment, metal aluminum is used as the signal line SL, and the anode and the metal molybdenum film are set to the same potential as the signal line SL, while the cathode and the polycrystalline silicon film PS are suspended at a fixed potential. As a result, three complementary capacitors Csub1, Csub3, and Csub4 can be produced.

  FIG. 15 is a block diagram showing the overall configuration of an embodiment of the image display apparatus according to the present invention. As shown in the figure, this image display apparatus basically includes a pixel array unit 1, a scanner unit, and a signal unit. The pixel array unit 1 includes first scanning lines WS, second scanning lines AZ2, third scanning lines AZ1, and fourth scanning lines DS arranged in rows, signal lines SL arranged in columns, and scanning of these. A matrix pixel circuit 2 connected to the lines WS, AZ2, AZ1, DS and the signal line SL, and a plurality of first potentials Vofs, second potentials Vini, and third potentials Vcc necessary for the operation of each pixel circuit 2. Power line. The signal unit includes a horizontal selector 3 and supplies a video signal to the signal line SL. In accordance with the present invention, a complementary capacitor Csub is connected to each signal line SL. The scanner unit includes a write scanner 4, a drive scanner 5, a first correction scanner 71, and a second correction scanner 72. The first scan line WS, the fourth scan line DS, the third scan line AZ1, and the second scan, respectively. A control signal is supplied to the line AZ2 to sequentially scan the pixel circuit for each row.

  FIG. 16 is a circuit diagram showing a specific configuration of pixels included in the image display apparatus shown in FIG. As illustrated, the pixel circuit 2 includes a sampling transistor Tr1, a drive transistor Trd, a first switching transistor Tr2, a second switching transistor Tr3, a third switching transistor Tr4, a holding capacitor Cs, and a complementary capacitor Csub. A light emitting element EL. The sampling transistor Tr1 conducts according to a control signal supplied from the first scanning line WS during a predetermined sampling period, and samples the signal potential of the video signal supplied from the signal line SL into the holding capacitor Cs. The storage capacitor Cs applies the input voltage Vgs to the gate G of the drive transistor Trd in accordance with the signal potential of the sampled video signal. The drive transistor Trd supplies an output current Ids corresponding to the input voltage Vgs to the light emitting element EL. The light emitting element EL emits light with a luminance corresponding to the signal potential of the video signal by the output current Ids supplied from the drive transistor Trd during a predetermined light emission period.

  The first switching transistor Tr2 is turned on in response to a control signal supplied from the second scanning line AZ2 prior to the sampling period, and sets the gate G of the drive transistor Trd to the first potential Vofs. The second switching transistor Tr3 is turned on according to a control signal supplied from the third scanning line AZ1 prior to the sampling period, and sets the source S of the drive transistor Trd to the second potential Vini. The third switching transistor Tr4 is turned on in response to a control signal supplied from the fourth scanning line DS prior to the sampling period to connect the drive transistor Trd to the third potential Vcc, and thus to the threshold voltage Vth of the drive transistor Trd. The corresponding voltage is held in the holding capacitor Cs to correct the influence of the threshold voltage Vth. Further, the third switching transistor Tr4 conducts again in response to the control signal supplied from the fourth scanning line DS during the light emission period, connects the drive transistor Trd to the third potential Vcc, and causes the output current Ids to flow through the light emitting element EL. .

As is apparent from the above description, the pixel circuit 2 includes five transistors Tr1 to Tr4 and Trd, two capacitors Cs and Csub, and one light emitting element EL. The transistors Tr1 to Tr3 and Trd are N channel type polysilicon TFTs. Only the transistor Tr4 is a P-channel type polysilicon TFT. However, the present invention is not limited to this, and N-channel and P-channel TFTs can be mixed as appropriate. The light emitting element EL is, for example, a diode type organic EL device having an anode and a cathode. However, the present invention is not limited to this, and the light emitting element generally includes all devices that emit light by current drive.

  FIG. 17 is a schematic diagram in which only the pixel circuit 2 is extracted from the image display apparatus shown in FIG. In order to facilitate understanding, the video signal Vsig sampled by the sampling transistor Tr1, the input voltage Vgs and output current Ids of the drive transistor Trd, and the capacitance component Coled of the light emitting element EL are added. Hereinafter, the operation of the pixel circuit 2 according to the present embodiment will be described with reference to FIG.

  FIG. 18 is a timing chart of the pixel circuit shown in FIG. The operation of the pixel circuit shown in FIG. 17 will be described with reference to FIG. FIG. 18 shows the waveforms of control signals applied to the scanning lines WS, AZ2, AZ1, and DS along the time axis T. In order to simplify the notation, the control signals are also represented by the same reference numerals as the corresponding scanning lines. Since the transistors Tr1, Tr2, and Tr3 are N-channel type, they are turned on when the scanning lines WS, AZ2, and AZ1 are at a high level and turned off when the scanning lines are at a low level. On the other hand, since the transistor Tr4 is a P-channel type, it is turned off when the scanning line DS is at a high level and turned on when it is at a low level. This timing chart also shows the change in the potential of the gate G and the change in the potential of the source S of the drive transistor Trd, along with the waveforms of the control signals WS, AZ1, AZ2, and DS.

  In the timing chart of FIG. 18, the state change of each control signal that appears during one field is represented by timings T1 to T7. Each row of the pixel array is sequentially scanned once during one field. The timing chart represents the waveforms of the control signals WS, AZ1, AZ2, and DS applied to the pixels for one row.

  At timing T0 before the field starts, the control signals WS, AZ2, and AZ1 are at a low level. Therefore, the N-channel transistors Tr1, Tr2, Tr3 are in an off state. Further, the control signal DS is at a high level. Therefore, the P-channel transistor Tr4 is also off. Accordingly, at the timing T0, all the transistors Tr1 to Tr4 are in an off state. At this time, the gate G (hereinafter sometimes referred to as the node G) and the source S (hereinafter sometimes referred to as the node S) of the drive transistor Trd hold a certain potential as shown in the figure. Since it is off, the circuit is floating.

  At the timing T1 when the field starts, the control signal AZ1 becomes high level, so that the switching transistor Tr3 is turned on. As a result, the source S of the drive transistor Trd is connected to the reference potential Vini. That is, the potential of the node S rapidly decreases to Vini. At this time, since the node G is a floating potential, the potential of the node G decreases to VF due to the influence of the rapid decrease in the potential of the node S.

  At timing T2 when the period F has elapsed from timing T1, the control signal AZ2 rises and the switching transistor Tr2 is turned on. As a result, the gate G of the drive transistor Trd is connected to the reference potential Vofs. At this stage, the node S is already connected to the reference potential Vini. Here, Vofs−Vini> Vth is satisfied, and by setting Vofs−Vini = Vgs> Vth, preparation for Vth correction performed at timing T3 is performed. In other words, the period T1-T3 corresponds to a reset period of the drive transistor Trd. When the threshold voltage of the light emitting element EL is VthEL, VthEL> Vini is set. Thereby, a minus bias is applied to the light emitting element EL, and a so-called reverse bias state is obtained. This reverse bias state is necessary for normally performing the Vth correction operation and the mobility correction operation to be performed later.

  At timing T3, the control signal AZ1 is set to the low level, and the control signal DS is also set to the low level. As a result, the transistor Tr3 is turned off while the transistor Tr4 is turned on. As a result, the drain current Ids flows into the storage capacitor Cs, and the Vth correction operation is started. At this time, the gate G of the drive transistor Trd is held at Vofs, and the current Ids flows until the drive transistor Trd is cut off. When cut off, the source potential (S) of the drive transistor Trd becomes Vofs−Vth. At timing T4 after the drain current is cut off, the control signal DS is returned to the high level again, and the switching transistor Tr4 is turned off. Further, the control signal AZ2 is also returned to the low level, and the switching transistor Tr2 is also turned off. As a result, Vth is held and fixed in the holding capacitor Cs. Thus, the timing T3-T4 is a period for detecting the threshold voltage Vth of the drive transistor Trd. Here, this detection period T3-T4 is called a Vth correction period.

  After performing the Vth correction in this way, the control signal WS is switched to the high level at timing T5, the sampling transistor Tr1 is turned on, and the video signal Vsig is written in the storage capacitor Cs. The storage capacitor Cs is sufficiently smaller than the equivalent capacitor Coled of the light emitting element EL. As a result, most of the video signal Vsig is written in the storage capacitor Cs. To be precise, for Vofs. The difference Vsig−Vofs of Vsig is written in the storage capacitor Cs. Therefore, the voltage Vgs between the gate G and the source S of the drive transistor Trd becomes a level (Vsig−Vofs + Vth) obtained by adding Vth previously detected and held and Vsig−Vofs sampled this time. For simplification of explanation, if Vofs = 0 V, the gate-source voltage Vgs becomes Vsig + Vth as shown in the timing chart of FIG. The sampling of the video signal Vsig is performed until timing T7 when the control signal WS returns to the low level. That is, the timing T5-T7 corresponds to the sampling period.

  At timing T6 before the end of the sampling period T7, the control signal DS becomes low level and the switching transistor Tr4 is turned on. As a result, the drive transistor Trd is connected to the power supply Vcc, so that the pixel circuit proceeds from the non-light emitting period to the light emitting period. In this manner, the mobility correction of the drive transistor Trd is performed in the period T6-T7 in which the sampling transistor Tr1 is still on and the switching transistor Tr4 is on. That is, in this example, the mobility correction is performed in a period T6-T7 in which the rear part of the sampling period and the head part of the light emission period overlap. Note that, at the beginning of the light emission period in which the mobility correction is performed, the light emitting element EL is actually in a reverse bias state, and thus does not emit light. In the mobility correction period T6-T7, the drain current Ids flows through the drive transistor Trd while the gate G of the drive transistor Trd is fixed at the level of the video signal Vsig. Here, by setting Vofs−Vth <VthEL, the light emitting element EL is placed in a reverse bias state, so that it exhibits simple capacitance characteristics instead of diode characteristics. Therefore, the current Ids flowing through the drive transistor Trd is written to the capacitor C = Cs + Coled obtained by combining both the storage capacitor Cs and the equivalent capacitor Coled of the light emitting element EL. As a result, the source potential (S) of the drive transistor Trd increases. In the timing chart of FIG. 18, this rise is represented by ΔV. Since this increase ΔV is eventually subtracted from the gate / source voltage Vgs held in the holding capacitor Cs, negative feedback is applied. In this way, the mobility μ can be corrected by negatively feeding back the output current Ids of the drive transistor Trd to the input voltage Vgs of the drive transistor Trd. The negative feedback amount ΔV can be optimized by adjusting the time width t of the mobility correction period T6-T7.

At timing T7, the control signal WS becomes low level and the sampling transistor Tr1 is turned off. As a result, the gate G of the drive transistor Trd is disconnected from the signal line SL. Since the application of the video signal Vsig is cancelled, the gate potential (G) of the drive transistor Trd can be increased and increases with the source potential (S). Meanwhile, the gate / source voltage Vgs held in the holding capacitor Cs maintains a value of (Vsig−ΔV + Vth). As the source potential (S) rises, the reverse bias state of the light emitting element EL is canceled, so that the light emitting element EL actually starts to emit light by the inflow of the output current Ids. The relationship between the drain current Ids and the gate voltage Vgs at this time is given by the following equation by substituting Vsig−ΔV + Vth into Vgs of the basic characteristic equation of the transistor.
Ids = kμ (Vgs−Vth) ² = kμ (Vsig−ΔV) ²
In the above formula, k is a constant. From this characteristic equation, it can be seen that the term Vth is canceled and the output current Ids supplied to the light emitting element EL does not depend on the threshold voltage Vth of the drive transistor Trd. Basically, the drain current Ids is determined by the signal voltage Vsig of the video signal. In other words, the light emitting element EL emits light with a luminance corresponding to the video signal Vsig. At that time, Vsig is corrected by the negative feedback amount ΔV. This correction amount ΔV works so as to cancel the effect of mobility μ located just in the coefficient part of the characteristic equation. Therefore, the drain current Ids substantially depends only on the video signal Vsig. Thereafter, when a predetermined timing is reached, the control signal DS becomes high level, the switching transistor Tr4 is turned off, the light emission ends, and the field ends. In other words, the sequence of FIG. 18 returns to the timing T0. Thereafter, the process proceeds to the next field, and the Vth correction operation, the mobility correction operation, and the light emission operation are repeated again.

  As described above, the image display apparatus according to the present embodiment performs the mobility correction operation in the period T6-T7. This mobility correction operation needs to be performed in a state where the potential of the node G is fixed to Vsig, and the potential of the node S increases by a predetermined correction amount ΔV due to negative feedback of the drive current that flows during the correction period. In the present invention, a complementary capacitor Csub is connected to the signal line SL. Therefore, even if the node S rises by ΔV, the node G hardly changes and is fixed at Vsig. Thereby, a normal mobility correction operation can be performed. If the complementary capacitor Csub is not connected to the signal line SL, the potential at the node G also fluctuates due to the rise in the potential at the node S, and the mobility cannot be corrected correctly.

It is a block diagram which shows an example of a general image display apparatus. FIG. 2 is a circuit connection diagram of the image display device shown in FIG. 1. 2 is a timing chart for explaining operations of the image display apparatus shown in FIG. 1. It is a block diagram which shows the other example of a general image display apparatus. It is a wiring diagram of the image display apparatus shown in FIG. 5 is a timing chart for explaining the operation of the image display apparatus shown in FIG. 4. It is a schematic diagram which shows the 1st variation factor of a signal potential. It is a schematic diagram which shows the 2nd variation factor of a signal potential. It is a schematic diagram which shows the 3rd variation factor of a signal potential. It is a schematic diagram showing the principle of the present invention. FIG. 3 is a schematic diagram comparing a circuit configuration and a device configuration of the image display apparatus according to the present invention. It is a schematic diagram which shows an example of the complementary capacity | capacitance formed in the image display apparatus concerning this invention. It is a schematic diagram which similarly shows the other example of a complementation capacity | capacitance. It is a schematic diagram which similarly shows another example of a complementary capacity | capacitance. 1 is a block diagram illustrating an overall configuration of an embodiment of an image display device according to the present invention. FIG. 16 is a circuit diagram illustrating a configuration of a pixel included in the image display device illustrated in FIG. 15. FIG. 17 is a schematic diagram for explaining an operation of the image display apparatus illustrated in FIGS. 15 and 16. 6 is a timing chart for explaining the operation.

Explanation of symbols

0 ... panel, 1 ... pixel array, 2 ... pixel, 3 ... selector, 4 ... scanner, SL ... signal line, WS ... scanning line, EL ... light emission Element, Csub ... complementary capacitance

Claims (4)

Scanning lines arranged in rows, signal lines arranged in columns, pixels having gradations which are arranged and change at portions where each signal line and scanning line intersect, and a horizontal drive circuit connected to each signal line And a vertical drive circuit connected to each scanning line,
The horizontal drive circuit supplies a signal voltage corresponding to image data to each signal line every predetermined horizontal period,
The vertical driving circuit selects a pixel in a corresponding row by applying a control signal to one scanning line for each horizontal period,
The selected pixel is an image display device whose gradation changes according to the signal voltage supplied to the signal line,
An image is characterized in that a complementary capacitor is connected to each signal line and suppresses a phenomenon in which the signal voltage supplied to the signal line fluctuates due to the operation of the horizontal drive circuit side or the pixel side. Display device. The horizontal drive circuit is connected to each signal line via a horizontal switch, and opens and closes the horizontal switch for each horizontal cycle to supply a signal voltage to each signal line,
The image display device according to claim 1, wherein the complementary capacitor suppresses a change in the signal voltage caused by an opening / closing operation of the horizontal switch. The pixel has a sampling switch and a pixel capacity,
The sampling switch is connected between the signal line and the pixel capacitor,
The horizontal driving circuit, after supplying a signal voltage to each signal line in the horizontal cycle, electrically disconnects each signal line from the horizontal driving circuit,
Thereafter, the vertical drive circuit outputs the control signal to select the corresponding row of pixels,
The sampling switch of the pixel in the selected row is turned on in response to the control signal, performs a write operation of taking a signal voltage from the signal line and holding it in the pixel capacitor,
The image display device according to claim 1, wherein the complementary capacitor suppresses a variation in the signal voltage that occurs during a write operation of the sampling switch. The pixel has a sampling switch and a correction circuit,
The sampling switch is turned on according to the control signal and takes in the signal voltage from the signal line,
The correction circuit performs a correction operation of the captured signal voltage,
The image display apparatus according to claim 1, wherein the complementary capacitor suppresses a variation in signal voltage caused by the correction operation.

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