JP2008035694A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device such as an RFID or the like which can easily generate an arbitrary stable power supply potential. <P>SOLUTION: A circuit constituting the semiconductor device is classified according to whether an arbitrary stable power supply potential is required or not. The power supply potential which is generated using an antenna and a rectifying circuit from a wireless signal received from the antenna via a regulator is supplied to the circuit which requires the arbitrary stable power supply potential. On the other hand, the power supply potential which is generated by the rectifying circuit is supplied to the circuits other than the circuit which requires the arbitrary stable power supply potential. Thereby, the semiconductor device which has a regulator circuit small in a layout area and easy for design can be provided, allowing the semiconductor device to easily generate the arbitrary stable power supply potential. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device such as an RFID formed on a glass substrate or a flexible substrate. The present invention also relates to a semiconductor device that performs non-contact communication.

In recent years, individual identification technology using wireless communication such as electromagnetic fields or radio waves has attracted attention. In particular, as a semiconductor device that communicates data by wireless communication, an individual identification technique using an RFID (Radio Frequency Identification) tag has attracted attention. An RFID tag (hereinafter simply referred to as RFID) is also called an IC (Integrated Circuit) tag, an RF tag, a wireless tag, an electronic tag, an IC chip, or a wireless chip. Individual identification technology using RFID has begun to be used for production and management of individual objects, and is expected to be applied to personal authentication.

Some RFIDs do not have a power supply and can be driven by using electric waves or electromagnetic power from the outside. Such an RFID generates a DC voltage from a signal such as an external radio wave or electromagnetic wave using a rectifier, and further operates using a voltage dropped to a certain value or less via a regulator such as a regulator (for example, Non-Patent Document 1).
"RFID Handbook 2nd Edition, Principles and Applications of Contactless IC Cards", Nikkan Kogyo Shimbun, Klaus Finkenzeller, Translated by Software Engineering Laboratory, p69-71

  FIG. 17 shows a circuit configuration of such a conventional RFID. The RFID illustrated in FIG. 17 includes an antenna 1001, a rectifier circuit 1002, a regulator circuit 1003, and a circuit group 1004 constituting the RFID including other clock generation circuits, logic circuits, and the like. Note that when the RFID is operated, in order to supply a stable DC voltage below a certain level to all the circuits included in the circuit group 1004, the area occupied by the regulator circuit 1003 increases, and the design thereof is difficult.

Communication between the RFID and the reader / writer is controlled by a clock. That is, if the clock frequency fluctuates during operation, the RFID cannot correctly interpret commands and data from the reader / writer to the RFID. If the clock frequency fluctuates during operation, the response from the RFID to the reader / writer cannot be correctly interpreted on the reader / writer side.

The clock is generated from a radio signal. If the transistors constituting the RFID circuit sufficiently follow the frequency of the carrier wave of the radio signal, a clock is generated by directly dividing the carrier wave by the RFID circuit. When the transistors included in the RFID circuit do not operate sufficiently at the frequency of the carrier wave of the radio signal, a clock is generated by a method such as self-oscillation in the RFID circuit and synchronization with the radio signal. Note that when the RFID circuit self-oscillates, the power supply of the oscillation circuit is a power supply potential generated by the RFID. Therefore, a regulator circuit is used so that the power supply potential does not change, and the power supply potential is converted into an arbitrary potential.

  By the way, a logic circuit synchronized with a clock easily changes its power supply potential because the state in the logic circuit changes all at once when the clock potential changes. In this specification, power supply noise means that a power supply potential for supplying power to a circuit changes due to circuit operation. If the power consumption of a circuit that uses the output of the regulator circuit as a power supply potential is large, the regulator circuit must change a large amount of power in order to suppress power supply noise, and the design of the regulator circuit becomes more difficult.

  In view of the above problems, the present invention provides a semiconductor device such as an RFID equipped with a regulator circuit that is easy to design while supplying a stable power supply to a circuit that requires an arbitrary stable power supply potential such as a clock generation circuit. This is the issue.

  The circuits constituting the semiconductor device are classified according to whether or not an arbitrary stable power supply potential is necessary, a circuit that requires an arbitrary stable power supply potential is defined as a first circuit, and a circuit other than the first circuit is defined as a second circuit. Circuit. A power supply potential generated by using an antenna and a rectifier circuit from a radio signal received from the antenna is supplied to the first circuit via a regulator. That is, the output of the regulator circuit is supplied as a power supply potential to at least a first circuit that requires an arbitrary stable power supply potential, and a circuit other than a circuit that requires an arbitrary power supply potential, that is, a second circuit is generated by a rectifier circuit The power supply potential is supplied.

With such a configuration, the regulator circuit can be easily designed with a layout area smaller than that of the conventional regulator circuit configuration. Further, power consumption in the regulator circuit can be reduced.

One aspect of the present invention includes an antenna that transmits and receives signals, a rectifier circuit, a regulator circuit, a first circuit, and a second circuit that transmits and receives signals to and from the first circuit. The circuit is a circuit that requires an arbitrary stable potential, and the power supply potential generated by the antenna and the rectifier circuit is supplied to the first circuit and the second circuit, and the first circuit The semiconductor device is characterized in that the power supply potential is supplied through the regulator circuit.

According to one aspect of the present invention, an antenna that transmits and receives a signal, a rectifier circuit, a first regulator circuit, a second regulator circuit, a first circuit, and a second circuit that exchanges signals with the first circuit. The first circuit is a circuit that requires an arbitrary stable potential, and the first circuit includes the antenna and the rectifier circuit through the first regulator circuit. In the semiconductor device, the generated power supply potential is supplied, and the power supply potential generated by the antenna and the rectifier circuit is supplied to the second circuit through the second regulator circuit. is there.

  The first regulator circuit and the second regulator circuit may have the same circuit configuration or different circuit configurations. Further, when the circuit configuration is the same, the sizes of the elements constituting the first regulator circuit and the second regulator circuit may be the same or different. Even if the circuit configuration and the element size are the same, the regulator circuit can be more easily designed by changing the load. In this case, the stability of the first regulator circuit is designed better than that of the second regulator circuit.

One aspect of the present invention includes an antenna that transmits and receives signals, a rectifier circuit, a regulator circuit, a voltage limiter circuit, a first circuit, and a second circuit that exchanges signals with the first circuit. The first circuit is a circuit that requires an arbitrary stable potential, and the power supply potential generated by the antenna and the rectifier circuit is supplied to the first circuit via the regulator circuit. In the semiconductor device, the second circuit is supplied with a power supply potential generated by the antenna and the rectifier circuit through the voltage limiter circuit.

In the above configuration, the first circuit is a clock generation circuit, but is not limited thereto. For example, when the sensor potential is detected by an AD converter circuit, fluctuations in the power supply potential of the AD converter circuit hinder accurate reading of the sensor potential. Therefore, the AD converter circuit is a circuit that requires an arbitrary stable power supply potential. It can be said that there is a first circuit. Thus, the first circuit is a circuit that requires an arbitrary stable power supply potential. The second circuit is a logic circuit for interpreting and responding to a radio signal, for example.

The exchange of signals between the first circuit and the second circuit may be performed via a level shifter circuit.

  The RFID may have a rewritable built-in ROM. Note that in the built-in ROM, a circuit that requires an arbitrary potential belongs to the first circuit, and circuits other than the first circuit belong to the second circuit.

  Note that RFID not only generates a power source from a signal received by an antenna, but also extracts a radio signal. A power supply potential generated by a rectifier circuit may be used in an analog circuit that extracts a radio signal. However, in the present invention, the circuit using the potential generated by the rectifier circuit as a power source, that is, the first circuit and the second circuit are not limited to a part of the elements, but more effective when targeting a large number of elements. Is.

  In this specification, in a potential difference generated by an RFID and supplied to a circuit, a lower potential is referred to as a ground, and a higher potential is referred to as a power supply with respect to the reference. It is assumed that the ground is common to each circuit, and the present invention will be described with respect to the power supply. Conversely, the present invention may be applied with a higher potential difference as a reference common to each circuit. Further, although the potential of the power supply line may vary depending on the location due to parasitic resistance, a power supply line that is not separated by a transistor or a capacitor is regarded as one type of power supply.

  In the present invention, the transistor is not particularly limited. Thin film transistors (TFTs) using non-single crystal semiconductor films typified by amorphous silicon and polycrystalline silicon, transistors formed using semiconductor substrates and SOI substrates, MOS transistors, junction transistors, bipolar transistors, ZnO Or a transistor using a compound semiconductor such as a-InGaZnO, a transistor using an organic semiconductor, or a carbon nanotube can be used. There is no particular limitation on the kind of the substrate on which the transistor is provided, and for example, a single crystal substrate, an SOI substrate, a glass substrate, a plastic substrate, or the like can be used.

  In the above description, two types of functions of the regulator circuit are used. The first function is to output an arbitrary potential, and the second function is to stabilize the output potential. Among the power supply potential fluctuations in the RFID, the first fluctuation is the power supply potential fluctuation caused by the positional relationship between the RFID and the reader / writer and the power supplied from the reader / writer due to the radio signal. The fluctuation is defined as power supply noise generated in a circuit or the like included in the RFID. By dividing the first circuit and the second circuit as described above, the first regulator that supplies power to the first circuit uses the first function to suppress the first fluctuation, The second function is used in order to suppress the power supply noise generated in the first circuit, that is, the second fluctuation.

  Further, by dividing the circuit into the first circuit and the second circuit, it is not necessary to consider the second function in the design of the first regulator circuit with respect to the second variation generated in the second circuit. Therefore, the design of the first regulator circuit is easy.

  In addition, since the power supply potential of the second circuit does not need to have stability of the power supply potential as compared with the first circuit, there may be a first fluctuation and the second regulator circuit may or may not be present. good.

  Therefore, the second regulator circuit also uses the first function to suppress the first fluctuation and the second function to suppress the second fluctuation generated in the second circuit. The design need not be more complicated than the first regulator circuit. That is, the second regulator circuit can reduce the size of the transistor and the layout area as compared with the first regulator circuit. Further, power consumption in the regulator circuit can be reduced.

By using the present invention, a semiconductor device such as an RFID or a wireless chip having a regulator circuit with a small layout area and easy design can be provided. In addition, the influence of noise generated in the semiconductor device on circuit operation can be reduced, and a highly reliable semiconductor device can be obtained.

Embodiments of the present invention will be described below with reference to the drawings. However, the present invention can be implemented in many different modes, and those skilled in the art can easily understand that the modes and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention is not construed as being limited to the description of this embodiment mode. Note that in all the drawings for describing the embodiments, the same portions or portions having similar functions are denoted by the same reference numerals, and repetitive description thereof is omitted.

(Embodiment 1)
FIG. 1 is a block diagram showing the configuration of the RFID of the present invention.

  The RFID illustrated in FIG. 1 includes an antenna 101, a rectifier circuit 102, a regulator circuit 103, a first circuit 104, a level shifter circuit 105, and a second circuit 106. The antenna 101 and the rectifier circuit 102 generate the power supply potential required for the first circuit 104 and the second circuit 106 from radio waves or electromagnetic waves from a reader / writer that receives from the antenna 101, that is, radio signals (also referred to as communication signals). To do. In practice, a signal is extracted from the antenna 101, processed by the second circuit 106, and the result processed by the second circuit 106 is transmitted from the antenna 101 to the reader / writer.

  The first circuit 104 is a circuit that requires an arbitrary stable power supply potential, such as a clock generation circuit, and the second circuit 106 is a circuit other than a circuit that requires an arbitrary stable power supply potential, that is, the first circuit. Circuits other than 104 are shown. The second circuit 106 is a logic circuit for interpreting and responding to a radio signal, for example. For example, if the transistor included in the second circuit operates without being broken even at about 1V to 10V, the power supply potential of the second circuit may be about 1V to about 10V.

Next, specific examples of the first circuit 104 and the second circuit 106 together with the operation of the RFID will be described with reference to FIGS. However, the first circuit and the second circuit are not limited to this.

In the RFID 300, a communication signal received by the antenna circuit 301 is input to the demodulation circuit 305 in the signal processing circuit 302. Usually, a communication signal is sent by performing a process such as ASK modulation or PSK modulation on a carrier wave such as 13.56 MHz or 915 MHz. FIG. 3 shows an example in which a carrier wave is 915 MHz as a communication signal. In FIG. 3, in order to process a signal, a reference clock signal is required. Here, a clock is generated from a communication signal. The clock generation circuit 306 has an oscillation circuit inside, and synchronizes the oscillation signal with the communication signal and supplies it to the logic circuit 307 as a clock. The modulated communication signal is demodulated by the demodulation circuit 305. The demodulated signal is also sent to the logic circuit 307 and analyzed. The signal analyzed by the logic circuit 307 is sent to the memory control circuit 308. Based on the signal, the memory control circuit 308 controls the memory circuit 309, extracts the data stored in the memory circuit 309, and sends it to the logic circuit 310. The signal sent to the logic circuit 310 is encoded by the logic circuit 310 and then amplified by the amplifier 311. The modulation circuit 312 modulates the carrier wave by the signal. On the other hand, after the carrier wave entering the rectifier circuit 303 is rectified, the demodulation circuit 305, the clock generation circuit 306, the logic circuit 307, the memory control circuit 308, the memory circuit 309, the logic circuit 310, It is supplied to the amplifier 311, the modulation circuit 312, and the like. In this way, the RFID 300 operates.

Note that the demodulation circuit 305, the logic circuit 307, the memory control circuit 308, the memory circuit 309, the logic circuit 310, the amplifier 311, the modulation circuit 312 and the like to which the power supply potential generated from the communication signal is supplied interprets the radio signal and responds. This corresponds to a circuit other than a circuit that requires an arbitrary stable power supply potential, that is, a second circuit. Note that although the logic circuit depends on the clock frequency and the characteristics of the transistors constituting the circuit, the logic circuit operates even when the minimum power supply potential is about 1 V and the maximum power supply potential is about 10 V if the transistor is not destroyed.

On the other hand, since the clock frequency of the clock generation circuit 306 that generates a clock necessary for processing a signal changes depending on the supplied power supply potential, a circuit that requires an arbitrary stable power supply potential, that is, the first Corresponds to a circuit. As described above, a stable power supply potential generated from the communication signal received from the antenna circuit 301 through the rectifier circuit 303 and the regulator circuit is supplied to the first circuit as described above.

Note that the first circuit is not limited to the clock generation circuit. For example, when the sensor potential is detected by an AD converter circuit, fluctuations in the power supply potential of the AD converter circuit hinder accurate reading of the sensor potential. Therefore, the AD converter circuit is a circuit that requires an arbitrary stable power supply potential. That is, it can be said to be a first circuit. Thus, the first circuit refers to a circuit that requires an arbitrary stable power supply potential.

  The level shifter circuit 105 has a signal amplitude so that the signal output from the first circuit 104 can be received by the second circuit 106 when the power supply potentials input to the first circuit 104 and the second circuit 106 are different. Or the signal amplitude is changed so that the signal output from the second circuit 106 can be received by the first circuit 104. Depending on the difference between the two power supply potentials, the level shifter circuit 105 may be omitted.

The level shifter circuit 105 is also referred to as a level converter circuit or a level conversion circuit. In the present invention, a generally known dedicated circuit may be used for the level shifter circuit 105. Further, depending on the case, it may be configured by only an N-type transistor and a resistor like an inverter of an NMOS circuit. Of course, a level shifter circuit can also be configured with a P-type transistor and a resistor for the P-type. Further, depending on the difference between the power supply potentials of the first circuit 104 and the second circuit 106, the level shifter circuit 105 can also be configured by an inverter circuit in consideration of the balance between N-type and P-type characteristics in the case of a CMOS circuit. That is, the inverter circuit and the NAND circuit that constitute the logic circuit included in the first circuit 104 or the second circuit 106 can perform the same function as the level shifter circuit. Signals can also be exchanged between the first circuit 104 and the second circuit 106.

  Note that in FIG. 1, the power supply potential of the line 107 is supplied from the rectifier circuit 102 to the first circuit 104 via the regulator circuit 103, and the power supply potential of the line 108 is supplied from the rectifier circuit 102 to the second circuit 106. It shows that. Lines 109 and 110 indicate a signal exchanged between the first circuit 104 and the second circuit 106 and that the power supply potential is supplied to the level shifter circuit 105 for changing the signal amplitude. The power supply of the level shifter circuit 105 uses the same power supply potential supplied to the first circuit 104 and / or the same power supply potential supplied to the second circuit 106 depending on the circuit configuration of the level shifter circuit 105. Can do. Therefore, the level shifter circuit 105 is included in the first circuit 104 and / or the second circuit 106. In FIG. 1, however, the first level shifter circuit 105 is shown to emphasize that the signal amplitude needs to be changed. The circuit 104 and the second circuit 106 are shown separately.

  Further, since the power supply potential output from the regulator circuit 103 is not used as the power supply for the second circuit 106, the power consumed by the second circuit 106 and the power supply noise generated by the second circuit 106 There is no need to consider the design on the output side. Since the second circuit 106 affects the input side of the regulator circuit 103, there is no need to consider it at all. However, in the conventional case where the power supply potential is also supplied to the second circuit 106 via the regulator circuit. In comparison with this, the design of the regulator circuit 103 becomes much easier.

Note that in order to separate the input terminal of the regulator circuit 103 and the power supply terminal of the second circuit 106, a plurality of rectifier circuits 102 may be provided to have respective power supply potentials. A plurality of antennas may be provided. With such a structure, power supply potentials supplied to the first circuit 104 and the second circuit 106 can be independently generated using different antennas and rectifier circuits. You can also.

  Next, one configuration example of the regulator circuit 103 is shown in FIG. The regulator circuit illustrated in FIG. 4 includes a resistor 402, a Zener diode 403, an operational amplifier 404, a resistor 406, a resistor 407, and a transistor 408. Note that the case where the transistor 408 is a p-type transistor is described here.

The power supply potential generated by the rectifier circuit 102 in FIG. 1 is supplied to the terminal 401 of the regulator circuit. The resistor 402 serves as a current source, and a Zener diode 403 generates a reference potential. The obtained reference potential is input to the inverting input terminal of the operational amplifier 404. Note that in the case where the Zener diode 403 is not used, a potential may be generated by a circuit using a threshold voltage of a transistor in order to generate a reference potential that does not depend on the power supply potential. A terminal 405 is an output terminal of the regulator circuit, and the output potential is divided using the resistors 406 and 407 and input to the non-inverting input terminal of the operational amplifier 404. The output terminal of the operational amplifier 404 is connected to the gate terminal of the P-type transistor 408, and controls the current flowing from the terminal 401 to the terminal 405. Note that the transistor 408 may be an n-type transistor, in which case the inverting input terminal and the non-inverting terminal of the operational amplifier 404 are connected in reverse.

  In the regulator circuit, when the current consumption of the circuit using the terminal 405 as a power supply potential increases and the potential of the terminal 405 decreases, the potential of the non-inverting input terminal of the operational amplifier 404 decreases. When the potential of the non-inverting input terminal of the operational amplifier 404 is decreased, the potential of the output terminal of the operational amplifier 404 is also decreased, and the current flowing from the terminal 401 to the terminal 405 through the transistor 408 is increased. In this manner, the regulator circuit is a feedback circuit in which when the potential of the terminal 405 decreases, the current flowing from the terminal 401 to the terminal 405 increases and the potential of the decreased terminal 405 is restored.

  In the present invention, since the power supply potential obtained from the output terminal of the regulator circuit is supplied only to the first circuit 104, a circuit using the potential of the terminal 405 as the power supply potential compared to the conventional case where the power supply potential is also supplied to the second circuit. The current consumption becomes smaller. Therefore, the value of current flowing from the terminal 401 to the terminal 405 through the transistor 408 can be reduced. Therefore, the regulator circuit can be easily designed. Note that heat generation of the transistor 408 can also be suppressed.

  In the present invention, power supply noise hardly occurs in the first circuit 104. That is, there are fewer circuits using the output terminal 405 of the regulator circuit as a power source than in the conventional configuration. Therefore, in order to suppress instantaneous power supply fluctuation due to power supply noise, it is not necessary to make a circuit that can instantaneously increase the current flowing from the terminal 401 to the terminal 405. Even if it occurs, the amount of instantaneously increasing the current flowing from the terminal 401 to the terminal 405 may be smaller than the conventional current difference. Therefore, it is not necessary to complicate the circuit configuration of the regulator circuit or increase the channel width of the transistor 408, and the regulator circuit can be further reduced.

In the present invention, the regulator circuit is not limited to the above, and a circuit configuration called a linear regulator, a series regulator, a shunt regulator, a switching regulator, a generally known circuit configuration, or the like can be used. In particular, it is possible to select a circuit configuration that has a smaller layout area than the conventional regulator circuit configuration and consumes less power in the regulator circuit.

The clock generation circuit included in the first circuit 104 that requires an arbitrary stable power supply potential has a logic inversion higher than that of other signals. The logic inversion is a change from a state where the signal potential is higher than an arbitrary threshold value to a state where the signal potential is lower than an arbitrary threshold value, or vice versa. When a CMOS circuit is used as the clock generation circuit, the current consumption increases at the time of change. Therefore, the clock generation circuit often consumes more current than other logic circuits configured with the same number of elements. On the other hand, the power supply potential output from the rectifier circuit 102 and the power supply potential output from the regulator circuit 103 by inputting the output of the rectifier circuit 102 to the regulator circuit 103 in the configuration of FIG. Generally, the potential is lower. That is, the clock generation circuit has a higher operating frequency than other logic circuits, but the power supply potential is low. In order to reduce power consumption, it is desirable to lower the power supply potential of the entire circuit. However, when the power supply potential of the entire circuit cannot be lowered, the power consumption can be reduced even a little by lowering the power supply potential of a part of the circuit. When lowering the power supply potential of a part of the circuit, it is efficient to lower the power supply potential of a circuit having a high operating frequency if the circuit is composed of the same number of elements. Therefore, the fact that the clock generation circuit is included in the first circuit in the configuration of FIG. 1 of the present invention is efficient in order to reduce power consumption.

  Note that the present invention is not intended to make a difference in power supply potential, unlike a multi-power supply circuit using a multi-power supply circuit for reducing power consumption or a booster circuit for a specific circuit. Rather, if there is no power supply potential difference between the first circuit 104 and the second circuit 106, it is necessary to provide a level shifter circuit for a signal exchanged between the first circuit 104 and the second circuit 106 as described above. And there is an effect that there is no power consumption, layout area and signal delay in the level shifter circuit 105, which is desirable.

As described above, the load of the first regulator circuit 103 that supplies power only to the first circuit 104 is the load of the conventional regulator circuit that supplies the power supply potential to both the first circuit 104 and the second circuit 106. Less than load. If the load on the regulator circuit 103 is small, the regulator circuit 103 can be easily designed. In addition, since the power to be changed in order to suppress the output potential fluctuation can be small, the layout area can be reduced by reducing the size of the transistor or changing the circuit configuration. Further, power supply noise generated in the second circuit 106 is unlikely to affect the power supply potential of the first circuit 104. In the conventional circuit configuration, the first circuit 104 and the circuit corresponding to the second circuit 106 share the power supply, so that power supply noise generated in the circuit corresponding to the second circuit 106 corresponds to the first circuit 104. There is a possibility that the power supply potential of the circuit to be lowered is lowered and the circuit operation is adversely affected. Even in the present invention, if power supply noise occurs in the first circuit, it is difficult to say that there is no possibility of adversely affecting the circuit operation. However, only the first circuit needs to be carefully designed, The regulator circuit that supplies the power supply potential of the first circuit can be designed so that the power supply noise in the first circuit is less likely to occur as much as the load is reduced. It is also possible to reduce power consumption in the regulator circuit. Conversely, the output potential of the regulator circuit can be further stabilized while maintaining the layout area and the power consumption in the regulator circuit.

  Further, by using the power supply potential generated by the rectifier circuit 102 without using the regulator circuit as the second circuit 106, the layout area that should have been occupied by the regulator circuit can be reduced, or the inside of the regulator circuit can be reduced. Can reduce the power that was supposed to be consumed.

As described above, a semiconductor device having a regulator circuit with a small layout area and easy design can be provided.

(Embodiment 2)
In this embodiment, a structure which is different from that in Embodiment 1 is described with reference to FIG. 2 has a configuration in which a regulator circuit 201 is added to the RFID shown in FIG. 1, and an antenna 101, a rectifier circuit 102, a regulator circuit 103, a first circuit 104, a level shifter circuit 105, and the like. The second circuit 106 and the regulator circuit 201 are included. In addition, the same code | symbol is used about the same thing as FIG. 1, and the description is abbreviate | omitted. Further, in order to distinguish the regulator circuit 103 and the regulator circuit 201, they are referred to as a first regulator circuit and a second regulator circuit, respectively.

  In FIG. 2, the regulator circuit 201 prevents the power supply potential of the second circuit 106 from becoming too high. The state in which the power supply potential of the second circuit 106 is too high is a state in which a voltage that destroys the transistors included in the second circuit 106 is applied, or the first circuit so that the signal amplitude cannot be changed by the level shifter circuit 105. This indicates a state in which the difference between the power supply potentials of 104 and the second circuit 106 becomes large. Therefore, by adding the second regulator circuit 201, a more reliable RFID can be obtained.

  Although it is preferable that the output potential of the second regulator circuit 201 is fixed, the target output potential of the regulator circuit 201 is different from the output potential of the first regulator circuit 103 and does not need to be fixed. Therefore, the second regulator circuit 201 may be a circuit for supplying the same power supply potential as that of the first regulator circuit 103 or a circuit for supplying a different power supply potential. As described above, the second regulator circuit 201 does not require the same function as the first regulator circuit 103. For example, if the first circuit 104 includes an oscillation circuit, and the oscillation frequency of the oscillation circuit depends on the power supply potential and a power supply of 2V ± 0.2V is required to oscillate at 10 MHz ± 1 MHz, 10 MHz ± In order to obtain 1 MHz oscillation, the output potential of the first regulator circuit 103 must be 2V ± 0.2V. On the other hand, the output potential of the second regulator circuit 201 is not limited to 2V ± 0.2V, but may be 3V ± 0.3V or 4V ± 0.4V if the variation is within ± 10%. In addition, when the fluctuation of the power supply potential output from the first regulator circuit 103 is within 5%, for example, the fluctuation of the power supply potential output from the second regulator circuit 201 is within 10%. It may not be as stable as the circuit 103. Therefore, the second regulator circuit 201 can be manufactured with a simple design by reducing the transistors included in the regulator circuit as compared with the first regulator circuit 103. In addition, power consumption in the regulator circuit is small.

In addition, there are variations in devices in the manufacturing process. For example, in order to set the output voltage of the first regulator circuit 103 to an arbitrary stable value, a complicated correction circuit is added, or the characteristics of the device are increased in a later process. In some cases, the layout may be such that correction such as cutting of the wiring with a laser can be added, but the second regulator circuit 201 does not require such a complicated correction circuit or layout for cutting. Therefore, when the power supply potential generated by the second regulator circuit 201 is used for the second circuit 106, the second regulator circuit 201 does not need the same function as the first regulator circuit 103. The design can be made easier by reducing the layout area and reducing the power consumption in the regulator circuit.

Therefore, a semiconductor device having a regulator circuit with a small layout area and easy design can be provided.

Note that the second regulator circuit 201 may be replaced with a voltage limiter circuit. The voltage limiter circuit is a circuit that limits the power supply potential by changing the current flowing from the power supply to the ground when the power supply potential exceeds an arbitrary value. For example, a diode-connected transistor can be used in addition to a Schottky barrier type, PIN type, or PN type diode.

Further, this embodiment mode can be combined with any of the other embodiment modes in this specification as appropriate.

(Embodiment 3)
In this embodiment, an example of a method for manufacturing a semiconductor device such as an RFID described in the above embodiment will be described with reference to partial cross-sectional views.

  First, as shown in FIG. 5A, a separation layer 503 is formed on one surface of a substrate 501 with an insulating film 502 interposed therebetween, and then an insulating film 504 functioning as a base film and a semiconductor film 505 (for example, an amorphous film) A film containing crystalline silicon). Note that the insulating film 502, the separation layer 503, the insulating film 504, and the semiconductor film 505 can be formed successively.

  The substrate 501 is selected from a glass substrate, a quartz substrate, a metal substrate (for example, a stainless steel substrate), a semiconductor substrate such as a ceramic substrate, and a Si substrate. In addition, a substrate such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), or acrylic can be selected as the plastic substrate. Note that in this step, the separation layer 503 is provided over the entire surface of the substrate 501 with the insulating film 502 interposed therebetween. However, if necessary, a separation layer is provided over the entire surface of the substrate 501 and then selectively removed by photolithography. May be provided.

  The insulating film 502 and the insulating film 504 are formed using silicon oxide, silicon nitride, silicon oxynitride (SiOxNy) (x> y> 0), silicon nitride oxide (SiNxOy) (x>) by a CVD method, a sputtering method, or the like. It is formed using an insulating material such as y> 0). For example, in the case where the insulating films 502 and 504 have a two-layer structure, a silicon nitride oxide film may be formed as the first insulating film and a silicon oxynitride film may be formed as the second insulating film. Alternatively, a silicon nitride film may be formed as the first insulating film, and a silicon oxide film may be formed as the second insulating film. The insulating film 502 functions as a blocking layer for preventing an impurity element from being mixed into the separation layer 503 or an element formed thereon from the substrate 501, and the insulating film 504 is formed over the substrate 501 and the separation layer 503. It functions as a blocking layer that prevents an impurity element from entering the device. In this manner, by forming the insulating films 502 and 504 functioning as blocking layers, an alkali metal such as Na or alkaline earth metal from the substrate 501 and an impurity element contained in the release layer from the release layer 503 are formed thereon. It is possible to prevent an adverse effect on an element to be formed. Note that the insulating films 502 and 504 may be omitted when quartz is used for the substrate 501.

For the separation layer 503, a metal film, a stacked structure of a metal film and a metal oxide film, or the like can be used. As the metal film, tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), niobium (Nb), nickel (Ni), cobalt (Co), zirconium (Zr), zinc (Zn), A single layer or a stack of films made of an element selected from ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), or an alloy material or a compound material containing the element as a main component To form. These materials can be formed by using various CVD methods such as a sputtering method and a plasma CVD method. A stacked structure of a metal film and a metal oxide film, after forming a metal film described above, the plasma treatment in or under N _{2 O} atmosphere an oxygen atmosphere, by performing heat treatment in or under N _{2 O} atmosphere an oxygen atmosphere The oxide or oxynitride of the metal film can be provided on the surface of the metal film. For example, in the case where a tungsten film is provided as a metal film by a sputtering method, a CVD method, or the like, a metal oxide film made of tungsten oxide can be formed on the tungsten film surface by performing plasma treatment on the tungsten film. In this case, the oxide of tungsten is represented by WOx, X is 2 to 3, X is 2 (WO ₂ ), X is 2.5 (W ₂ O ₅ ), and X is In the case of 2.75 (W ₄ O ₁₁ ), X is 3 (WO ₃ ), and the like. In forming the tungsten oxide, there is no particular limitation on the value of X mentioned above, and it is preferable to determine which oxide is formed based on the etching rate or the like. In addition, for example, after a metal film (for example, tungsten) is formed, an insulating film such as silicon oxide (SiO ₂ ) is provided on the metal film by a sputtering method, and a metal oxide (for example, for example, Tungsten oxide) may be formed over tungsten. Further, as the plasma treatment, for example, the above-described high-density plasma treatment may be performed. In addition to the metal oxide film, metal nitride or metal oxynitride may be used. In this case, plasma treatment or heat treatment may be performed on the metal film in a nitrogen atmosphere or a nitrogen and oxygen atmosphere.

  The semiconductor film 505 is formed with a thickness of 25 to 200 nm (preferably 30 to 150 nm) by a sputtering method, an LPCVD method, a plasma CVD method, or the like.

  Next, the semiconductor film 505 is irradiated with laser light for crystallization. Note that the semiconductor film 505 may be crystallized by a combination of laser light irradiation, a thermal crystallization method using an RTA or a furnace annealing furnace, a thermal crystallization method using a metal element that promotes crystallization, or the like. Good. After that, as shown in FIG. 5B, the obtained semiconductor film is etched into a desired shape to form crystallized semiconductor films 505a to 505f, and gate insulation is performed so as to cover the semiconductor films 505a to 505f. A film 506 is formed.

  Note that the gate insulating film 506 is formed using silicon oxide, silicon nitride, silicon oxynitride (SiOxNy) (x> y> 0), silicon nitride oxide (SiNxOy) (x> y> 0) by a CVD method, a sputtering method, or the like. ) Or the like. For example, in the case where the gate insulating film 506 has a two-layer structure, a silicon oxynitride film may be formed as the first insulating film and a silicon nitride oxide film may be formed as the second insulating film. Alternatively, a silicon oxide film may be formed as the first insulating film, and a silicon nitride film may be formed as the second insulating film.

  An example of a manufacturing process of the semiconductor films 505a to 505f will be briefly described below. First, an amorphous semiconductor film with a thickness of 50 to 60 nm is formed using a plasma CVD method. Next, after a solution containing nickel, which is a metal element that promotes crystallization, is held on the amorphous semiconductor film, the amorphous semiconductor film is subjected to dehydrogenation treatment (500 ° C., 1 hour), heat Crystallization treatment (550 ° C., 4 hours) is performed to form a crystalline semiconductor film. After that, crystallized semiconductor films 505a to 505f are formed by irradiating laser light and using a photolithography method. Note that the amorphous semiconductor film may be crystallized only by laser light irradiation without performing thermal crystallization using a metal element that promotes crystallization.

Note that as a laser oscillator used for crystallization, a continuous wave laser beam (CW laser beam) or a pulsed laser beam (pulse laser beam) can be used. The laser beam that can be used here is a gas laser such as Ar laser, Kr laser, or excimer laser, single crystal YAG, YVO ₄ , forsterite (Mg ₂ SiO ₄ ), YAlO ₃ , GdVO ₄ , or polycrystalline ( (Ceramics) YAG, Y ₂ O ₃ , YVO ₄ , YAlO ₃ , GdVO ₄ with one or more of Nd, Yb, Cr, Ti, Ho, Er, Tm, Ta added as dopants Lasers oscillated from one or more of laser, glass laser, ruby laser, alexandrite laser, Ti: sapphire laser, copper vapor laser or gold vapor laser as a medium can be used. By irradiating the fundamental wave of such a laser beam and the second to fourth harmonics of these fundamental waves, a crystal having a large grain size can be obtained. For example, the second harmonic (532 nm) or the third harmonic (355 nm) of an Nd: YVO ₄ laser (fundamental wave 1064 nm) can be used. In this case, a laser power density is about 0.01 to 100 MW / cm ² (preferably 0.1 to 10 MW / cm ²⁾ is required. Then, irradiation is performed at a scanning speed of about 10 to 2000 cm / sec. Note that single crystal YAG, YVO ₄ , forsterite (Mg ₂ SiO ₄ ), YAlO ₃ , GdVO ₄ , or polycrystalline (ceramic) YAG, Y ₂ O ₃ , YVO ₄ , YAlO ₃ , GdVO ₄ , dopants Nd, Yb, Cr, Ti, Ho, Er, Tm, Ta as a medium, a laser, Ar ion laser, or Ti: sapphire laser with one or more added as a medium should be continuously oscillated It is also possible to perform pulse oscillation at an oscillation frequency of 10 MHz or more by performing Q switch operation, mode synchronization, or the like. When a laser beam is oscillated at an oscillation frequency of 10 MHz or higher, the semiconductor film is irradiated with the next pulse during the period from when the semiconductor film is melted by the laser to solidification. Therefore, unlike the case of using a pulse laser having a low oscillation frequency, the solid-liquid interface can be continuously moved in the semiconductor film, so that crystal grains continuously grown in the scanning direction can be obtained.

Alternatively, the gate insulating film 506 may be formed by performing the above-described high-density plasma treatment on the semiconductor films 505a to 505f and oxidizing or nitriding the surface. For example, the plasma treatment is performed by introducing a rare gas such as He, Ar, Kr, or Xe and a mixed gas such as oxygen, nitrogen oxide (NO ₂ ), ammonia, nitrogen, or hydrogen. When excitation of plasma in this case is performed by introducing microwaves, high-density plasma can be generated at a low electron temperature. The surface of the semiconductor film can be oxidized or nitrided by oxygen radicals (which may include OH radicals) or nitrogen radicals (which may include NH radicals) generated by this high-density plasma.

  By such treatment using high-density plasma, an insulating film with a thickness of 1 to 20 nm, typically 5 to 10 nm, is formed over the semiconductor film. Since the reaction in this case is a solid-phase reaction, the interface state density between the insulating film and the semiconductor film can be extremely low. Such high-density plasma treatment directly oxidizes (or nitrides) a semiconductor film (crystalline silicon or polycrystalline silicon), so that the thickness of the formed insulating film ideally has extremely small variation. can do. In addition, since oxidation is not strengthened even at the crystal grain boundaries of crystalline silicon, a very favorable state is obtained. That is, the surface of the semiconductor film is solid-phase oxidized by the high-density plasma treatment shown here, thereby forming an insulating film with good uniformity and low interface state density without causing an abnormal oxidation reaction at the grain boundaries. can do.

  Note that the gate insulating film 506 may be only an insulating film formed by high-density plasma treatment, or an insulating film such as silicon oxide, silicon oxynitride, or silicon nitride formed by a CVD method using plasma or thermal reaction. May be deposited and laminated. In any case, a transistor formed by including an insulating film formed by high-density plasma in part or all of the gate insulating film can reduce variation in characteristics.

  In addition, the semiconductor films 505a to 505f obtained by crystallization by scanning in one direction while irradiating the semiconductor film with a continuous wave laser or a laser beam oscillating at a frequency of 10 MHz or more are provided in the scanning direction of the beam. There is a characteristic that crystals grow. By arranging the transistors in accordance with the scanning direction in the channel length direction (the direction in which carriers flow when a channel formation region is formed) and combining the gate insulating layer, characteristic variation is small and field effect mobility is reduced. A high thin film transistor (TFT: Thin Film Transistor) can be obtained.

  Next, a first conductive film and a second conductive film are stacked over the gate insulating film 506. Here, the first conductive film is formed with a thickness of 20 to 100 nm by a CVD method, a sputtering method, or the like. The second conductive film is formed with a thickness of 100 to 400 nm. The first conductive film and the second conductive film include tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), niobium ( Nb) or the like or an alloy material or a compound material containing these elements as a main component. Alternatively, a semiconductor material typified by polycrystalline silicon doped with an impurity element such as phosphorus is used. Examples of the combination of the first conductive film and the second conductive film include a tantalum nitride film and a tungsten film, a tungsten nitride film and a tungsten film, a molybdenum nitride film and a molybdenum film, and the like. Since tungsten and tantalum nitride have high heat resistance, heat treatment for thermal activation can be performed after the first conductive film and the second conductive film are formed. In the case of a three-layer structure instead of a two-layer structure, a stacked structure of a molybdenum film, an aluminum film, and a molybdenum film is preferably employed.

  Next, a mask made of a resist is formed by photolithography, and an etching process for forming a gate electrode and a gate line is performed, so that the gate electrode 507 is formed above the semiconductor films 505a to 505f. Here, an example in which the gate electrode 507 is provided with a stacked structure of a first conductive film 507a and a second conductive film 507b is shown.

Next, as illustrated in FIG. 5C, an impurity element imparting n-type conductivity is added to the semiconductor films 505 a to 505 f at a low concentration by ion doping or ion implantation with the gate electrode 507 as a mask, and then Then, a mask made of resist is selectively formed by photolithography, and an impurity element imparting p-type is added at a high concentration. As the impurity element exhibiting n-type, phosphorus (P), arsenic (As), or the like can be used. As the p-type impurity element, boron (B), aluminum (Al), gallium (Ga), or the like can be used. Here, phosphorus (P) is used as an impurity element imparting n-type conductivity, and is selectively introduced into the semiconductor films 505a to 505f so as to be included at a concentration of 1 × 10 ¹⁵ to 1 × 10 ¹⁹ / cm ^3. An impurity region 508 indicating a mold is formed. In addition, boron (B) is used as an impurity element imparting p-type, and is selectively introduced into the semiconductor films 505c and 505e so as to be included at a concentration of 1 × 10 ¹⁹ to 1 × 10 ²⁰ / cm ^3. Impurity regions 509 are formed.

  Subsequently, an insulating film is formed so as to cover the gate insulating film 506 and the gate electrode 507. As the insulating film, a single layer or a stacked layer of a film containing an inorganic material such as silicon, silicon oxide, or silicon nitride, or a film containing an organic material such as an organic resin, by a plasma CVD method, a sputtering method, or the like. Form. Next, the insulating film is selectively etched by anisotropic etching mainly in the vertical direction, so that an insulating film 510 (also referred to as a sidewall) in contact with the side surface of the gate electrode 507 is formed. The insulating film 510 is used as a mask for doping when forming an LDD (Lightly Doped Drain) region.

Subsequently, an impurity element imparting n-type conductivity is added to the semiconductor films 505a, 505b, 505d, and 505f in a high concentration by using a resist mask formed by a photolithography method, the gate electrode 507, and the insulating film 510 as a mask. Thus, an n-type impurity region 511 is formed. Here, phosphorus (P) is used as an impurity element imparting n-type, and the semiconductor films 505a, 505b, 505d, and 505f are selectively used so as to be included at a concentration of 1 × 10 ¹⁹ to 1 × 10 ²⁰ / cm ^3. Then, an impurity region 511 having an n-type concentration higher than that of the impurity region 508 is formed.

  Through the above steps, n-channel thin film transistors 500a, 500b, 500d, and 500f and p-channel thin film transistors 500c and 500e are formed as shown in FIG. Note that these thin film transistors 500a to 500f are thin film transistors that constitute a semiconductor device such as an RFID of the present invention.

  Note that in the n-channel thin film transistor 500a, an impurity region 511 in which a channel formation region is formed in a region of the semiconductor film 505a overlapping with the gate electrode 507 and a source region or a drain region is formed in a region not overlapping with the gate electrode 507 and the insulating film 510. A low concentration impurity region (LDD region) is formed between the channel formation region and the impurity region 511, which is a region overlapping with the insulating film 510. Similarly, in the n-channel thin film transistors 500b, 500d, and 500f, a channel formation region, a low-concentration impurity region, and an impurity region 511 are formed.

  In the p-channel thin film transistor 500c, a channel formation region is formed in a region of the semiconductor film 505c that overlaps with the gate electrode 507, and an impurity region 509 that forms a source region or a drain region is formed in a region that does not overlap with the gate electrode 507. Yes. Similarly, a channel formation region and an impurity region 509 are formed in the p-channel thin film transistor 500e. Note that the p-channel thin film transistors 500c and 500e are not provided with an LDD region here, but the p-channel thin film transistor may be provided with an LDD region, or the n-channel thin film transistor may not be provided with an LDD region. Good.

  Next, as illustrated in FIG. 6A, an insulating film is formed as a single layer or a stacked layer so as to cover the semiconductor films 505a to 505f, the gate electrode 507, and the like, and the thin film transistors 500a to 500f are formed over the insulating film. A conductive film 513 that is electrically connected to the impurity regions 509 and 511 forming the source region or the drain region is formed. Insulating film is formed by CVD, sputtering, SOG, droplet discharge, screen printing, etc., inorganic materials such as silicon oxide and silicon nitride, polyimide, polyamide, benzocyclobutene, acrylic, epoxy, etc. A single layer or a stacked layer is formed using an organic material or a siloxane material. Here, the insulating film is provided in two layers, and a silicon nitride oxide film is formed as the first insulating film 512a, and a silicon oxynitride film is formed as the second insulating film 512b. The conductive film 513 forms a source electrode or a drain electrode of the thin film transistors 500a to 500f.

  Note that before the insulating films 512a and 512b are formed or after one or more thin films of the insulating films 512a and 512b are formed, the crystallinity of the semiconductor film is restored and the activity of the impurity element added to the semiconductor film is increased. Heat treatment for the purpose of hydrogenation of the semiconductor film is preferably performed. For the heat treatment, thermal annealing, laser annealing, RTA, or the like is preferably applied.

  The conductive film 513 is formed of aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), molybdenum (Mo), nickel (Ni), platinum (Pt), CVD, sputtering, or the like. An element selected from copper (Cu), gold (Au), silver (Ag), manganese (Mn), neodymium (Nd), carbon (C), silicon (Si), or an alloy containing these elements as a main component The material or compound material is formed as a single layer or a stacked layer. The alloy material containing aluminum as a main component corresponds to, for example, a material containing aluminum as a main component and containing nickel, or an alloy material containing aluminum as a main component and containing nickel and one or both of carbon and silicon. The conductive film 513 may employ, for example, a stacked structure of a barrier film, an aluminum silicon (Al—Si) film, and a barrier film, or a stacked structure of a barrier film, an aluminum silicon (Al—Si) film, a titanium nitride film, and a barrier film. . Note that the barrier film corresponds to a thin film formed of titanium, titanium nitride, molybdenum, or molybdenum nitride. Aluminum and aluminum silicon are suitable materials for forming the conductive film 513 because they have low resistance and are inexpensive. In addition, when an upper layer and a lower barrier layer are provided, generation of hillocks of aluminum or aluminum silicon can be prevented. In addition, when a barrier film made of titanium, which is a highly reducing element, is formed, even if a thin natural oxide film is formed on the semiconductor film, the natural oxide film is reduced and good contact is made with the semiconductor film. Can do.

  Next, an insulating film 514 is formed so as to cover the conductive film 513, and a conductive film 515 that is electrically connected to the conductive film 513 that forms a source electrode or a drain electrode of the thin film transistor is formed over the insulating film 514. . Note that FIG. 6B illustrates a conductive film 515 that is electrically connected to a conductive film 513 that forms a source electrode or a drain electrode of the thin film transistor 500a. The conductive film 515 can be formed using any of the materials shown for the conductive film 513 described above.

  Next, as illustrated in FIG. 6B, a conductive film 516 functioning as an antenna is formed so as to be electrically connected to the conductive film 515.

  Note that the insulating film 514 is formed of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x> y), silicon nitride oxide (SiNxOy) (x> y) by a CVD method, a sputtering method, or the like. An insulating film having oxygen or nitrogen such as, a film containing carbon such as DLC (diamond-like carbon), an organic material such as epoxy, polyimide, polyamide, polyvinylphenol, benzocyclobutene, acrylic, or a siloxane material such as a siloxane resin A single layer or a stacked structure can be provided. Note that the siloxane material corresponds to a material including a Si—O—Si bond. Siloxane has a skeleton structure formed of a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aryl group) is used. A fluoro group can also be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent.

  The conductive film 516 is formed using a conductive material by a CVD method, a sputtering method, a printing method such as screen printing or gravure printing, a droplet discharge method, a dispenser method, a plating method, or the like. Conductive materials are aluminum (Al), titanium (Ti), silver (Ag), copper (Cu), gold (Au), platinum (Pt) nickel (Ni), palladium (Pd), tantalum (Ta), molybdenum An element selected from (Mo) or an alloy material or a compound material containing these elements as a main component is formed in a single layer structure or a laminated structure.

  For example, when the conductive film 516 functioning as an antenna is formed using a screen printing method, a conductive paste in which conductive particles having a particle size of several nanometers to several tens of micrometers are dissolved or dispersed in an organic resin is selected. Can be provided by printing. The conductive particles include silver (Ag), gold (Au), copper (Cu), nickel (Ni), platinum (Pt), palladium (Pd), tantalum (Ta), molybdenum (Mo) and titanium (Ti). Any one or more metal particles, silver halide fine particles, or dispersible nanoparticles can be used. In addition, as the organic resin contained in the conductive paste, one or more selected from organic resins that function as a binder, a solvent, a dispersant, and a coating material of metal particles can be used. Typically, an organic resin such as an epoxy resin or a silicone resin can be given. In forming the conductive film, it is preferable to fire after extruding the conductive paste. For example, when fine particles containing silver as a main component (for example, a particle size of 1 nm or more and 100 nm or less) are used as a material for the conductive paste, the conductive film is obtained by being cured by baking in a temperature range of 150 to 300 ° C. Can do. Further, fine particles mainly composed of solder or lead-free solder may be used. In this case, it is preferable to use fine particles having a particle diameter of 20 μm or less. Solder and lead-free solder have the advantage of low cost.

Next, as illustrated in FIG. 6C, after an insulating film 517 is formed so as to cover the conductive film 516, a layer including the thin film transistors 500 a to 500 f, the conductive film 516, and the like (hereinafter referred to as “element formation layer 518”). Is removed from the substrate 501. Here, the element formation layer 518 is peeled from the substrate 501 with physical force after an opening is formed in a region avoiding the thin film transistors 500a to 500f by irradiation with laser light (for example, UV light). it can. In addition, before the element formation layer 518 is peeled from the substrate 501, an etching agent may be introduced into the formed opening to selectively remove the peeling layer 503. As the etchant, a gas or liquid containing halogen fluoride or an interhalogen compound is used. For example, chlorine trifluoride (ClF ₃ ) is used as a gas containing halogen fluoride. Then, the element formation layer 518 is peeled from the substrate 501. Note that a part of the peeling layer 503 may be left without being removed. By doing so, it is possible to suppress the consumption of the etching agent and shorten the processing time required for removing the release layer. Further, the element formation layer 518 can be held over the substrate 501 even after the peeling layer 503 is removed. In addition, cost can be reduced by reusing the substrate 501 from which the element formation layer 518 is separated.

  The insulating film 517 is formed of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x> y), silicon nitride oxide (SiNxOy) (x> y), or the like by CVD or sputtering. Single layer made of an insulating film containing oxygen or nitrogen, a film containing carbon such as DLC (diamond-like carbon), an organic material such as epoxy, polyimide, polyamide, polyvinylphenol, benzocyclobutene, acrylic, or a siloxane material such as a siloxane resin Alternatively, a stacked structure can be provided.

  In this embodiment mode, as illustrated in FIG. 7A, after an opening is formed in the element formation layer 518 by laser light irradiation, one surface of the element formation layer 518 (an exposed surface of the insulating film 517). ), The element formation layer 518 is peeled from the substrate 501.

  Next, as illustrated in FIG. 7B, after the second sheet material 520 is attached to the other surface (the surface exposed by peeling) of the element formation layer 518, one of heat treatment and pressure treatment is performed. Or both are performed and the 2nd sheet material 520 is bonded together. As the first sheet material 519 and the second sheet material 520, a hot melt film or the like can be used.

  In addition, as the first sheet material 519 and the second sheet material 520, films provided with antistatic measures for preventing static electricity (hereinafter referred to as antistatic films) can be used. Examples of the antistatic film include a film in which an antistatic material is dispersed in a resin, a film on which an antistatic material is attached, and the like. The film provided with an antistatic material may be a film provided with an antistatic material on one side, or a film provided with an antistatic material on both sides. Furthermore, a film provided with an antistatic material on one side may be attached to the layer so that the surface provided with the antistatic material is on the inside of the film, or on the outside of the film. It may be pasted. Note that the antistatic material may be provided on the entire surface or a part of the film. The antistatic material here is a surfactant such as metal, oxide of indium and tin (ITO: Indium Tin Oxide), amphoteric surfactant, cationic surfactant or nonionic surfactant. Can be used. In addition, as the antistatic material, a resin material containing a crosslinkable copolymer polymer having a carboxyl group and a quaternary ammonium base in the side chain can be used. An antistatic film can be obtained by sticking, kneading, or applying these materials to a film. By sealing with an antistatic film, it is possible to prevent the semiconductor element from being adversely affected by external static electricity or the like when handled as a product.

  Through the above steps, the semiconductor device of the present invention can be manufactured. Note that although an example in which the antenna is formed over the same substrate as the thin film transistor is described in this embodiment mode, the present invention is not limited to this structure. The thin film transistor and the antenna are electrically connected to each other by bonding a first substrate over which a layer having a thin film transistor is formed and a second substrate over which a conductive layer functioning as an antenna is formed using a resin containing conductive particles. You may connect.

Further, the shape of the antenna is not particularly limited to the above. If a circuit other than an antenna constituting a semiconductor device such as an RFID is a circuit 801, for example, a structure in which an antenna 802 is arranged around a circuit 801 on a substrate as shown in FIG. Alternatively, a coiled antenna 802 connected to a circuit 801 on the substrate may be used as shown in FIG. Further, as shown in FIG. 8C, the antenna 802 for receiving high-frequency electromagnetic waves may be formed in the circuit 801 on the substrate. Alternatively, as shown in FIG. 8D, the circuit 801 on the substrate may have a shape of an antenna 802 that is 180 degrees omnidirectional (same reception is possible from any direction). Further, as shown in FIG. 8E, the antenna 802 extended in a bar shape with respect to the circuit 801 on the substrate may be used. The length required for the antenna differs depending on the frequency used for reception. For example, when the frequency is 2.45 GHz, it may be about 60 mm (1/2 wavelength) if a half-wave dipole antenna is provided, and about 30 mm (1/4 wavelength) if a monopole antenna is provided.

Moreover, although the process which peeled after forming elements, such as a thin film transistor, on the board | substrate was shown above, it is good also as a product as it is, without peeling. Further, after an element such as a thin film transistor is provided over a glass substrate, the semiconductor substrate can be thinned and miniaturized by polishing the glass substrate from the side opposite to the surface on which the element is provided.

  Note that this embodiment can be implemented in combination with any of the other embodiments in this specification.

(Embodiment 4)
In this embodiment, a method for manufacturing a transistor included in the semiconductor device of the present invention, which is different from that in the above embodiment, will be described. The transistor in the semiconductor device of the present invention can be formed of a MOS transistor on a single crystal substrate in addition to the thin film transistor on the insulating substrate described in the above embodiment.

In this embodiment, an example of a method for manufacturing a transistor included in a semiconductor device such as an RFID will be described with reference to partial cross-sectional views in FIGS.

  First, regions 902 and 903 (hereinafter also referred to as regions 902 and 903) in which elements are separated are formed in the semiconductor substrate 900 (see FIG. 9A). The regions 902 and 903 provided in the semiconductor substrate 900 are separated by an insulating film 901 (also referred to as a field oxide film). Note that here, an example in which a single crystal Si substrate having n-type conductivity is used as the semiconductor substrate 900 and a p-well 904 is provided in a region 903 of the semiconductor substrate 900 is shown.

  The substrate 900 can be used without any particular limitation as long as it is a semiconductor substrate. For example, a single crystal Si substrate having an n-type or p-type conductivity, a compound semiconductor substrate (GaAs substrate, InP substrate, GaN substrate, SiC substrate, sapphire substrate, ZnSe substrate, etc.), bonding method or SIMOX (Separation by Implanted) An SOI (Silicon on Insulator) substrate manufactured by an Oxygen method or the like can be used.

  For the element isolation regions 902 and 903, a selective oxidation method (LOCOS (Local Oxidation of Silicon) method), a trench isolation method, or the like can be used as appropriate.

  The p well formed in the region 903 of the semiconductor substrate 900 can be formed by selectively introducing an impurity element having p-type conductivity into the semiconductor substrate 900. As the p-type impurity element, boron (B), aluminum (Al), gallium (Ga), or the like can be used.

  Note that in this embodiment, since a semiconductor substrate having n-type conductivity is used as the semiconductor substrate 900, no impurity element is introduced into the region 902, but an impurity element exhibiting n-type is introduced. Thus, an n-well may be formed in the region 902. As the impurity element exhibiting n-type, phosphorus (P), arsenic (As), or the like can be used. On the other hand, when a semiconductor substrate having p-type conductivity is used, an n-type impurity element is introduced into the region 902 to form an n-well, and no impurity element is introduced into the region 903. Good.

  Next, as illustrated in FIG. 9B, insulating films 905 and 906 are formed so as to cover the regions 902 and 903, respectively.

  The insulating films 905 and 906 can be formed using a silicon oxide film, for example, by performing heat treatment to oxidize the surfaces of the regions 902 and 903 provided in the semiconductor substrate 900. In addition, after a silicon oxide film is formed by a thermal oxidation method, the surface of the silicon oxide film is nitrided by performing nitriding treatment, so that a silicon oxide film and a film containing oxygen and nitrogen (silicon oxynitride film) are stacked. You may form with a structure.

  In addition, as described above, the insulating films 905 and 906 may be formed by plasma treatment. For example, the surface of the regions 902 and 903 provided in the semiconductor substrate 900 is subjected to oxidation treatment or nitridation treatment by high-density plasma treatment, so that a silicon oxide (SiOx) film or a silicon nitride (SiNx) film is formed as the insulating films 905 and 906. Can be formed. Alternatively, after the surface of the regions 902 and 903 is oxidized by high-density plasma treatment, nitriding treatment may be performed by performing high-density plasma treatment again. In this case, a silicon oxide film is formed in contact with the surfaces of the regions 902 and 903, a silicon oxynitride film is formed over the silicon oxide film, and the insulating films 905 and 906 are formed by stacking a silicon oxide film and a silicon oxynitride film. The resulting film. Alternatively, after a silicon oxide film is formed on the surfaces of the regions 902 and 903 by a thermal oxidation method, oxidation treatment or nitridation treatment may be performed by high-density plasma treatment.

Note that the insulating films 905 and 906 function as gate insulating films in transistors to be completed later.

  Next, as illustrated in FIG. 9C, a conductive film is formed so as to cover the insulating films 905 and 906 formed above the regions 902 and 903. Here, an example is shown in which a conductive film 907 and a conductive film 908 are sequentially stacked as the conductive film. Needless to say, the conductive film may be formed of a single layer or a stacked structure of three or more layers.

  The conductive films 907 and 908 are selected from tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), niobium (Nb), and the like. Or an alloy material or a compound material containing these elements as main components. Alternatively, a metal nitride film obtained by nitriding these elements can be used. In addition, a semiconductor material typified by polycrystalline silicon doped with an impurity element such as phosphorus can be used.

  Here, the conductive film 907 is formed using tantalum nitride, and the conductive film 908 is formed using tungsten in a stacked structure. In addition, as the conductive film 907, a single layer or a stacked film selected from tungsten nitride, molybdenum nitride, or titanium nitride is used. As the conductive film 908, a single layer or a stacked film selected from tantalum, molybdenum, or titanium is used. Can be used.

  Next, the conductive films 907 and 908 which are provided in a stacked manner are selectively removed by etching, so that the conductive films 907 and 908 are left in portions above the regions 902 and 903, so that FIG. Gate electrodes 909 and 910 are formed as shown in FIG.

  Next, a resist mask 911 is selectively formed so as to cover the region 902, and an impurity element is formed by introducing an impurity element into the region 903 using the resist mask 911 and the gate electrode 910 as a mask (FIG. 10B )reference). As the impurity element, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity is used. As the impurity element exhibiting n-type, phosphorus (P), arsenic (As), or the like can be used. As the p-type impurity element, boron (B), aluminum (Al), gallium (Ga), or the like can be used. Here, phosphorus (P) is used as the impurity element.

  By introducing the impurity element, an impurity region 912 that forms a source region or a drain region and a channel formation region 913 are formed in the region 903 as illustrated in FIG.

  Next, as illustrated in FIG. 10C, a resist mask 914 is selectively formed so as to cover the region 903, and an impurity element is introduced into the region 902 using the resist mask 914 and the gate electrode 909 as masks. Form a region. As the impurity element, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity is used. As the impurity element exhibiting n-type, phosphorus (P), arsenic (As), or the like can be used. As the p-type impurity element, boron (B), aluminum (Al), gallium (Ga), or the like can be used. Here, an impurity element (eg, boron (B)) having a conductivity type different from that of the impurity element introduced into the region 903 in FIG. 10C is introduced. As a result, an impurity region 915 and a channel formation region 916 that form a source region or a drain region are formed in the region 902.

  Next, as shown in FIG. 16, a second insulating film 917 is formed so as to cover the insulating films 905 and 906 and the gate electrodes 909 and 910, and regions 902 and 903 are formed on the second insulating film 917, respectively. A wiring 918 electrically connected to the impurity regions 912 and 915 thus formed is formed.

  The second insulating film 917 is formed by silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x> y), silicon nitride oxide (SiNxOy) (x> y) by a CVD method, a sputtering method, or the like. ) Such as an insulating film containing oxygen or nitrogen, a film containing carbon such as DLC (Diamond Like Carbon), an organic material such as epoxy, polyimide, polyamide, polyvinylphenol, benzocyclobutene, acrylic, or a siloxane material such as a siloxane resin. It can be provided in a single layer or laminated structure. Note that the siloxane material corresponds to a material including a Si—O—Si bond. Siloxane has a skeleton structure formed of a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. A fluoro group can also be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent.

  The wiring 918 is formed of aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), molybdenum (Mo), nickel (Ni), platinum (Pt), copper (Cu) by CVD or sputtering. ), Gold (Au), silver (Ag), manganese (Mn), neodymium (Nd), carbon (C), silicon (Si), or an alloy material or compound containing these elements as a main component The material is a single layer or a laminate. The alloy material containing aluminum as a main component corresponds to, for example, a material containing aluminum as a main component and containing nickel, or an alloy material containing aluminum as a main component and containing nickel and one or both of carbon and silicon. The wiring 918 may employ, for example, a stacked structure of a barrier film, an aluminum silicon (Al—Si) film, and a barrier film, or a stacked structure of a barrier film, an aluminum silicon (Al—Si) film, a titanium nitride film, and a barrier film. Note that the barrier film corresponds to a thin film formed of titanium, titanium nitride, molybdenum, or molybdenum nitride. Aluminum and aluminum silicon are optimal materials for forming the wiring 918 because they have low resistance and are inexpensive. In addition, when an upper layer and a lower barrier layer are provided, generation of hillocks of aluminum or aluminum silicon can be prevented. In addition, when a barrier film made of titanium, which is a highly reducing element, is formed, even if a thin natural oxide film is formed on the crystalline semiconductor film, the natural oxide film is reduced, and the crystalline semiconductor film is excellent. Contact can be made.

Note that the structure of the transistor is not limited to the above structure, and may be, for example, an inverted stagger structure, a fin FET structure, or the like. Note that in the fin FET structure, the short channel effect accompanying the miniaturization of the transistor size can be suppressed.

Further, this embodiment mode may be freely combined with the description of other embodiment modes in this specification.

(Embodiment 5)
In this embodiment, a method for manufacturing a transistor included in the semiconductor device of the present invention, which is different from that in the above embodiment, will be described. The transistor in the semiconductor device of the present invention can be formed using a MOS transistor provided by a different manufacturing method from the MOS transistor over the single crystal substrate described in the above embodiment.

In this embodiment, an example of a method for manufacturing a transistor included in a semiconductor device such as an RFID will be described with reference to partial cross-sectional views in FIGS.

  First, an insulating film is formed over the substrate 1200 as illustrated in FIG. Here, single crystal Si having n-type conductivity is used as the substrate 1200, and the insulating film 1201 and the insulating film 1202 are formed over the substrate 1200. For example, heat treatment is performed on the substrate 1200 to form silicon oxide (SiOx) as the insulating film 1201, and silicon nitride (SiNx) is formed over the insulating film 1201 by a CVD method.

  Further, the substrate 1200 can be used without any particular limitation as long as it is a semiconductor substrate. For example, a single crystal Si substrate having an n-type or p-type conductivity, a compound semiconductor substrate (GaAs substrate, InP substrate, GaN substrate, SiC substrate, sapphire substrate, ZnSe substrate, etc.), bonding method or SIMOX (Separation by IMplanted) An SOI (Silicon on Insulator) substrate manufactured using an OXygen method or the like can be used.

  Alternatively, the insulating film 1202 may be provided by nitriding the insulating film 1201 by high-density plasma treatment after the insulating film 1201 is formed. Note that the insulating film provided over the substrate 1200 may be provided with a single layer or a stacked structure of three or more layers.

  Next, as illustrated in FIG. 12B, a resist mask 1203 pattern is selectively formed over the insulating film 1202, and selective etching is performed on the substrate 1200 by using the resist mask 1203 as a mask. A recess 1204 is formed in the substrate. Etching of the substrate 1200 and the insulating films 1201 and 1202 can be performed by dry etching using plasma.

  Next, as shown in FIG. 12C, after the pattern of the resist mask 1203 is removed, an insulating film 1205 is formed so as to fill the recess 1204 formed in the substrate 1200.

  The insulating film 1205 is formed using silicon oxide, silicon nitride, silicon oxynitride (SiOxNy) (x> y> 0), silicon nitride oxide (SiNxOy) (x> y> 0), or the like using a CVD method, a sputtering method, or the like. It is formed using an insulating material. Here, as the insulating film 1205, a silicon oxide film is formed using TEOS (tetraethoxysilane) gas by an atmospheric pressure CVD method or a low pressure CVD method.

  Next, as shown in FIG. 13A, a surface of the substrate 1200 is exposed by performing a grinding process, a polishing process, or a CMP (Chemical Mechanical Polishing) process. Here, regions 1207 and 1208 are provided between the insulating films 1206 formed in the recesses 1204 of the substrate 1200 by exposing the surface of the substrate 1200. Note that the insulating film 1206 is obtained by removing the insulating film 1205 formed over the surface of the substrate 1200 by grinding, polishing, or CMP. Subsequently, a p-well 1209 is formed in the region 1208 by selectively introducing an impurity element having p-type conductivity.

  As the p-type impurity element, boron (B), aluminum (Al), gallium (Ga), or the like can be used. Here, boron (B) is introduced into the region 1208 as the impurity element.

  Note that in this embodiment, since a semiconductor substrate having an n-type conductivity type is used as the substrate 1200, no impurity element is introduced into the region 1207, but by introducing an impurity element exhibiting n-type conductivity. An n-well may be formed in the region 1207. As the impurity element exhibiting n-type, phosphorus (P), arsenic (As), or the like can be used.

  On the other hand, when a semiconductor substrate having p-type conductivity is used, an n-type impurity element is introduced into the region 1207 to form an n-well, and no impurity element is introduced into the region 1208. Good.

  Next, as illustrated in FIG. 13B, insulating films 1210 and 1211 are formed over the surfaces of the regions 1207 and 1208 of the substrate 1200, respectively.

  As the insulating films 1210 and 1211, for example, the surfaces of the regions 1207 and 1208 provided in the substrate 1200 are oxidized by heat treatment, whereby the insulating films 1210 and 1211 can be formed using silicon oxide films. In addition, after a silicon oxide film is formed by a thermal oxidation method, the surface of the silicon oxide film is nitrided by performing nitriding treatment, so that a silicon oxide film and a film containing oxygen and nitrogen (silicon oxynitride film) are stacked. You may form with a structure.

  In addition, as described above, the insulating films 1210 and 1211 may be formed by plasma treatment. For example, the surface of the regions 1207 and 1208 provided in the substrate 1200 is oxidized or nitrided by high-density plasma treatment, whereby a silicon oxide (SiOx) film or a silicon nitride (SiNx) film is used as the insulating films 1210 and 1211. Can be formed. Alternatively, the surface of the regions 1207 and 1208 may be oxidized by high-density plasma treatment, and then nitridation may be performed by performing high-density plasma treatment again. In this case, a silicon oxide film is formed in contact with the surfaces of the regions 1207 and 1208, a silicon oxynitride film is formed over the silicon oxide film, and the insulating films 1210 and 1211 are formed by stacking a silicon oxide film and a silicon oxynitride film. The resulting film. Alternatively, after a silicon oxide film is formed on the surfaces of the regions 1207 and 1208 by a thermal oxidation method, oxidation treatment or nitridation treatment may be performed by high-density plasma treatment.

  Note that the insulating films 1210 and 1211 formed in the regions 1207 and 1208 of the substrate 1200 function as gate insulating films in transistors to be completed later.

  Next, as illustrated in FIG. 13C, a conductive film is formed so as to cover the insulating films 1210 and 1211 formed over the regions 1207 and 1208 provided in the substrate 1200. Here, an example is shown in which a conductive film 1212 and a conductive film 1213 are sequentially stacked as the conductive film. Needless to say, the conductive film may be formed of a single layer or a stacked structure of three or more layers.

  The conductive films 1212 and 1213 are selected from tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), niobium (Nb), and the like. Or an alloy material or a compound material containing these elements as main components. Alternatively, a metal nitride film obtained by nitriding these elements can be used. In addition, a semiconductor material typified by polycrystalline silicon doped with an impurity element such as phosphorus can be used.

  Here, the conductive film 1212 is formed using tantalum nitride, and the conductive film 1213 is formed using tungsten in a stacked structure. In addition, the conductive film 1212 is a single layer or a laminated film selected from tantalum nitride, tungsten nitride, molybdenum nitride, or titanium nitride, and the conductive film 1213 is selected from tungsten, tantalum, molybdenum, or titanium. A single layer or a laminated film can be used.

  Next, as shown in FIG. 14A, the conductive films 1212 and 1213 provided in a stacked manner are selectively removed by etching, so that a conductive film is formed over part of the regions 1207 and 1208 of the substrate 1200. Conductive films 1214 and 1215 functioning as gate electrodes are formed by leaving 1212 and 1213, respectively. Here, in the substrate 1200, the surfaces of the regions 1207 and 1208 that do not overlap with the conductive films 1214 and 1215 are exposed.

  Specifically, in a region 1207 of the substrate 1200, a portion of the insulating film 1210 formed below the conductive film 1214 that does not overlap with the conductive film 1214 is selectively removed, so that edges of the conductive film 1214 and the insulating film 1210 are removed. The parts are formed so as to roughly match. Further, in the region 1208, a portion of the insulating film 1211 formed below the conductive film 1215 that does not overlap with the conductive film 1215 is selectively removed so that the end portions of the conductive film 1215 and the insulating film 1211 substantially coincide with each other. To form.

  In this case, an insulating film or the like that does not overlap with the formation of the conductive films 1214 and 1215 may be removed, or the resist mask remaining after the formation of the conductive films 1214 and 1215 or the conductive films 1214 and 1215 is used as a mask. A portion of the insulating film that does not become necessary may be removed.

  Next, as shown in FIG. 14B, an impurity element is selectively introduced into the regions 1207 and 1208 of the substrate 1200. Here, a low-concentration impurity element imparting n-type conductivity is selectively introduced into the region 1208 using the conductive film 1215 as a mask, so that the impurity region 1217 is formed. On the other hand, a low concentration impurity element imparting p-type conductivity is selectively introduced into the region 1207 using the conductive film 1214 as a mask, so that an impurity region 1216 is formed. As the impurity element imparting n-type conductivity, phosphorus (P), arsenic (As), or the like can be used. As the impurity element imparting p-type conductivity, boron (B), aluminum (Al), gallium (Ga), or the like can be used.

  Next, sidewalls 1218 in contact with the side surfaces of the conductive films 1214 and 1215 are formed. Specifically, a film containing an inorganic material such as silicon, silicon oxide, or silicon nitride, or a film containing an organic material such as an organic resin is formed in a single layer or stacked layers by a plasma CVD method, a sputtering method, or the like. Form. Then, the insulating film can be selectively etched by anisotropic etching mainly in the vertical direction so as to be in contact with the side surfaces of the conductive films 1214 and 1215. Note that the sidewall 1218 is used as a mask for doping when an LDD (Lightly Doped Drain) region is formed. Here, the sidewalls 1218 are formed so as to be in contact with the side surfaces of the insulating films and the floating gate electrodes formed below the conductive films 1214 and 1215.

  Subsequently, an impurity element functioning as a source region or a drain region is formed by introducing an impurity element into the regions 1207 and 1208 of the substrate 1200 using the sidewalls 1218 and the conductive films 1214 and 1215 as masks (FIG. 14C )reference). Here, a high-concentration n-type impurity element is introduced into the region 1208 of the substrate 1200 using the sidewall 1218 and the conductive film 1215 as a mask, and a high-concentration p is used as the region 1207 using the sidewall 1218 and the conductive film 1214 as a mask. Impurity elements that impart molds are introduced.

  As a result, an impurity region 1220 that forms a source region or a drain region, a low-concentration impurity region 1221 that forms an LDD region, and a channel formation region 1222 are formed in the region 1207 of the substrate 1200. In the region 1208 of the substrate 1200, an impurity region 1223 that forms a source region or a drain region, a low-concentration impurity region 1224 that forms an LDD region, and a channel formation region 1225 are formed.

  Note that in this embodiment, the impurity element is introduced in a state where the regions 1207 and 1208 of the substrate 1200 that do not overlap with the conductive films 1214 and 1215 are exposed. Accordingly, channel formation regions 1222 and 1225 formed in the regions 1207 and 1208 of the substrate 1200 can be formed in a self-aligned manner with the conductive films 1214 and 1215.

  Next, as illustrated in FIG. 15A, a second insulating film 1226 is formed so as to cover an insulating film, a conductive film, or the like provided over the regions 1207 and 1208 of the substrate 1200, and an opening is formed in the insulating film 1226. A portion 1227 is formed.

  The second insulating film 1226 is formed by silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x> y), silicon nitride oxide (SiNxOy) (x> y) by a CVD method, a sputtering method, or the like. ) Such as an insulating film containing oxygen or nitrogen, a film containing carbon such as DLC (Diamond Like Carbon), an organic material such as epoxy, polyimide, polyamide, polyvinylphenol, benzocyclobutene, acrylic, or a siloxane material such as a siloxane resin. It can be provided in a single layer or laminated structure. Note that the siloxane material corresponds to a material including a Si—O—Si bond. Siloxane has a skeleton structure formed of a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. A fluoro group can also be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent.

  Next, as illustrated in FIG. 15B, a conductive film 1228 is formed in the opening 1227 by a CVD method, and the conductive films 1229a to 1229d are formed over the insulating film 1226 so as to be electrically connected to the conductive film 1228. Are selectively formed.

  The conductive films 1228 and 1229a to 1229d are formed of aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), molybdenum (Mo), nickel (Ni), platinum (Pt) by CVD or sputtering. ), Copper (Cu), gold (Au), silver (Ag), manganese (Mn), neodymium (Nd), carbon (C), silicon (Si), or these elements as main components An alloy material or a compound material to be formed is a single layer or a laminated layer. The alloy material containing aluminum as a main component corresponds to, for example, a material containing aluminum as a main component and containing nickel, or an alloy material containing aluminum as a main component and containing nickel and one or both of carbon and silicon. The conductive films 1228 and 1229a to 1229d include, for example, a laminated structure of a barrier film, an aluminum silicon (Al—Si) film, and a barrier film, and a laminated structure of a barrier film, an aluminum silicon (Al—Si) film, a titanium nitride film, and a barrier film. Should be adopted. Note that the barrier film corresponds to a thin film formed of titanium, titanium nitride, molybdenum, or molybdenum nitride. Aluminum and aluminum silicon are suitable materials for forming the conductive film 1228 because they have low resistance and are inexpensive. In addition, when an upper layer and a lower barrier layer are provided, generation of hillocks of aluminum or aluminum silicon can be prevented. In addition, when a barrier film made of titanium, which is a highly reducing element, is formed, even if a thin natural oxide film is formed on the crystalline semiconductor film, the natural oxide film is reduced, and the crystalline semiconductor film is excellent. Contact can be made. Here, the conductive film 1228 can be formed by selectively growing tungsten (W) by a CVD method.

  Through the above steps, a semiconductor device including a p-type transistor formed in the region 1207 of the substrate 1200 and an n-type transistor formed in the region 1208 can be obtained.

Note that the structure of the transistor is not limited to the above structure, and may be, for example, an inverted stagger structure, a fin FET structure, or the like. Note that in the fin FET structure, the short channel effect accompanying the miniaturization of the transistor size can be suppressed.

Further, this embodiment mode may be freely combined with the description of other embodiment modes in this specification.

(Embodiment 6)
In this embodiment, the use of a semiconductor device such as an RFID according to the present invention will be described. The semiconductor device of the present invention includes, for example, banknotes, coins, securities, bearer bonds, certificate documents (driver's license, resident's card, etc.), packaging containers (wrapping paper, bottles, etc.), recording media (DVD software) And videotapes), vehicles (bicycles, etc.), personal items (such as bags and glasses), foods, plants, animals, human bodies, clothing, daily necessities, electronic equipment, etc. and luggage tags It can be used as a so-called ID label, ID tag, or ID card provided on an article. Electronic devices refer to liquid crystal display devices, EL display devices, television devices (also simply referred to as televisions, television receivers, television receivers), mobile phones, and the like. Note that the regulator circuit included in the semiconductor device of the present invention has a small layout area, is easy to design, and can reduce adverse effects of noise generated in the semiconductor device on circuit operation. Therefore, a highly reliable semiconductor device can be provided in an article or the like.

  In this embodiment, an application example of the present invention and an example of a product to which they are attached will be described with reference to FIG.

  FIG. 16A illustrates an example of a state of a completed semiconductor device having an RFID according to the present invention. A plurality of ID labels 1603 incorporating RFID 1602 are formed on a label mount 1601 (separate paper). The ID label 1603 is stored in the box 1604. On the ID label 1603, information (product name, brand, trademark, trademark owner, seller, manufacturer, etc.) related to the product or service is recorded, while the built-in RFID includes An ID number unique to the product (or product type) is attached, and it is possible to easily grasp illegal activities such as forgery, infringement of intellectual property rights such as trademark rights and patent rights, and unfair competition. In addition, in the RFID, a great deal of information that cannot be clearly stated on the container or label of the product, for example, the product's production area, sales place, quality, raw materials, efficacy, use, quantity, shape, price, production method, usage method, Production time, use time, expiration date, handling instructions, intellectual property information related to products, etc. can be input, and a trader and a consumer can access such information with a simple reader. In addition, rewriting and erasing can be easily performed from the producer side, but rewriting and erasing etc. are not possible from the trader and the consumer side.

  FIG. 16B illustrates a label-like ID tag 1611 in which an RFID 1612 is incorporated. By providing the ID tag 1611 on the product, product management becomes easy. For example, when a product is stolen, the culprit can be quickly grasped by following the route of the product. Thus, by providing the ID tag, it is possible to distribute a product excellent in so-called traceability.

  FIG. 16C shows an example of a state of a completed product of the ID card 1621 including the RFID 1622 according to the present invention. The ID card 1621 includes all kinds of cards such as a cash card, a credit card, a prepaid card, an electronic ticket, electronic money, a telephone card, and a membership card.

  FIG. 16D shows a state of a completed product of the bearer bond 1631. An RFID 1632 is embedded in the bearer bond 1631, and the periphery thereof is molded with resin to protect the RFID. Here, the resin is filled with a filler. The bearer bond 1631 can be created in the same manner as the ID label, ID tag, and ID card according to the present invention. The bearer bonds include stamps, tickets, tickets, admission tickets, gift certificates, book tickets, stationery tickets, beer tickets, gift tickets, various gift certificates, various service tickets, etc. Is not to be done. Further, by providing the RFID 1632 of the present invention to bills, coins, securities, bearer bonds, certificates, etc., an authentication function can be provided, and forgery can be prevented by utilizing this authentication function. .

  FIG. 16E shows a book 1643 attached with an ID label 1641 containing an RFID 1642 according to the present invention. The RFID 1642 of the present invention is fixed to an article by being pasted or embedded on the surface. As shown in FIG. 16E, a book is embedded in paper, and a package made of an organic resin is embedded in the organic resin, and is fixed to each article. The RFID 1642 of the present invention realizes a small size, a thin shape, and a light weight, and thus does not impair the design of the product itself even after being fixed to the product.

Although not shown here, by providing the RFID of the present invention to packaging containers, recording media, personal items, foods, clothing, daily necessities, electronic devices, etc., the efficiency of the inspection system etc. can be improved. Can be planned. In addition, forgery and theft can be prevented by providing RFID for vehicles. In addition, by embedding in creatures such as animals, it is possible to easily identify individual creatures. For example, by burying a wireless tag in a living creature such as livestock, it is possible to easily identify the year of birth, sex, type, or the like.

  As described above, the RFID of the present invention can be provided and used for any article (including living creatures).

Further, this embodiment mode may be freely combined with the description of other embodiment modes in this specification.

4A and 4B illustrate a semiconductor device of the present invention. 4A and 4B illustrate a semiconductor device of the present invention. 4A and 4B illustrate a semiconductor device of the present invention. The figure which shows one structural example of a regulator circuit Partial sectional view of the semiconductor device of the present invention Partial sectional view of the semiconductor device of the present invention Partial sectional view of the semiconductor device of the present invention 4A and 4B illustrate a semiconductor device of the present invention. Sectional drawing of the transistor which the semiconductor device of this invention has Sectional drawing of the transistor which the semiconductor device of this invention has Sectional drawing of the transistor which the semiconductor device of this invention has Sectional drawing of the transistor which the semiconductor device of this invention has Sectional drawing of the transistor which the semiconductor device of this invention has Sectional drawing of the transistor which the semiconductor device of this invention has Sectional drawing of the transistor which the semiconductor device of this invention has The figure explaining an example of the article | item concerning this invention The figure explaining the conventional composition

Explanation of symbols

Reference Signs List 101 antenna 102 rectifier circuit 103 regulator circuit 104 first circuit 105 level shifter circuit 106 second circuit 201 regulator circuit 300 RFID
301 Antenna Circuit 302 Signal Processing Circuit 303 Rectification Circuit 305 Demodulation Circuit 306 Clock Generation Circuit 307 Logic Circuit 308 Memory Control Circuit 309 Memory Circuit 310 Logic Circuit 311 Amplifier 312 Modulation Circuit 401 Terminal 402 Resistance 403 Zener Diode 404 Operational Amplifier 405 Terminal 406 Resistance 407 Resistance 408 Transistor 1001 Antenna 1002 Rectifier circuit 1003 Regulator circuit 1004 Circuit group

Claims (5)

An antenna that transmits and receives signals, a rectifier circuit, a regulator circuit, a first circuit, and a second circuit that exchanges signals with the first circuit;
The first circuit is a circuit that requires an arbitrary stable potential;
The power supply potential generated by the antenna and the rectifier circuit is supplied to the first circuit and the second circuit,
The semiconductor device, wherein the power supply potential is supplied to the first circuit through the regulator circuit. An antenna that transmits and receives signals, a rectifier circuit, a first regulator circuit, a second regulator circuit, a first circuit, and a second circuit that exchanges signals with the first circuit;
The first circuit is a circuit that requires an arbitrary stable potential;
The power supply potential generated by the antenna and the rectifier circuit is supplied to the first circuit via the first regulator circuit.
A power supply potential generated by the antenna and the rectifier circuit is supplied to the second circuit through the second regulator circuit. An antenna that transmits and receives signals, a rectifier circuit, a regulator circuit, a voltage limiter circuit, a first circuit, and a second circuit that exchanges signals with the first circuit;
The first circuit is a circuit that requires an arbitrary stable potential;
The power supply potential generated by the antenna and the rectifier circuit is supplied to the first circuit via the regulator circuit,
A power supply potential generated by the antenna and the rectifier circuit is supplied to the second circuit through the voltage limiter circuit. In any one of Claims 1 thru | or 3,
The semiconductor device, wherein the first circuit includes a clock generation circuit. In any one of Claims 1 thru | or 4,
The semiconductor device according to claim 1, wherein signal exchange between the first circuit and the second circuit is performed through a level shifter circuit.

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