JP2002269519A - Semiconductor device and ic card using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the influence which accompanies increase in a memory area 21 in an IC card 31 comprising the electrically rewritable nonvolatile memory area 21, a control circuit 26 for performing arithmetic processings by the use of the data of the memory area 21, and a noncontact interface 33 for conduct communication of signal and a power supply without contact with an external device. SOLUTION: A regulator 46 for the memory area 21 is provided in the noncontact interface 33 separately from a regulator 45 for the control circuit 36. Accordingly, in the rewriting of the memory area 21 by the power supply by the noncontact interface 33, no booster circuit is required for generation of high voltage, and the power consumption can be thus suppressed, so that a flash memory which is easy to increase in capacity can be mounted. Further more, the power source voltage for the control circuit 36 can be stabilized and sneaking in of noise into the power supply system for the control circuit 36 can be minimized to suppress malfunctions also.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention has an electrically rewritable non-volatile storage area, and uses a non-contact power supplied from an external device to rewrite the non-volatile storage area. The present invention relates to a semiconductor device for producing a required voltage, and particularly to an IC card suitably used as a non-contact IC card using the semiconductor device.

[0002]

2. Description of the Related Art The non-contact type IC card is widely used for a lift ticket at a ski resort, a tag for clothing, and the like, and recently, a commuter pass for a public organization.
FIG. 9 is a block diagram showing an electrical configuration of an IC card 1 which is a typical conventional semiconductor device. The IC card 1 generally includes a CPU core 2, a non-contact interface 3, a booster circuit 4, and an antenna 5
The SI is configured by being provided inside a card-shaped base material.

The CPU core 2 has almost the same configuration as that of a normal microcomputer.
ROM 7, RAM 8, and a non-volatile storage area E
An EPROM 9 is provided. The ROM 7 stores a program of a function required for the IC card 1, and the RAM 8 is used as a working memory during the calculation by the program. The EEPROM 9 is used to hold data.

The non-contact interface 3 includes a modulation circuit 11 for generating a signal to be transmitted to an external device via the antenna 5, a demodulation circuit 12 for demodulating a signal received from the external device, and a clock from the received signal. A clock separation circuit 13 for separating CLK, a rectification circuit 14 for rectifying power supplied from the external device, a power supply from the rectification circuit 14 for stabilizing the power,
And a regulator 15 for supplying to the power supply.

In the IC card 1 configured as described above, access from an external device is performed by a signal obtained by converting an electromagnetic wave input / output via the antenna 5. Access to the EEPROM 9 as a memory is performed by a program in the ROM 7. Further, general IC cards cannot be directly accessed from outside. Therefore, unauthorized access to the memory can be controlled by software, and high confidentiality of information in the memory is realized.

The above-mentioned EEPROM is an example of a semiconductor having an electrically rewritable nonvolatile storage area mounted on an IC card. First, the structure of the EEPROM will be described. Figure 1
0 is a diagram showing a typical basic structure of the memory cell c of the EEPROM. This memory cell c is 2 cells / 1
It has a bit configuration and includes a selection transistor q1 and a memory transistor q2.

FIG. 11 is a configuration diagram of a cell array ca using the cell structure of FIG. The cell array ca includes memory cells c11 to c1n; c21 to c2n; cm1 to c
mn. The ground line sg of each memory transistor q2 is commonly connected to a ground line gnd. Control gate g of each memory transistor q2
c are bundled for each memory cell in a row, and the gate line w
1, w2, ..., wn. Also, the selection transistor q1
Are similarly bundled, and the gate lines w11,
w22,..., Wmm. The data input / output bit lines sb of the selection transistor q1 are bundled for each column and become bit lines b1, b2,..., Bn.

The EEPROM 9 has a feature that writing and erasing can be performed bit by bit because of the selection transistor q1 as described above. For example, when erasing the memory cell c11, the gate lines w1, w1
1 and the bit line b1 are applied with a high voltage (for example, 20 V), and the remaining gate lines w2 to wm; w22 to Wmm
When the bit lines b2 to bn are set to a low voltage (for example, 0 V), a high voltage is applied only to the memory cell c11, and the remaining memory cells c12 to c1n; c21 to c2n; cm
1 to cmn have a low voltage, that is, no voltage is applied, and only the memory cell c11 can be erased as described above.

When reading data from the memory cell c11, a high voltage (for example, 5 V) is applied only to the gate line w11, and the remaining gate lines w1 to wm; w
When a low voltage (for example, 0 V) is applied to 22 to wmm,
For example, the threshold values of the memory cells c12 to c1n become negative,
Even in a depletion type storage state where the gate is turned on even at 0 V, it is cut off by the selection transistor q1, and only data from the memory cell c11 is output to the bit line b1. Thus, the EEPROM 9
The use of the selection transistor q1 makes it very easy to use.

However, the EEPR in the CPU core 2
Rewriting or erasing the data of the OM 9 requires a high voltage (for example, 20 V) as described above. Therefore, a power supply voltage Vpp higher than the power supply voltage Vcc of the control circuit 6 is required, and the booster circuit 4 further boosts the power supply voltage Vcc from the regulator 15 to the power supply voltage Vpp and performs EE
It is supplied to the PROM 9.

On the other hand, recent IC cards are required to be compatible with various uses such as electronic money, basic resident register, medical data, and the like, and accordingly, it is necessary to realize a large data area. I'm under pressure. However, the EEPROM 9 serving as the data area has a capacity of 2 cells / 1 cell as described above.
Bit, and is not suitable for increasing the capacity. That is,
Increasing the area of the data region means that the area of the LSI also increases, and chip breakage due to bending, disconnection of bonding wires, and the like are likely to occur, resulting in low reliability.

In view of the above, a semiconductor device having an electrically rewritable nonvolatile storage area that can be expected to have a large capacity includes a flash memory occupying a small area per bit. FIG. 12 shows a typical structure of the memory cell C of the flash memory. This memory cell C
Has a one-cell / one-bit configuration, which includes a control gate GC, a floating gate GF, a source S, and a drain D, and is called a floating gate type field effect transistor.

FIG. 13 is a configuration diagram of a cell array CA using the cell structure of FIG. The cell array CA includes memory cells C11 to C1n; C21 to C2n;
mn. The source S is common for a certain number (for example, blocks, m × n in FIG. 13), and m word lines W1, W2,..., Respectively connected to n control gates GC. Wm
And n bit lines B1, B2,..., Bn connected to the m drains D, respectively.

In the operation of the flash memory thus configured, first, when writing data to the memory cell C, a high voltage (eg, 12 V) is applied to the control gate GC, and a high voltage (eg, 7 V) is similarly applied to the drain D. , Source S
Is applied by applying a low voltage (for example, 0 V) to the floating gate FG. On the other hand, erasing is performed by applying a low voltage (for example, 0 V) to the control gate GC.
A low voltage (eg, 0 V) is applied to the drain D, and a high voltage (eg, 12 V) is applied to the source S to generate a high electric field between the floating gate GF and the source S. GF
This is performed by extracting the electrons inside from the source S. further,
In reading, a high voltage (for example, 5 V) is applied to the control gate GC, a low voltage (for example, 1 V) is applied to the drain D, and a low voltage (for example, 0 V) is similarly applied to the source S. This is performed by amplifying the data with an internal sense amplifier and determining whether the data is “1” or “0”.

The reason why the voltage of the drain D is set lower than that of the control gate GC at the time of writing is to prevent parasitic weak writing (soft programming) to a memory cell where writing is not performed as much as possible. This is because a plurality of memory cells C are connected to one word line W1 to Wm and one bit line B1 to Bn, respectively, like the selection transistor q1 that separates the memory transistor q2 from the bit lines b1 to bn. This is because a simple configuration is not provided.

In order to maintain high reliability and to perform writing and erasing (hereinafter collectively referred to as rewriting for simplicity) of the flash memory in this manner, very complicated control is required. For this reason, many recent semiconductor devices equipped with a flash memory have a built-in control circuit called a state machine in order to improve the apparent usability of the user, thereby realizing automatic rewriting. .

FIG. 14 is a diagram showing a specific configuration example of the flash memory 21 for realizing such automatic rewriting. The control circuit 6 controls the booster circuit 4 and the write / erase voltage generation circuit 2 via the control bus 22 during normal operation.
3, row decoder 24, column decoder 25, sense amplifier 2
6. The input / output buffer 27 and the address register 28 are controlled as required. The booster circuit 4 operates at the time of rewriting data, and generates the high voltage Vpp of, for example, 12 V. The write / erase voltage generation circuit 23 is a circuit that generates a high voltage necessary for a rewrite operation from the high voltage Vpp boosted by the booster circuit 4, and is applied to, for example, the drain D of the flash memory cell C at the time of writing. High voltage (7
V) is the high voltage Vpp from the booster circuit 4 (12
V) is generated by lowering the voltage with a built-in regulator circuit. The power supply voltage (for example, Vcc) of another peripheral circuit such as the sense amplifier 26 is separated.

[0018]

When the flash memory 21 as described above is used for the IC card 1 shown in FIG.
The memory capacity of the flash memory 21 is about 1 Kbyte or more, whereas the memory capacity of the flash memory 21 is about 16 Kbytes, so that the power consumption in the memory increases and the loss in the booster circuit 4 becomes a problem. For example, with the above capacity, an EEPROM
9, the power consumption of the flash memory 21 is about twice that of the power consumption of the flash memory 21, and the power consumption of the voltage Vpp system is larger than that of the voltage Vcc system.
For this reason, the loss of the regulator 15 and the loss of the voltage boosting circuit 4 add up to the ratio of the voltage Vpp-related loss to the total loss of the IC card 1, resulting in an extremely large power consumption. There is.

The voltage Vcc from the regulator 15
Since the power of the system is mainly consumed by the control circuit 6 and the voltage Vcc is kept at a constant level following the consumption, when the power consumption of the voltage Vpp system in the flash memory 21 increases, the power supply voltage Vcc increases. In addition to being unstable, there is a problem that a change in power consumption in the booster circuit 4 enters the power supply voltage Vcc as noise and affects communication through the rectifier circuit 14.

On the other hand, as a contact / non-contact IC card, there is one disclosed in Japanese Patent Application Laid-Open No. 10-320510. This prior art includes an RF circuit and an electrically rewritable nonvolatile storage area, and when the power is supplied from the contact, the power consumption is covered by it.
Power is supplied from the F circuit. In this prior art, similarly to the configuration shown in FIG. 9, the voltage supplied to the nonvolatile storage area is the same as the voltage for operating other peripheral circuits, and it is necessary to mount a booster circuit.

An object of the present invention is to have an electrically rewritable nonvolatile storage area, and to set a voltage required for rewriting the nonvolatile storage area based on electric power supplied from an external device in a non-contact manner. It is an object of the present invention to provide a semiconductor device to be manufactured, which can suppress the influence of the increase in the storage area and an IC card using the same.

[0022]

According to the present invention, there is provided a semiconductor device comprising:
An electrically rewritable non-volatile storage area, a control circuit that performs arithmetic processing using data in the storage area, and a non-contact interface function unit that performs signal communication and power supply without contact with an external device. The non-contact interface function unit generates a power supply voltage required for rewriting the nonvolatile storage area different from a power supply voltage for the control circuit, together with power supply means for the control circuit. And a power supply means for a storage area to be provided.

According to the above configuration, when power is supplied to a nonvolatile storage area such as a flash memory which requires a high rewrite voltage, the power supply means for the control circuit is provided in the non-contact interface function unit. Is separately provided with power supply means for the storage area.

Therefore, when rewriting the electrically rewritable nonvolatile storage area by supplying power through the non-contact interface, a booster circuit is not required to generate a high voltage, thereby reducing power consumption and increasing capacity. It is possible to mount a flash memory which can be easily implemented. Furthermore, the power supply voltage for the control circuit can be stabilized, and noise spillage to the power supply system for the control circuit can be reduced, and malfunction can be suppressed. In this way, it is possible to suppress the influence of the increase in the storage area.

Further, in the semiconductor device according to the present invention, the non-contact interface function unit includes a full-wave rectifier circuit including a diode bridge and two capacitors provided between one AC terminal and two DC terminals. 2 with
A voltage doubler rectifier circuit is further provided, and an output voltage of the doubler rectifier circuit is commonly supplied to a power supply unit for the control circuit and a power supply unit for a storage area.

According to the above configuration, a high voltage can be more easily generated by using the double voltage rectifier circuit. Further, a double voltage can be created with a simple configuration in which only two capacitors are added to the full-wave rectifier circuit.

Further, the semiconductor device of the present invention includes a booster circuit for boosting a power supply voltage for the storage area, a voltage detection circuit for monitoring a power supply voltage required for rewriting the nonvolatile storage area, When the detection circuit detects that the output voltage of the power supply means for the storage area is not the power supply voltage required for rewriting the nonvolatile storage area, the power supply voltage for rewriting the nonvolatile storage area A selection circuit for switching the output voltage of the power supply means for the storage area to the output voltage of the booster circuit and supplying the output voltage.

According to the above configuration, the output voltage of the power supply means for the storage area is naturally higher than the output voltage of the power supply means for the control circuit even if the booster circuit is provided as in the conventional IC card. Since the voltage is used, the circuit scale of the booster circuit can be small, and power loss can be reduced.
In addition, the voltage detecting circuit operates the boosting circuit only when the voltage needs to be boosted, so that the boosting circuit does not consume power unnecessarily and receives the electromagnetic wave in an optimized state from the antenna. Even in the case where it is not possible (for example, when the distance from the reader / writer device is long), it is possible to obtain the high voltage necessary for rewriting the nonvolatile storage area, and it is possible to stably supply power in a non-contact manner. .

Further, the IC card according to the present invention is characterized in that the above-mentioned semiconductor device is provided inside a card-like base material.

[0030]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described.
It is as follows if it demonstrates based on FIGS. 1-4 and FIG.

FIG. 1 is a block diagram showing an electrical configuration of an IC card 31 which is a semiconductor device according to one embodiment of the present invention. The IC card 31 generally includes a CPU core 32, a non-contact interface 33, and an antenna 34.
An LSI having the following configuration is mounted on a card-shaped base material.

Although the CPU core 32 has almost the same structure as a normal microcomputer, it has the flash memory 21 shown in FIG. 14 as a nonvolatile storage area, and has a control circuit 36, a ROM 37, and a RAM.
38 are further provided. The ROM 37 stores a program of a function required for the IC card 31, and the RAM 38 is used as a working memory during the calculation by the program. Flash memory 2
1 is used to hold data, and as shown in FIG. 14, a control bus 22, a write / erase voltage generation circuit 23, a row decoder 24, a column decoder 25, a sense amplifier 26, an input / output buffer 27, an address It comprises a register 28 and a cell array CA.

The non-contact interface 33 includes a modulation circuit 41 for generating a signal to be transmitted to an external device via an antenna 34, a demodulation circuit 42 for demodulating a signal received from the external device, and a clock from a received signal. A clock separation circuit 43 for separating CLK, a rectification circuit 44 for rectifying power supplied from the external device, and a rectification circuit 44
And regulators 45 and 46 for stabilizing the power from the power supply.

Electromagnetic waves transmitted from an external reader / writer (not shown) pass through an antenna 34 mounted on the IC card 31 to excite electromotive force, and are converted into a positive voltage through a rectifier circuit 44. And regulator 4
5 and 46 are smoothed. The regulator 46 is
A high voltage Vpp for rewriting is supplied to the flash memory 21 in the CPU core 32. The regulator 45 is
The power supply voltage Vcc is supplied not only to the flash memory 21 but also to circuits other than the flash memory 21 in the CPU core 32.

The control signal converted into the electromagnetic wave is received by the antenna 34, and the clock separation circuit 43 generates the internal clock CLK. The frequency of the internal clock CLK is approximately 1 to 5 MHz. Further, the signal received by the antenna 34 is transmitted through a demodulation circuit 42 to a CP.
It is provided to a control circuit 36 in the U core 32. The control circuit 32 uses the applied signal to read the ROM 37, RA
The M38 and the flash memory 21 are controlled to perform processing such as calculation. The result calculated in the CPU core 32 is converted into an AC signal having a predetermined band through the modulation circuit 41, and is output from the antenna 34 as an electromagnetic wave. The reader / writer device receives this electromagnetic wave and demodulates it into a signal through a demodulation circuit. Thus, the communication between the reader / writer device and the IC card 31 is completed.

The rectifier circuit 44 is configured, for example, as shown in FIG. The rectifier circuit 44 performs full-wave rectification, and can obtain approximately twice as much power as half-wave rectification. Antenna 48 of reader / writer device 47
The voltage induced in the antenna 34 is subjected to full-wave rectification by a rectifier circuit 44 implemented by a bridge circuit including diodes D1 to D4, and is provided to the regulators 45 and 46. The voltage generated by the rectifier circuit 44 is a voltage Vpp required to rewrite the flash memory 21.
(For example, 14 V) and is output via the regulator 46.

On the other hand, the regulator 45
6, circuits necessary for the read operation of the ROM 37 and the RAM 38 and the flash memory 21 (the row decoder 2
4. An operating power supply voltage Vcc for the address register 28, the cell array CA, the column decoder 25, the sense amplifier 26, and the input / output buffer 27, for example, 5 V or 3.3 V is generated.

When data is written to or erased from the flash memory 21 as a result of an operation or the like by the control circuit 36, the control circuit 36 enables the write / erase voltage generation circuit 23. The write / erase voltage generation circuit 23
The high voltage Vpp (for example, 12
V), a voltage to be applied to the control gate GC, the drain D, and the source S of the memory cell CA shown in FIGS. The control circuit 36 controls the row decoder 24
In addition, the circuit in the flash memory 21 such as the column decoder 25 is controlled, and the voltage generated by the write / erase voltage generation circuit 23 is applied to the memory cell CA.

For example, at the time of writing, a high voltage (eg, 12 V) is applied to the control gate GC, and the drain D
A high voltage (for example, 7 V) is applied to the source S, and a low voltage (for example, 0 V) is applied to the source S. At the time of erasing, a low voltage (eg, 0 V) is applied to the control gate GC, and the drain D
A low voltage (for example, 0 V) is applied to the source S, and a high voltage (for example, 12 V) is applied to the source S. Such a flash memory 2
Operations such as communication with the reader / writer device other than rewriting of the data 1 are the same as those of the IC card 1 shown in FIG.

FIG. 3 is a diagram showing an example of the configuration of the regulator 45. This regulator 45 includes a voltage dividing resistor R1,
The divided voltage Vadj of the output voltage by R2 and the reference voltage Vref generated by the reference voltage generation circuit 51, for example, 1.
2V, and the error amplifier 52 varies the gate voltage of the power transistor Q1 interposed in series with the input / output line 53 and changes the on-resistance in accordance with the comparison result, thereby changing the ON resistance. This is a series regulator that maintains the output voltage, and can obtain a relatively large current capacity.

FIG. 4 is a diagram showing an example of the configuration of the regulator 46. This regulator 46 compares the divided voltage Vadj of the output voltage by the voltage dividing resistors R1 and R2 with a reference voltage Vref generated by the reference voltage generating circuit 51, for example, 1.2 V, and corresponds to the comparison result. Then, the error amplifier 54 increases the shunt current of the power transistor Q2 interposed between the input / output line 53 and the ground when the divided voltage Vadj of the output voltage becomes higher than the reference voltage Vref. Increasing the voltage drop between the terminals of the current limiting resistor R3 interposed in series with the line 53,
This is a shunt-type regulator that maintains a desired output voltage by decreasing when the divided voltage value Vadj of the output voltage becomes lower than the reference voltage Vref, thereby reducing a voltage drop between terminals of the current limiting resistor R3. Good current can be obtained.

As described above, the two regulators 45, 4
6 in parallel, the flash memory 21
A booster circuit is not required to generate a high voltage necessary for rewriting data, and when an electrically rewritable nonvolatile storage area is increased, for example, when the memory capacity is 1 Mbit, power consumption is reduced to about 24 mW. Can be suppressed. On the other hand, in the IC card 1 shown in FIG. 9, the loss in the regulator 15 is added to the loss in the booster circuit 4, and the power consumption is about 60 mW. Therefore, the power consumption is 6
It can be reduced by as much as 0%. In addition, the voltage Vcc can be stabilized, and noise escaping into the voltage Vcc system can be reduced, and malfunction can be suppressed.

Another embodiment of the present invention will be described below with reference to FIGS. 5 and 6.

FIG. 5 is a block diagram showing an electrical configuration of an IC card 61 which is a semiconductor device according to another embodiment of the present invention. This IC card 61 is the same as the IC card 3 described above.
Similar to FIG. 1, corresponding portions are denoted by the same reference numerals and description thereof is omitted. It should be noted that in the IC card 61, a double voltage rectifier circuit 64 is used as a rectifier circuit in the non-contact interface 63.

FIG. 6 is an electric circuit diagram of the double voltage rectifier circuit 64. Parts corresponding to the rectifier circuit 44 in FIG. 2 are denoted by the same reference numerals, and description thereof will be omitted. In the double voltage rectification circuit 64, one of the AC terminals (between the diodes D3 and D4 in FIG. 6) is connected to the diode bridge.
Capacitors C1 and C2 are respectively provided between the two DC terminals (in FIG. 6, between the diodes D2 and D4 and between the diodes D1 and D3).

In the positive half cycle of the AC wave generated by the electromagnetic induction of the electromagnetic wave from the reader / writer device 47, the diode D2 conducts and the capacitor C1 is charged. Also,
During the negative half cycle, diode D1 conducts and capacitor C2 charges. As a result, the output of the double voltage rectifier circuit 64 becomes the sum of the charged voltages of the capacitors C1 and C2, and a voltage approximately twice that of the full-wave rectifier circuit 44 of FIG. 2 is obtained.

Therefore, as described above, rewriting of data in flash memory 21 requires a high voltage (eg, 12 V).
On the other hand, considering the stable supply of the high voltage from the regulator 46, the amplitude of the AC wave may be set to, for example, about 7 V. Thus, a high voltage can be generated more easily. In addition, a double voltage can be created with a simple configuration in which the capacitors C1 and C2 are added to the full-wave rectifier circuit 44.

Regarding still another embodiment of the present invention,
This will be described below with reference to FIG.

FIG. 7 is a block diagram showing an electrical configuration of an IC card 71 which is a semiconductor device according to still another embodiment of the present invention. This IC card 71 is similar to the above-described IC card 31, and corresponding portions are denoted by the same reference numerals, and description thereof will be omitted. It should be noted that in this IC card 61, the boosting circuit 77 and the voltage detecting circuit 7
8 and a selector 79.

The output voltage Vpp of the regulator 46 is detected by the voltage detection circuit 78, and the output voltage Vpp
When the voltage becomes lower than the voltage (for example, 8 V) necessary for rewriting the data in the flash memory 21, the control circuit 76 of the CPU core 72 activates the booster circuit 77 to boost the output voltage Vpp of the regulator 46 and A selector 79 provided between the flash memory 21 and the booster circuit 7 is provided from the regulator 46 side.
7 to supply the boosted voltage to the flash memory 21.

That is, at the start of the write and erase operations, the control circuit 76 monitors the output of the voltage detection circuit 78 for a certain period of time. The reason for waiting for a certain period of time is to wait for the output voltage Vpp of the regulator 46, which is a data rewriting power supply of the flash memory 21, to sufficiently rise, in order to prevent erroneous writing of data. After the end of the standby time, if the output voltage Vpp is a voltage necessary for data rewriting and the output of the voltage detection circuit 78 is at a high level, the control circuit 76 disables the boosting circuit 77 to perform the boosting operation. At the same time, the selector 79 selects the output of the regulator 46. On the other hand, if the output voltage Vpp is not a voltage required for data rewriting and the output of the voltage detection circuit 78 is at a low level, the control circuit 76 enables the boosting circuit 77 to perform the boosting operation. At the same time, the selector 79 selects the output high voltage (for example, 12 V) of the booster circuit 77. The booster circuit 77 is disabled except for the data rewriting operation of the flash memory 21.

With this configuration, as with the conventional IC card 1, although the booster circuit 77 is provided, the output voltage Vpp of the regulator 46 is naturally the output voltage Vcc of the regulator 15 (for example, 5 V or 3 V).
Since the voltage is higher than V) (for example, 7 V), the circuit size of the booster circuit 77 can be smaller than that of the conventional booster circuit 4, and the power loss can be reduced. Also, the voltage detection circuit 78 operates the booster circuit 77 only when the voltage needs to be boosted.
7 does not consume power unnecessarily and cannot receive electromagnetic waves in an optimized state from the antenna 34 (for example, even when the distance from the reader / writer device is long), rewriting the flash memory 21. Voltage required for the power supply can be obtained, and the power can be supplied stably without contact.

Further, since the boosting circuit 77 is not built in the non-contact interface 33, the boosting circuit 77
Can be stabilized when the boosting operation is unnecessary.

Another embodiment of the present invention will be described below with reference to FIG.

FIG. 8 is a block diagram showing an electrical configuration of an IC card 81 which is a semiconductor device according to another embodiment of the present invention. This IC card 81 is the same as the IC card 6 described above.
1 and 71, corresponding portions are denoted by the same reference numerals, and description thereof is omitted. It should be noted that in the IC card 81, the doubling rectifier 6
4 as well as the booster circuit 77, the voltage detection circuit 78, and the selector 79.

With this configuration, the output voltage Vp of the regulator 46 for the double voltage rectifier circuit 64 is
The possibility that p is a high voltage increases, and the booster circuit 7
7 can be made smaller.

In the above description, the case where the flash memory 21 is mounted on the non-contact type IC cards 31 and 61 is described as an example. However, the non-volatile storage area electrically rewritable with the non-contact power supply circuit is used. It is apparent that the present invention can be applied to the case where a high voltage is required for rewriting the nonvolatile storage area, regardless of whether or not each is on one chip. It is also apparent that the present invention can be applied to an IC card having a combined function of contact / non-contact type as disclosed in JP-A-10-320510.

[0058]

As described above, the semiconductor device of the present invention has the following features.
In rewriting an electrically rewritable nonvolatile storage area by power supply through a non-contact interface, power supply means for the storage area is provided separately from power supply means for the control circuit.

Therefore, a booster circuit is not required to generate a high voltage, and a flash memory which suppresses power consumption and can easily be increased in capacity can be mounted. Further, the power supply voltage for the control circuit can be stabilized,
Reducing noise into the power supply system for the control circuit is reduced, and malfunction can be suppressed. In this way, it is possible to suppress the influence of the increase in the storage area.

Further, as described above, in the semiconductor device of the present invention, the non-contact interface function unit includes a full-wave rectifier circuit composed of a diode bridge, one AC terminal and two AC terminals.
A doubling rectifier circuit including two capacitors provided between the rectifying circuit and the two DC terminals; and a power supply unit for the control circuit and a power supply unit for the storage area using the output voltage of the doubling rectification circuit. Give to the common.

Therefore, a high voltage can be generated more easily, and a doubled voltage can be generated with a simple configuration in which only two capacitors are added to the full-wave rectifier circuit.

Further, as described above, in the semiconductor device of the present invention, it has been detected that the output voltage of the power supply means for the storage area is not the power supply voltage required for rewriting the nonvolatile storage area. At this time, the output voltage of the power supply means for the storage area is switched to a voltage boosted by a booster circuit as a power supply voltage for rewriting the nonvolatile storage area.

Therefore, even if a booster circuit is provided similarly to the conventional IC card, the output voltage of the power supply means for the storage area is naturally higher than the output voltage of the power supply means for the control circuit. , The circuit size of the booster circuit can be small,
Power loss can also be reduced. In addition, the voltage detecting circuit operates the boosting circuit only when the voltage needs to be boosted, so that the boosting circuit does not consume power unnecessarily and receives the electromagnetic wave in an optimized state from the antenna. Even in the case where it is not possible (for example, when the distance from the reader / writer device is long), it is possible to obtain the high voltage necessary for rewriting the nonvolatile storage area, and it is possible to stably supply power in a non-contact manner. .

Further, in the IC card of the present invention, as described above, the above-described semiconductor device is mounted on a card-shaped base material.

[Brief description of the drawings]

FIG. 1 is an IC as a semiconductor device according to an embodiment of the present invention.
FIG. 3 is a block diagram illustrating an electrical configuration of the card.

FIG. 2 is an electric circuit diagram of a rectifier circuit in the IC card of FIG.

FIG. 3 is a diagram illustrating a configuration example of a series regulator in the IC card of FIG. 1;

FIG. 4 is a diagram showing a configuration example of a shunt regulator in the IC card of FIG. 1;

FIG. 5 shows a semiconductor device I according to another embodiment of the present invention.
It is a block diagram which shows the electric constitution of a C card.

FIG. 6 is an electric circuit diagram of a double voltage rectifier circuit in the IC card of FIG. 5;

FIG. 7 is a block diagram showing an electrical configuration of an IC card which is a semiconductor device according to still another embodiment of the present invention.

FIG. 8 shows a semiconductor device I according to another embodiment of the present invention.
It is a block diagram which shows the electric constitution of a C card.

FIG. 9 is a block diagram showing an electrical configuration of an IC card which is a typical conventional semiconductor device.

10 is an EEPR used for the IC card shown in FIG. 9;
FIG. 3 is a diagram showing a typical basic structure of an OM memory cell.

11 is a configuration diagram of a cell array using the cell structure of FIG.

FIG. 12 is a diagram showing a typical structure of a memory cell of a flash memory.

13 is a configuration diagram of a cell array using the cell structure of FIG.

FIG. 14 is a diagram illustrating a specific configuration example of a flash memory.

[Explanation of symbols]

Reference Signs List 21 flash memory (non-volatile storage area) 22 control bus 23 write / erase voltage generation circuit 24 row decoder 25 column decoder 26 sense amplifier 27 input / output buffer 28 address register 31, 61, 71, 81 IC card 32, 72 CPU core 33, 63 Non-contact interface 34, 48 Antenna 36, 76 Control circuit 37 ROM 38 RAM 41 Modulation circuit 42 Demodulation circuit 43 Clock separation circuit 44 Rectification circuit 45 Regulator (Series type regulator, power supply means for control circuit) 46 Regulator ( (Shunt type regulator, power supply means for storage area) 47 Reader / writer device 51 Reference voltage generation circuit 52, 54 Error amplifier 53 Input / output line 64 Double voltage rectification circuit 77 Boost circuit 78 Voltage detection circuit 79 Select (Selection circuit) B1, B2, ..., Bn bit line C memory cell C11~C1n; C21~C2n; Cm1~Cmn
Memory cell CA Cell array C1, C2 Capacitor D Drain D1 to D4 Diode GC Control gate GF Floating gate Q1, Q2 Power transistor R1, R2 Voltage dividing resistor R3 Current limiting resistor S Source W1, W2,..., Wm Word line

 ──────────────────────────────────────────────────の Continued on the front page F term (reference) 2C005 MA17 MA25 MA29 NA06 QA00 QA11 QA15 5B011 DB01 DB05 EA06 EB01 GG03 5B035 BB09 CA12 CA23 CA31

Claims (4)

[Claims] An electrically rewritable non-volatile storage area, a control circuit for performing arithmetic processing using data in the storage area, and a non-contact type for performing signal communication and power supply without contacting an external device In the semiconductor device having an interface function unit, the non-contact interface function unit is required for rewriting the nonvolatile storage area different from a power supply voltage for the control circuit together with the power supply unit for the control circuit. A semiconductor device comprising: a power supply unit for a storage area that generates a power supply voltage. 2. A double voltage rectifier circuit comprising: a full-wave rectifier circuit comprising a diode bridge; and two capacitors provided between one AC terminal and two DC terminals. 2. The semiconductor device according to claim 1, further comprising: applying an output voltage of the double voltage rectifier circuit to a power supply unit for the control circuit and a power supply unit for a storage area in common. A booster circuit for boosting a power supply voltage for the storage area; a voltage detection circuit for monitoring a power supply voltage necessary for rewriting the nonvolatile storage area; When it is detected that the output voltage of the power supply means is not the power supply voltage required for rewriting the nonvolatile storage area, the power for the storage area is used as the power supply voltage for rewriting the nonvolatile storage area. 3. The semiconductor device according to claim 1, further comprising: a selection circuit that switches from an output voltage of the supply unit to an output voltage of the booster circuit and supplies the output voltage. 4. An IC card, wherein the semiconductor device according to claim 1 is mounted on a card-shaped base material.