WO2006123415A1

WO2006123415A1 - Semiconductor integrated circuit apparatus and id tag

Info

Publication number: WO2006123415A1
Application number: PCT/JP2005/009187
Authority: WO
Inventors: Takashi Shinohara; Kousuke Tsuji
Original assignee: Hitachi Ulsi Systems Co., Ltd.
Priority date: 2005-05-19
Filing date: 2005-05-19
Publication date: 2006-11-23

Abstract

In a semiconductor integrated circuit apparatus (1) used for an ID tag of RFID or the like, a regulator circuit (3) generates, from a primary voltage (VCC) generated by a rectifying circuit (2), and outputs first and second power supply voltages (VDD1,VDD2). A voltage switching part (5) is normally adapted to output the first power supply voltage (VDD1) generated by the regulator circuit (3), so that the first power supply voltage (VDD1) is supplied to a logic circuit (6) and a memory (7). In a case where information is written into the memory (7), the logic circuit (6) performs no switching of the voltage switching part (5), so that the first power supply voltage (VDD1), which is a voltage for writing, is supplied to the logic circuit (6) and the memory (7). In a case where information is read from the memory (7), the logic circuit (6) performs a switching of the voltage switching part (5), so that the second power supply voltage (VDD2), which is a voltage for reading and lower than first power supply voltage (VDD1), is supplied to the logic circuit (6) and the memory (7).

Description

Specification

Semiconductor integrated circuit device and ID tag

Technical field

TECHNICAL FIELD [0001] The present invention relates to a communication technology of a semiconductor integrated circuit device, and more particularly to a technology effective for power saving of a semiconductor integrated circuit device used for RFID (Radio Frequency IDentification).

Background art

[0002] RFID is spreading as an automatic recognition technology capable of data communication by wireless communication. This RFID is composed of an ID tag that can store information and a reader Z writer that reads and writes information in the ID tag. The ID tag is a power source for semiconductor integrated circuit devices such as non-contact IC chips.

Such a semiconductor integrated circuit device is also configured with power such as a regulator unit, a power supply monitoring unit, a memory, and a logic circuit. The regulator unit receives an electric wave from the reader Z writer and generates an operating power supply voltage for the semiconductor integrated circuit device.

The power supply monitoring unit outputs a reset signal to the EEPROM and the logic circuit when the operating power supply voltage generated by the regulator unit becomes lower than an arbitrary voltage level. The memory consists of non-volatile semiconductor memory such as EEPROM (Electricaly Erasable and Programmable Read Only Memory). The logic circuit controls communication control and memory operation control.

Disclosure of the invention

Problems to be solved by the invention

However, the present inventor has found that the semiconductor integrated circuit device used for the ID tag as described above has the following problems.

[0006] That is, a nonvolatile semiconductor memory such as an EEPROM requires more power when writing data than when reading data, and therefore requires a higher voltage level and power supply voltage than when reading data. Become.

[0007] However, the regulator unit generates a single power source, and thus reads data. Even in the case of output z write or misalignment, an operation power supply voltage at a high voltage level suitable for data write is supplied, and there is a problem that power consumption during data read increases.

[0008] In addition, the threshold voltage of the reset signal output from the power supply monitoring unit is also set higher in accordance with a high voltage level suitable for data writing. Therefore, even when the voltage level of the operating power supply voltage is such that data can be read out, a reset signal is output, and as a result, there is a problem that the communication distance at the time of data reading is shortened. .

An object of the present invention is to provide a technique capable of extending a communication distance while reducing power consumption during an information reading operation in a semiconductor integrated circuit device used for an ID tag or the like.

[0010] The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

Means for solving the problem

[0011] Among the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

[0012] A semiconductor integrated circuit device according to the present invention includes a nonvolatile semiconductor memory having a plurality of nonvolatile memory cells, a logic unit that controls communication control and operation control of the nonvolatile semiconductor memory, a nonvolatile semiconductor memory, and a logic unit A voltage generator that supplies a first or second power supply voltage to be supplied to the power generator, and the voltage generator rectifies power generated by the received radio wave or electromagnetic induction to generate a primary voltage. The first power supply voltage and the second power supply voltage at a voltage level lower than the first power supply voltage are respectively generated from the rectifying unit to be generated and the primary voltage generated by the rectifying unit. And a regulator unit that outputs a difference between the first power supply voltage and the second power supply voltage based on the signal, and the regulator unit is configured to output the first power supply voltage when information is written to the nonvolatile semiconductor memory. 1 power supply Outputs of the pressure, when the information is read from the non-volatile semiconductor memories and outputs a second power supply voltage.

[0013] Further, the semiconductor integrated circuit device of the present invention includes a first and a second generated by the regulator unit. And a voltage monitoring unit that monitors the second power supply voltage, and the voltage monitoring unit is non-volatile when the first power supply voltage falls below the first set voltage value during the write operation of the nonvolatile semiconductor memory. When a reset signal is output to each of the semiconductor memory and the logic unit, and the second power supply voltage becomes lower than the second set voltage value lower than the first set voltage value during the read operation, the nonvolatile semiconductor memory And a reset signal to the logic part.

Furthermore, in the semiconductor integrated circuit device of the present invention, the regulator unit is based on a regulator that generates a first power supply voltage and a second power supply voltage from a primary voltage, respectively, and a control signal output from the logic unit. The voltage switching unit switches the connection destination, selects either the first power supply voltage or the second power supply voltage, and supplies the selected voltage to the nonvolatile semiconductor memory and the logic unit.

Furthermore, in the semiconductor integrated circuit device of the present invention, the regulator unit includes a trimming circuit that trims a voltage based on a trimming signal, and the trimming circuit corrects a voltage variation of the regulator due to a device manufacturing variation or the like. It is.

In the semiconductor integrated circuit device of the present invention, the nonvolatile semiconductor memory has a trimming signal storage unit that stores a trimming signal used in the trimming circuit.

[0017] The outline of other inventions of the present application will be briefly described.

[0018] The present invention provides a nonvolatile semiconductor memory having a plurality of nonvolatile memory cells, a logic unit that controls communication control and operation control of the nonvolatile semiconductor memory, a nonvolatile semiconductor memory, and a logic unit that supplies the logic unit An ID tag having a voltage generator for supplying a first power supply voltage or a second power supply voltage, the voltage generator having a rectifier that rectifies received radio waves or electromagnetic induction power to generate a primary voltage; The first power supply voltage and the second power supply voltage at a voltage level lower than the first power supply voltage are respectively generated from the primary voltage generated by the rectifying unit, and the logic unit outputs a control signal based on the output control signal. And a regulator unit that outputs either the first power supply voltage or the second power supply voltage, and the regulator unit outputs the first power supply voltage when information is written to the nonvolatile semiconductor memory. , No When the information is read from the source semi-conductor memory is designed to output a second power supply voltage. The invention's effect [0019] The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

(1) While reducing the power consumption of the semiconductor integrated circuit device, it is possible to increase the communication distance during the read operation and improve the reliability of information writing.

(2) According to the above (1), by configuring an ID tag using a semiconductor integrated circuit device, it is possible to realize high performance of the ID tag and improve the reliability of the ID tag. Can do.

Brief Description of Drawings

FIG. 1 is a block diagram of a semiconductor integrated circuit device according to a first embodiment of the present invention.

2 is an explanatory diagram showing an internal configuration of a regulator circuit provided in the semiconductor integrated circuit device of FIG. 1 and a connection configuration of its periphery.

FIG. 3 is an explanatory diagram showing an internal configuration of a regulator circuit provided in a semiconductor integrated circuit device according to a second embodiment of the present invention and a connection configuration of its peripheral portion.

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

[Embodiment 1]

FIG. 1 is a block diagram of a semiconductor integrated circuit device according to Embodiment 1 of the present invention. FIG. 2 shows an internal configuration of a regulator circuit provided in the semiconductor integrated circuit device of FIG. It is explanatory drawing.

In the first embodiment, the semiconductor integrated circuit device 1 is used, for example, as an RFID ID tag that is one of automatic recognition technologies. As shown in FIG. 1, the semiconductor integrated circuit device 1 includes a rectifier circuit (rectifier unit) 2, a regulator circuit (regulator unit, regulator) 3, a secondary voltage monitoring circuit (voltage monitoring unit) 4, and a voltage switching unit (regulator unit). ) 5, logic circuit (logic part) 6, memory (nonvolatile semiconductor memory) 7, and reference voltage circuit 8 are also configured. [0026] The rectifier circuit 2 is connected to an antenna ANT! The rectifier circuit 2 rectifies the electric power generated by electromagnetic induction of the radio wave output from the reader Z writer that reads and writes information in the ID tag via the antenna ANT and outputs it as the primary voltage VCC.

[0027] Further, the rectifier circuit 2 demodulates the analog signal received by the antenna ANT into a digital signal and outputs it to the logic circuit 6, and modulates the digital signal output from the logic circuit 6 into an analog signal. Send to reader Z writer via antenna ANT.

The regulator circuit 3 stabilizes the primary voltage VCC output from the rectifier circuit 2, and generates a first power supply voltage VDD1 and a second power supply voltage VDD2 as secondary voltages.

[0029] The first power supply voltage (for example, about 1.7 V) VDD1 is used when information is written to the memory 7 as a write voltage. The second power supply voltage (for example, about 1.3 V) VDD2 is at a voltage level lower than that of the first power supply voltage VDD1, and is used when reading information from the memory 7 as a read voltage.

[0030] The secondary voltage monitoring circuit 4 monitors the voltage levels of the first power supply voltage VDD1 and the second power supply voltage VDD2 generated by the regulator circuit 3, respectively, and these first and second power supply voltages. When VDDl and VDD2 are below the set voltage level, a reset signal is output to logic circuit 6 and memory 7, respectively.

In the voltage switching unit 5, two input units are connected to the regulator circuit 3, and an output unit is connected to the logic circuit 6 and the memory 7, respectively. Based on the control signal output from the logic circuit 6, the voltage switching unit 5 uses either the first power supply voltage VDD1 or the second power supply voltage VDD2 generated by the regulator circuit 3 as the logic circuit 6 and the memory 7 And supply to each.

[0032] The logic circuit 6 controls the operation of the memory 7 in reading and writing information. The memory 7 is composed of, for example, a nonvolatile semiconductor memory such as an EEPROM, and reads and writes information based on the control of the logic circuit 6.

The reference voltage circuit 8 also generates the reference voltage VREF for the primary voltage VCC output from the rectifier circuit 2 and supplies the reference voltage VREF to the regulator circuit 3 and the secondary voltage monitoring circuit 4, respectively.

FIG. 2 is an explanatory diagram showing the internal configuration of the regulator circuit 3 and the connection configuration of the periphery thereof. FIG.

As shown in the figure, the regulator circuit 3 includes an operational amplifier 3a, a transistor 3b, and a plurality of resistors 3c. Transistor 3b is a P-channel MOS (Metal Oxide

¾emiconauctor

[0036] The negative (one) side input terminal of the operational amplifier 3a is connected so that the reference voltage VREF generated by the reference voltage circuit 8 is input, and the output of the operational amplifier 3a is connected to the transistor 3b. The gate is connected!

[0037] The reference voltage V generated by the reference voltage circuit 8 is connected to one connection portion of the transistor 3b.

Connected to receive REF! A plurality of resistors 3c are connected in series between the other connection portion of the transistor 3b and the reference potential VSS.

[0038] One connection of the transistor 3b is connected to one input of the voltage switching unit 5, and the voltage output from the one connection of the transistor 3b is the first power supply voltage VDD1.

[0039] The other connection part of the voltage switching part 5 is connected so that a power supply voltage of an arbitrary voltage level divided by the plurality of resistors 3c is output. The divided voltage supplied to the other connection portion of the voltage switching portion 5 becomes the second power supply voltage VDD2.

[0040] The secondary voltage monitoring circuit 4 includes a reference voltage VREF output from the reference voltage circuit 8, a first monitoring voltage VW1 having an arbitrary voltage level divided by the plurality of resistors 3c, and the first voltage The second monitoring voltage VW2, which is lower than the monitoring voltage, and the mode signal output from the logic circuit 6 are connected to each other.

[0041] The mode signal is a signal indicating whether the memory 7 performs a write operation or a read operation, and the secondary voltage monitoring circuit 4 determines whether the read operation or the write operation is performed based on the mode signal. .

[0042] The first monitoring voltage VW1 is a voltage for monitoring the voltage level of the first power supply voltage VDD1 used during the write operation, and the second monitoring voltage VW2 is the second power supply voltage used during the read operation. This voltage monitors the voltage level of VDD2.

Next, the operation of the semiconductor integrated circuit device 1 in the present embodiment will be described.

[0044] First, when information is written to the memory 7, the rectifier circuit 2 receives the signal via the antenna ANT. The primary voltage vcc is output by rectifying the received radio wave or electromagnetic induction power. The regulator circuit 3 generates and outputs the first and second power supply voltages VDD1 and VDD2 from the primary voltage VCC output from the rectifier circuit 2, respectively.

[0045] The voltage switching unit 5 is normally set to output the first power supply voltage VDD1 generated by the regulator circuit 3. The voltage switching unit 5 is connected to the logic circuit 6 and the memory 7 via the voltage switching unit 5. The first power supply voltage VDD 1 is supplied to each.

If the logic circuit 6 is a command for writing information to the digital signal memory 7 demodulated in the rectifier circuit 2, the logic circuit 6 performs control so that the voltage switching unit 5 is not switched. As a result, the logic circuit 6 and the memory 7 have the first power supply voltage VD that is the write voltage.

D 1 will be supplied.

[0047] In this manner, when writing information, the first power supply voltage VDD1 at a voltage level higher than the second power supply voltage VDD2 is supplied to the logic circuit 6 and the memory 7, respectively. 7 can write stable information.

[0048] If the digital signal demodulated in the rectifier circuit 2 is a command for reading information from the memory 7, the logic circuit 6 performs control so that the voltage switching unit 5 is switched, and the regulator The second power supply voltage VDD2, which is the read voltage generated by the circuit 3, is supplied to the logic circuit 6 and the memory 7.

Accordingly, a voltage level lower than the first power supply voltage VDD1, which is a write voltage, can be supplied for reading information, so that the power consumption of the semiconductor integrated circuit device 1 is reduced. be able to.

[0050] Next, the operation of the secondary voltage monitoring circuit 5 will be described.

[0051] The secondary voltage monitoring circuit 5 outputs a reset signal to the logic circuit 6 and the memory 7 when the regulator circuit 3 becomes lower than an arbitrary voltage level, and malfunctions of the semiconductor integrated circuit device 1. Prevent such as.

The secondary voltage monitoring circuit 5 determines whether to monitor the first power supply voltage VDD 1 or the second power supply voltage VDD 2 based on the mode signal output from the logic circuit 6.

[0053] For example, when the mode signal indicates a write operation, the secondary voltage monitoring circuit 5 Monitor the power supply voltage VDD1. In this case, the first monitor voltage VW1 generated by the voltage division of multiple resistors 3c is compared with the reference voltage VREF. Output to logic circuit 6 and memory 7, respectively.

[0054] When the mode signal indicates a read operation, the secondary voltage monitoring circuit 5 monitors the second power supply voltage VW2. The secondary voltage monitoring circuit 5 compares the second monitoring voltage VW2 having a voltage level lower than the first monitoring voltage VW1 with the reference voltage VREF, and the second monitoring voltage VW2 is lower than the reference voltage VREF. When it becomes low, a reset signal is output to the logic circuit 6 and the memory 7, respectively.

[0055] As described above, during the read operation, the reset signal is output based on the second monitor voltage VW2 having a voltage level lower than the first monitor voltage VW1, thereby lowering the operating voltage lower limit in the read operation. It becomes possible to do.

Accordingly, according to the present embodiment, it is possible to stably write information while reducing the power consumption of the semiconductor integrated circuit device 1.

[0057] Further, it is possible to extend the communication distance during the read operation by individually performing the reset control during the information read operation and the write operation.

[0058] (Embodiment 2)

FIG. 3 is an explanatory diagram showing the internal configuration of the regulator circuit provided in the semiconductor integrated circuit device according to the second embodiment of the present invention and the connection configuration of the peripheral portion thereof.

In the second embodiment, the semiconductor integrated circuit device 1 includes a rectifier circuit 2, a regulator circuit 3, a secondary voltage monitoring circuit 4, a voltage switching unit 5, a logic circuit having the same configuration as in the first embodiment. 6. A trimming circuit 9 is newly provided in the memory 7, the reference voltage circuit 8, and the like.

The reference voltage VREF output from the reference voltage circuit 8 is connected so as to be supplied to the trimming circuit 9. The trimming voltage output from the trimming circuit 9 is connected to the negative side input terminal of the operational amplifier 3a of the regulator circuit 3 and the secondary voltage monitoring circuit 5 as the reference voltage VREF1.

[0061] The trimming circuit 9 performs arbitrary processing based on a trimming bit signal preset in the memory 7. Generates the voltage level reference voltage VREF1. Since other connection configurations are the same as those in FIGS. 1 and 2 of the first embodiment, description thereof will be omitted.

[0062] The trimming circuit 9 trims the reference voltage VREF output from the reference voltage circuit 8 to obtain a reference voltage VREF1 with a more accurate voltage level in consideration of process variations during manufacturing in the semiconductor integrated circuit device 1. Adjust as follows. Then, the reference voltage VREF1 adjusted by the trimming circuit 9 is supplied to the regulator circuit 3 and the secondary voltage monitoring circuit 5.

[0063] The trimming bit signal is obtained by measuring the reference voltage VREF output from the reference voltage circuit 8 when the semiconductor integrated circuit device 1 is probed, for example, and obtaining the desired reference voltage VREF1 from the measured value. Determine the trimming voltage to be generated and set it in memory 7. Alternatively, the trimming signal may be set Z, etc., by communication with the reader Z writer.

[0064] Thereby, in the second embodiment, a more accurate reference voltage VREF1 can be generated, so that variations in the communication distance between the reader Z writer and the semiconductor integrated circuit device 1 can be suppressed. , Information can be written more stably.

In the second embodiment, the technique for suppressing the variation in the communication distance between the reader Z writer and the semiconductor integrated circuit device 1 by the trimming circuit 9 has been described.

Furthermore, the voltage level of the reference voltage VREF1 may be arbitrarily adjusted by changing the trimming bit signal.

[0066] This makes it possible to arbitrarily adjust the monitoring voltage when outputting the reset signal output from the secondary voltage monitoring circuit 5, and the communication distance between the reader Z writer and the semiconductor integrated circuit device 1 Can be easily changed.

[0067] As described above, the invention made by the present inventor has been specifically described based on the embodiment.

Needless to say, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention.

[0068] For example, in the first and second embodiments, the power described in the ID tag for generating power supply voltage by rectifying power by electromagnetic induction of radio waves output from the reader Z writer is described.

It can also be applied to ID tags with built-in batteries. [0069] Thereby, it is possible to reduce the power consumption when reading information, so that the life of the battery can be extended.

Industrial applicability

The present invention is suitable for a technique for reducing power consumption and improving reliability of a semiconductor integrated circuit device used for an RFID ID tag.

Claims

The scope of the claims

[1] a nonvolatile semiconductor memory having a plurality of nonvolatile memory cells;

A logic unit that controls communication control and operation control of the nonvolatile semiconductor memory; a first power supply voltage supplied to the nonvolatile semiconductor memory and the logic unit; or a voltage level lower than the first power supply voltage. A voltage generator for supplying a second power supply voltage,

The voltage generator is

A rectification unit that rectifies the electric power received by radio waves or electromagnetic induction to generate a primary voltage;

The first power supply voltage and the second power supply voltage are respectively generated from the primary voltage generated by the rectifier, and the first power supply voltage or the second power supply voltage is generated based on the control signal output from the logic unit. A regulator unit for outputting any one of the second power supply voltages,

The regulator part is:

The first power supply voltage is output when information is written to the nonvolatile semiconductor memory, and the second power supply voltage is output when information is read from the nonvolatile semiconductor memory. A semiconductor integrated circuit device.

[2] In the semiconductor integrated circuit device according to claim 1,

A voltage monitoring unit for monitoring the first and second power supply voltages generated by the regulator unit;

The voltage monitoring unit

When the first power supply voltage becomes equal to or lower than a first set voltage value during the write operation of the nonvolatile semiconductor memory, a reset signal is output to the nonvolatile semiconductor memory and the logic unit, respectively, and the nonvolatile semiconductor memory reads A reset signal is output to the non-volatile semiconductor memory and the logic unit when the second power supply voltage becomes equal to or lower than a second set voltage value lower than the first set voltage value during operation. Semiconductor integrated circuit device.

[3] The semiconductor integrated circuit device according to claim 1, The regulator part is:

Primary voltage force Regulators that generate the first and second power supply voltages, respectively, and switching the connection destination based on the control signal output from the logic unit, the first power supply voltage or the second power supply voltage A semiconductor integrated circuit device comprising: a voltage switching unit that selects one of power supply voltages and supplies the selected voltage to the nonvolatile semiconductor memory and the logic unit.

[4] The semiconductor integrated circuit device according to claim 1,

The regulator part is:

A trimming circuit that trims a voltage based on a trimming signal is provided.

A semiconductor integrated circuit device, wherein the trimming circuit corrects voltage variations of the regulator due to device manufacturing variations or the like.

[5] The semiconductor integrated circuit device according to claim 4,

The nonvolatile semiconductor memory is

A semiconductor integrated circuit device comprising a trimming signal storage unit for storing a trimming signal used in the trimming circuit.

[6] a nonvolatile semiconductor memory having a plurality of nonvolatile memory cells;

An ID having a logic unit that controls communication control and operation control of the nonvolatile semiconductor memory, and a voltage generation unit that supplies the first or second power supply voltage supplied to the nonvolatile semiconductor memory and the logic unit A tag,

The voltage generator is

A rectifying unit that rectifies power generated by electromagnetic induction of received radio waves to generate a primary voltage, and a first power supply voltage and a voltage level lower than the first power supply voltage from the primary voltage generated by the rectifying unit. Each of the first power supply voltage and a regulator unit that outputs either the first power supply voltage or the second power supply voltage based on a control signal output from the logic unit. ,

The regulator part is:

When information is written to the nonvolatile semiconductor memory, a first power supply voltage is output. When information is read from the nonvolatile semiconductor memory, a second power supply voltage is output. An ID tag characterized by

[7] In the ID tag according to claim 6,

The voltage monitoring unit

When the first power supply voltage becomes equal to or lower than a first set voltage value during the write operation, the nonvolatile semiconductor memory outputs a reset signal to the nonvolatile semiconductor memory and the logic unit, respectively, and the nonvolatile semiconductor memory reads An ID tag, wherein a reset signal is output to the nonvolatile semiconductor memory and the logic unit when the voltage becomes equal to or lower than a second set voltage value lower than the first set voltage value during operation.

[8] In the ID tag according to claim 6,

The regulator part is:

Primary voltage force Regulators that generate the first and second power supply voltages, respectively, and switching the connection destination based on the control signal output from the logic unit, the first power supply voltage or the second power supply voltage An ID tag comprising: a voltage switching unit that selects one of power supply voltages and supplies the selected voltage to the nonvolatile semiconductor memory and the logic unit.

[9] In the ID tag according to claim 6,

The regulator part is:

A trimming circuit that trims a voltage based on a trimming signal is provided.

An ID tag characterized in that the trimming circuit corrects voltage variations of the regulator due to device manufacturing variations and the like.

[10] In the ID tag according to claim 9,

The nonvolatile semiconductor memory is

An ID tag comprising a trimming signal storage unit for storing a trimming signal used in the trimming circuit.