JP2008035153A - Analog switching circuit - Google Patents

Analog switching circuit Download PDF

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JP2008035153A
JP2008035153A JP2006205652A JP2006205652A JP2008035153A JP 2008035153 A JP2008035153 A JP 2008035153A JP 2006205652 A JP2006205652 A JP 2006205652A JP 2006205652 A JP2006205652 A JP 2006205652A JP 2008035153 A JP2008035153 A JP 2008035153A
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terminal
type fet
gate
gate terminal
switch circuit
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JP4828343B2 (en
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Tsuneji Tsutsumi
恒次 堤
Kenji Suematsu
憲治 末松
Mitsuhiro Shimozawa
充弘 下沢
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Mitsubishi Electric Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To solve a problem that bias voltage dependence characteristics of an ON resistor do not completely become flat according to characteristics deviation of NMOS and PMOS in the conventional circuit if a large amplitude signal is input, distortion occurs in the output signal even though there is a method to temporarily make power supply voltage twice and make a value of the ON resister small, but the method can not make the switching circuit on for a long time. <P>SOLUTION: In an analog circuit to make a drain terminal or a source terminal of an FET (Field Effect Transistor) as an input or an output terminal, give control voltage on a gate terminal, and perform switching; low distortion characteristics are realized by inserting a capacitor between the source terminal or the drain terminal and the gate terminal, and connecting a resister between the gate terminal and the control terminal, since voltage between the gate terminal and the source terminal/the drain terminal can be maintained large at a time of large signal input. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

この発明はアナログスイッチ回路に関し、詳しくは、振幅の大きな信号が入力されると、発生する出力信号の歪みを小さくする技術に関する。   The present invention relates to an analog switch circuit, and more particularly to a technique for reducing distortion of an output signal generated when a signal having a large amplitude is input.

図１０に従来のアナログスイッチ回路の回路図を示す。この回路は、ＮＭＯＳ(Negative Metal Oxide Semiconductor)トランジスタＭＮ１のソース端子と、ＰＭＯＳ(Positive Metal Oxide Semiconductor)トランジスタＭＰ１のソース端子及びＮＭＯＳトランジスタＭＮ１のドレイン端子とＰＭＯＳトランジスタＭＰ１のドレイン端子がそれぞれ接続されてスイッチ部１を構成している。制御信号入力ＣＩＮはＭＮ１のゲート端子とインバータ回路Ｇ１入力に接続され、Ｇ１の出力がＭＰ１のゲート端子に接続されることにより、ＭＮ１とＭＰ1に論理的に反転の電圧がかかるようになっている。   FIG. 10 shows a circuit diagram of a conventional analog switch circuit. In this circuit, a source terminal of an NMOS (Negative Metal Oxide Semiconductor) transistor MN1, a source terminal of a PMOS (Positive Metal Oxide Semiconductor) transistor MP1, a drain terminal of the NMOS transistor MN1, and a drain terminal of the PMOS transistor MP1 are connected to each other. Part 1 is configured. The control signal input CIN is connected to the gate terminal of MN1 and the input of the inverter circuit G1, and the output of G1 is connected to the gate terminal of MP1, whereby a logically inverted voltage is applied to MN1 and MP1. .

スイッチをオンにする場合は、ＣＩＮにＨの信号が入力され、ＭＮ１のゲート端子にＨ、ＭＰ１のゲート端子にＬの電圧が印加されるため、それぞれのトランジスタは導通状態となる。一方、スイッチをオフする場合は、ＣＩＮにＬの信号が入力され、ＭＮ１のゲート端子にＬ、ＭＰ１のゲート端子にＨの電圧が印加されるため、それぞれのトランジスタは非導通状態となる。   When the switch is turned on, an H signal is input to CIN, and an H voltage is applied to the gate terminal of MN1 and an L voltage is applied to the gate terminal of MP1, so that each transistor becomes conductive. On the other hand, when the switch is turned off, an L signal is input to CIN, and an L voltage is applied to the gate terminal of MN1 and an H voltage is applied to the gate terminal of MP1, so that the respective transistors are turned off.

スイッチがオン時の入出力端子電圧ＶＤＤ（以下「バイアス電圧」とする）に対する入出力端子間抵抗値（以下「オン抵抗」とする）の関係を図１１に示す。ＭＰ１のオン抵抗特性と、ＭＮ１のオン抵抗特性が、ＶＤＤ/２を中心として対称となるようにＭＰ１とＭＮ１のトランジスタサイズが調整される。この結果、スイッチ部全体としてのオン抵抗（ＭＮ１とＭＰ１の並列抵抗）は、バイアス電圧に対してほぼフラットな特性となる。 FIG. 11 shows the relationship between the input / output terminal resistance VDD (hereinafter referred to as “bias voltage”) and the input / output terminal resistance value (hereinafter referred to as “on resistance”) when the switch is on. The transistor sizes of MP1 and MN1 are adjusted so that the on-resistance characteristics of MP1 and the on-resistance characteristics of MN1 are symmetric about VDD / 2. As a result, the on-resistance (parallel resistance of MN1 and MP1) of the entire switch unit has a substantially flat characteristic with respect to the bias voltage.

特開平６-２６０９１６号公報JP-A-6-260916

しかし、上述のアナログスイッチ回路では実際には基板バイアス効果や、プロセスばらつきによるＮＭＯＳ、ＰＭＯＳの特性誤差が原因となり、図１１に示されるようにオン抵抗のバイアス電圧依存特性は完全にフラットにはならない。このとき、振幅の大きな信号がスイッチに入力されると、出力される信号に歪みが発生してしまい問題となる。   However, in the above-described analog switch circuit, the bias voltage dependence characteristic of the on-resistance is not completely flat as shown in FIG. 11 due to the substrate bias effect and NMOS and PMOS characteristic errors due to process variations. . At this time, if a signal having a large amplitude is input to the switch, the output signal is distorted, which causes a problem.

電源電圧を一時的に２倍にすることにより、オン抵抗を小さくする方法が、特開平６-２６０９１６号公報で開示されている。しかし、この方法ではスイッチ回路を長時間オンにできないといった問題点が挙げられる。   Japanese Patent Laid-Open No. 6-260916 discloses a method of reducing the on-resistance by temporarily doubling the power supply voltage. However, this method has a problem that the switch circuit cannot be turned on for a long time.

この発明は、信号線とスイッチングトランジスタのゲート電極とをＡＣ(Alternating Current)的に結合し、振幅の大きな信号が入力された場合でもゲート端子-ソース端子、ゲート端子-ドレイン端子間の電圧をほぼ一定に保つことにより、オン抵抗のバイアス電圧依存性を小さくし、スイッチで発生するひずみを小さくすることを目的とする。   In the present invention, the signal line and the gate electrode of the switching transistor are coupled in an AC (Alternating Current) manner, and even when a signal having a large amplitude is input, the voltage between the gate terminal and the source terminal and the gate terminal and the drain terminal is substantially reduced. By keeping constant, the purpose is to reduce the bias voltage dependence of the on-resistance and to reduce the distortion generated by the switch.

この発明に係るアナログスイッチ回路は、ＦＥＴのドレイン端子又はソース端子を入力あるいは出力端子とし、ゲート端子に制御電圧を与えてスイッチングを行うアナログスイッチ回路において、ソース端子又はドレイン端子とゲート端子との間にキャパシタを印加し、かつゲート端子と制御端子の間に抵抗を接続して構成する。   An analog switch circuit according to the present invention is an analog switch circuit that performs switching by using a drain terminal or a source terminal of an FET as an input or output terminal, and applying a control voltage to the gate terminal, between the source terminal or the drain terminal and the gate terminal. A capacitor is applied to the capacitor, and a resistor is connected between the gate terminal and the control terminal.

この発明によれば、信号振幅にしたがってゲート端子電位も変動することにより、ゲート端子ソース端子間、ゲート端子ドレイン端子間の電圧がほぼ一定値に保たれ、トランジスタのオン抵抗は入力信号の振幅に拠らずほぼ一定となり、低ひずみ特性が実現できる。   According to the present invention, the gate terminal potential also fluctuates according to the signal amplitude, so that the voltage between the gate terminal and the source terminal and between the gate terminal and the drain terminal is maintained at a substantially constant value. Regardless, it is almost constant and low strain characteristics can be realized.

実施の形態１．
図１は、この発明に係るアナログスイッチ回路の一例を示す図である。スイッチ部１を構成しているＮＭＯＳトランジスタＭＮ１とＰＭＯＳトランジスタＭＰ１のゲート端子それぞれに直列に抵抗Ｒ１とＲ２が接続され、また、ＭＮ１とＭＰ１のゲート端子と、出力端子ＯＵＴの間にそれぞれキャパシタＣ１、Ｃ２が接続されている。ここでＣ１、Ｃ２はトランジスタのゲート端子と入力端子ＩＮの間に接続してもよく、ゲート端子と出力端子ＯＵＴ間、ゲート端子と入力端子ＩＮ間の両方に接続してもよい。また、ここではトランジスタとしてＳｉＭＯＳトランジスタを使用したが、その他ＧａＡｓなどのＦＥＴ(Field Effect Transistor)でも良い。 Embodiment 1 FIG.
FIG. 1 is a diagram showing an example of an analog switch circuit according to the present invention. Resistors R1 and R2 are connected in series to the gate terminals of the NMOS transistor MN1 and the PMOS transistor MP1 constituting the switch unit 1, respectively, and a capacitor C1, between the gate terminals of the MN1 and MP1 and the output terminal OUT, respectively. C2 is connected. Here, C1 and C2 may be connected between the gate terminal of the transistor and the input terminal IN, or may be connected between the gate terminal and the output terminal OUT and between the gate terminal and the input terminal IN. Further, here, a SiMOS transistor is used as the transistor, but other FET (Field Effect Transistor) such as GaAs may be used.

次に、動作について説明する。
時定数 １／（Ｃ１×Ｒ１）、１／（Ｃ２×Ｒ２）が通過する信号の周波数と同等かそれ以下であれば、信号振幅にしたがってＭＮ１、ＭＰ１のゲート端子電位も変動する。スイッチ回路に大振幅の信号が入力した場合の各部の電圧波形を図８に示す。なお、入出力端子は、ＶＤＤ／２のＤＣバイアスがかかっているものとする。各トランジスタのゲート端子電圧が信号振幅に従って変動することにより、ゲート端子ソース端子間、ゲート端子ドレイン端子間の電圧がほぼ一定値（ここでは、ＭＰ１のゲート端子ソース端子/ドレイン端子間電圧はほぼＶＤＤ／２、ＭＮ１のゲート端子ソース端子/ドレイン端子間電圧はほぼ−ＶＤＤ／２）に保たれていることが分かる。これにより、トランジスタのオン抵抗は入力信号の振幅に拠らずほぼ一定となり、信号のひずみも小さくなる。 Next, the operation will be described.
If the time constants 1 / (C1 × R1) and 1 / (C2 × R2) are equal to or less than the frequency of the signal that passes, the gate terminal potentials of MN1 and MP1 also vary according to the signal amplitude. FIG. 8 shows voltage waveforms at various portions when a large amplitude signal is input to the switch circuit. It is assumed that the input / output terminal is subjected to a VDD / 2 DC bias. As the gate terminal voltage of each transistor fluctuates in accordance with the signal amplitude, the voltage between the gate terminal and the source terminal and between the gate terminal and the drain terminal is almost constant (here, the voltage between the gate terminal source terminal / drain terminal of MP1 is approximately VDD). It can be seen that the voltage between the gate terminal, the source terminal and the drain terminal of MN1, is maintained at approximately -VDD / 2). As a result, the on-resistance of the transistor becomes substantially constant regardless of the amplitude of the input signal, and the signal distortion is reduced.

実施の形態２．
図２は、この発明の実施の形態２を示す回路図で、図１における抵抗Ｒ１、Ｒ２をそれぞれ、インダクタＬ１、インダクタＬ２に置き換えた回路である。動作原理は、図１の回路と同じである。ただし、信号の周波数は、時定数 １／√（Ｌ１×Ｃ１）、１／√（Ｌ２×Ｃ２）、と同等かそれ以上である必要がある。 Embodiment 2. FIG.
FIG. 2 is a circuit diagram showing Embodiment 2 of the present invention, which is a circuit in which the resistors R1 and R2 in FIG. 1 are replaced with an inductor L1 and an inductor L2, respectively. The operating principle is the same as the circuit of FIG. However, the frequency of the signal needs to be equal to or higher than the time constants 1 / √ (L1 × C1) and 1 / √ (L2 × C2).

実施の形態３．
図３は、この発明の実施の形態３を示す回路図で、図１における抵抗Ｒ１、Ｒ２をそれぞれ、ＰＭＯＳトランジスタＭＰ２とＮＭＯＳトランジスタＭＮ３のソース端子とソース端子、ドレイン端子とドレイン端子がそれぞれ接続された並列回路、ＮＭＯＳトランジスタＭＮ２とＰＭＯＳトランジスタＭＰ３のソース端子とソース端子、ドレイン端子とドレイン端子がそれぞれ接続された並列回路に置き換えた回路である。ＭＰ２のソース端子は制御信号入力端子ＣＩＮに、ドレイン端子はＭＮ１のゲート端子に、ゲート端子はスイッチ入力端子ＩＮに接続されている。ＭＮ２のドレイン端子はインバータＧ１の出力に、ソース端子はＭＰ１のゲート端子に、ゲート端子はスイッチ入力端子ＩＮに接続されている。ここで、ＭＰ２、ＭＮ２のゲート端子は、スイッチ出力端子へ接続されていても良い。また、ここではＭＮ３のゲート端子はＧ１の出力に、ＭＰ３のゲート端子はＣＩＮに接続されている。 Embodiment 3 FIG.
FIG. 3 is a circuit diagram showing Embodiment 3 of the present invention. The resistors R1 and R2 in FIG. 1 are connected to the source terminal and source terminal of the PMOS transistor MP2 and NMOS transistor MN3, respectively, and the drain terminal and drain terminal are connected. A parallel circuit in which the source terminal and source terminal of the NMOS transistor MN2 and the PMOS transistor MP3, and the drain terminal and drain terminal of the NMOS transistor MN2 and the drain terminal are connected, respectively. The source terminal of MP2 is connected to the control signal input terminal CIN, the drain terminal is connected to the gate terminal of MN1, and the gate terminal is connected to the switch input terminal IN. The drain terminal of MN2 is connected to the output of the inverter G1, the source terminal is connected to the gate terminal of MP1, and the gate terminal is connected to the switch input terminal IN. Here, the gate terminals of MP2 and MN2 may be connected to the switch output terminal. Here, the gate terminal of MN3 is connected to the output of G1, and the gate terminal of MP3 is connected to CIN.

この回路の動作を説明する。各部の電圧波形を図９に示す。無信号時、ＭＰ２はソース端子、ドレイン端子にＶＤＤ、ゲート端子にＶＤＤ／２の電圧がかかっており、オン状態となっているため、ソース端子ドレイン端子間の抵抗は小さい。ここにスイッチ入力に大振幅信号が入力された場合を考える。入力信号が正に振れる場合は、ＭＰ２のゲート端子はＶＤＤに近い電位へと変化し、オフ状態となる。このとき、ＭＰ２のソース端子ドレイン端子間抵抗が大きくなり、図１の回路の原理と同じくＭＮ１のゲート端子電位が入力信号に追従してＶＤＤより大きくなる。逆に、入力信号が負に振れる場合は、ＭＰ２のゲート端子はＶＤＤ／２から０Ｖに近い電位へと変化し、オン状態は変わらない。このため、ＭＮ１のゲート端子で電圧は、ほぼＶＤＤのままである。以上より、スイッチに大振幅信号が入力されたとき、ＭＮ１のゲート端子ソース端子/ドレイン端子間電圧は常にＶＤＤ／２程度以上が確保され、オン抵抗を小さくできる。   The operation of this circuit will be described. The voltage waveform of each part is shown in FIG. When there is no signal, MP2 has a source terminal, a voltage of VDD / 2 applied to the drain terminal, and a voltage of VDD / 2 applied to the gate terminal, and is in an on state, so that the resistance between the source terminal and the drain terminal is small. Consider a case where a large amplitude signal is input to the switch input. When the input signal swings positively, the gate terminal of MP2 changes to a potential close to VDD and is turned off. At this time, the resistance between the source terminal and the drain terminal of MP2 becomes large, and the gate terminal potential of MN1 becomes larger than VDD following the input signal as in the principle of the circuit of FIG. Conversely, when the input signal fluctuates negatively, the gate terminal of MP2 changes from VDD / 2 to a potential close to 0V, and the ON state does not change. For this reason, the voltage at the gate terminal of MN1 remains approximately VDD. From the above, when a large amplitude signal is input to the switch, the voltage between the gate terminal, the source terminal and the drain terminal of MN1 is always secured to about VDD / 2 or more, and the on-resistance can be reduced.

ＭＮ２の動作についても同様である。無信号時、ＭＮ２はソース端子、ドレイン端子に０、ゲート端子にＶＤＤ／２の電圧がかかっており、オン状態となっているため、ソース端子ドレイン端子間の抵抗は小さい。ここにスイッチ入力に大振幅信号が入力されたとき、入力信号が正に振れる場合は、ＭＮ２のゲート端子はＶＤＤ／２からＶＤＤに近い電位へと変化し、ＭＮ２のオン状態は変わらない。逆に、入力信号が負に振れる場合は、ＭＮ２のゲート端子は０に近い電位へと変化し、オフ状態となる。このとき、ＭＮ２のソース端子ドレイン端子間抵抗が大きくなり、図１の回路の原理と同じくＭＰ１のゲート端子電位が入力信号に追従して０Ｖより小さくなる。結果的にＭＰ１のゲート端子ソース端子/ドレイン端子間電圧が保たれ、オン抵抗を小さくできる。   The same applies to the operation of MN2. When there is no signal, MN2 has a voltage of 0 on the source terminal and drain terminal and a voltage of VDD / 2 on the gate terminal, and is in an on state, so the resistance between the source terminal and the drain terminal is small. Here, when a large amplitude signal is input to the switch input, if the input signal swings positively, the gate terminal of MN2 changes from VDD / 2 to a potential close to VDD, and the ON state of MN2 does not change. Conversely, when the input signal swings negative, the gate terminal of MN2 changes to a potential close to 0 and is turned off. At this time, the resistance between the source terminal and the drain terminal of MN2 increases, and the gate terminal potential of MP1 follows the input signal and becomes smaller than 0 V, as in the circuit principle of FIG. As a result, the voltage between the gate terminal, the source terminal and the drain terminal of MP1 is maintained, and the on-resistance can be reduced.

なお、上記のスイッチ回路がオンの状態では、ＭＮ３とＭＰ３はいずれも完全にオフとなるため、他の回路の動作に影響は与えない。逆にスイッチ回路がオフの状態では、ＭＮ３とＭＰ３はいずれもオンとなりソース端子ドレイン端子間抵抗が小さくなるため、ＭＰ１とＭＮ１のゲート端子電位を確実にＶＤＤ、０Ｖに設定する役割を果たす。   Note that, when the switch circuit is on, both MN3 and MP3 are completely off, so that the operation of other circuits is not affected. Conversely, when the switch circuit is off, both MN3 and MP3 are turned on and the resistance between the source terminal and the drain terminal is reduced, so that the gate terminal potentials of MP1 and MN1 are reliably set to VDD and 0V.

この回路の構成の場合、入力端子から大振幅信号が入ってくるとき以外は、ＭＮ２、ＮＰ２はオンとなり、ソース端子ゲート端子間抵抗は小さい。このため、スイッチ回路のオン-オフ切り替え時間を犠牲にすることがないという利点がある。   In the case of this circuit configuration, except when a large amplitude signal is input from the input terminal, MN2 and NP2 are turned on and the resistance between the source terminal and the gate terminal is small. Therefore, there is an advantage that the switching time of the switch circuit is not sacrificed.

図４〜６は図１〜３のスイッチ部１を単一のＦＥＴで構成したスイッチ部２に置き換えた回路である。ここでは、スイッチ部２はＮＭＯＳトランジスタＭＮ４で構成したが、ＰＭＯＳトランジスタであっても、ＧａＡｓ、ＧａＮ、ＳｉＧｅなどのＪＦＥＴ、ＭＥＳＦＥＴ、ＨＦＥＴ、ＨＥＭＴなどであっても良い。動作原理は図１〜３の回路と同じで、大信号時のスイッチングトランジスタのゲート端子ーソース端子/ドレイン端子電圧を大きく保てるため、低ひずみ特性が実現できる。   4 to 6 are circuits in which the switch unit 1 of FIGS. 1 to 3 is replaced with a switch unit 2 constituted by a single FET. Here, the switch unit 2 is configured by the NMOS transistor MN4. However, the switch unit 2 may be a PMOS transistor or a JFET such as GaAs, GaN, or SiGe, a MESFET, an HFET, or a HEMT. The operation principle is the same as that of the circuits of FIGS. 1 to 3, and the gate terminal-source terminal / drain terminal voltage of the switching transistor at the time of a large signal can be kept large.

実施の形態４．
図７は、この発明の実施の形態４を示す回路図で、図１のスイッチ回路を用いてＳＰ３Ｔ（３分岐）スイッチを構成した回路である。ここでは、キャパシタ、Ｃ１、Ｃ２、Ｃ２１、Ｃ２２、Ｃ３１、Ｃ３２が、各トランジスタのゲート端子と出力端子ＯＵＴ１〜ＯＵＴ３（図では各トランジスタのドレイン端子）間に接続されていることが特徴である。図１〜６の構成においては、Ｃ１もしくはＣ２は各トランジスタのゲート端子と、スイッチの入力端子間ＩＮに接続されていても良い。ここで、各キャパシタの接続をゲート端子と出力端子間ＯＵＴ１〜ＯＵＴ３にのみに限定しているのは、以下の理由によるものである。 Embodiment 4 FIG.
FIG. 7 is a circuit diagram showing a fourth embodiment of the present invention, which is a circuit in which an SP3T (3-branch) switch is configured using the switch circuit of FIG. Here, the capacitors C1, C2, C21, C22, C31, and C32 are characterized in that they are connected between the gate terminals of the transistors and the output terminals OUT1 to OUT3 (the drain terminals of the transistors in the drawing). 1 to 6, C1 or C2 may be connected between the gate terminal of each transistor and the input terminal IN of the switch. Here, the reason why the connection of each capacitor is limited to only between the gate terminals and the output terminals OUT1 to OUT3 is as follows.

信号線路にキャパシタを接続すると、たとえもう一方の端子がオープンであっても、キャパシタの寄生容量により、ＧＮＤと信号線路の間に容量が付加されることになる。このため、Ｃ１、Ｃ２、Ｃ２１、Ｃ２２、Ｃ３１、Ｃ３２を各トランジスタのゲート端子と入力端子ＩＮ間に接続すると、１〜３のいずれか一つのスイッチだけがオンの場合でも、信号線路にすべてのキャパシタの容量が付加され、信号の損失が増大する原因になってしまう。ここで、Ｃ１、Ｃ２、Ｃ２１、Ｃ２２、Ｃ３１、Ｃ３２を各トランジスタのゲート端子と出力端子ＯＵＴ１〜ＯＵＴ３間に接続すると、オフのスイッチのキャパシタの容量は信号線路からはほぼ見えないため、損失が増大するなどの影響を与えない。   When a capacitor is connected to the signal line, even if the other terminal is open, a capacitance is added between GND and the signal line due to the parasitic capacitance of the capacitor. Therefore, when C1, C2, C21, C22, C31, and C32 are connected between the gate terminal and the input terminal IN of each transistor, all of the signal lines are connected even when only one of the switches 1 to 3 is on. The capacitance of the capacitor is added, which causes an increase in signal loss. Here, when C1, C2, C21, C22, C31, and C32 are connected between the gate terminal of each transistor and the output terminals OUT1 to OUT3, the capacitance of the off-switch capacitor is almost invisible from the signal line, so that loss is lost. Does not affect the increase.

この発明に係るアナログスイッチ回路はベースバンドあるいは高周波信号を切り替えるスイッチ等に使用される。   The analog switch circuit according to the present invention is used for a switch for switching a baseband or a high frequency signal.

この発明の実施の形態１に係るアナログスイッチ回路を示す回路図である。1 is a circuit diagram showing an analog switch circuit according to a first embodiment of the present invention. この発明に実施の形態２に係るアナログスイッチ回路を示す回路図である。It is a circuit diagram which shows the analog switch circuit based on Embodiment 2 of this invention. この発明に実施の形態３に係るアナログスイッチ回路を示す回路図である。It is a circuit diagram which shows the analog switch circuit based on Embodiment 3 of this invention. 実施の形態１のスイッチ部を単一のＦＥＴで構成したスイッチ部に置き換えた回路図である。FIG. 3 is a circuit diagram in which the switch unit of the first embodiment is replaced with a switch unit configured with a single FET. 実施の形態２のスイッチ部を単一のＦＥＴで構成したスイッチ部に置き換えた回路図である。FIG. 6 is a circuit diagram in which the switch unit of the second embodiment is replaced with a switch unit configured by a single FET. 実施の形態３のスイッチ部を単一のＦＥＴで構成したスイッチ部に置き換えた回路図である。FIG. 10 is a circuit diagram in which the switch unit of the third embodiment is replaced with a switch unit configured with a single FET. この発明に実施の形態４に係るアナログスイッチ回路を示す回路図である。It is a circuit diagram which shows the analog switch circuit based on Embodiment 4 of this invention. 大振幅信号入力時のスイッチ回路各部の電圧波形図である。It is a voltage waveform diagram of each part of the switch circuit when a large amplitude signal is input. 実施の形態３のアナログスイッチ回路各部の電圧波形図である。FIG. 10 is a voltage waveform diagram of each part of the analog switch circuit according to the third embodiment. 従来のアナログスイッチ回路の回路図である。It is a circuit diagram of a conventional analog switch circuit. 従来のアナログスイッチ回路のバイアス電圧に対するオン抵抗値の特性図である。It is a characteristic diagram of the on-resistance value with respect to the bias voltage of the conventional analog switch circuit.

符号の説明Explanation of symbols

１、２；スイッチ部、Ｇ１；インバータ回路、ＭＮ１、ＭＮ２、ＭＮ３、ＭＮ４；ＮＭＯＳトランジスタ、ＭＰ１、ＭＰ２、ＭＰ３；ＰＭＯＳトランジスタ、Ｒ１、Ｒ２；抵抗、ＩＮ；入力端子、ＯＵＴ；出力端子、Ｃ１、Ｃ２、Ｃ２１、Ｃ２２、Ｃ３１、Ｃ３２；キャパシタ、Ｌ１、Ｌ２；インダクタ。   1, 2; switch part, G1; inverter circuit, MN1, MN2, MN3, MN4; NMOS transistor, MP1, MP2, MP3; PMOS transistor, R1, R2; resistor, IN; input terminal, OUT; output terminal, C1, C2, C21, C22, C31, C32; capacitors, L1, L2; inductors.

Claims (6)

第１のＮ形ＦＥＴのソース端子と第１のＰ形ＦＥＴのソース端子、及び第１のＮ形ＦＥＴのドレイン端子と、第１のＰ形ＦＥＴのドレイン端子がそれぞれ接続され、それぞれのＦＥＴのゲート端子の一方に正、他方に反転した制御電圧が与えられてスイッチングを行うアナログスイッチ回路において、第１のＮ形ＦＥＴのゲート端子とソース端子又はドレイン端子間に第１のキャパシタが、第１のＮ形ＦＥＴのゲート端子と第１のＮ形ＦＥＴへの制御端子との間に第１の抵抗が接続され、第１のＰ形ＦＥＴのゲート端子とソース端子又はドレイン端子間に第２のキャパシタが、第１のＰ形ＦＥＴのゲート端子と第１のＰ形ＦＥＴへの制御端子との間に第２の抵抗が接続されることを特徴とするアナログスイッチ回路。   The source terminal of the first N-type FET and the source terminal of the first P-type FET, and the drain terminal of the first N-type FET and the drain terminal of the first P-type FET are connected to each other. In an analog switch circuit that performs switching by applying a control voltage that is positive and inverted to one of the gate terminals, a first capacitor is provided between the gate terminal of the first N-type FET and the source terminal or the drain terminal. A first resistor is connected between a gate terminal of the first N-type FET and a control terminal to the first N-type FET, and a second resistor is connected between the gate terminal of the first P-type FET and the source terminal or the drain terminal. An analog switch circuit, wherein the capacitor has a second resistor connected between a gate terminal of the first P-type FET and a control terminal to the first P-type FET. 第１の抵抗を第１のインダクタ又は第１の抵抗と第１のインダクタを直列に接続した回路に、第２の抵抗を第２のインダクタ又は第２の抵抗と第２のインダクタを直列に接続した回路に置き換えたことを特徴とする請求項１記載のアナログスイッチ回路。   The first resistor is connected to the first inductor or a circuit in which the first resistor and the first inductor are connected in series, and the second resistor is connected to the second inductor or the second resistor and the second inductor in series. 2. The analog switch circuit according to claim 1, wherein the analog switch circuit is replaced with a circuit. 第１の抵抗を第２のＰ形ＦＥＴに、第２の抵抗を第２のＮ形ＦＥＴに置き換え、
第２のＰ形ＦＥＴのドレイン端子が第１のＮ形ＦＥＴのゲート端子に、ソース端子が第１のＮ形ＦＥＴへの制御端子に、ゲート端子がアナログスイッチ回路全体の入力または出力端子に接続され、第２のＮ形ＦＥＴのソース端子が第１のＰ形ＦＥＴのゲート端子に、ドレイン端子が第１のＰ形ＦＥＴへの制御端子に、ゲート端子がスイッチ回路全体の入力または出力端子に接続され、第２のＰ形ＦＥＴに並列に第３のＮ形ＦＥＴが、第２のＮ形ＦＥＴに並列に第３のＰ形ＦＥＴが接続され、上記第３のＮ形ＦＥＴ、第３のＰ形ＦＥＴは、スイッチ回路がオフ状態のときにオンとなるように制御されることを特徴とする請求項１記載のアナログスイッチ回路。 Replacing the first resistor with a second P-type FET and the second resistor with a second N-type FET;
The drain terminal of the second P-type FET is connected to the gate terminal of the first N-type FET, the source terminal is connected to the control terminal to the first N-type FET, and the gate terminal is connected to the input or output terminal of the entire analog switch circuit. The source terminal of the second N-type FET is the gate terminal of the first P-type FET, the drain terminal is the control terminal to the first P-type FET, and the gate terminal is the input or output terminal of the entire switch circuit. A third N-type FET connected in parallel to the second P-type FET, and a third P-type FET connected in parallel to the second N-type FET; 2. The analog switch circuit according to claim 1, wherein the P-type FET is controlled to be turned on when the switch circuit is in an off state. ＦＥＴのドレイン端子又はソース端子を入力あるいは出力端子とし、ゲート端子に制御電圧を与えてスイッチングを行うアナログスイッチ回路において、ソース端子又はドレイン端子とゲート端子との間にキャパシタを印加し、かつゲート端子と制御端子の間に抵抗を接続したことを特徴とするアナログスイッチ回路。   In an analog switch circuit that performs switching by using a drain terminal or a source terminal of an FET as an input or output terminal and applying a control voltage to the gate terminal, a capacitor is applied between the source terminal or the drain terminal and the gate terminal, and the gate terminal An analog switch circuit characterized in that a resistor is connected between the control terminal and the control terminal. ゲート端子と制御端子の間に接続された抵抗を、インダクタ、又は抵抗とインダクタを直列に接続した回路に置換したことを特徴とする請求項４記載のアナログスイッチ回路。   5. The analog switch circuit according to claim 4, wherein the resistor connected between the gate terminal and the control terminal is replaced with an inductor or a circuit in which the resistor and the inductor are connected in series. アナログスイッチ回路がＳＰＳＴ（Single-Pole/Single-Throw Switch)型で構成され、このＳＰＳＴスイッチ回路をｎ個用いて入力端子が１つ、出力端子がｎ個を持つＳＰｎＴスイッチ回路構成し、第１および第２のキャパシタが各ＦＥＴのゲートと、出力側端子との間に接続されたことを特徴とする請求項１乃至５の何れか一つに記載のアナログスイッチ回路。   The analog switch circuit is configured as an SPST (Single-Pole / Single-Throw Switch) type, and an SPnT switch circuit having one input terminal and n output terminals is configured using n SPST switch circuits. 6. The analog switch circuit according to claim 1, wherein the second capacitor is connected between the gate of each FET and the output side terminal.
JP2006205652A 2006-07-28 2006-07-28 Analog switch circuit Expired - Fee Related JP4828343B2 (en)

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Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009111751A (en) * 2007-10-30 2009-05-21 Rohm Co Ltd Analog switch and selector circuit using the same
JP2011166449A (en) * 2010-02-09 2011-08-25 Seiko Instruments Inc Transmission gate and semiconductor device
US8076966B2 (en) 2009-02-24 2011-12-13 Fujitsu Semiconductor Limited Analog switch circuit for wide frequency band
JP2012142796A (en) * 2010-12-29 2012-07-26 New Japan Radio Co Ltd Variable gain type amplifier
WO2013179890A1 (en) 2012-05-28 2013-12-05 ソニー株式会社 Single-phase differential conversion circuit, balun, switch and communication device
CN106160715A (en) * 2015-04-17 2016-11-23 瑞昱半导体股份有限公司 The multiplexer that switching switchs and comprises it
JP2017153095A (en) * 2017-03-15 2017-08-31 ラピスセミコンダクタ株式会社 Semiconductor circuit and semiconductor device
CN109150141A (en) * 2018-10-23 2019-01-04 上海艾为电子技术股份有限公司 A kind of analog switching circuit and its method of controlling switch and device
CN112968692A (en) * 2021-02-06 2021-06-15 江南大学 High-voltage selection circuit for memory array

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08307232A (en) * 1995-04-28 1996-11-22 Japan Radio Co Ltd Fet switch
JPH098621A (en) * 1995-06-16 1997-01-10 Nec Corp Fet switch circuit
JP2004048411A (en) * 2002-07-12 2004-02-12 Nec Corp High frequency switch
JP2005072993A (en) * 2003-08-26 2005-03-17 New Japan Radio Co Ltd Fet switch circuit
JP2008017416A (en) * 2006-07-10 2008-01-24 Matsushita Electric Ind Co Ltd High-frequency switch device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08307232A (en) * 1995-04-28 1996-11-22 Japan Radio Co Ltd Fet switch
JPH098621A (en) * 1995-06-16 1997-01-10 Nec Corp Fet switch circuit
JP2004048411A (en) * 2002-07-12 2004-02-12 Nec Corp High frequency switch
JP2005072993A (en) * 2003-08-26 2005-03-17 New Japan Radio Co Ltd Fet switch circuit
JP2008017416A (en) * 2006-07-10 2008-01-24 Matsushita Electric Ind Co Ltd High-frequency switch device

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009111751A (en) * 2007-10-30 2009-05-21 Rohm Co Ltd Analog switch and selector circuit using the same
US8076966B2 (en) 2009-02-24 2011-12-13 Fujitsu Semiconductor Limited Analog switch circuit for wide frequency band
JP2011166449A (en) * 2010-02-09 2011-08-25 Seiko Instruments Inc Transmission gate and semiconductor device
JP2012142796A (en) * 2010-12-29 2012-07-26 New Japan Radio Co Ltd Variable gain type amplifier
US9621139B2 (en) 2012-05-28 2017-04-11 Sony Corporation Single phase differential conversion circuit, balun, switch, and communication device
WO2013179890A1 (en) 2012-05-28 2013-12-05 ソニー株式会社 Single-phase differential conversion circuit, balun, switch and communication device
KR20150023233A (en) 2012-05-28 2015-03-05 소니 주식회사 Single-phase differential conversion circuit, balun, switch and communication device
CN106160715A (en) * 2015-04-17 2016-11-23 瑞昱半导体股份有限公司 The multiplexer that switching switchs and comprises it
JP2017153095A (en) * 2017-03-15 2017-08-31 ラピスセミコンダクタ株式会社 Semiconductor circuit and semiconductor device
CN109150141A (en) * 2018-10-23 2019-01-04 上海艾为电子技术股份有限公司 A kind of analog switching circuit and its method of controlling switch and device
CN109150141B (en) * 2018-10-23 2023-09-15 上海艾为电子技术股份有限公司 Analog switch circuit and switch control method and device thereof
CN112968692A (en) * 2021-02-06 2021-06-15 江南大学 High-voltage selection circuit for memory array
CN112968692B (en) * 2021-02-06 2023-08-25 江南大学 High-voltage selection circuit oriented to memory array

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