JP2008034660A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device and a manufacturing method thereof capable of easily decreasing a cell pitch so as to reduce a chip area or attain high integration. <P>SOLUTION: A trench 10 is formed to a semiconductor layer 19 of a MOS transistor 1. An inner wall face of the trench 10 is covered by a gate insulation layer 11, and a gate layer 12 is embedded to the inside of the trench 10. Further, a silicon oxide film layer 13 is formed on the trench 10. A source diffusion layer 15a and a well contact layer are formed to both sides of the trench 10 along a lengthwise direction (X direction) of the trench 10. Since the source diffusion layer 15a and the well contact layer are adjacent to each other along the lengthwise direction, the forming region of source contact layers 14a, 14b in contact with them can be reserved in the lengthwise direction. Thus, the cell pitch in the Y direction can be reduced without being limited by the forming region of the source contact layers 14a, 14b. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device having a trench type semiconductor element and a method for manufacturing the same.

  As an insulated gate FET, for example, a MOS field effect transistor (hereinafter referred to as MOS transistor) using a silicon oxide film as an insulating film is known. The structure for forming a MOS transistor on a semiconductor substrate can be roughly divided into two types, a vertical type and a horizontal type. Further, the vertical structure can be further divided into a planar structure and a trench structure. In particular, a MOS transistor having a vertical trench structure has characteristics of high breakdown voltage, large current, and low ON resistance. Therefore, the MOS transistor having a trench structure is useful for application to a power supply device capable of flowing a large current.

(First conventional example)
23A to 23H are cross-sectional views showing a cross-sectional structure of a MOS transistor 20 which is a first conventional example described in Patent Document 1. FIG.

  As shown in FIG. 23A, the MOS transistor 20 includes a single crystal silicon substrate (N + type) 21, and an epitaxial layer (N− type) 22 is provided on the single crystal silicon substrate (N + type) 21. Yes. A trench 28 is formed in the epitaxial layer (N− type) 22, and an inner wall surface thereof is covered with a gate insulating film layer 29. In the trench 28, polycrystalline silicon containing N-type impurities is buried to form a gate layer 30. A well diffusion layer (P− type) 23 is provided on the epitaxial layer (N− type) 22 and on both sides of the trench 28.

  23A to 23H, the layer displaying “N +” is a layer having a high N-type impurity concentration, and the layer displaying “N−” is a layer having a low N-type impurity concentration. Show. Similarly, a layer displaying “P +” is a layer having a high P-type impurity concentration, and a layer displaying “P−” is a layer having a low P-type impurity concentration.

  A source diffusion layer (N + type) 24 is provided on both upper sides of the trench 28 in the well diffusion layer (P− type) 23. The upper surface of the gate layer 30 is covered with a silicon oxide film 25 (insulating film). A source electrode 26 is connected to the source diffusion layer (N + type) 24. A drain electrode 27 is connected to the back surface of the single crystal silicon substrate (N + type) 21.

  According to the MOS transistor 20, a channel is formed on the side surface of the trench 28 by applying a positive potential to the gate layer 30 made of polycrystalline silicon. As a result, as indicated by an arrow in FIG. 23A, electrons move along a path from the source electrode 26 to the drain electrode 27, and a current flows between the source electrode 26 and the drain electrode 27.

  Next, a method for manufacturing the MOS transistor 20 shown in FIG. 23A will be described with reference to FIGS.

  As shown in FIG. 23B, a single crystal silicon epitaxial layer (N− type) 22 is formed on the entire surface of the single crystal silicon substrate (N + type) 21 by an epitaxial growth method, followed by photolithography, The well diffusion layer (P− type) 23 and the source diffusion layer (N + type) 24 are formed using a known technique such as an impurity ion implantation technique or an impurity diffusion technique. Hereinafter, these are referred to as a semiconductor layer 34. A silicon oxide film 33 is formed on the surface of the semiconductor layer 34.

  Next, as shown in FIG. 23C, the silicon oxide film 33 is processed into a predetermined shape so as to become a mask for forming the trench 28. Subsequently, using the silicon oxide film 33 as a mask, the silicon diffusion technique is used to penetrate the source diffusion layer (N + type) 24 and the well diffusion layer (P− type) 23 into the semiconductor layer 34 to form single crystal silicon. A trench 28 extending to the epitaxial layer (N− type) 22 is formed.

  Next, as shown in FIG. 23D, a gate insulating film layer 29 is formed on the inner wall surface of the trench 28. Then, as shown in FIG. 23E, a polycrystalline silicon film (N-type) 30 ′ is deposited so as to be embedded in the trench 28 using the CVD technique.

  Next, as shown in FIG. 23F, the polycrystalline silicon film (N-type) 30 ′ has an upper surface that is the upper surface of the semiconductor layer 34 (that is, the lower surface of the silicon oxide film 33) and a source diffusion layer (N + type). ) Etch back until it is positioned between the lower surface of 24. The upper surface of the polycrystalline silicon film (N-type) 30 ′ is located 0.25 to 0.5 μm below the upper surface of the semiconductor layer 34. In this way, the polycrystalline silicon film (N type) 30 ′ is processed into the gate layer 30.

  Next, as shown in FIG. 23G, the surface of the gate layer 30 is oxidized to form a silicon oxide film 25 on the gate layer 30. The silicon oxide film 25 is formed thicker than the silicon oxide film 33 provided on the surface of the semiconductor layer 34, and the upper surface of the silicon oxide film 25 and the upper surface of the silicon oxide film 33 are substantially flat. At this time, the upper surface of the gate layer 30 needs to be located below the surface of the semiconductor layer 34 and above the lower surface of the source diffusion layer (N + type) 24.

  Next, as shown in FIG. 23 (h), the silicon oxide film 33 formed on the semiconductor layer 34 is removed and brought into contact with the well diffusion layer (P− type) 23 and the source diffusion layer (N + type) 24. Thus, the source electrode 26 is formed on the semiconductor layer 34. On the other hand, the drain electrode 27 is formed on the back surface of the single crystal silicon substrate (N + type) 21.

  Thus, the MOS transistor 20 which is the first conventional example is manufactured.

(Second conventional example)
24A to 24E are cross-sectional views showing a cross-sectional structure of a MOS transistor 35 which is a second conventional example described in Patent Document 1. FIG.

  In the MOS transistor 35 shown in FIG. 24A, the gate layer 30 made of polycrystalline silicon (N-type) protrudes above the surface of the semiconductor layer 34, and further, laterally (outside the opening of the trench 28 ( The MOS transistor 20 shown in FIG. 23A is different from the MOS transistor 20 shown in FIG. The MOS transistor 35 shown in FIG. 24A is formed so as to be connected to the source electrode 26 between the adjacent trenches 28.

  A method for manufacturing the MOS transistor 35 shown in FIG. 24A will be described with reference to FIGS.

  As shown in FIG. 24B, the MOS transistor 35 includes a trench 28, a gate insulating film layer 29, and a gate layer 30 in the same process as in FIGS. 23B to 23E of the first conventional example. Is formed. In FIGS. 24A to 24E, the layer displaying “N +” has a high N-type impurity concentration, and the layer displaying “N−” has a low N-type impurity concentration. Indicates the layer. Furthermore, the layer displaying “P−” indicates a layer having a low P-type impurity concentration. Hereinafter, a different part from the 1st prior art example shown to Fig.23 (a)-(h) is demonstrated.

  First, as shown in FIG. 24B, using a known technique such as a photoengraving technique, the polycrystalline silicon film (N-type) is patterned and protrudes laterally outside the opening of the trench 28. A gate layer 30 having a U-shaped section or a T-shaped section is formed.

  Next, as shown in FIG. 24C, an interlayer insulating film layer 41 is formed. Then, as shown in FIG. 24D, the interlayer insulating film layer 41 is patterned by using a known technique such as a photoengraving technique to form a contact pattern.

  Finally, as shown in FIG. 24E, between the adjacent trenches 28, on the semiconductor layer 34 so as to be in contact with the well diffusion layer (P− type) 23 and the source diffusion layer (N + type) 24. A source electrode 26 is formed. On the other hand, the drain electrode 27 is formed on the back surface of the semiconductor layer 34.

  Thus, the MOS transistor 35 which is the second conventional example is manufactured.

(Third conventional example)
FIG. 25 is a cross-sectional view showing a cross-sectional structure of a MOS transistor 37 which is a third conventional example described in Patent Document 3. In FIG.

  As shown in FIG. 25, the insulated gate semiconductor device 36 includes a MOS transistor 37 as a power insulated semiconductor element, and a lateral MOSFET 38 as a lateral insulated gate semiconductor element for protecting the MOS transistor 37. In addition, a polycrystalline silicon diode 39 is provided as a circuit element for protecting the MOS transistor 37, and these elements are formed on the same chip.

  The MOS transistor 37 of the insulated gate semiconductor device 36 includes a silicon substrate (N type) 21. On the silicon substrate (N-type) 21, an n-type epitaxial layer 22 and a p-type well diffusion layer 40 are formed as the semiconductor layer 34. In these semiconductor layers 34, trenches 28 as lattice-shaped grooves are formed.

  Polycrystalline silicon (N-type) is buried in the trench 28 via a gate insulating film layer 29 to form gate layers 30 a and 30 b that serve as the first electrode of the MOS transistor 37. Although the gate layers 30a and 30b are drawn separately, the trenches 28 are connected to each other because they have a lattice shape.

  A gate electrode 32 is formed on the gate layer 30a with an oxide film 25 interposed therebetween. The gate electrode 32 is connected to the gate layer 30 a through a contact region formed in the oxide film 25. On the gate layer 30b, a source electrode 26 serving as a third electrode of the MOS transistor 37 is formed via the oxide film 25. Between the adjacent trenches 28, a p-type well diffusion layer 40, a high-concentration well diffusion layer (P-type) 23, and a source diffusion layer (N-type) 24 are formed. The layer (P type) 23 and the source diffusion layer (N type) 24 are connected. A drain electrode (not shown) which is the second electrode of the MOS transistor 37 is formed on the back surface of the silicon substrate (N-type) 21.

  A method for manufacturing the MOS transistor 37 included in the insulated gate semiconductor device 36 shown in FIG. 25 will be described below. In the MOS transistor 37, a trench 28 and a gate insulating film layer 29 are formed as in FIGS. 23A to 23H of the first conventional example.

  Here, a polycrystalline silicon film (N-type) is deposited so that polycrystalline silicon (N-type) is buried in the trench 28 and the surface of the semiconductor layer 34 is substantially flat. Next, the region to be etched of the polycrystalline silicon film (N type) is patterned using a photoresist.

  Then, the polycrystalline silicon film (N type) used as the contact region of the gate electrode 32 is patterned by performing etch back using the patterned photoresist as a mask. Unlike the gate layer 30 b, the gate layer 30 a connected to the gate electrode 32 protrudes in the lateral direction (lateral MOSFET 38 side) along the surface of the semiconductor layer 34 outside the opening of the trench 28.

  Next, a well diffusion layer (P-type) 23 and a source diffusion layer (N-type) 24 are formed using a known technique such as a photoengraving technique, an impurity ion implantation technique, and an impurity diffusion technique. Next, an oxide film 25 is deposited on the semiconductor layer 34. Then, the deposited oxide film 25 is selectively etched to form contact regions of the gate electrode 32 and the source electrode 26, and the gate electrode 32 and the source electrode 26 are formed in the formed contact regions.

In this way, the trench type MOSFET which is the third conventional example is manufactured.
JP 08-23092 (published on January 23, 1996) JP 2003-324197 (published November 14, 2003) JP 2000-91344 (released March 31, 2000)

  The size of the MOS transistor having a trench structure is determined by the unit element size (cell pitch). For this reason, in order to reduce the size of the MOS transistor, it is necessary to reduce the cell pitch. On the other hand, the cell pitch is limited by the size (especially width) of the trench and the size of the contact region (for example, the interval between adjacent trenches).

  The conventional MOS transistor described above has the following problems when it is to be miniaturized.

  In the first conventional MOS transistor shown in FIG. 23A, when the size of the trench 28 is reduced, the contact diameter (line width) of the gate electrode is reduced. For this reason, precise alignment accuracy is required when forming the contact portion of the gate electrode. Therefore, since such alignment accuracy must be taken into account, this limits the miniaturization of the trench 28. As a result, the size of the trench 28 cannot be reduced, and the cell pitch and further miniaturization of the MOS transistor cannot be realized.

  In the MOS transistor of the second conventional example shown in FIG. 24A, the gate layer 30 protrudes outward from the opening of the trench 28 and projects laterally. For this reason, the cell pitch is increased, which hinders miniaturization of the MOS transistor. In the MOS transistor of the second conventional example shown in FIG. 24A, the semiconductor layer 34 is connected to the source electrode 26 between two adjacent trenches 28, so that the interval between adjacent trenches is increased. When reducing the size, it is necessary to consider the size of the contact portion of the source electrode 26. Therefore, the interval between adjacent trenches 28 cannot be sufficiently reduced, which hinders miniaturization of the MOS transistor.

  Furthermore, in the MOS transistor of the third conventional example shown in FIG. 25, the gate layer 30a is connected to the gate electrode 32 by projecting laterally along the surface of the semiconductor layer 34 outside the opening of the trench 28. The gate contact portion to be formed is formed. Further, the oxide film 25 is selectively etched to form a source contact portion. For this reason, in order to form each contact part, precise alignment accuracy is required. Further, it is necessary to secure a design margin for forming the source contact portion between the adjacent trenches 28, which hinders the reduction of the cell pitch.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a smaller semiconductor device by reducing the cell pitch. It is another object of the present invention to provide a method for manufacturing a semiconductor device that does not require precise alignment accuracy. More specifically, it is to provide a semiconductor device and a method for manufacturing the same that can easily reduce the cell pitch and reduce the chip area or increase the integration density by using a conventional processing apparatus and processing technology.

In order to solve the above problems, a semiconductor device according to the present invention provides
A groove formed in a semiconductor layer formed on a semiconductor substrate;
A gate insulating layer covering an inner wall surface of the groove;
A gate layer embedded in the trench and connected to the gate electrode;
A first insulating layer formed to cover the opening of the groove;
A first conductive layer of a first conductivity type formed on both sides of the groove so as to be in contact with the groove;
A second conductive layer of a second conductivity type formed on both sides of the groove so as to be in contact with the groove;
A source contact layer formed so as to cover the groove, the first conductive layer, and the second conductive layer, and connected to a source electrode;
The first conductive layer and the second conductive layer are adjacent to each other in the longitudinal direction of the groove.

  According to the above configuration, the groove is formed in the semiconductor layer formed on the semiconductor substrate. The inner wall surface of this groove is covered with a gate insulating layer. In addition, a gate layer is embedded in the trench through a gate insulating layer. Further, a first insulating layer is formed in the opening of the groove.

  A first conductive layer of the first conductivity type and a second conductive layer of the second conductivity type are formed on both sides of the groove so as to be in contact with the groove. At this time, the first conductive layer and the second conductive layer are adjacent to each other along the longitudinal direction of the groove.

  A source contact layer is formed on the trench and the first conductive layer and the second conductive layer formed on both sides thereof. The source contact layer is formed so as to cover the trench, the first conductive layer, and the second conductive layer. At this time, the trench and the source contact layer are insulated by the first insulating film.

  As described above, the first conductive layer and the second conductive layer are formed so as to be adjacent to each other along the longitudinal direction of the groove, and the first conductive layer and the second conductive layer are insulated from the gate layer embedded in the groove. Since the source contact layer is formed so as to cover the conductive layer and the second conductive layer, the source contact layer formation region can be secured along the longitudinal direction of the groove. That is, the source contact layer formation region is not restricted by the size of the trench in the width direction.

  Therefore, even when the cell pitch is reduced in the groove width direction, a sufficient source contact layer formation region can be secured. As a result, it is possible to provide a small semiconductor device with a reduced cell pitch.

  In addition, since the source contact portion can be formed simply by forming the source contact layer so as to cover the first conductive layer and the second conductive layer, a precise position for forming the source contact portion is provided. In addition, there is an effect that accuracy is not required.

The semiconductor device according to the present invention further includes a gate contact layer in contact with the gate layer and formed on the semiconductor layer via an element isolation layer, and the gate layer is interposed via the gate contact layer. It is preferable to be connected to the gate electrode.

  According to the above configuration, the gate contact layer is formed on the gate layer. A gate contact layer is also formed on the semiconductor layer. At this time, the gate contact layer on the gate layer and the gate contact layer on the semiconductor layer are formed as one continuous layer. Since the element isolation layer is formed between the semiconductor layer and the gate contact layer, the semiconductor layer and the gate contact layer are electrically insulated.

  Thus, since the gate contact layer is formed so as to cover the gate layer and the semiconductor layer, the size of the gate contact layer is not limited by the size of the gate layer. That is, since the formation region of the gate contact layer extends from the gate layer to the element isolation layer, the formation region of the gate contact layer can be secured even if the size of the gate layer is reduced. For this reason, it is possible to reduce the size of the gate layer without considering the formation region of the gate contact layer, and it is possible to reduce the cell pitch.

  Further, it is preferable that at least a part of the side wall of the groove is in contact with the element isolation layer.

  According to the above configuration, a part of the side wall of the groove is in contact with the element isolation layer, so that the gate layer embedded in the groove and the other layer formed in the semiconductor layer can be sufficiently insulated. it can. Thereby, the performance of the semiconductor device can be improved.

  The semiconductor substrate is preferably formed of single crystal silicon containing N-type or P-type impurities.

  The semiconductor layer preferably has an epitaxial layer on the semiconductor substrate, and the conductivity type of the epitaxial layer is preferably N-type or P-type.

  The first conductive layer preferably includes an N-type or P-type impurity as the first conductivity type.

  The second conductive layer preferably includes an N-type or P-type impurity different from the first conductivity type.

  The gate layer is preferably formed of polycrystalline silicon containing N-type or P-type impurities.

  The gate contact layer is preferably made of polycrystalline silicon containing impurities of the same type as the gate layer.

The semiconductor device according to the present invention further includes a second insulating layer formed on the source contact layer and the gate contact layer,
A first metal layer connected to a source contact layer in a first contact region formed in the second insulating layer;
It is preferable that a second metal layer connected to the gate contact layer is provided in the second contact region formed in the second insulating layer.

  According to the above configuration, the source contact is formed by forming the first conductive layer containing the N-type impurity and the second conductive layer containing the P-type impurity so as to be adjacent along the longitudinal direction of the groove. Since the formation region of the layer is secured, a smaller N-channel MOSFET can be provided. Also, a P-channel MOSFET provided with a first conductive layer containing a P-type impurity and a second conductive layer containing an N-type impurity has the same effect as the N-channel MOSFET.

In order to solve the above problems, a method for manufacturing a semiconductor device according to the present invention provides:
Forming a groove in a semiconductor layer formed on the semiconductor substrate;
Coating the inner wall surface of the groove with a gate insulating layer;
Embedding a gate layer connected to a gate electrode in the trench;
Forming a first insulating layer so as to cover the opening of the groove;
Forming a source contact layer on the semiconductor layer so as to cover the groove;
Forming a first conductive type first conductive layer and a second conductive type second conductive layer on the semiconductor layer covered with the source contact layer so as to be in contact with both sides of the groove. And
In the step of forming the first conductive layer and the second conductive layer, the first conductive layer and the second conductive layer are formed so as to be adjacent to each other in the longitudinal direction of the groove. It is said.

  According to the above configuration, the source contact layer is formed so as to cover the semiconductor layer in which the groove is formed. Then, a first conductive layer and a second conductive layer are formed in the semiconductor layer covered with the source contact layer by, for example, an ion implantation method. At this time, the first conductive layer and the second conductive layer are formed so as to be in contact with both sides of the groove and adjacent to the longitudinal direction of the groove.

  This eliminates the need for a design margin for forming the source contact layer even when the cell pitch is reduced. As a result, the source contact region can be easily formed and the cell pitch can be reduced, so that an effect that a small semiconductor device can be easily manufactured is produced.

The method of manufacturing a semiconductor device according to the present invention further includes a step of etching the first insulating layer formed in the opening of the groove to expose a part of the gate layer;
Preferably, the method further includes a step of forming a gate contact layer on the exposed gate layer and the element isolation layer formed on the semiconductor layer.

  According to the above structure, the gate contact layer is formed on the partially exposed gate layer by etching the first insulating layer. A gate contact layer is also formed on the semiconductor layer. At this time, the gate contact layer on the gate layer and the gate contact layer on the semiconductor layer are formed as one continuous layer. Then, an element isolation layer is formed between the semiconductor layer and the gate contact layer to electrically isolate the two layers.

  Thus, since the gate contact layer is formed, the size of the gate contact layer is not limited by the size of the gate layer. For this reason, it is possible to reduce the size of the gate layer without considering the formation region of the gate contact layer, and it is possible to reduce the cell pitch. In addition, there is an effect that precise alignment accuracy is not necessary for forming the gate contact layer.

The step of forming the source contact layer and the gate contact layer includes:
Preferably, the source contact layer and the gate contact layer are formed simultaneously by forming a polycrystalline silicon layer on the semiconductor layer and selectively etching the polycrystalline silicon layer.

  According to the above configuration, the polycrystalline silicon layer is formed so as to cover the entire semiconductor layer in which the trench is formed. By etching the polycrystalline silicon layer, a source contact layer is formed which covers and covers the first insulating layer and the semiconductor layer formed in the opening of the trench. Similarly, the polycrystalline silicon layer is etched to form a gate contact layer that covers and contacts the gate layer and the element isolation layer.

  As described above, since the source contact layer and the gate contact layer are simultaneously formed by etching one polycrystalline silicon layer, the manufacturing process of the semiconductor device can be reduced.

  As described above, the semiconductor device according to the present invention includes the first conductive layer and the second conductive layer formed so as to be adjacent to each other along the longitudinal direction of the groove formed in the semiconductor layer. A source contact layer formed so as to cover the first conductive layer and the second conductive layer is provided.

  As a result, even when the cell pitch is reduced in the width direction of the groove, a sufficient region for forming the source contact layer can be secured, and the semiconductor device can be downsized.

  An embodiment of the present invention will be described with reference to FIGS. 1 to 19 as follows.

(Configuration of MOS transistor 1)
The configuration of a MOS transistor (semiconductor device) 1 according to the present invention will be described below with reference to FIG. FIG. 1 is a schematic perspective view of a MOS transistor 1 of this embodiment.

  As shown in FIG. 1, a MOS transistor 1 includes a single crystal silicon substrate (semiconductor substrate) 2, an epitaxial layer 3, an element isolation layer 6, a well diffusion layer 7, a trench (groove) 10, a gate insulating layer 11, and a gate layer 12. , A silicon oxide film layer (first insulating layer) 13, source contact layers 14a and 14b, a gate contact layer 14c, and a source diffusion layer 15a (first conductive layer). Further, the MOS transistor 1 includes a well contact layer 15b (second conductive layer) (see FIG. 7A) adjacent to the source diffusion layer 15a, and the source diffusion layer 15a and the well contact layer 15b are formed in the trench 10. Are formed adjacent to each other along the longitudinal direction of the gate layer 12 in other words.

  The single crystal silicon substrate 2, epitaxial layer 3 and well diffusion layer 7 constitute a semiconductor layer 19.

  In FIGS. 1 to 19A to 19F, “P” is indicated for a layer containing a P-type impurity, and “N” is indicated for a layer containing an N-type impurity. In addition, “P +” is displayed in a layer containing a P-type impurity at a higher concentration than the layer displaying “P”.

  Further, as shown in FIG. 1, the longitudinal direction of the trench 10 is the X direction, the width direction of the trench 10 is perpendicular to the X direction and the width direction of the trench 10 is the Y direction, and the direction perpendicular to the X direction and the Y direction, that is, the depth of the trench 10 Let the direction be the Z direction.

  The configuration of the MOS transistor 1 according to the present embodiment will be described more specifically as follows.

  As shown in FIG. 1, an epitaxial layer 3 is formed on a single crystal silicon substrate 2. Single crystal silicon substrate 2 contains P-type impurities, and its conductivity type is P-type. Epitaxial layer 3 includes a P-type impurity, and its conductivity type is P-type, but the concentration of P-type impurity is lower than that of single crystal silicon substrate 2. A well diffusion layer 7 is formed in the epitaxial layer 3. Well diffusion layer 7 includes N-type impurities, and its conductivity type is N-type.

  Further, in the well diffusion layer 7, a source diffusion layer 15a and a well contact layer 15b (FIG. 7A) are formed. Source diffusion layer 15a includes a P-type impurity, and its conductivity type is P-type. Further, the well contact layer 15 b is configured with the same conductivity type as the well diffusion layer 7. In this embodiment, the well contact layer 15b contains the same N-type impurity as the well diffusion layer 7, and its conductivity type is N-type. An isolation layer 6 is formed on a region of the epitaxial layer 3 where the trench 10, the well diffusion layer 7, the source diffusion layer 15a and the well contact layer 15b are not formed.

  Further, the MOS transistor 1 includes a trench 10 that penetrates the source diffusion layer 15a and the well contact layer 15b and is formed to a depth reaching the epitaxial layer 3. The trench 10 is formed in a groove shape having a long side extending in the arrow X direction shown in FIG. The inner wall surface of the trench 10 is covered with a gate insulating layer 11. Further, a gate layer 12 formed of polycrystalline silicon containing an N-type impurity is embedded in the trench 10. Since one of the side walls in the direction of arrow X of the trench 10 reaches the element isolation layer 6 and the inner wall surface of the trench 10 is covered with the gate insulating layer 11, the trench 10 is buried in the trench 10. The gate layer 12, the epitaxial layer 3, the well diffusion layer 7, the source diffusion layer 15a, and the well contact layer 15b are electrically insulated.

  The upper surface of the gate layer 12 embedded in the trench 10 is formed higher than the upper surface of the well diffusion layer 7 and lower than the upper surface of the source diffusion layer 15a. A silicon oxide film layer 13 is formed in the opening of the trench 10. The silicon oxide film layer 13 is formed on the gate insulating layer 11 and the gate layer 12 so as to close the opening of the trench 10.

  Further, the MOS transistor 1 includes source contact layers 14a and 14b that form source contact portions, and a gate contact layer 14c that forms a gate contact portion. As shown in FIG. 7A, the source contact layers 14a and 14b are formed so as to cover the trench 10, the source diffusion layer 15a, and the well contact layer 15b covered with the silicon oxide film layer 13. The gate contact layer 14 c is formed so as to be in contact with a part of the gate layer 12 embedded in the trench 10 and to cover the element isolation layer 6 formed on the epitaxial layer 3.

  As will be described in detail later, a gate contact layer 14 c electrically connected to the gate layer 12 is formed on the gate layer 12, and a gate contact layer 14 c is also formed on the semiconductor layer 19. At this time, the gate contact layer 14c on the gate layer 12 and the gate contact layer 14c on the semiconductor layer 19 are formed of one continuous layer. Since the element isolation layer 6 is formed between the semiconductor layer 19 and the gate contact layer 14c, the semiconductor layer 19 and the gate contact layer 14c are electrically insulated.

  Thus, since the gate contact layer 14 c is formed so as to cover the gate layer 12 and the semiconductor layer 19, the size of the gate contact layer 14 c is not limited by the size of the gate layer 12. That is, the gate contact portion is separated from the source contact portion, and the region where the gate contact layer 14c is formed extends from the gate layer 12 to the element isolation layer 6, thereby reducing the size of the gate layer 12. Even in this case, the formation region of the gate contact layer 14c can be secured. For this reason, the size of the gate layer 12 can be reduced without considering the formation region of the gate contact layer 14c, and the cell pitch can be reduced.

  Further, since the gate layer 12 is embedded in the trench 10 by etch back, as will be described later, the gate layer does not protrude from the opening of the trench as in the conventional example shown in FIGS. . This also contributes to reducing the cell pitch in the width direction (Y direction) of the trench 10. In the conventional example shown in FIG. 25, when the gate layer 30a is formed in the trench 28, the formation region of the gate layer 30a is patterned using a resist mask and further etched. For this reason, high processing accuracy is required, and it is necessary to secure a design margin, which hinders cell pitch reduction. On the other hand, in this embodiment, since the gate layer 12 is embedded in the trench 10 by etch back, high processing accuracy is not required. As a result, it is not necessary to secure a design margin, and the cell pitch can be reduced, that is, the size of the MOS transistor 1 can be reduced.

(Configuration of source contact layers 14a and 14b and gate contact layer 14c)
The configurations of the source contact layers 14a and 14b and the gate contact layer 14c included in the MOS transistor 1 of the present embodiment will be described in more detail with reference to FIGS. 2 is a schematic plan view of the MOS transistor 1 as viewed from the direction of the arrow Z (upper surface) in FIG. 1, and FIGS. 3 to 8 are cross-sectional views of the MOS transistor 1.

  As shown in FIG. 2, the source contact layer 14 a and the source contact layer 14 b are formed adjacent to each other in the longitudinal direction of the trench 10. Further, the source contact layers 14a and 14b and the gate contact layer 14c are formed so as to be adjacent to each other in the longitudinal direction of the trench 10, but the source contact layers 14a and 14b and the gate contact layer 14c are in any region. Are not in contact with each other and are not electrically connected.

  FIG. 3 is a cross-sectional view taken along the line A-A ′ in FIG. 2. As shown in FIG. 3, the source contact layer 14 a is formed so as to cover the source diffusion layer 15 a and the silicon oxide film layer 13 on the trench 10. Thus, the source contact layer 14a is in contact with the source diffusion layer 15a, while being electrically insulated from the gate layer 12 embedded in the trench 10 through the silicon oxide film layer 13. Yes.

  FIG. 4 is a cross-sectional view taken along the line B-B ′ in FIG. 2. As shown in FIG. 4, the source contact layer 14 b is formed so as to cover the well contact layer 15 b and the silicon oxide film layer 13 on the trench 10. In this way, the source contact layer 14b is in contact with the well contact layer 15b, while being electrically insulated from the gate layer 12 embedded in the trench 10 via the silicon oxide film layer 13. Yes.

  5 is a cross-sectional view taken along the line C-C ′ in FIG. 2, and FIG. 6 is a cross-sectional view taken along the line D-D ′ in FIG. 2. As shown in FIG. 5, the gate contact layer 14 c is formed so as to cover the element isolation layer 6 and the trench 10. In the cross section, the gate contact layer 14 c is in contact with the gate layer 12 embedded in the trench 10. Further, as shown in FIGS. 5 and 6, since the element isolation layer 6 is formed between the gate contact layer 14c and the epitaxial layer 3, the gate contact layer 14c and the epitaxial layer 3 are in any cross section. It is electrically insulated.

  7A is a cross-sectional view taken along the line E-E ′ in FIG. 2, and FIG. 7B is an enlarged view of the region A shown in FIG. As shown in FIG. 7A, the source diffusion layer 15a and the well contact layer 15b formed in the well diffusion layer 7 are adjacent to each other along the longitudinal direction of the well diffusion layer 7 (longitudinal direction of the trench 10). ing. As already described, the source contact layer 14a is formed on the source diffusion layer 15a, and the source contact layer 14b is formed on the well contact layer 15b.

  By forming the source diffusion layer 15a and the well contact layer 15b in this manner, the formation region of the source contact layers 14a and 14b can be secured in the longitudinal direction of the well diffusion layer 7 (longitudinal direction of the trench 10). . Therefore, the cell pitch in the width direction of trench 10 (arrow Y direction in FIG. 1) can be reduced without being limited to the region where source contact layers 14a and 14b are formed, and miniaturization of MOS transistor 1 is realized. Can do.

  FIG. 7B is an enlarged view showing the edge shape on the well diffusion layer 7 side of the element isolation layer 6 shown in FIG. As shown in FIG. 7B, the edge shape of the element isolation layer 6 on the well diffusion layer 7 side is a so-called bird's beak shape. The edge shape of the element isolation layer 6 will be described later in the description of the method for manufacturing the MOS transistor 1 of the present invention.

  FIG. 8 is a cross-sectional view taken along the line F-F ′ in FIG. 2. As shown in FIG. 8, a part of the silicon oxide film layer 13 formed on the trench 10 is not cut out in a region not in contact with the source contact layers 14a and 14b. In the region where the silicon oxide film layer 13 is notched, the gate contact layer 14 c is formed so as to contact the gate layer 12 and cover the element isolation layer 6. Here, the trench 10 penetrates into the formation region of the element isolation layer 6 shown in FIGS. 7A and 7B, that is, the element isolation layer 6 side further than the bird's beak-shaped edge portion of the element isolation layer 6. It is formed so that it may be located in. The gate contact layer 14 c is formed of polycrystalline silicon containing N-type impurities, like the gate layer 12. Further, since the gate contact layer 14c and the epitaxial layer 3 are separated by the element isolation layer 6, the gate contact layer 14c and the epitaxial layer 3 are electrically insulated.

  As described above, since the formation region of the gate contact layer 14c extends from the gate layer 12 to the element isolation layer 6, the size (particularly the width) of the trench 10 in which the gate layer 12 is embedded is appropriately changed. However, a sufficient formation region of the gate contact layer 14c can be secured. Therefore, the trench 10 can be reduced without being limited to the formation region of the gate contact layer 14c, and the MOS transistor 1 can be downsized.

(Manufacturing method of MOS transistor 1)
A method for manufacturing the MOS transistor 1 according to the present invention will be described with reference to FIGS. 9A and 9B to FIGS. 9A is a cross-sectional view of the MOS transistor 1 viewed from the direction of the arrow X in FIG. 1 along the YZ section, and FIG. 9B is a cross-sectional view of the MOS transistor 1 viewed from the direction of the arrow Y in FIG. It is sectional drawing shown by Z cut surface.

  9A and 9B, the MOS transistor 1 includes a single crystal silicon substrate 2, an epitaxial layer 3, an element isolation layer 6, a well diffusion layer 7, a trench 10, a gate insulating layer 11, a gate layer 12, A silicon oxide film layer 13, source contact layers 14a and 14b, a gate contact layer 14c, a source diffusion layer 15a, a well contact layer 15b (FIG. 7A) are provided, and an interlayer insulating layer (second insulating layer) is provided. 16, a source electrode (first metal layer) 17a, a gate electrode (second metal layer) 17b, and a drain electrode 18.

  As shown in FIG. 9A, the source electrode 17a is connected to the source contact layer 14a. Further, as shown in FIGS. 7A and 8, the source contact layer 14a and the source contact layer 14b are formed by dividing P-type impurities and N-type impurities in a series of patterned polycrystalline silicon films. Is done. For this reason, the source electrode 17a is also connected to the source contact layer 14b. An interlayer insulating layer 16 is formed between the source contact layers 14a and 14b and the source electrode 17a, and the contact between the source contact layers 14a and 14b and the source electrode 17a is separated by the interlayer insulating layer 16, Insulated.

  As shown in FIG. 9B, the gate electrode 17b is connected to the gate contact layer 14c. Here, the source electrode 17a connected to the source contact layers 14a and 14b and the gate electrode 17b connected to the gate contact layer 14c are separated and are not in contact with each other in any cross section. By applying a negative potential to the gate layer 12 through the gate electrode 17b connected to the gate contact layer 14c, a channel is formed on the side surface of the trench 10 shown in FIG. Current flows between the source electrode 17a and the drain electrode 18 by carriers moving along the direction of the arrow in this channel.

  Hereinafter, the manufacturing process of the MOS transistor 1 shown in FIGS. 9A and 9B will be described with reference to FIGS. 10A to 10D and FIGS. 19A to 19F. In the manufacturing process of the MOS transistor 1 of this embodiment, various films and layers to be formed are formed by using a conventional film forming technique such as a chemical vapor deposition method (CVD method) or a thermal oxidation method. For etching these films and layers, conventional etching techniques such as dry etching, wet etching, and photo etching are used.

(First manufacturing process)
FIGS. 10A to 10D are views showing a first manufacturing process of the MOS transistor 1. 10A is a cross-sectional view of the YZ cut plane perpendicular to the arrow X direction in FIG. 1, and FIG. 10B is a cross-section of the XZ cut plane perpendicular to the arrow Y direction in FIG. FIG. FIG. 10C is a partial plan view of FIG. 10A viewed from above, and FIG. 10D is a plan view of FIG. 10B viewed from above.

  10A and 10C show the vicinity of the source contact portion, and FIGS. 10B and 10D show the vicinity of the gate contact portion.

  In the first manufacturing process, first, an epitaxial layer 3 is formed on a single crystal silicon substrate 2 as shown in FIGS. Here, the single crystal silicon substrate 2 contains P-type impurities and has a resistivity (specific resistance) of, for example, 0.005 to 0.01 Ω · cm. Also, the concentration of P-type impurities is low.

  Next, a first silicon oxide film 4 is deposited on the epitaxial layer 3 so as to have a film thickness of, for example, 10 nm to 50 nm. The first silicon oxide film 4 is used as a mask when the silicon oxide film layer 13 is formed in a sixth manufacturing process described later. Further, a first silicon nitride film 5 is deposited on the first silicon oxide film 4 so as to have a film thickness of 100 nm to 300 nm, for example (FIGS. 10A and 10C). Further, by selectively etching the first silicon nitride film 5, a region for forming the element isolation layer 6 is patterned in the subsequent second manufacturing process (FIGS. 10B and 10D). By etching the first silicon nitride film 5 in this way, a part of the first silicon oxide film 4 is exposed.

(Second manufacturing process)
FIGS. 11A to 11D are views showing a second manufacturing process of the MOS transistor 1. 11A is a cross-sectional view of the YZ cut plane perpendicular to the arrow X direction in FIG. 1, and FIG. 11B is a cross-section of the XZ cut plane perpendicular to the arrow Y direction in FIG. FIG. FIG. 11C is a partial plan view of FIG. 11A viewed from above, and FIG. 11D is a plan view of FIG. 11B viewed from above.

  11A and 11C show the vicinity of the source contact portion, and FIGS. 11B and 11D show the vicinity of the gate contact portion.

  In the second manufacturing process, first, as shown in FIGS. 11A to 11D, the element isolation layer 6 is formed in the region (FIGS. 11A and 11C) patterned in the first manufacturing process. For example, deposition is performed so that the layer thickness is 200 nm to 1100 nm. After the element isolation layer 6 is formed, the first silicon nitride film 5 is removed by wet etching (FIGS. 11B and 11D). Here, when the element isolation layer 6 is formed, the first silicon oxide film 4 and the silicon substrate existing on the lower side of the first silicon nitride film 5 shown in FIG. A part of the epitaxial layer 3) is also oxidized. Thereby, the element isolation film 6 is formed so as to enter the first silicon oxide film 4, and the region that has entered the oxide film has a so-called bird's beak shape. In FIGS. 7A and 11B, the shape of the bird's beak at the edge is simplified.

Next, a well diffusion layer 7 is formed by ion-implanting N-type impurities into the epitaxial layer 3 (FIGS. 11A and 11B). At this time, for example, phosphorus (31P +) is used for ion implantation, and ion energy of 80 keV to 360 keV is implanted at about 1.0E + 12 to 1.0E + 14 / cm ² . By performing ion implantation in this way, the well diffusion layer 7 is formed so that, for example, the surface impurity concentration is 5 × 10 ^{16 to} 7 × 10 ¹⁷ (atoms / cm ³ ) and the depth is 1 to 5 μm. The semiconductor layer 19 is composed of the single crystal silicon substrate 2, the epitaxial layer 3, and the well diffusion layer 7 formed in this manufacturing process.

(Third manufacturing process)
12A to 12D are diagrams showing a third manufacturing process of the MOS transistor 1. 12A is a cross-sectional view of the YZ cut plane perpendicular to the arrow X direction in FIG. 1, and FIG. 12B is a cross-section of the XZ cut plane perpendicular to the arrow Y direction in FIG. FIG. FIG. 12C is a partial plan view of FIG. 12A viewed from above, and FIG. 12D is a plan view of FIG. 12B viewed from above.

  FIGS. 12A and 12C show the vicinity of the source contact portion, and FIGS. 12B and 12D show the vicinity of the gate contact portion.

  In the third manufacturing process, first, as shown in FIGS. 12A to 12D, a second silicon nitride film 8 is formed on the first silicon oxide film 4 and the element isolation layer 6, for example, with a film thickness. Is deposited to be 100 nm to 300 nm. The second silicon nitride film 8 is used as a mask when the silicon oxide film layer 13 is formed in a sixth manufacturing process described later. Further, a CVD oxide film 9 is deposited on the second silicon nitride film 8 so as to have a film thickness of, for example, 100 nm to 400 nm. Since this CVD oxide film 9 is used as a mask when forming the trench 10 in the subsequent fourth manufacturing process, it may be deposited so as to have a thickness suitable for the formation of the trench 10. Next, by etching the first silicon oxide film 4, the element isolation layer 6, the second silicon nitride film 8 and the CVD oxide film 9, a region for forming the trench 10 is patterned in the subsequent fourth manufacturing process. To do.

(Fourth manufacturing process)
FIGS. 13A to 13D are views showing a fourth manufacturing process of the MOS transistor 1. 13A is a cross-sectional view of the YZ cut plane perpendicular to the arrow X direction in FIG. 1, and FIG. 13B is a cross-section of the XZ cut plane perpendicular to the arrow Y direction in FIG. FIG. FIG. 13C is a partial plan view of FIG. 13A viewed from the top, and FIG. 13D is a plan view of FIG. 13B viewed from the top.

  13A and 13C show the vicinity of the source contact portion, and FIGS. 13B and 13D show the vicinity of the gate contact portion.

  In the fourth manufacturing process, first, as shown in FIGS. 13A to 13D, the first silicon oxide film 4, the element isolation layer 6, and the second silicon patterned in the third manufacturing process. Trench 10 is formed by etching semiconductor layer 19 using nitride film 8 and CVD oxide film 9 as a mask. At this time, the trench 10 has a depth that penetrates the well diffusion layer 7 and reaches the epitaxial layer 3. For example, the trench 10 is formed to have a depth of 1.2 μm to 10.0 μm from the upper surface of the semiconductor layer 19. The depth of the trench 10 can be appropriately changed according to desired electrical characteristics.

  The trench 10 is formed in a groove shape having a long side extending in the arrow X direction. At this time, the trench 10 is arranged such that a part of the side wall of the trench 10 is located closer to the element isolation layer 6 than the boundary line between the first silicon oxide film 4 and the element isolation layer 6 shown in FIG. Is formed (FIG. 13D). By forming the trench 10 in this way, it is possible to electrically insulate the gate layer 12 formed in a fifth manufacturing process described later from each layer constituting the semiconductor layer 19. Furthermore, in the ninth manufacturing process to be described later, the gate contact layer 14c can be formed so as to be in contact with the gate layer 12 and cover the element isolation layer 6, so that the gate contact layer 14c and the semiconductor layer 19 are configured. Each layer can be electrically insulated.

(Fifth manufacturing process)
14A to 14D are diagrams showing a fifth manufacturing process of the MOS transistor 1. 14A is a cross-sectional view of the YZ cut plane perpendicular to the arrow X direction in FIG. 1, and FIG. 14B is a cross-section of the XZ cut plane perpendicular to the arrow Y direction in FIG. FIG. FIG. 14C is a plan view of FIG. 14A viewed from the top, and FIG. 14D is a plan view of FIG. 14B viewed from the top.

  14A and 14C show the vicinity of the source contact portion, and FIGS. 14B and 14D show the vicinity of the gate contact portion.

  In the fifth manufacturing process, first, as shown in FIGS. 14A to 14D, a gate insulating layer is formed by covering the inner wall surface of the trench 10 formed in the fourth manufacturing process with a silicon oxide film. 11 is formed. At this time, the silicon oxide film covering the inner wall surface is formed to have a thickness of, for example, 50 nm to 100 nm. At this time, the gate insulating layer 11 is formed so as to oxidize a part of the semiconductor layer (the epitaxial layer 3 in FIG. 14B) and to erode to the semiconductor layer 19 side. Therefore, as shown in FIG. 14B, the gate insulating layer 11 is formed below the element isolation layer 6 so that the upper surface of the gate insulating layer 11 is in contact with the lower surface of the element isolation layer 6. Further, polycrystalline silicon containing N-type impurities is deposited so as to be embedded in the trench 10. At this time, the polycrystalline silicon is deposited so that the layer thickness is, for example, 100 nm to 1000 nm. The thickness of the deposited polycrystalline silicon is appropriately changed according to the size (especially width) of the trench 10.

  Next, the polycrystalline silicon layer is etched back to form the gate layer 12. The amount of etch back varies depending on the thickness of the deposited polycrystalline silicon layer. However, in order to appropriately insulate the silicon oxide film layer 13 formed in the sixth manufacturing process, which will be described later, and the source contact layers 14a and 14b formed in the ninth manufacturing process, many layers are deposited in the trench 10. The upper surface of the crystalline silicon needs to be controlled so as to be located in a range from the upper surface of the well diffusion layer 7 to the lower surface of the second silicon nitride film 8. Further, as a result of etching back the upper surface of the polycrystalline silicon, that is, the upper surface of the gate layer 12 so as to be in the above-described position, the upper surface of the gate layer 12 is in the range from the lower surface to the upper surface of the element isolation layer 6 in the vicinity of the gate contact portion. It will be located (FIG.14 (b)).

  At this time, for example, when the upper surface of the polycrystalline silicon deposited in the trench 10 is higher than the above-described range, that is, when the upper surface of the gate layer 12 is located above the lower surface of the second silicon nitride film 8, this will be described later. The silicon oxide film layer 13 formed in the sixth manufacturing process grows only in the longitudinal (depth) direction. This is because the side wall portion of the gate layer 12 is covered with the second silicon nitride film 8 so that it cannot be grown in the width direction (lateral direction) of the gate layer 12.

  Therefore, when the upper surface of the gate layer 12 is located near the upper surface of the second silicon nitride film 8, a sufficient space is provided between the source contact layers 14a and 14b formed in the ninth manufacturing process described later and the gate layer 12. In order to insulate, it is necessary to further increase the thickness of the silicon oxide film layer 13. This is because if the thickness of the silicon oxide film layer 13 is small, the side surface of the gate layer 12 may be exposed when the second silicon nitride film 8 is etched in a seventh manufacturing process described later. This is because it becomes difficult to sufficiently insulate between the source contact layers 14a and 14b and the gate layer 12.

  However, when the thickness of the silicon oxide film layer 13 is increased, the gate contact layer 14c is formed by etching a part of the element isolation film 6 together with the silicon oxide film layer 13 in an eighth manufacturing process described later. Etching is difficult when patterning the region. That is, although the silicon oxide film layer 13 does not grow in the lateral direction, an etching amount is required in which the etching margin is added to the thickness of the silicon oxide film. This causes a problem that the gate insulating layer 11 formed on the sidewall of the trench 10 and the element isolation film 6 are removed by excessive etching.

  Therefore, it is necessary to etch back so that the upper surface of the gate layer 12 is located below the lower surface of the second silicon nitride film 8.

  On the other hand, when the upper surface of the polycrystalline silicon deposited in the trench 10 is lower than the above-described range, that is, when the upper surface of the gate layer 12 is located lower than the upper surface of the well diffusion layer 7, a sixth production described later. The silicon oxide film layer 13 formed in the process grows not only in the longitudinal (depth) direction but also in the lateral direction (outside from the trench 10).

  Therefore, when the silicon oxide film layer 13 is formed, the thickness of the silicon oxide film layer 13 formed closer to the trench 10 in the semiconductor layer 19 existing between the adjacent trenches 10 becomes thicker. The layer thickness of the silicon oxide film layer 13 formed at a position farther from 10 becomes thinner. For this reason, it becomes difficult to perform accurate etching in a seventh manufacturing process described later.

  When the silicon oxide film layer 13 grown on the semiconductor layer 19 is removed, if the etching amount is increased, the source contact layers 14a and 14b formed in the ninth manufacturing process are in direct contact with the gate layer 12 and are sufficiently There is a risk that insulation will not be possible. Further, when the etching amount is reduced, the region where the source contact layers 14a, 14b and the semiconductor layer 19 are in contact with each other is separated from the trench 10 and the resistance component increases, thereby affecting the characteristics of the manufactured MOS transistor 1. become. Further, when the thickness of the silicon oxide film layer 13 is reduced, there arises a problem that the source contact layers 14a and 14b formed in the ninth manufacturing process described later cannot be sufficiently insulated from the gate layer 12. .

Therefore, it is necessary to etch back so that the upper surface of the gate layer 12 is positioned above the upper surface of the well diffusion layer 7.
(Sixth manufacturing process)
FIGS. 15A to 15D are views showing a sixth manufacturing process of the MOS transistor 1. 15A is a cross-sectional view of the YZ cut plane perpendicular to the arrow X direction in FIG. 1, and FIG. 15B is a cross-section of the XZ cut plane perpendicular to the arrow Y direction in FIG. FIG. FIG. 15C is a partial plan view of FIG. 15A viewed from above, and FIG. 15D is a plan view of FIG. 15B viewed from above.

  FIGS. 15A and 15C show the vicinity of the source contact portion, and FIGS. 15B and 15D show the vicinity of the gate contact portion.

  In the sixth manufacturing process, first, as shown in FIGS. 15A to 15D, after the CVD oxide film 9 on the second silicon nitride film 8 is etched back, the gate layer formed in the trench 10 is formed. A silicon oxide film layer 13 is formed on the layer 12 by selectively depositing a silicon oxide film using a thermal oxidation method. The silicon oxide film layer 13 needs to be formed to have a layer thickness sufficient to insulate the gate layer 12 and the source contact layers 14a and 14b formed in a ninth manufacturing process described later. For this reason, the silicon oxide film layer 13 is formed to have a thickness of, for example, 200 nm to 1000 nm.

(Seventh manufacturing process)
FIGS. 16A to 16D are diagrams showing a seventh manufacturing process of the MOS transistor 1. 16A is a cross-sectional view of the YZ cut plane perpendicular to the arrow X direction in FIG. 1, and FIG. 16B is a cross-section of the XZ cut plane perpendicular to the arrow Y direction in FIG. FIG. FIG. 16C is a partial plan view of FIG. 16A viewed from the top, and FIG. 16D is a plan view of FIG. 16B viewed from the top.

  16A and 16C show the vicinity of the source contact portion, and FIGS. 16B and 16D show the vicinity of the gate contact portion.

  In the seventh manufacturing process, first, as shown in FIGS. 16A to 16D, the second silicon nitride film 8 is removed by wet etching. Further, the first silicon oxide film 4 on the well diffusion layer 7 is etched. At this time, for example, a photoresist pattern is formed on the first silicon oxide film 4, and various etching techniques (dry etching or wet etching or a combination of dry etching and wet etching are used by using the photoresist pattern as an etching mask. ) To selectively remove the first silicon oxide film 4.

(Eighth manufacturing process)
FIGS. 17A to 17E are views showing an eighth manufacturing process of the MOS transistor 1. 17A is a cross-sectional view of the YZ cut plane perpendicular to the arrow X direction in FIG. 1, and FIG. 17B is a cross-section of the XZ cut plane perpendicular to the arrow Y direction in FIG. FIG. FIG. 17C is a partial plan view of FIG. 17A viewed from the top, and FIG. 17D is a plan view of FIG. 17B viewed from the top. Furthermore, FIG.17 (e) is arrow sectional drawing in GG 'of FIG.17 (d).

  FIGS. 17A and 17C show the vicinity of the source contact portion, and FIGS. 17B, 17D and 17E show the vicinity of the gate contact portion.

  In the eighth manufacturing process, first, as shown in FIGS. 17B and 17D, the silicon oxide film layer 13 on the gate layer 12 is etched. In the region where the silicon oxide film layer 13 is selectively removed, the gate layer 12 inside the trench 10 is partially exposed. As shown in FIGS. 17A to 17E, when the silicon oxide film layer 13 is etched, high processing accuracy is required to selectively remove only the silicon oxide film layer 13. Etching is performed including part of the element isolation layer 6 formed on the epitaxial layer 3 to expose part of the gate layer 12.

  Next, the eighth manufacturing process will be described in more detail with reference to FIGS. 20A to 20C show a process leading to the configuration of the cross-sectional view shown in FIG. 17E in the eighth manufacturing process, and FIG. 20D shows the process in the ninth manufacturing process shown in FIG. As shown in the cross-sectional view of (h), the gate contact layer 14c is formed.

  As shown in FIG. 20A, at the end of the seventh manufacturing process, the element isolation layer 6 is formed on the epitaxial layer 3 and the gate insulating layer 11, and the silicon oxide film layer is formed on the gate layer 12. 13 is formed. Next, as shown in FIG. 20B, a photoresist pattern 42 is formed on the element isolation layer 6. By etching using the photoresist pattern 42 as an etching mask, the formation region of the gate contact layer 14c is patterned.

  Thereby, as shown in FIG. 20C, together with the silicon oxide film layer 13, a part of the element isolation layer 6 is also removed. As described above, when the silicon oxide film layer 13 is removed and the gate layer 12 is exposed, the silicon oxide film layer 13 and a part of the element isolation layer 6 are etched together, so that the processing becomes easy. Then, in a ninth manufacturing process described later, as shown in FIG. 20D, a gate contact layer 14c is formed on the pattern formed by etching. Thereafter, the photoresist pattern 42 is removed, and the patterning of the gate contact layer 14c is completed.

  Here, in FIG. 20C described above, when the silicon oxide film layer 13 and the element isolation layer 6 are partially removed, if the etching is not performed normally, the manufactured MOS transistor 1 operates normally. There is a possibility not to.

  For example, as shown in FIG. 21A, when the etching is performed excessively, the element isolation layer 6 between the adjacent gate layers 12 and a part of the gate insulating layer 11 are removed, and the gate layer 12 A part of the side is exposed. Then, when the gate contact layer 14c is formed in the region patterned by this excessive etching, as shown in FIG. 21B, the gate contact layer 14c is in direct contact with the epitaxial layer 3, and between the two elements is formed. It cannot be insulated and conducts.

  On the other hand, as shown in FIG. 22A, when the etching is insufficient, the silicon oxide film layer 13 remains on the gate layer 12. When the gate contact layer 14c is formed in the region patterned by this etching as shown in FIG. 22B, the remaining silicon oxide film layer 13 is formed between the gate contact layer 14c and the gate layer 12. Insulated and not conductive.

  For this reason, it is necessary to design the etching amount appropriately. And in order to prevent the malfunction by etching failure, it is preferable that the layer thickness of the element isolation layer 6 formed in a 2nd manufacturing process is thicker than the layer thickness of the silicon oxide film layer 13 formed in a 6th manufacturing process.

(9th manufacturing process)
FIGS. 18A to 18F are views showing a ninth manufacturing process of the MOS transistor 1. 18A is a cross-sectional view of the YZ cut plane perpendicular to the arrow X direction in FIG. 1, and FIG. 18B is a cross-section of the XZ cut plane perpendicular to the arrow Y direction in FIG. FIG. FIG. 18C is a partial plan view of FIG. 18A viewed from the top, and FIG. 18D is a plan view of FIG. 18B viewed from the top. Further, FIG. 18E is a cross-sectional view of another YZ cut plane perpendicular to the arrow X direction in FIG. 1, and FIG. 18F is an arrow at HH ′ in FIG. FIG.

  In the ninth manufacturing process, first, a polycrystalline silicon film is collectively deposited on the well diffusion layer 7, the silicon oxide film layer 13, and the element isolation layer 6 without distinguishing between the source contact portion and the gate contact portion. . At this time, in the eighth manufacturing process, a part of the silicon oxide film layer 13 is removed, and a polycrystalline silicon film is deposited also on the region where the gate layer 12 is exposed. Next, as shown in FIGS. 18A to 18F, the deposited polycrystalline silicon film is etched to form source contact layers 14a and 14b (see FIGS. 1 and 7) and a gate contact layer 14c. For patterning at the same time.

  Then, a source contact layer 14a is formed by ion-implanting a P-type impurity into a part of a region in contact with the well diffusion layer 7 in the patterned polycrystalline silicon film, and the well diffusion layer of the polycrystalline silicon film is formed. A source contact layer 14b (FIG. 18 (e)) is formed by ion-implanting N-type impurities into another region in contact with 7. The source contact layers 14 a and 14 b are formed so as to cover the trench 10, but the source contact layers 14 a and 14 b and the gate layer 12 are electrically insulated by the silicon oxide film layer 13. Further, by implanting N-type impurities into a region of the polycrystalline silicon film that is in contact with the gate layer 12 and in contact with the element isolation layer 6, the N-type gate contact layer 14c (FIG. 18B). (D) (f)) is formed.

At this time, boron fluoride (BF ₂ ), for example, as a P-type impurity is implanted into the source contact layer 14a at an ion energy of 30 keV to 80 keV at about 1.0E + 13 to 1.0E + 16 / cm ² . Further, arsenic (As), for example, is implanted into the source contact layer 14b and the gate contact layer 14c as an N-type impurity at an ion energy of 30 keV to 80 keV and about 1.0E + 13 to 1.0E + 16 / cm ² .

After ion implantation, these layers are heat-treated (850 ° C. to 950 ° C.), and BF ₂ implanted into the source contact layer 14a is diffused into the well diffusion layer 7 to form the source diffusion layer 15a (FIG. 18 ( a)). At the same time, As implanted into the source contact layer 14b is diffused into the well diffusion layer 7 to form the well contact layer 15b (FIG. 18E). At this time, the source diffusion layer 15a and the well contact layer 15b are formed to have a depth of 0.2 μm to 0.5 μm, for example.

  Thus, since the source diffusion layer 15a and the well contact layer 15b are formed adjacent to each other in the longitudinal direction of the trench 10 rather than in the width direction of the trench 10, the formation regions of the source contact layers 14a and 14b are trenches. 10 in the longitudinal direction. Thereby, even when the cell pitch in the width direction of trench 10 (arrow Y direction in FIG. 1) is reduced, a sufficient area for forming source contact layers 14a and 14b can be secured. As a result, the cell pitch in the width direction of the trench 10 can be reduced without being limited to the formation region of the source contact layers 14a and 14b, and the MOS transistor 1 can be downsized.

  Further, the gate contact layer 14 c formed of a polycrystalline silicon film has an N conductivity type due to the implantation of As, and the same conductivity type as the gate layer 12. Since the gate contact layer 14c is formed so as to be in contact with the gate layer 12 exposed in the above-described eighth manufacturing process and to cover the element isolation layer 6, the formation region of the gate contact layer 14c is formed on the trench 10 To the element isolation layer 6. For this reason, even if the size (particularly the width) of the trench 10 in which the gate layer 12 is embedded is appropriately changed, a sufficient formation region of the gate contact layer 14c can be secured. Therefore, the trench 10 can be reduced without being limited to the formation region of the gate contact layer 14c, and the MOS transistor 1 can be downsized.

(10th manufacturing process)
FIGS. 19A to 19F are views showing a tenth manufacturing process of the MOS transistor 1. 19A is a cross-sectional view of the YZ cut plane perpendicular to the arrow X direction in FIG. 1, and FIG. 19B is a cross-section of the XZ cut plane perpendicular to the arrow Y direction in FIG. FIG. FIG. 19C is a partial plan view of FIG. 19A viewed from above, and FIG. 19D is a plan view of FIG. 19B viewed from above. Furthermore, FIG.19 (e) is arrow sectional drawing in II 'of FIG.19 (d), FIG.19 (f) is arrow sectional drawing in JJ' of FIG.19 (d). is there.

  FIGS. 19A and 19C show the vicinity of the source contact portion, and FIGS. 19B and 19D show the vicinity of the gate contact portion.

In the tenth manufacturing process, first, as shown in FIGS. 19A to 19F, interlayer insulation is formed on the element isolation layer 6, the silicon oxide film layer 13, the source contact layers 14a and 14b, and the gate contact layer 14c. The layer 16 is formed so that the layer thickness is, for example, 300 nm to 1000 nm. Thereafter, as shown in FIG. 19 (c) ~ (f) , the contact region 17b ₁ of the contact region 17a ₁ and the gate electrode 17b of the source electrode 17a, is patterned on the interlayer insulating layer 16. On the patterned interlayer insulating layer 16, for example, an Al—Si film as a metal thin film is deposited by sputtering. The deposited metal thin film is etched to form the source electrode 17a and the gate electrode 17b.

  As a result, as shown in FIG. 19A, the source electrode 17a and the source contact layer 14a are in contact with each other at the contact point 17a '. Further, the source electrode 17a and the source contact layer 14b are in contact with each other in a different cross section (not shown). Further, as shown in FIG. 19B, the gate electrode 17b and the gate contact layer 14c are in contact with each other at a contact point 17b '. Note that the contacts 17a ′ and 17b ′ shown in FIGS. 19C and 19D are merely indicated by broken lines for convenience of explanation, and in the present embodiment, these contacts 17a ′ and 17b ′ are formed from the upper surface of the MOS transistor 1. You can't see.

  Finally, the drain electrode 18 is formed on the back surface of the single crystal silicon substrate 2 (the surface where the epitaxial layer 3 is not formed).

  As described above, the MOS transistor 1 according to the present invention is manufactured. Even if the above-described MOS transistor 1 of the present invention is manufactured using a conventional processing apparatus and processing technique, the cell pitch can be reduced to, for example, about 50% of the conventional one. The reason is as follows.

  In the generation of a design rule of 0.5 μm, the cell pitch of a MOS transistor having a trench structure is generally about 3 μm. At this time, the width of the trench is about 0.8 μm to 1 μm, and the interval between adjacent trenches is about 2 μm.

  On the other hand, since the MOS transistor 1 according to the present invention is not limited by the formation region of the gate contact layer 14c, the width of the trench 10 can be reduced to the minimum value of the design rule. For this reason, the width of the trench 10 can be reduced to about 0.7 μm even if it is considered that the width of the trench 10 is expanded by silicon oxidation after the manufacture of the MOS transistor 1.

  Further, in the MOS transistor 1 of the present invention, the source contact layers 14 a and 14 b are formed in the longitudinal direction of the trench 10. For this reason, the space | interval of adjacent trenches 10 can be reduced, without being restrict | limited by the formation region of source contact layers 14a and 14b.

  Further, the source contact layers 14a and 14b and the gate contact layer 14c are simultaneously formed by etching one polycrystalline silicon film. Thereby, a source contact part and a gate contact part can be formed easily.

  For example, as shown in FIG. 3, in the MOS transistor 1 according to the present invention, both ends of the silicon oxide film layer 13 formed on the trench 10 protrude outward from the trench 10 by about 0.2 μm. Further, when the MOS transistor 1 according to the present invention is configured to have a current value equivalent to that of a conventional MOS transistor in which the source electrode is directly contacted with the source diffusion region, the source contact layer 14a is interposed between the adjacent trenches 10. The width of the region where the source diffusion layer 15a is in contact (the length in the direction of arrow Y in FIG. 1) is about 0.5 μm. Thus, the interval between adjacent trenches is about 0.9 μm. The cell pitch of the MOS transistor 1 is represented by the sum of the width of the trench 10 and the interval between adjacent trenches, and the cell pitch of the MOS transistor 1 according to the present invention is about 1.6 μm.

  Thus, according to the MOS transistor 1 and the manufacturing method thereof according to the present invention, the cell pitch can be reduced by about 50% as compared with the conventional MOS transistor (cell pitch of about 3 μm).

  In the present embodiment, the MOS transistor 1 is a P-channel type, but the same effect can be obtained even with an N-channel type configuration.

  The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope of the claims. That is, embodiments obtained by combining technical means appropriately changed within the scope of the claims are also included in the technical scope of the present invention.

(Other configurations)
The present invention can also be expressed as follows.

(First configuration)
Forming an epitaxial layer on the single crystal silicon substrate;
Forming a first silicon oxide film and a first silicon nitride film, etching the first silicon nitride film using a known photoetching technique, and forming an element isolation region; and a surface of the epitaxial layer Performing impurity ion implantation and diffusion to form a well diffusion layer;
Forming a trench using the second silicon nitride film and the CVD oxide film as a mask;
Forming a gate oxide film on the inner wall surface of the trench;
A step of filling the inside of the trench with a polycrystalline silicon film, a step of covering the surface of the polycrystalline silicon film with a silicon oxide film,
Forming a second polycrystalline silicon film and performing high-concentration impurity ion implantation and diffusion;
A method of manufacturing a semiconductor device including a step of forming an interlayer insulating film and a metal wiring.

(Second configuration)
The method for manufacturing a semiconductor device according to the first structure, wherein the impurity contained in the single crystal silicon substrate is N-type or P-type.

(Third configuration)
The method for manufacturing a semiconductor device according to the first configuration, wherein the epitaxial layer is N-type or P-type.

(Fourth configuration)
The method for manufacturing a semiconductor device according to the first configuration, wherein the well diffusion layer is N-type or P-type.

(Fifth configuration)
The method of manufacturing a semiconductor device according to the first configuration, wherein the polycrystalline silicon film embedded in the trench is N-type or P-type.

(Sixth configuration)
The semiconductor device manufacturing method according to the first configuration, wherein a part of the trench portion, such as both ends or one end, is applied to the second silicon oxide film region.

(Seventh configuration)
The semiconductor device manufacturing method according to the first configuration, wherein the high-concentration impurity layer in contact with the gate oxide film on the upper wall surface of the trench functions as a source region of the transistor and a diffusion region for controlling a potential of the well diffusion layer.

(Eighth configuration)
After selectively etching the first silicon oxide film on the silicon substrate and the insulating film (fourth silicon oxide film) on the trench, a second polycrystalline silicon film is formed, and the source and gate electrodes are formed. The method for manufacturing a semiconductor device according to the first configuration, wherein the drawing is performed simultaneously.

(Ninth configuration)
The semiconductor according to the first configuration, wherein the second polycrystalline silicon film is selectively etched, a part of the second polycrystalline silicon contacting the gate electrode is formed on the field oxide film, and forms a gate contact region Device manufacturing method.

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a MOS transistor having a trench structure suitable for application to a power supply device capable of flowing a large current and a manufacturing method thereof.

1 is a schematic perspective view showing a MOS transistor 1 according to the present invention. FIG. 2 is a schematic plan view of a MOS transistor 1 as viewed from the direction of arrow Z in FIG. 1. FIG. 3 is a cross-sectional view taken along the line A-A ′ of FIG. 2. FIG. 3 is a cross-sectional view taken along the line B-B ′ of FIG. 2. It is arrow sectional drawing in C-C 'of FIG. FIG. 3 is a cross-sectional view taken along the line D-D ′ in FIG. 2. (A) is an arrow sectional view in E-E 'of FIG. 2, (b) is an enlarged view of the area | region A shown to Fig.7 (a). FIG. 3 is a cross-sectional view taken along line F-F ′ in FIG. 2. (A) is sectional drawing which shows the MOS transistor 1 seen from the arrow X direction of FIG. 1, (b) is sectional drawing which shows the MOS transistor 1 seen from the arrow Y direction of FIG. (A)-(d) is a figure which shows the 1st manufacturing process of MOS transistor 1. FIG. (A)-(d) is a figure which shows the 2nd manufacturing process of MOS transistor 1. FIG. (A)-(d) is a figure which shows the 3rd manufacturing process of MOS transistor 1. FIG. (A)-(d) is a figure which shows the 4th manufacturing process of MOS transistor 1. FIG. (A)-(d) is a figure which shows the 5th manufacturing process of MOS transistor 1. FIG. (A)-(d) is a figure which shows the 6th manufacturing process of MOS transistor 1. FIG. (A)-(d) is a figure which shows the 7th manufacturing process of MOS transistor 1. FIG. (A)-(e) is a figure which shows the 8th manufacturing process of MOS transistor 1. FIG. (A)-(f) is a figure which shows the 9th manufacturing process of MOS transistor 1. FIG. (A)-(f) is a figure which shows the 10th manufacturing process of MOS transistor 1. FIG. (A)-(d) is a figure explaining the 8th manufacturing process of MOS transistor 1 in detail. (A) (b) is a figure explaining the case where it etched excessively in the 8th manufacturing process of MOS transistor 1. FIG. (A) (b) is a figure explaining the case where etching is insufficient in the 8th manufacturing process of MOS transistor 1. FIG. (A)-(h) is sectional drawing which shows the cross-section of the trench type MOSFET which is a 1st prior art example. (A)-(e) is sectional drawing which shows the cross-section of the trench type MOSFET which is a 2nd prior art example. It is sectional drawing which shows the cross-section of the trench type MOSFET which is a 3rd prior art example.

Explanation of symbols

1 MOS transistor (semiconductor device)
2 Single crystal silicon substrate (semiconductor substrate)
3 Epitaxial layer 6 Element isolation layer 7 Well diffusion layer 10 Trench (groove)
11 Gate insulating layer 12 Gate layer 13 Silicon oxide film layer (first insulating layer)
14a, 14b Source contact layer 14c Gate contact layer 15a Source diffusion layer (first conductive layer)
15b Well contact layer (second conductive layer)
16 Interlayer insulation layer (second insulation layer)
17a Source electrode (first metal layer)
17b Gate electrode (second metal layer)
19 Semiconductor layer

Claims (13)

A groove formed in a semiconductor layer formed on a semiconductor substrate;
A gate insulating layer covering an inner wall surface of the groove;
A gate layer embedded in the trench and connected to the gate electrode;
A first insulating layer formed to cover the opening of the groove;
A first conductive layer of a first conductivity type formed on both sides of the groove so as to be in contact with the groove;
A second conductive layer of a second conductivity type formed on both sides of the groove so as to be in contact with the groove;
A source contact layer formed so as to cover the groove, the first conductive layer, and the second conductive layer, and connected to a source electrode;
The semiconductor device, wherein the first conductive layer and the second conductive layer are adjacent to each other in the longitudinal direction of the groove.   It further comprises a gate contact layer that is in contact with the gate layer and formed on the semiconductor layer via an element isolation layer, and the gate layer is connected to the gate electrode via the gate contact layer. The semiconductor device according to claim 1.   The semiconductor device according to claim 1, wherein at least a part of a side wall of the groove is in contact with the element isolation layer.   3. The semiconductor device according to claim 1, wherein the semiconductor substrate is made of single crystal silicon containing an N-type or P-type impurity.   The semiconductor device according to claim 4, wherein the semiconductor layer has an epitaxial layer on the semiconductor substrate, and a conductivity type of the epitaxial layer is N-type or P-type.   The semiconductor device according to claim 1, wherein the first conductive layer includes an N-type or P-type impurity as a first conductivity type.   The semiconductor device according to claim 1, wherein the second conductive layer contains an N-type or P-type impurity different from the first conductivity type.   3. The semiconductor device according to claim 1, wherein the gate layer is made of polycrystalline silicon containing an N-type or P-type impurity.   9. The semiconductor device according to claim 8, wherein the gate contact layer is made of polycrystalline silicon containing impurities of the same type as the gate layer. A second insulating layer formed on the source contact layer and the gate contact layer;
A first metal layer connected to a source contact layer in a first contact region formed in the second insulating layer;
3. The semiconductor device according to claim 1, further comprising: a second metal layer connected to the gate contact layer in the second contact region formed in the second insulating layer. Forming a groove in a semiconductor layer formed on the semiconductor substrate;
Coating the inner wall surface of the groove with a gate insulating layer;
Embedding a gate layer connected to a gate electrode in the trench;
Forming a first insulating layer so as to cover the opening of the groove;
Forming a source contact layer on the semiconductor layer so as to cover the groove;
Forming a first conductive type first conductive layer and a second conductive type second conductive layer on the semiconductor layer covered with the source contact layer so as to be in contact with both sides of the groove. And
In the step of forming the first conductive layer and the second conductive layer, the first conductive layer and the second conductive layer are formed so as to be adjacent to each other in the longitudinal direction of the groove. A method for manufacturing a semiconductor device. Etching the first insulating layer formed in the opening of the trench to expose a portion of the gate layer;
12. The method of manufacturing a semiconductor device according to claim 11, further comprising a step of forming a gate contact layer on the exposed gate layer and an element isolation layer formed on the semiconductor layer. The step of forming the source contact layer and the gate contact layer includes:
13. The semiconductor according to claim 12, wherein a polycrystalline silicon layer is formed on the semiconductor layer, and the source contact layer and the gate contact layer are simultaneously formed by selectively etching the polycrystalline silicon layer. Device manufacturing method.

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