JP2008034025A - Disk signal analyzing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve a disk signal analyzing device in which optimum adaptive equalization can be performed even when quality and properties are different for each disk and in area on disks, and even when formats of disks are different. <P>SOLUTION: The disk signal analyzing device has the adaptive equalization processing function for PRML signal processing for the disk signal, and is provided with a learning function of tap coefficient control in the adaptive equalization processing. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a disk signal analyzing apparatus, and more particularly, recorded with at least two values including a high-density optical disk signal including a PRML (Partial Response Maximum Likelihood) signal processing function such as a DVD or a next-generation recording medium. The present invention relates to a disk signal analyzing apparatus used for analyzing and evaluating a disk signal.

  PRML signal processing is one of the reproduction signal processing methods for increasing the density, and is based on the PR method in which the waveform is adjusted by a method that intentionally provides inter-code interference, and the data sequence recorded with correlation between the data. This is a data channel technology that employs the ML method for detecting the most probable data string.

In a magnetic disk or optical disk, it is difficult to determine whether data or noise is detected only by a signal detected by an MR head or an optical pickup. Therefore, PRML signal processing is used to accurately make this determination. That is, the recorded code is always affected by the previously written code. Therefore, in the PRML signal processing, this intersymbol interference is used to obtain the most accurate code when there is a correlation between a waveform equalization method (PR method) that corrects reproduction distortion when reproducing data and the reproduced data. A detection method (ML method) is used in combination. Not only magnetic disk devices but also optical disk devices and video recording VTRs are attracting attention.
JP 2003-203429 A

  FIG. 6 is a block diagram showing an example of a PRML signal processing circuit 100 in a conventional disk signal analyzing apparatus, which has the same configuration as the PRML signal processing circuit of a high-density optical disk drive. A circuit and function blocks for analyzing the reproduction signal are connected to the subsequent stage of the circuit, but not shown.

  In the PRML signal processing circuit 100, the analog input circuit 1 performs amplification and impedance conversion of an input RF signal, and an amplifier that amplifies the signal, an AGC (AutoGain Control) that averages the gain, and an unnecessary offset of the RF signal. An offset cancel circuit to be removed is provided.

The output signal of the analog input circuit 1 is input to the A / D converter 2 and converted into a digital signal.
The output signal of the A / D converter 2 is input to the equalization circuit 3, and the characteristic of the quantized RF signal converted and output from the A / D converter 2 is provided in the preceding stage of the PRML signal processing circuit 100. Equalization processing is performed so as to approximate the target PR characteristic that matches the transfer function of the optical characteristic.
The memory 4 holds reference level data for calculating the equalization error of the equalization signal output from the equalization circuit 3.

The Viterbi decoding circuit 5 decodes the binary signal from the equalized signal using the Viterbi algorithm based on the reference level data held in the memory 4.
The target signal generation circuit 6 generates and sends an ideal target level from the binary signal decoded by the Viterbi decoding circuit 5, and is composed of an FIR filter or the like.

  The tap coefficient control circuit 7 optimizes the filter tap coefficient of the equalization circuit 3 so as to minimize the equalization error. The quantized RF signal output from the A / D converter 2 and the target signal generation circuit The target level signal output from 6 and the equalization signal output from the equalization circuit 3 are input.

FIG. 7 is a block diagram illustrating an internal configuration example of the equalization circuit 3 in FIG. 6, which is configured as a digital transversal filter 300. Specifically, a digital transversal filter 300, a delay circuit _D 0 _{~D N-1} 301 which delays the input signal _{x k} successive number of taps of the filter, the input signal _{x k ~x k-N-1} filter The circuit includes a multiplier circuit 302 that multiplies tap coefficients C _{0 to} C _N−1 and an adder circuit that outputs the sum of the multiplier circuits 302 as an equalized signal y _k .

FIG. 8 is a functional block diagram including an adaptive equalization filter composed of the equalization circuit 3 and the tap coefficient control circuit 7 and an arithmetic unit based on the LMS algorithm used for tap coefficient control. In FIG. 8, x _k is an input signal, C _k is a tap coefficient of an adaptive equalization filter, y _k is an equalization signal, d _k is a training signal that is an ideal equalization signal, and e _k is an equalization signal y _k . It is an error signal of the training signal. LMS (LeastMeanSquare) calculation unit, such that the error signal _{e k} is minimized, to optimize the tap coefficients of the filter using the algorithm follows.
C _{n + 1} = C _n + μ * x _n * e _n (1)
μ is a step size, and is a parameter for controlling the correction amount of one tap coefficient.

FIG. 9 is a flowchart showing the operation of the PRML signal processing circuit 100 of FIG.
(A) An RF signal detected by an optical pickup or the like is input to the PRML signal processing circuit 100, and desired signal conversion is performed by the analog input circuit 1.
(B) The analog output signal output from the analog input circuit 1 is quantized into a digital signal by the A / D converter 2. The sampling clock of the A / D converter 2 is regenerated and given by a subsequent PLL circuit (not shown).
(C) The equalization circuit 3 equalizes the quantized RF signal by a convolution operation. At this time, the tap number N and the tap coefficients C _{0 to} C _N−1 of the equalization circuit 3 are given initial values that can be approximated to a target PR response waveform that matches the optical transfer function of the optical pickup.
(D) The Viterbi decoding circuit 5 calculates an equalization error from the equalized signal output from the equalization circuit 3 and the ideal level stored in the reference level memory 4, and converts it into a binary signal using a known Viterbi algorithm. Decrypt. For example, when PR (1221) is an ideal response waveform, seven levels of ideal levels are stored in the reference level memory 4.
(E) The target waveform generation circuit 6 outputs a target level signal from the binary signal decoded by the Viterbi decoding circuit 5. For example, when PR (1221) is an ideal response waveform, it passes through an FIR filter having tap coefficients with a ratio of approximately 1: 2: 2: 1 to generate a target level signal.
(F) The tap coefficient generation circuit is based on the quantized RF signal output from the A / D converter 2, the equalization signal output from the equalization circuit 3, and the target level signal output from the target waveform generation circuit. The tap coefficient is corrected to an optimum value by using the LMS algorithm of equation (1). Each circuit connected to the subsequent stage of the A / D converter 2 operates at a clock timing synchronized with the A / D sampling. However, the equalized signal and the quantized RF signal input to the tap coefficient control circuit 7 are A delay circuit (flip-flop) for matching the data timing is appropriately arranged.
(G) Steps (A) to (F) are sequentially performed at the timing of the sampling clock until a series of sampling processes is completed, and the tap coefficient of the equalization circuit 3 converges to an optimum value that minimizes the equalization error. To be controlled.

However, according to such a conventional configuration, when the quality and characteristics are different for each disk or disk area due to waveform distortion, optical characteristics, etc., a difference occurs in the convergence time from the initial value of the tap coefficient, Depending on the input signal, it may diverge or the optimum analysis may not be performed.
In addition, when there is a difference in the format of the disk, such as the size of the header area and data area on the disk, an optimal convergence value cannot be obtained unless an adaptive equalization is attempted using an appropriate tap coefficient. A correct quality evaluation cannot be performed.

  An object of the present invention is to realize a disk signal analyzing apparatus that can perform optimum adaptive equalization even when the quality and characteristics differ from disk to disk or in the area on the disk or even when the disk format is different.

  The invention according to claim 1, which solves the above problem, is a disk signal analyzing apparatus having an adaptive equalization processing function for PRML signal processing on a disk signal, and a learning function of tap coefficient control in the adaptive equalization processing Is provided.

  The invention according to claim 2 is an analog input circuit for performing desired signal conversion on an input RF signal, an A / D converter for quantizing an analog RF signal output from the analog input circuit, and an A / D converter An equalization circuit for approximating the RF signal quantized with the target PR response waveform, a Viterbi decoding circuit for decoding a binary signal from the equalized signal output from the equalization circuit by a Viterbi algorithm, and the Viterbi decoding A target waveform generation circuit that generates and outputs a target level signal from a binary signal output by the circuit; and a tap coefficient of the equalization circuit so that an equalization error between the equalization signal and the target level signal is minimized. A tap coefficient control circuit to be optimized, a tap coefficient memory for holding optimized tap coefficient data, and a control mode memory for designating a control mode of the tap coefficient control circuit. The tap coefficient control circuit has an adaptive equalization processing function for PRML signal processing for a disk signal characterized by accessing the tap coefficient memory based on an externally input equalization control signal and the state of the control mode memory. It is a disk signal analyzing apparatus having.

  According to a third aspect of the present invention, when the equalization control signal input from the outside is disabled, the tap coefficient control circuit stops updating the tap coefficient to the equalization circuit, and when enabled, the tap coefficient control circuit 3. The disk signal analyzing apparatus according to claim 2, wherein the updating is resumed.

  According to a fourth aspect of the present invention, the control mode memory has a control mode of at least one of a learning mode, a reproduction mode, a reproduction learning mode, and an OFF mode, and the tap coefficient control circuit has a control mode in a learning mode. Is stored in the tap coefficient memory based on the edge signal of the equalization control signal, and in the reproduction mode, the optimal tap coefficient stored in the tap coefficient memory is stored based on the edge signal of the equalization control signal. When set to read equalization circuit and in learning playback mode, the optimum tap coefficient stored in the tap coefficient memory is read based on the edge signal of the equalization control signal, and the new optimum tap coefficient is tap coefficient with the next edge signal. 4. The data storage device according to claim 2, wherein the tap coefficient memory is not accessed in the OFF mode. Disk is a signal analyzer.

According to the disk signal analyzing apparatus of the present invention, the optimum tap coefficient is learned based on the control mode, the tap coefficient memory, and the external equalization control signal, and can be used at the time of reproduction. Even when signals with different qualities are evaluated in this area, a highly reliable quality evaluation becomes possible.
In addition, since it has functions for performing equalization stop, equalization learning, and reproduction signal evaluation based on the level and edge of the equalization control signal, analysis and circuit evaluation independent of the disk format are possible.

Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a block diagram showing an embodiment of a PRML signal processing circuit 500 in the disk signal analyzing apparatus according to the present invention, and is a part common to the conventional example of FIG. 6 constituted by an analog input circuit 1 to a tap coefficient control circuit 7. Are given the same reference numerals. 1 and FIG. 6 is a connection relationship among the tap coefficient control circuit 7, the control mode memory 8, and the tap coefficient memory 9.

  Note that the equalization circuit 3 includes a transversal filter 300 as shown in FIG. The equalization circuit 3 and the tap coefficient control circuit 7 for realizing adaptive equalization are realized by functional blocks using the LMS algorithm as shown in FIG. In addition, since all the circuits of the disk signal analyzing apparatus according to the present invention operate at the timing of the clock signal synchronized with the sampling of the A / D converter 2, a delay circuit for data timing synchronization is appropriately used. The illustration and description of are omitted.

  In FIG. 1, the tap coefficient control circuit 7 includes a quantized RF signal output from the A / D converter 2, a target level signal output from the target signal generation circuit 6, and the equalization circuit 3 as in FIG. In addition to the equalization signal output from the input, the equalization control signal for determining whether to perform equalization processing and the data for determining the tap coefficient control method stored in the control mode memory 8 A plurality of tap coefficient initial value data stored in the tap coefficient memory 9 is input. The tap coefficient control circuit 7 calculates and outputs optimum filter tap coefficient data for controlling the filter tap coefficient of the equalization circuit 3 to an optimum value based on these input data.

  The tap coefficient control circuit 7 uses a tap coefficient control mode in which the data stored in the tap coefficient memory 9 is not used. There are four modes: a learning mode to be stored in the coefficient memory 9, a reproduction mode in which the learned equalization interval optimum tap coefficients are read from the tap coefficient memory 9 and set in the equalization circuit 3, and a reproduction learning mode in which both learning and reproduction are performed. is there.

  The equalization control signal stops equalization processing and a series of PRML signal processing when it is at a high level, and resumes processing when it is at a low level. The tap coefficient control circuit 7 does not update the tap coefficient at the high level. Generally, it is used as a mask signal in the case of reading the address portion of the disk, reading the VFO section for pulling in the PLL, or jumping the track of the disk.

  2 to 4 are timing charts showing the operation of the disk signal analyzing apparatus in each of these control modes, and also show the states of the equalization control signal, the control mode memory 8 and the tap coefficient memory 9. FIG. 5 is a flowchart showing the operation in each control mode of the disk signal analyzing apparatus according to the present invention. (A) is when the control mode is OFF, (B) is when the control mode is the learning mode, and (C) is This is a case where the control mode is the reproduction learning mode. The equalization learning / reproducing operation is analyzed for circuit design so that the same area of the disk can be reproduced with high quality. The starting position of the disc evaluation area at the time of learning and playback is synchronized with an external trigger signal, but the description thereof is omitted.

1) OFF mode (timing chart FIG. 2, flowchart FIG. 5 (A))
(A) C [0] is set as an initial value of the tap coefficient for the equalization circuit 3.
(B) “OFF mode” is stored in the control mode memory 8.
(C to g) The tap coefficient control circuit 7 performs conventional A / D conversion and adaptive equalization processing with the tap coefficient C [0] as an initial value by detecting the falling edge of the control signal, and the control signal is During the low level, the tap coefficient of the equalization circuit 3 is sequentially updated.

(G, c) Subsequently, when detecting the rising edge of the control signal, the tap coefficient control circuit 7 holds the optimum tap coefficient C [1] at that time until the falling edge of the control signal is detected again. During this time, the tap coefficient is not updated. When the falling edge of the control signal is detected, the adaptive equalization process is repeated with the tap coefficient C [1] as an initial value in the same flow as the above steps c to g. No updating / reading is performed on the tap coefficient memory 9.

2) Learning mode (timing chart FIG. 3, flowchart FIG. 5 (b))
(A ′) C [0] is set as an initial value of the tap coefficient for the equalization circuit 3.
(B ′) “Learning mode” is stored in the control mode memory 8.
(C ′ to g ′) The tap coefficient control circuit 7 performs conventional A / D conversion and adaptive equalization processing with the tap coefficient C [0] as an initial value by detecting the falling edge of the control signal, and performs control. While the signal is at a low level, the tap coefficient of the equalization circuit 3 is sequentially updated to perform equalization learning.

(G ′ to h ′, c ′) Subsequently, when detecting the rising edge of the control signal, the tap coefficient control circuit 7 stores the final optimum tap coefficient C [1] in the tap coefficient memory 9. Until the falling edge of the control signal is detected again, the current optimum tap coefficient C [1] is held. During this time, the tap coefficient is not updated. When the falling edge of the control signal is detected, the equalization learning process is repeated with the tap coefficient C [1] as an initial value in the same flow as the above steps c ′ to g ′, and the optimum tap coefficient C [2] is stored in the tap coefficient memory 9. ], C [3], C [4] are sequentially stored.

3) Reproduction learning mode (timing chart FIG. 4, flowchart FIG. 5 (c))
(A ″) C [0] is set as an initial value of the tap coefficient for the equalizing circuit 3.
(B ″) “Reproduction learning mode” is stored in the control mode memory 8.
(C ″ to h ″) The tap coefficient control circuit 7 reads the tap coefficient C [1] from the tap coefficient memory 9 by detecting the falling edge of the control signal, and performs the conventional A / D conversion as an initial value. An adaptive equalization process is performed, and while the control signal is at a low level, the tap coefficients are sequentially updated and the equalization process is performed.

(H ″ to i ″, c ″) Subsequently, the tap coefficient control circuit 7 stores the final optimum tap coefficient C ′ [1] in the tap coefficient memory 9 by detecting the rising edge of the control signal. . Until the falling edge of the control signal is detected again, the current optimum tap coefficient C ′ [1] is held. During this time, the tap coefficient is not updated. When the falling edge of the control signal is detected, the tap coefficient control circuit 7 reads the tap coefficient C [2] optimum for the corresponding area from the tap coefficient memory 9, and the same flow as the above steps c ″ to h ″ as an initial value. Then, the equalization learning process is repeated, and the optimum tap coefficients C ′ [2], C ′ [3], C ′ [4] are sequentially stored in the tap coefficient memory 9.

  In the above embodiment, the control mode memory is provided. However, this state may be given by an external signal.

  In the above-described embodiment, the learning function is based on the premise that the same area of the disc is evaluated during learning and playback, but the corresponding optimum tap coefficient is searched from the tap coefficient memory based on the address information of the header portion. It may be shaped.

  In addition, since adaptive equalization technology is also used in communication fields other than optical disks, it can also be used for quality evaluation of communication channels.

  As described above, as an adaptive equalization function for PRML signal processing in the disc signal analysis apparatus, the tap coefficient control mode is equipped with the OFF mode, the learning mode, the playback mode, and the playback learning mode, thereby improving the quality characteristics of the disc. The corresponding optimum tap coefficient can be learned in advance, and the tap coefficient can be used at the time of reproduction evaluation.

  As a result, even when signals having different qualities are evaluated for each disk or in an area on the disk as described above, highly reliable quality evaluation can be performed.

  Furthermore, since it has functions for performing equalization stop, equalization learning, and reproduction signal evaluation based on the level and edge of the equalization control signal, analysis and circuit evaluation independent of the disk format become possible.

It is a block diagram which shows the Example of the PRML signal processing circuit in the disc signal analysis apparatus of this invention. It is a timing chart showing operation of a disk signal analysis device. It is a timing chart showing operation of a disk signal analysis device. It is a timing chart showing operation of a disk signal analysis device. It is a flowchart showing the operation | movement in each control mode of the disc signal analysis apparatus based on this invention. It is a block diagram which shows an example of the PRML signal processing circuit in the conventional disc signal analysis apparatus. It is a block diagram which shows the internal structural example of the equalization circuit 3 in FIG. It is a functional block diagram including the calculating part based on the LMS algorithm used for an adaptive equalization filter and tap coefficient control. 7 is a flowchart showing the operation of the PRML signal processing circuit 100 of FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Analog input circuit 2 A / D converter 3 Equalization circuit 4 Memory 5 Viterbi decoding circuit 6 Target signal generation circuit 7 Tap coefficient control circuit 8 Control mode memory 9 Tap coefficient memory 500 PRML signal processing circuit

Claims (4)

A disc signal analyzing apparatus having an adaptive equalization processing function for PRML signal processing on a disc signal,
A disc signal analyzing apparatus provided with a learning function of tap coefficient control in the adaptive equalization processing. An analog input circuit for performing desired signal conversion on the input RF signal;
An A / D converter that quantizes an analog RF signal output from the analog input circuit;
An equalizer circuit for approximating the RF signal quantized by the A / D converter to a target PR response waveform;
A Viterbi decoding circuit for decoding a binary signal from the equalized signal output from the equalization circuit by a Viterbi algorithm;
A target waveform generation circuit that generates and outputs a target level signal from the binary signal output by the Viterbi decoding circuit;
A tap coefficient control circuit that optimizes a tap coefficient of the equalization circuit so that an equalization error between the equalization signal and the target level signal is minimized;
A tap coefficient memory for holding optimized tap coefficient data;
A control mode memory for designating a control mode of the tap coefficient control circuit,
The tap coefficient control circuit accesses the tap coefficient memory based on an equalization control signal input from the outside and the state of the control mode memory, and an adaptive equalization processing function for PRML signal processing for a disk signal A disk signal analyzing apparatus.   The tap coefficient control circuit stops updating tap coefficients when the equalization control signal input from the outside is disabled, and restarts updating tap coefficients when enabled. The disk signal analyzing apparatus according to claim 2. The control mode memory has at least one of a learning mode, a reproduction mode, a reproduction learning mode, and an OFF mode,
The tap coefficient control circuit stores the optimum tap coefficient in the tap coefficient memory based on the edge signal of the equalization control signal when the control mode is the learning mode, and the edge signal of the equalization control signal when in the reproduction mode. The optimal tap coefficient stored in the tap coefficient memory is read and set in the equalization circuit, and in the learning reproduction mode, the optimum tap coefficient stored in the tap coefficient memory is read based on the edge signal of the equalization control signal and the next 4. The disk signal analyzing apparatus according to claim 2, wherein a new optimum tap coefficient is stored in the tap coefficient memory using the edge signal of the first and second tap signals, and the tap coefficient memory is not accessed in the OFF mode.

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