JP2008028176A - Inspection apparatus and method for solid-state imaging element wafer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an inspection apparatus and a method for solid-state imaging element wafers capable of specifying positions of defective pixels on a wafer in the case of inspecting the defective pixels. <P>SOLUTION: An inspection/analysis apparatus 30 for inspecting defective pixels on the wafer comprises a prober 32, a light source 34, and a tester 36. The tester 36 controls the prober 32 and the light source 34 to execute defective pixel inspection of each solid-state imaging element on the wafer. The tester 36 specifies an element matrix coordinate of a defect detected element whose defective pixels are detected on the wafer and a pixel matrix coordinate of each defective pixel on the defect detected element. The tester 36 uses a conversion formula generated on the basis of wafer design information to convert both the coordinates into pixel position coordinates of the defective pixels on the wafer. The tester 36 displays a wafer top view on a monitor 58, and displays marks representing the defective pixels on the wafer top view. Thus, the positions of the defective pixels on the wafer can be specified. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device wafer inspection apparatus and method for detecting defective pixels of each solid-state imaging device of a solid-state imaging device wafer.

  Digital cameras using a solid-state imaging device such as a CCD image sensor are widely used (see Patent Document 1). In recent years, the number of pixels of a solid-state imaging device used in a digital camera in particular has been increasing due to the demand for further fine image quality and the development of semiconductor microfabrication technology. As the number of pixels increases in this manner, it is becoming difficult to manufacture a solid-state imaging device in which defective pixels due to minute dust and crystal defects are not completely present (see Patent Documents 2 and 3).

For this reason, a solid-state imaging device manufacturer usually performs defective pixel inspection of individual solid-state imaging devices in a wafer state after the solid-state imaging devices are formed in a substantially matrix shape on a silicon wafer. Then, the number of defective pixels of each solid-state imaging device is counted, and those having the number of defective pixels within the allowable range are shipped as non-defective products after being separated into pieces by dicing.
JP 2005-286887 A JP 2002-84463 A JP 2005-117359 A

  By the way, in the past, at the time of defective pixel inspection, the number of defective pixels of each solid-state image sensor is counted, and a wafer map in which the PASS / FAIL of each solid-state image sensor is mapped is created. The manufacturing defect was analyzed. For this reason, even if defective pixel inspection is performed, the position of each defective pixel on the solid-state image sensor wafer is not specified, and information such as the position where the defective pixel is generated and the distribution of the defective pixels is not obtained. It was not used to analyze manufacturing defects.

  The present invention has been made to solve the above-described problems, and an object thereof is to provide a solid-state imaging device wafer inspection apparatus and method capable of specifying the position of a defective pixel on a wafer during defective pixel inspection. .

  The inspection apparatus for a solid-state image sensor wafer according to the present invention inspects each of the solid-state image sensors of a solid-state image sensor wafer in which a plurality of solid-state image sensors are formed in a matrix and is arranged in a matrix on the solid-state image sensor. On the solid-state imaging device wafer, a defective pixel detecting means for detecting a defective pixel from a plurality of pixels and the solid-state imaging device in which the defective pixel is detected based on the detection result of the defective pixel as a defect detection imaging device Coordinate specifying means for specifying element matrix coordinates representing matrix coordinates of the defect detection image sensor and pixel matrix coordinates representing matrix coordinates of the defective pixel on the defect detection image sensor, and the solid image sensor wafer on the solid-state image sensor wafer In order to identify the position of a defective pixel, the element matrix coordinates and the pixel matrix coordinates are coordinates created based on design information of the solid-state image sensor wafer. Using interchangeable, characterized in that it comprises a coordinate conversion means for converting the pixel coordinates of the defective pixel in the solid-state imaging device on the wafer.

  Display means for displaying a wafer plan view of the solid-state image sensor wafer as viewed from the formation surface side of the solid-state image sensor, and a mark representing the defective pixel at a position corresponding to the pixel position coordinates on the wafer plan view It is preferable to provide display control means for displaying.

  There are a plurality of types of defects of the defective pixels, and the display control unit preferably changes at least one of the color or shape of the mark displayed on the wafer plan view according to the type of the defect.

  When there are a plurality of defect types of the defective pixel, and the display control means designates the type of defect to be displayed, only the mark corresponding to the designated defect type is displayed on the wafer plan view. It is preferable to display.

  In the solid-state imaging device inspection method of the present invention, the individual solid-state imaging devices of a solid-state imaging device wafer in which a plurality of solid-state imaging devices are formed in a matrix are inspected and arranged in a matrix on the solid-state imaging device. A defective pixel detection step of detecting a defective pixel from a plurality of pixels, and the solid-state imaging device wafer, wherein the solid-state imaging device in which the defective pixel is detected is used as a defect detection imaging device based on the detection result of the defective pixel A coordinate specifying step for specifying an element matrix coordinate representing a matrix coordinate of the defect detection image sensor on the upper side, and a pixel matrix coordinate representing a matrix coordinate of the defective pixel on the defect detection image sensor; and on the solid-state image sensor wafer. In order to identify the position of the defective pixel, the element matrix coordinates and the pixel matrix coordinates are created based on design information of the solid-state imaging element wafer. By using the coordinate conversion formula, characterized in that it comprises a coordinate conversion step of converting the pixel coordinates of the defective pixel in the solid-state imaging device on the wafer.

  The solid-state image sensor wafer inspection apparatus according to the present invention includes a defective pixel detection unit that detects defective pixels of individual solid-state image sensors of the solid-state image sensor wafer, element matrix coordinates of the defect detection image sensor on the solid-state image sensor wafer, And coordinate specifying means for specifying a pixel matrix coordinate of the defective pixel on the defect detection imaging device, and a coordinate conversion formula created based on design information of the solid-state imaging device wafer for the element matrix coordinate and the pixel matrix coordinate And a coordinate conversion means for converting the pixel position coordinates of the defective pixel on the solid-state image pickup device wafer, so that the position of the defective pixel on the solid-state image pickup device wafer can be easily identified at the time of defective pixel inspection. can do. As a result, information such as the occurrence position of the defective pixel can be used for analysis of a manufacturing defect of the solid-state imaging device wafer, so that the cause of the manufacturing defect of the solid-state imaging device wafer can be easily identified.

  The solid-state image sensor wafer inspection method of the present invention includes a defective pixel detection step for detecting a defective pixel of each solid-state image sensor of the solid-state image sensor wafer, and element matrix coordinates of the defect detection image sensor on the solid-state image sensor wafer, And a coordinate specifying step for specifying a pixel matrix coordinate of the defective pixel on the defect detection imaging device, and a coordinate conversion formula created based on design information of the solid-state imaging device wafer for the element matrix coordinate and the pixel matrix coordinate And a coordinate conversion step for converting the pixel position coordinates of the defective pixel on the solid-state image sensor wafer, so that the position of the defective pixel on the solid-state image sensor wafer can be easily determined in the same manner at the time of the defective pixel inspection. Can be identified.

  A solid-state imaging device wafer (hereinafter simply referred to as a wafer) 10 as shown in FIG. 1 is formed by forming a plurality of solid-state imaging devices 12 in a matrix (substantially two-dimensional matrix) on a silicon wafer. The diameter, thickness, material, and the like of the wafer 10 are determined according to, for example, the type of device formed on the wafer 10.

  As shown in FIG. 2, the solid-state imaging device 12 is an interline transfer type CCD image sensor, and is provided for each of the light receiving elements 14 arranged in a matrix (two-dimensional matrix) and each vertical column of the light receiving elements 14. A vertical CCD (VCCD) 16, a read transfer gate (TG) 18 provided between the light receiving element 14 and the VCCD 16, a horizontal CCD (HCCD) 20 commonly connected to the last stage of each VCCD 16, An output gate (OG) 22 and a floating diffusion (FD) 24 provided adjacent to the final stage of the HCCD 20 and a source follower type amplifier circuit 26 connected to the FD 24 are configured. Reference numeral 28 in the figure denotes a plurality of electrode pads (input / output pads) that serve as input / output terminals for signals and power.

  The light receiving element 14 photoelectrically converts incident light, and generates and accumulates signal charges corresponding to the amount of incident light. The TG 18 transfers the signal charge accumulated in the light receiving element 14 to the VCCD 16. The VCCD 16 receives the signal charge transferred from the light receiving element 14 and performs vertical transfer one line at a time toward the HCCD 20. The HCCD 20 receives the signal charges output from the last stage of the VCCD 16 one by one, and sequentially performs horizontal transfer toward the OG 22 each time one line (one horizontal line) of signal charges is received. The OG 22 transfers the signal charges sent from the HCCD 20 to the FD 24 in order for each pixel. The FD 24 converts the signal charge transferred from the OG 22 into a voltage signal. The amplifier circuit 26 amplifies the voltage signal generated by the FD 24 and outputs it as the imaging signal Vout.

  Each solid-state image sensor 12 is singulated into individual solid-state image sensors 12 by dicing after being inspected by an inspection apparatus 30 described later in a wafer state. As shown in FIG. 3, the inspection apparatus 30 is an embodiment of the present invention, and includes a prober 32, a light source 34, and a tester 36. The inspection device 30 performs predetermined electrical inspection including inspection of defective pixels 37 on each solid-state imaging device 12.

  The prober 32 includes a wafer table 40 that holds the wafer 10 and a probe card (connection portion) 42 that is provided to face the wafer table 40 so as to sandwich the wafer 10. The probe card 42 is provided with a plurality of probe pins 44 corresponding to each electrode pad 28 (see FIG. 2) included in one solid-state imaging device 12. The probe card 42 obtains electrical continuity with the solid-state imaging device 12 by bringing the probe pins 44 into contact with the electrode pads 28.

  The probe card 42 is electrically connected to the tester 36 and supplies power, control signals, and the like from the tester 36 to the solid-state image sensor 12 via the probe pins 44, and from the solid-state image sensor 12. An output signal is sent to the tester 36.

  A movement mechanism 46 and an elevating mechanism 48 are connected to the wafer table 40. The moving mechanism 46 horizontally moves the wafer table 40 in two directions, a right and left direction in the figure and a direction perpendicular to the paper surface. Further, the moving mechanism 46 is electrically connected to the tester 36. The tester 36 transmits a drive signal to the moving mechanism 46 to move the wafer table 40 horizontally, thereby aligning the desired solid-state imaging device 12 and the probe card 42 in the wafer 10.

  On the other hand, the elevating mechanism 48 moves the wafer table 40 up and down in the vertical direction in the figure. Similarly, the elevating mechanism 48 is connected to the tester 36, and an inspection position where each electrode pad 28 of the solid-state imaging device 12 and each probe pin 44 come into contact with each other according to a drive signal from the tester 36, and each electrode pad 28. The wafer table 40 is moved between the retracted position where the contact with each probe pin 44 is released. The tester 36 moves the wafer table 40 to the retracted position, for example, when the wafer 10 is set on the wafer table 40 or when the movement mechanism 46 is driven to adjust the position of the wafer 10. 10 is prevented from being damaged.

  The light source 34 is disposed at a position above the probe card 42, that is, at a position facing the solid-state imaging device 12 to be inspected. In addition, an opening is formed in the center of the probe card 42, and a predetermined amount of parallel light is irradiated from the light source 34 to the solid-state imaging device 12 to be inspected. The tester 36 controls the turning on / off of the light source 34 and the amount of parallel light to be irradiated.

  When the test start instruction is given, the tester 36 drives the moving mechanism 46 and the lifting mechanism 48 to align the positions of the solid-state imaging device 12 and the probe card 42, and then turns on the light source 34 to emit the illumination light L to the solid state. A predetermined electrical inspection including an inspection of the defective pixel 37 is performed by entering the imaging element and measuring an output signal from the solid-state imaging element 12. The electrical inspection items other than the defective pixel 37 include, for example, shading characteristics that cause a difference in output signal level between the central portion and the peripheral portion of the solid-state imaging device 12.

  The defective pixel 37 is a pixel that does not output an imaging signal (electric signal) at a predetermined level with respect to the incident light amount. As the defective pixel 37, white scratches (white dots) that output an imaging signal larger than a predetermined standard value with respect to the incident light amount, and black that output an imaging signal smaller than the predetermined standard value with respect to the incident light amount. Scratches (spots) are well known. That is, the white defect has a significantly brighter brightness than a normal pixel, and the black defect has a significantly darker brightness than a normal pixel. Such a defective pixel can be detected based on whether or not there is a pixel whose magnitude of the imaging signal deviates from a predetermined standard value on the tester 36 after reading the imaging signal for all pixels from the solid-state imaging device. it can.

  As shown in FIG. 4, the tester 36 includes a main controller 50, a power supply control unit 51, a defective pixel detection unit 52, a coordinate specifying unit 54, a coordinate conversion unit 56, a monitor 58, a display control unit 60, and a wafer plan view database storage unit. 62 (hereinafter simply referred to as a DB storage unit) is provided. The main controller 50 controls the prober 32, the light source 34 and the like in addition to the respective parts of the tester 36 according to a control program stored in a ROM (not shown). The power supply control unit 51 controls power supply to the prober 32.

  The defective pixel detection unit 52 constitutes the defective pixel detection means of the present invention together with the prober 32, the light source 34, and the power supply control unit 51. The defective pixel detection unit 52 has a predetermined upper limit standard value Vthu to a lower limit standard value Vthl among the imaging signals Vout of all the pixels of the solid-state imaging device 12 read out via the prober 32 during the defective pixel inspection. A defective pixel is detected by detecting an object outside the range. The defective pixel detection unit 52 determines the type of defect when detecting the defective pixel 37. For example, as described above, the defective pixel detection unit 52 determines a pixel that satisfies Vout> Vthu as a white defect, and determines a pixel that satisfies Vout <Vthl as a black defect.

  The coordinate specifying unit 54 corresponds to the coordinate specifying means of the present invention. The coordinate specifying unit 54 is based on the detection result of the defective pixel 37 in the defective pixel detection unit 52, and the matrix coordinates on the wafer 10 of the solid-state image sensor 12 (hereinafter referred to as the defect detection image sensor 12a) in which the defective pixel is detected. P1 (X1, Y1) (hereinafter simply referred to as element matrix coordinates) is specified, and matrix coordinates (hereinafter simply referred to as pixel matrix coordinates) P2 (X2) of all detected defective pixels 37 on the defect detection imaging element 12a. , Y2).

  As shown in FIG. 5, the element matrix coordinates P1 (X1, Y1) are among the matrix coordinates (1, 2) to (5, 6) of the solid-state imaging elements 12 formed in a matrix on the wafer 10. Identified from At the time of electrical characteristic inspection (defective pixel inspection), the inspection order of the solid-state imaging device 12 is determined in advance. For example, if the solid-state imaging device 12 is inspected in the order of matrix coordinates (2, 1) to (5, 1), the matrix coordinates (1, 2) to (6, 2), (1, 3). The solid-state image sensor is inspected in order. Therefore, since it can be determined from which solid-state imaging device 12 the defective pixel 37 is detected based on the inspection order of the solid-state imaging device 12, the coordinate specifying unit 54 includes the element matrix coordinates P1 (X1, X1) of the defect detection imaging device 12a. Y1) can be specified.

  As shown in FIG. 6, the pixel matrix coordinates P1 (X2, Y2) are the matrix coordinates (1, 1) to (n, m) of the pixels (each light receiving element 14) formed in a matrix on the wafer 10. Identified from Similar to the above-described specification of the element matrix coordinates P1, the coordinate specifying unit 54 determines the pixel matrix coordinates P2 of the defective pixel 37 based on information indicating which pixel the defective pixel 37 detected by the defective pixel detection unit 52 is. (X2, Y2) can be specified.

  When the electrical property inspection (defective pixel inspection) of the all-solid-state image pickup device 12 on the wafer 10 is completed, the element matrix coordinates P1 (X1, Y1) of all the defect detection image pickup devices 12a in the wafer 10 and the respective defect detection image pickup devices 12a. The pixel matrix coordinates P2 (X2, Y2) of all the defective pixels are specified. In the same manner, the wafers 10 are sequentially set on the tester 36 and the electrical characteristic inspection is performed, and the matrix coordinates P1 and P2 are specified. Table 1 below summarizes the coordinate identification results of each wafer 10.

  In the “wafer number column” of Table 1 above, the wafer numbers assigned to the wafers 10 are entered in the order in which they are inspected. In the present embodiment, in order to prevent complication of Table 1, only the detection result of the wafer 10 with the wafer number “N” is shown. In the “element number” column, element numbers assigned to the defect detection imaging elements 12a are entered in the order in which the inspections are performed.

  In the “defect number” column, the defect numbers assigned to the defective pixels 37 are assigned in the order detected in the inspection. In other words, j defect pixels 37 are detected in the defect detection image sensor 12 a with the element number “1”, and k defective pixels 37 are detected in the defect detection image sensor 12 a with the element number “M”.

  In the “element matrix coordinates” column, the X1 coordinate and the Y1 coordinate of the defect detection imaging element 12a are entered. Here, “_1” to “_M” indicate element numbers. For example, when the defect detection image sensor 12a having the element number “1” is the solid-state image sensor 12 having the matrix coordinates (2, 1), “X1_1” is “2” and “Y1_1” is “1”. Yes (see FIG. 5).

  In the “pixel matrix coordinate” column, the X2 coordinate and Y2 coordinate of the defective pixel 37 are entered. Here, “_11” to “_1j” and “_M1” to “_Mk” indicate “_ (element number) (defect number)”. For example, when the defective pixel 37 with the defect number “1” is a pixel with matrix coordinates (2, 1), “X2 — 11” is “2” and “Y2 — 11” is “1”.

  The coordinate conversion unit 56 converts the element matrix coordinates P1 (X1, Y1) of the defect detection image sensor 12a and the pixel matrix coordinates P2 (X2, Y2) of the defect pixels 37 in the defect detection image sensor 12a into the defective pixels 37. To pixel position coordinates P3 (X3, Y3) on the wafer. Here, the pixel position coordinates P3 (X3, Y3) are position coordinates having a predetermined point on the wafer 10 as the origin.

  The coordinate conversion is performed using the coordinate conversion formulas Fx (X1, Y1, X2, Y2) and Fy (X1, Y1, X2, Y2) stored in the coordinate conversion formula database (DB) 56a. The coordinate conversion formula Fx (X1, Y1, X2, Y2) is a conversion formula for obtaining the X3 coordinate of the pixel position coordinate P3 by inputting the element matrix coordinate P1 (X1, Y1) and the pixel matrix coordinate P2 (X2, Y2). It is. Similarly, the coordinate conversion formula Fy (X1, Y1, X2, Y2) is the input of the element matrix coordinates P1 (X1, Y1) and the pixel matrix coordinates P2 (X2, Y2), and the Y3 coordinates of the pixel position coordinates P3 are changed. This is the conversion formula to obtain. Both of these conversion formulas Fx and Fy are created based on the design information of the wafer 10. The coordinate conversion formula DB 56a stores a plurality of coordinate conversion formulas Fx and Fy created for each type of wafer 10.

  When the electrical property inspection of all the wafers 10 to be inspected is completed, the coordinate conversion unit 56 reads the coordinate conversion formulas Fx and Fy corresponding to the type of the wafer 10 with the wafer number “1” from the coordinate conversion formula DB 56a. Next, the coordinate conversion unit 56 coordinates the element matrix coordinates P1 (X1, Y1) of the defect detection imaging element 12a of the wafer 10 with the wafer number “1” and the pixel matrix coordinates P2 (X2, Y2) of the defective pixel 37. By sequentially inputting the conversion formulas Fx and Fy, the pixel position coordinate P3 (X3, Y3) of the defective pixel 37 of the wafer 10 with the wafer number “1” is obtained. Similarly, the pixel position coordinate P3 of the defective pixel 37 is obtained for the wafers 10 after the wafer number “2”. Table 2 below summarizes the calculation results of the pixel position coordinate P3 of the defective pixel 37 of each wafer 10.

  Table 2 is the same as Table 1 except for the “pixel position coordinate” column. In the “pixel position coordinate” column, the X3 coordinate and Y3 coordinate of the defective pixel 37 are entered. Here, “_11” to “_1j” and “_M1” to “_Mk” indicate “_ (element number) (defect number)” as described above. As described above, the pixel position coordinates P3 (X3, Y3) of all the defective pixels 37 of each wafer 10 are obtained.

  The monitor 58 corresponds to the display means of the present invention, and is used to display a wafer plan view 64 (see FIG. 7) when the wafer 10 is viewed from the surface on which the solid-state imaging device 12 is formed. The display on the monitor 58 is controlled by a display control unit 60 corresponding to the display control means of the present invention. The display control unit 60 accesses the wafer plan view DB storage unit 62 when the pixel position coordinate P3 (X3, Y3) of the defective pixel 37 of each wafer 10 is calculated by the coordinate conversion unit 56 described above. In this wafer plan view DB storage unit 62, wafer plan view data created based on the design information of the wafer 10 is stored for each type of wafer 10.

  As shown in FIG. 7, the display control unit 60 reads wafer plan view data corresponding to the type of the wafer 10 with the wafer number “1” from the wafer plan view DB storage unit 62, and displays the wafer plan view 64 on the monitor 58. It is displayed on the display screen 58a. At the same time, the display control unit 60 determines the pixel position coordinates P3 (X3) of all the defective pixels 37 of the corresponding wafer 10 from the total calculation result (see Table 2) of the pixel position coordinates P3 (X3, Y3) described above. , Y3). Next, the display control unit 60 converts each pixel position coordinate P3 into a position coordinate on the wafer plan view 64, and represents the defective pixel 37 at a position corresponding to each pixel position coordinate P3 on the wafer plan view 64. “×” mark is displayed.

  By confirming the “x” mark displayed on the wafer plan view 64, the position of each defective pixel 37 on the wafer 10 with the wafer number “1” can be easily specified. Then, by operating an operation unit (not shown) of the tester 36, the position of the defective pixel 37 on the wafer 10 after wafer number “2” is displayed on the monitor 58 in the same manner. Note that the position of the defective pixel 37 on the wafer 10 having a desired wafer number can be displayed by inputting the wafer number from an operation unit (not shown).

  Next, the procedure of electrical characteristic inspection (defective pixel inspection) will be described using the flowchart of FIG. When the wafer 10 is set on the wafer table 40, the tester 36 is instructed to perform inspection via an operation unit (not shown). The tester 36 drives the moving mechanism 46 and the elevating mechanism 48 to align the positions of the solid-state imaging device 12 and the probe card 42. Next, the tester 36 turns on the light source 34 and causes the illumination light L to enter the light receiving surface 14, and then measures the output signal from the solid-state imaging device 12, thereby performing predetermined electrical including inspection of the defective pixel 37. Conduct an inspection.

  The defective pixel detection unit 52 of the tester 36 detects the defective pixel 37 from all the pixels of each solid-state image sensor 12 after the electrical characteristic inspection of all the solid-state image sensors 12 is completed. Next, the coordinate specifying unit 54 of the tester 36 includes an element matrix coordinate P1 (X1, Y1) of the defect detection image pickup device 12a and a pixel matrix coordinate P2 (X2, Y2) of each defective pixel 37 in the defect detection image pickup device 12a. And identify. Similarly, element matrix coordinates P1 and pixel matrix coordinates P2 are specified for all wafers 10 to be inspected (see Table 1).

  When the specification of both the position coordinates P1 and P2 is completed, the coordinate conversion unit 56 reads the coordinate conversion formulas Fx and Fy corresponding to the type of the wafer 10 with the wafer number “1” from the coordinate conversion formula DB 56a. The coordinate conversion unit 56 inputs the corresponding element matrix coordinates P1 and pixel matrix coordinates P2 to the coordinate conversion formulas Fx and Fy. Thereby, the pixel position coordinate P3 (X3, Y3) of each defective pixel 37 can be obtained for the wafer 10 with the wafer number “1”. Similarly, the pixel position coordinate P3 of the defective pixel 37 is obtained for the wafers 10 after the wafer number “2” (see Table 2).

  When the pixel position coordinates P3 of the defective pixel 37 are obtained for all the wafers 10, the display control unit 60 displays the wafer plan view 64 corresponding to the type of the wafer 10 with the wafer number “1” on the display screen 58a of the monitor 58. To do. In addition, the display control unit 60 places “x” marks at positions corresponding to the pixel position coordinates P3 (X3, Y3) on the wafer plan view 64 based on the all pixel position coordinates P3 of the wafer 10 with the wafer number “1”. Is displayed. Similarly, the operation unit (not shown) of the tester 36 is operated to display the position of each defective pixel 37 on the wafer 10 after the wafer number “2” on the monitor 58.

  As described above, in the present embodiment, by displaying the “x” mark representing the defective pixel 37 on the wafer plan view 64, the defect on all the wafers 10 on which the defective pixel inspection (electric characteristic inspection) has been performed is performed. The position of the pixel 37 can be easily specified. Thereby, information such as the generation position and distribution of the defective pixel 37 can be used for analysis of a manufacturing defect of the wafer 10. For example, when a defective pixel 37 occurs at the same location on a plurality of wafers 10, it can be estimated that the cause of the defective pixel 37 is a scratch or dust attached to a photomask or the like. . Further, if the distribution of defective pixels 37 on the wafer 10 approximates the distribution when a defect occurs in a specific wafer manufacturing process, the process in which the defect has occurred can be easily specified.

  In the above embodiment, when the defective pixels 37 are displayed on the wafer plan view 64, “×” is uniformly used regardless of the type of the defective pixels 37 such as white scratches (white dots) and black scratches (black dots). However, the present invention is not limited to this, and the color and shape of the mark may be changed according to the type of the defective pixel 37.

  As described above, the defective pixel detection unit 52 determines the type (white scratch, black scratch, etc.) when detecting a defective pixel. Therefore, as shown in FIG. 9, when the display control unit 60 displays the defective pixel 37 on the wafer plan view 64, for example, the white defect pixel 37a is displayed with an “x” mark as in the above embodiment. The black defect pixel 37b may be displayed with a “+” mark. If there are other types of defective pixels 37, these pixels may be displayed with marks of any shape such as “Δ”, “◯”, “□”, “◇”. If the monitor 58 can display in color, the color of the mark may be changed instead of changing the shape of the mark according to the type of the defective pixel 37. Further, both the shape and color of the mark may be changed according to the type of the defective pixel 37.

  As described above, by changing at least one of the shape or color of the mark displayed on the wafer plan view 64 according to the type of the defective pixel 37, the generation position and distribution of the defective pixel 37 on the wafer 10 by type are changed. I can grasp it.

  Further, in the embodiment described with reference to FIG. 9 described above, all kinds of defective pixels 37 are displayed on the wafer plan view 64, but the present invention is not limited to this, and is designated. Only the defective pixel 37 of the type that has been selected may be displayed.

  For example, when the display of only the white defect pixel 37a is designated by the inspector or the like via the operation unit (not shown), the display control unit 60 is displayed on the wafer plan view 64 as shown in FIG. Only the “x” mark corresponding to the white defect pixel 37a is displayed. At this time, when there are N (≧ 3) types of defective pixels 37 or more, display of defective pixels 37 of (N−1) types or less may be designated. In this case as well, the occurrence position and distribution of the defective pixel 37 on the wafer 10 by type can be grasped.

  In the above embodiment, after defective pixel inspection (electric characteristic inspection) of all the wafers 10 to be inspected is completed, defective pixel detection, matrix coordinate specification, defect coordinate conversion, and defective pixel display are performed. However, the present invention is not limited to this, and the above-described series of processing may be performed every time inspection of one wafer 10 is completed.

  In the above embodiment, the solid-state imaging device 12 is formed on the wafer 10 in a substantially two-dimensional matrix. However, the present invention is not limited to this, and is formed in, for example, a staggered shape or a honeycomb shape. May be. Similarly, the light receiving elements 14 of the solid-state imaging element 12 may be arranged in a staggered pattern or a honeycomb pattern. Further, the above-described solid-state imaging device 12 may be a CMOS sensor.

It is a front view of a solid-state image sensor wafer. It is a block diagram which shows the structure of a solid-state image sensor. It is the schematic of an inspection apparatus. It is the block diagram which showed the electrical structure of the test | inspection apparatus. It is explanatory drawing for demonstrating the matrix coordinate of a solid-state image sensor. It is explanatory drawing for demonstrating the matrix coordinate of a pixel. It is explanatory drawing for demonstrating the wafer top view displayed on a monitor. It is a flowchart for demonstrating the procedure of an electrical property test | inspection (defective pixel test | inspection). It is explanatory drawing for demonstrating the wafer top view of other embodiment which changed the shape of the mark according to the kind of defective pixel. It is explanatory drawing for demonstrating the wafer top view of other embodiment which displays only the mark corresponding to the defective pixel of the designated kind.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Solid-state image sensor wafer 12 Solid-state image sensor 12a Defect detection image sensor 30 Inspection apparatus 32 Prober 34 Light source 36 Tester 37 Defective pixel 52 Defective pixel detection part 54 Coordinate specification part 56 Coordinate conversion part 56a Coordinate conversion type database 58 Monitor 60 Display control part 64 Wafer plan view

Claims (5)

A defect in which individual solid-state image sensors on a solid-state image sensor wafer in which a plurality of solid-state image sensors are formed in a matrix are inspected, and defective pixels are detected from a plurality of pixels arranged in a matrix on the solid-state image sensor Pixel detection means;
Based on the detection result of the defective pixel, the solid-state imaging device in which the defective pixel is detected as a defect detection imaging device, element matrix coordinates representing matrix coordinates of the defect detection imaging device on the solid-state imaging device wafer, and Coordinate specifying means for specifying pixel matrix coordinates representing matrix coordinates of the defective pixels on the defect detection image sensor;
In order to identify the position of the defective pixel on the solid-state image sensor wafer, the element matrix coordinates and the pixel matrix coordinates are converted using the coordinate conversion formula created based on the design information of the solid-state image sensor wafer. An inspection apparatus for a solid-state image sensor wafer, comprising: coordinate conversion means for converting into pixel position coordinates of the defective pixel on the solid-state image sensor wafer. Display means for displaying a wafer plan view of the solid-state image sensor wafer as viewed from the formation surface side of the solid-state image sensor;
2. The solid-state imaging device wafer inspection apparatus according to claim 1, further comprising display control means for displaying a mark representing the defective pixel at a position corresponding to the pixel position coordinate on the wafer plan view. There are multiple types of defects in the defective pixel,
3. The inspection of a solid-state imaging device wafer according to claim 2, wherein the display control unit changes at least one of the color or shape of the mark displayed on the wafer plan view according to the type of the defect. apparatus. There are multiple types of defects in the defective pixel,
3. The display control unit according to claim 2, wherein when the type of defect to be displayed is designated, only the mark corresponding to the designated type of defect is displayed on the wafer plan view. 3. The inspection apparatus for a solid-state imaging device wafer according to 3. A defect in which individual solid-state image sensors on a solid-state image sensor wafer in which a plurality of solid-state image sensors are formed in a matrix are inspected, and defective pixels are detected from a plurality of pixels arranged in a matrix on the solid-state image sensor A pixel detection step;
Based on the detection result of the defective pixel, the solid-state image sensor in which the defective pixel is detected as a defect detection image sensor, element matrix coordinates representing matrix coordinates of the defect detection image sensor on the solid-state image sensor wafer, and A coordinate specifying step for specifying pixel matrix coordinates representing matrix coordinates of the defective pixels on the defect detection image sensor;
In order to identify the position of the defective pixel on the solid-state image sensor wafer, the element matrix coordinates and the pixel matrix coordinates are converted using the coordinate conversion formula created based on the design information of the solid-state image sensor wafer, A method of inspecting a solid-state image sensor wafer, comprising: a coordinate conversion step of converting the pixel position coordinates of the defective pixel on the solid-state image sensor wafer.

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