JP2008028040A - Semiconductor device and its manufacturing method - Google Patents
Semiconductor device and its manufacturing method Download PDFInfo
- Publication number
- JP2008028040A JP2008028040A JP2006197276A JP2006197276A JP2008028040A JP 2008028040 A JP2008028040 A JP 2008028040A JP 2006197276 A JP2006197276 A JP 2006197276A JP 2006197276 A JP2006197276 A JP 2006197276A JP 2008028040 A JP2008028040 A JP 2008028040A
- Authority
- JP
- Japan
- Prior art keywords
- adhesive
- corner
- semiconductor element
- support plate
- semiconductor chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83194—Lateral distribution of the layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
Description
本発明は、半導体装置及びその製法、特に半導体装置の作動時に半導体素子の角部に発生する応力を緩和できる半導体装置及びその製法に関する。 The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device and a manufacturing method thereof that can relieve stress generated at corners of a semiconductor element when the semiconductor device is operated.
図９に示すように、支持板(1)と、支持板(1)の上面(1a)に接着剤(2)を介して固着された角形の半導体チップ(3)と、半導体チップ(3)の上面(3a)に形成された上部電極(14)に電気的に接続されるリード細線(5)と、支持板(1)、接着剤(2)、半導体チップ(3)及びリード細線(5)を被覆する樹脂封止体(4)とを備える樹脂封止型の半導体装置は、公知である。 As shown in FIG. 9, a support plate (1), a rectangular semiconductor chip (3) fixed to the upper surface (1a) of the support plate (1) with an adhesive (2), and a semiconductor chip (3) Lead wire (5) electrically connected to the upper electrode (14) formed on the upper surface (3a) of the substrate, support plate (1), adhesive (2), semiconductor chip (3) and lead wire (5 A resin-encapsulated semiconductor device including a resin-encapsulated body (4) that covers the substrate is known.
前記半導体装置を製造する際に、まず、支持板(1)の上面(1a)にエポキシ樹脂等の材料から成る絶縁性の接着剤(2)をスクリーン印刷又はディスペンサ等による周知の塗布法によって供給し、次に、接着剤(2)の粘着力により支持板(1)の上面(1a)に半導体チップ(3)を接着し、最後に、接着剤(2)を加熱硬化する。その後、例えば、周知のワイヤボンディング法によって、リード細線(5)を介して半導体チップ(3)の上部電極(14)を外部リード、配線導体又は他の素子の電極に接続する。次に、例えば、周知のトランスファモールド法によって、支持板(1)、接着剤(2)及び半導体チップ(3)を被覆する樹脂封止体(4)が形成される。 When manufacturing the semiconductor device, first, an insulating adhesive (2) made of a material such as an epoxy resin is supplied to the upper surface (1a) of the support plate (1) by a known coating method such as screen printing or a dispenser. Next, the semiconductor chip (3) is bonded to the upper surface (1a) of the support plate (1) by the adhesive force of the adhesive (2), and finally the adhesive (2) is cured by heating. Thereafter, the upper electrode (14) of the semiconductor chip (3) is connected to the external lead, the wiring conductor, or the electrode of another element via the fine lead wire (5) by, for example, a well-known wire bonding method. Next, a resin sealing body (4) that covers the support plate (1), the adhesive (2), and the semiconductor chip (3) is formed by, for example, a known transfer molding method.
前記製法では、接着剤(2)を介して支持板(1)の上面(1a)に半導体チップ(3)を載置するとき、半導体チップ(3)と上面(1a)との間の空気が接着剤(2)にも包囲されて外部に放出されず、接着剤(2)中にボイド（空洞又は未充填部）が発生する難点があった。その結果、支持板(1)の上面(1a)上に接着剤(2)全体が円滑且つ均一に延展されず、支持板(1)の上面(1a)に対して半導体チップ(3)が傾斜して接着され、半導体チップ(3)を平行に固着できない不具合が生じた。また、接着剤(2)内にボイドが発生すると、接着剤(2)にクラック（亀裂）が生じて、接着剤(2)の全面に均一に半導体チップ(3)が接触せず、半導体チップ(3)が剥がれ易くなる弊害が生じた。 In the manufacturing method, when the semiconductor chip (3) is placed on the upper surface (1a) of the support plate (1) via the adhesive (2), the air between the semiconductor chip (3) and the upper surface (1a) The adhesive (2) is surrounded and not released to the outside, and there is a problem that voids (cavities or unfilled portions) are generated in the adhesive (2). As a result, the entire adhesive (2) does not extend smoothly and uniformly on the upper surface (1a) of the support plate (1), and the semiconductor chip (3) is inclined with respect to the upper surface (1a) of the support plate (1). As a result, the semiconductor chip (3) cannot be fixed in parallel. In addition, if a void is generated in the adhesive (2), a crack occurs in the adhesive (2), and the semiconductor chip (3) does not come into uniform contact with the entire surface of the adhesive (2). (3) has a harmful effect that it is easy to peel off.
これに対し、下記特許文献１は、２つ以上に分割されたポリイミド樹脂から成るフィルムによって半導体チップをアイランド上に熱圧着した半導体装置を開示する。特許文献１の半導体装置によれば、フィルムの分割部分から空気が外部に放出され、フィルム中のボイドの発生を防止できる。
On the other hand,
しかしながら、分割された接着フィルムの取り扱いは不便であり、アイランド上の所定の位置に正確に複数のフィルムを配置することも困難である。
また、図９に示す半導体装置では、半導体チップ(3)、接着剤(2)及び樹脂封止体(4)を形成する各材質の線膨張係数が相違するため、半導体装置の作動時に発生する熱により、半導体チップ(3)と接着剤(2)及び樹脂封止体(4)の熱変形量が相違して、半導体チップ(3)に応力が加えられる。この際、図１０及び図１１に示すように、半導体チップ(3)の側面(3c)、特に側面(3c)が交差する角部(3d)に応力が集中し、半導体チップ(3)が破損又は電気的特性が劣化することがあった。
そこで、本発明は、半導体素子の角部への応力集中を抑制する半導体装置を提供することを目的とする。また、本発明は、半導体素子の角部への応力集中を抑制すると共に、支持板に半導体素子を固着する際に接着剤内のボイド発生を抑制する半導体装置の製法を提供することを目的とする。
However, the handling of the divided adhesive films is inconvenient, and it is difficult to accurately arrange a plurality of films at predetermined positions on the island.
Further, in the semiconductor device shown in FIG. 9, since the linear expansion coefficients of the respective materials forming the semiconductor chip (3), the adhesive (2), and the resin sealing body (4) are different, they are generated when the semiconductor device is operated. Due to the heat, the amount of thermal deformation of the semiconductor chip (3) differs from that of the adhesive (2) and the resin sealing body (4), and stress is applied to the semiconductor chip (3). At this time, as shown in FIG. 10 and FIG. 11, stress concentrates on the side surface (3c) of the semiconductor chip (3), particularly the corner (3d) where the side surface (3c) intersects, and the semiconductor chip (3) is damaged. Or electrical characteristics may deteriorate.
SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device that suppresses stress concentration at corners of a semiconductor element. Another object of the present invention is to provide a method of manufacturing a semiconductor device that suppresses stress concentration at the corners of a semiconductor element and suppresses void formation in an adhesive when the semiconductor element is fixed to a support plate. To do.
本発明の半導体装置は、支持板(1)と、支持板(1)の上面(1a)に接着剤(2)を介して固着された角形の半導体素子(3)と、少なくとも支持板(1)の一部、接着剤(2)及び半導体素子(3)を被覆する樹脂封止体(4)とを備える。接着剤(2)は、支持板(1)の上面(1a)に半導体素子(3)の下面(3b)を固着する介在部(7)と、半導体素子(3)の複数の側面(3c)を被覆する側面接着部(8)と、半導体素子(3)の複数の角部(3d)を被覆する角接着部(9)とを有する。角部(3d)に沿って介在部(7)から半導体素子(3)の上面(3a)に向かって角接着部(9)を延伸させ、側面(3c)に沿って介在部(7)から半導体素子(3)の上面(3a)に向かって側面接着部(8)を延伸させて、側面接着部(8)より高い位置まで角接着部(9)が形成される。半導体素子(3)、接着剤(2)及び樹脂封止体(4)を形成する各材質の線膨張係数の相違のため、半導体装置の作動時に発生する熱により、半導体チップ(3)と接着剤(2)及び樹脂封止体(4)の熱変形量が相違して、半導体素子(3)に応力が加えられる。このとき、半導体素子(3)の側面(3c)を被覆する側面接着部(8)よりも高い位置まで接着剤(2)の角接着部(9)を形成する角接着部(9)の高さ分によって、半導体素子(3)の各角部(3d)に加わる応力を低減し又は角部(3d)から側面(3c)側に応力を分散して、角接着部(9)での応力集中を低減することができる。従って、角部(3d)への応力集中に起因する半導体素子(3)の破損又は電気的特性の劣化を抑制することができる。 The semiconductor device of the present invention includes a support plate (1), a rectangular semiconductor element (3) fixed to the upper surface (1a) of the support plate (1) via an adhesive (2), and at least the support plate (1 ), A resin sealing body (4) covering the adhesive (2) and the semiconductor element (3). The adhesive (2) includes an interposition part (7) for fixing the lower surface (3b) of the semiconductor element (3) to the upper surface (1a) of the support plate (1), and a plurality of side surfaces (3c) of the semiconductor element (3). And a corner bonding portion (9) covering a plurality of corner portions (3d) of the semiconductor element (3). Extending the corner bonding portion (9) from the interposition portion (7) along the corner portion (3d) toward the upper surface (3a) of the semiconductor element (3), and extending from the interposition portion (7) along the side surface (3c) The side surface adhesion portion (8) is extended toward the upper surface (3a) of the semiconductor element (3), and the corner adhesion portion (9) is formed up to a position higher than the side surface adhesion portion (8). Due to the difference in coefficient of linear expansion of each material forming the semiconductor element (3), the adhesive (2), and the resin encapsulant (4), it is bonded to the semiconductor chip (3) by heat generated during operation of the semiconductor device. The amount of thermal deformation between the agent (2) and the resin sealing body (4) is different, and stress is applied to the semiconductor element (3). At this time, the height of the corner bonding portion (9) forming the corner bonding portion (9) of the adhesive (2) to a position higher than the side surface bonding portion (8) covering the side surface (3c) of the semiconductor element (3). By this, the stress applied to each corner (3d) of the semiconductor element (3) is reduced, or the stress is distributed from the corner (3d) to the side surface (3c), so that the stress at the corner bonding portion (9). Concentration can be reduced. Therefore, damage to the semiconductor element (3) or deterioration of electrical characteristics due to stress concentration on the corner (3d) can be suppressed.
また、本発明の半導体装置の製法は、半導体素子(3)の下面(3b)の中央部(3e)及び各角部(3d)に整合して、支持板(1)の上面(1a)に接着剤(2)を配置する工程と、接着剤(2)に整合して半導体素子(3)を接着剤(2)に載置し且つ半導体素子(3)を支持板(1)へ押圧して、接着剤(2)を介して支持板(1)と半導体素子(3)とを固着する工程と、少なくとも支持板(1)の一部、接着剤(2)及び半導体素子(3)を樹脂封止体(4)により被覆する工程とを含む。接着剤(2)に整合して半導体素子(3)を載置して、半導体素子(3)を支持板(1)へ押圧すると、半導体素子(3)の中央部(3e)に配置される接着剤(2)が、半導体素子(3)の外側に向かって圧延され且つ均一な厚みに扁平化されるので、半導体素子(3)と支持板(1)との間の空気は、半導体素子(3)の外側に向かって押圧されて外部に放出される。従って、半導体素子(3)と支持板(1)との間で接着剤(2)中にボイドが形成されず、支持板(1)上での半導体素子(3)の傾斜固着を防止することができる。また、半導体装置の作動時に発生する熱により、半導体素子(3)に応力が加えられる際に、半導体素子(3)の各角部(3d)に配置される接着剤(2)は、半導体素子(3)を支持板(1)へ押圧すると、角部(3d)に沿って半導体素子(3)の上面(3a)に向かって延伸して、半導体素子(3)の角部(3d)を高い位置で被覆するので、半導体装置の作動時に半導体素子(3)の角部(3d)に加わる応力は、角部(3d)の周辺部に分散される。よって、角部(3d)への応力集中による半導体素子(3)の破損又は電気的特性の劣化を抑制することができる。 Further, the manufacturing method of the semiconductor device of the present invention is aligned with the central portion (3e) and each corner portion (3d) of the lower surface (3b) of the semiconductor element (3), and on the upper surface (1a) of the support plate (1). Placing the adhesive (2), placing the semiconductor element (3) on the adhesive (2) in alignment with the adhesive (2) and pressing the semiconductor element (3) against the support plate (1); Fixing the support plate (1) and the semiconductor element (3) via the adhesive (2), and at least a part of the support plate (1), the adhesive (2) and the semiconductor element (3). And a step of covering with a resin sealing body (4). When the semiconductor element (3) is placed in alignment with the adhesive (2) and the semiconductor element (3) is pressed against the support plate (1), the semiconductor element (3) is arranged at the center (3e). Since the adhesive (2) is rolled toward the outside of the semiconductor element (3) and flattened to a uniform thickness, the air between the semiconductor element (3) and the support plate (1) It is pressed toward the outside of (3) and released to the outside. Therefore, no void is formed in the adhesive (2) between the semiconductor element (3) and the support plate (1), and the semiconductor element (3) is prevented from being tilted and fixed on the support plate (1). Can do. Further, when stress is applied to the semiconductor element (3) due to heat generated during operation of the semiconductor device, the adhesive (2) disposed at each corner (3d) of the semiconductor element (3) When (3) is pressed against the support plate (1), the corner (3d) of the semiconductor element (3) is extended along the corner (3d) toward the upper surface (3a) of the semiconductor element (3). Since the coating is performed at a high position, the stress applied to the corner (3d) of the semiconductor element (3) during operation of the semiconductor device is dispersed in the peripheral portion of the corner (3d). Therefore, damage of the semiconductor element (3) or deterioration of electrical characteristics due to stress concentration on the corner (3d) can be suppressed.
本発明の半導体装置及び半導体装置の製法によれば、半導体素子の角部への応力集中による半導体素子の破損又は電気的特性の劣化を抑制して、信頼性の高い半導体装置を提供することができる。また、本発明の半導体装置の製法によれば、半導体素子と支持板とを固着する接着剤中にボイドが形成されず、信頼性の高い半導体装置を製造することができる。 According to the semiconductor device and the method for manufacturing the semiconductor device of the present invention, it is possible to provide a highly reliable semiconductor device by suppressing damage to the semiconductor element or deterioration of electrical characteristics due to stress concentration on the corner of the semiconductor element. it can. Further, according to the method for manufacturing a semiconductor device of the present invention, no void is formed in the adhesive for fixing the semiconductor element and the support plate, and a highly reliable semiconductor device can be manufactured.
以下、本発明による半導体装置及びその製法の実施の形態を図１〜図８について説明する。但し、これらの図面では、図９に示す部分と実質的に同一の部分には同一の符号を付し、その説明を省略する。 DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a semiconductor device and a manufacturing method thereof according to the present invention will be described below with reference to FIGS. However, in these drawings, substantially the same parts as those shown in FIG. 9 are denoted by the same reference numerals, and description thereof is omitted.
図１に示すように、本実施の形態の半導体装置は、プリント基板又は金属製の放熱板等の支持板(1)と、支持板(1)の上面(1a)に接着剤(2)を介して固着された角形の半導体チップ(3)と、半導体チップ(3)の上面(3a)に形成された上部電極(14)と支持板(1)の周辺に配置された外部リード、支持板(1)上の配線導体又は他の素子の電極（何れも図示せず）とを電気的に接続するリード細線(5)と、支持板(1)、接着剤(2)、半導体チップ(3)及びリード細線(5)並びに外部リード、配線導体又は他の素子の電極を被覆する樹脂封止体(4)とを備える。半導体チップ(3)は、例えば、シリコン基板により形成されるダイオードチップ又はトランジスタチップ等の周知の半導体素子であり、平坦面を有する正方形、矩形又は多角形の板状に形成される。接着剤(2)は、例えば、エポキシ樹脂にシリカ等のフィラーを混入したエポキシ樹脂系接着剤等の周知の絶縁性接着剤である。樹脂封止体(4)は、例えば、エポキシ樹脂により形成され、支持板(1)上で半導体チップ(3)の上面(3a)及び側面(3c)、接着剤(2)並びにリード細線(5)を封止する。 As shown in FIG. 1, the semiconductor device of the present embodiment has a support plate (1) such as a printed circuit board or a metal heat sink, and an adhesive (2) on the upper surface (1a) of the support plate (1). A rectangular semiconductor chip (3) fixed via the upper electrode (14) formed on the upper surface (3a) of the semiconductor chip (3) and external leads and support plates arranged around the support plate (1) (1) Lead wire (5) for electrically connecting the wiring conductor or other element electrode (not shown) on the top, support plate (1), adhesive (2), semiconductor chip (3 ) And a fine lead wire (5), and a resin sealing body (4) covering the external lead, the wiring conductor, or the electrode of another element. The semiconductor chip (3) is a known semiconductor element such as a diode chip or a transistor chip formed of a silicon substrate, and is formed in a square, rectangular or polygonal plate shape having a flat surface. The adhesive (2) is a well-known insulating adhesive such as an epoxy resin adhesive in which a filler such as silica is mixed in an epoxy resin. The resin sealing body (4) is formed of, for example, an epoxy resin, and on the support plate (1), the upper surface (3a) and side surface (3c) of the semiconductor chip (3), the adhesive (2), and the lead wire (5 ) Is sealed.
接着剤(2)は、支持板(1)の上面(1a)に半導体チップ(3)の下面(3b)を固着する介在部(7)と、半導体チップ(3)の複数の側面(3c)を被覆する側面接着部(8)と、半導体チップ(3)の複数の角部(3d)を被覆する角接着部(9)とを有する。本実施の形態では、側面接着部(8)は、半導体チップ(3)の４つの側面(3c)を被覆し、角接着部(9)は、半導体チップ(3)の各側面(3c)が接続する４つの角部(3d)を被覆する。介在部(7)、側面接着部(8)及び角接着部(9)は、同一の材質により一体に形成され、支持板(1)の上面(1a)に半導体チップ(3)を強固に固着して、確実に保持することができる。 The adhesive (2) includes an interposition part (7) for fixing the lower surface (3b) of the semiconductor chip (3) to the upper surface (1a) of the support plate (1), and a plurality of side surfaces (3c) of the semiconductor chip (3). And a corner bonding portion (9) covering a plurality of corner portions (3d) of the semiconductor chip (3). In the present embodiment, the side surface bonding portion (8) covers the four side surfaces (3c) of the semiconductor chip (3), and the corner bonding portion (9) is connected to each side surface (3c) of the semiconductor chip (3). Cover the four corners (3d) to be connected. The interposition part (7), the side adhesion part (8) and the corner adhesion part (9) are integrally formed of the same material, and the semiconductor chip (3) is firmly fixed to the upper surface (1a) of the support plate (1). And can be held securely.
角接着部(9)は、角部(3d)に沿って介在部(7)から半導体チップ(3)の上面(3a)に向かって延伸して形成され、側面接着部(8)は、側面(3c)に沿って介在部(7)から半導体チップ(3)の上面(3a)に向かって延伸して形成される。角接着部(9)は、図２〜図４に示すように、側面接着部(8)より高い位置まで形成され、図１に示すように、角接着部(9)が介在部(7)から半導体チップ(3)の上面(3a)に向かって略山形に形成されるのに対し、側面接着部(8)は、略水平又は波形に形成される。半導体チップ(3)の角部(3d)を被覆する角接着部(9)が半導体チップ(3)の側面(3c)を被覆する側面接着部(8)よりも高い位置まで形成されるので、図５に示すように、半導体チップ(3)の側面(3c)を被覆する側面接着部(8)よりも高い位置まで接着剤(2)の角接着部(9)を形成する角接着部(9)の高さ分によって、半導体素子(3)の各角部(3d)に加わる応力を低減し又は角部(3d)から側面(3c)側に応力を分散して、角接着部(9)での応力集中を低減することができる。角接着部(9)の緩衝作用により、樹脂封止体(4)の熱膨張から半導体チップ(3)の角部(3d)を保護するのみならず、側面接着部(8)よりも角接着部(9)を半導体チップ(3)の高い位置まで形成することにより、接着剤(2)により十分に被覆される半導体チップ(3)の角部(3d)よりも接着剤(2)により十分に被覆されない半導体チップ(3)の側面(3c)に応力が分散して、半導体チップ(3)の角部(3d)に発生する応力集中が緩和される。角接着部(9)よりも側面接着部(8)を半導体チップ(3)の高い位置まで形成すると、半導体チップ(3)の角部(3d)に発生する応力が緩和されない。半導体チップ(3)の角部(3d)に発生する応力を緩和することにより、角部(3d)への応力集中に起因する半導体チップ(3)の破損又は電気的特性の劣化を抑制することができる。 The corner bonding portion (9) is formed by extending from the interposition portion (7) toward the upper surface (3a) of the semiconductor chip (3) along the corner portion (3d), and the side surface bonding portion (8) It is formed by extending from the interposition part (7) to the upper surface (3a) of the semiconductor chip (3) along (3c). The corner bonding portion (9) is formed up to a position higher than the side surface bonding portion (8) as shown in FIGS. 2 to 4, and as shown in FIG. 1, the corner bonding portion (9) is interposed between the interposition portions (7). From the side to the top surface (3a) of the semiconductor chip (3), the side surface bonding portion (8) is formed substantially horizontally or corrugated. Since the corner bonding portion (9) covering the corner portion (3d) of the semiconductor chip (3) is formed to a position higher than the side surface bonding portion (8) covering the side surface (3c) of the semiconductor chip (3), As shown in FIG. 5, the corner bonding portion (9) for forming the corner bonding portion (9) of the adhesive (2) up to a position higher than the side surface bonding portion (8) covering the side surface (3c) of the semiconductor chip (3). Depending on the height of 9), the stress applied to each corner (3d) of the semiconductor element (3) is reduced, or the stress is distributed from the corner (3d) to the side surface (3c), and the corner bonded portion (9 ) Can be reduced. The buffering action of the corner bonding part (9) not only protects the corner part (3d) of the semiconductor chip (3) from the thermal expansion of the resin sealing body (4), but also corner bonding more than the side surface bonding part (8). By forming the part (9) up to the high position of the semiconductor chip (3), the adhesive (2) is more sufficient than the corner (3d) of the semiconductor chip (3) that is sufficiently covered with the adhesive (2). Stress is dispersed on the side surface (3c) of the semiconductor chip (3) that is not covered with the metal, and the stress concentration generated at the corner (3d) of the semiconductor chip (3) is alleviated. When the side surface bonding portion (8) is formed to a position higher than the corner bonding portion (9) to the semiconductor chip (3), the stress generated at the corner portion (3d) of the semiconductor chip (3) is not relieved. By reducing the stress generated at the corner (3d) of the semiconductor chip (3), it is possible to suppress damage to the semiconductor chip (3) or deterioration of electrical characteristics due to stress concentration on the corner (3d). Can do.
図２〜図４に示すように、半導体チップ(3)の下面(3b)から上面(3a)までの高さをＨとすると、角接着部(9)の高さｈ1は、(０.６〜１)Ｈの範囲であり、側面接着部(8)の高さｈ2は、(０〜０.４)Ｈの範囲である。角接着部(9)により０.６Ｈ未満の高さで角部(3d)を被覆し又は側面接着部(8)により０.４Ｈより高く側面(3c)を被覆すると、角接着部(9)と側面接着部(8)との高さの差が不十分となり、半導体チップ(3)に発生する応力を角部(3d)から側面(3c)に良好に分散できない。 As shown in FIGS. 2 to 4, when the height from the lower surface (3b) to the upper surface (3a) of the semiconductor chip (3) is H, the height h 1 of the corner bonding portion (9) is (0. 6 to 1) H, and the height h 2 of the side surface bonding portion (8) is in the range of (0 to 0.4) H. When the corner (3d) is covered with a corner bonding portion (9) at a height of less than 0.6H or the side surface (3c) is coated with a side bonding portion (8) higher than 0.4H, the corner bonding portion (9) And the height difference between the side surface bonding portion (8) becomes insufficient, and the stress generated in the semiconductor chip (3) cannot be well distributed from the corner portion (3d) to the side surface (3c).
具体的には、厚さ２００〜６００μm程度の比較的厚いシリコン基板により形成される半導体チップ(3)を使用したとき、半導体チップ(3)の線膨張係数が７×１０-6程度、エポキシ樹脂により形成される接着剤(2)の線膨張係数が１０×１０-6程度、エポキシ樹脂により形成される樹脂封止体(4)の線膨張係数が３０×１０-6程度である。従来の半導体装置では、半導体装置の作動時に半導体素子(3)、接着剤(2)及び樹脂封止体(4)が隣接する半導体素子(3)の側面(3c)及び角部(3d)に応力が生じ、特に、半導体素子(3)の角部(3d)に応力が集中することが確認された。これに対し、本実施の形態の半導体装置では、角接着部(9)により、(０.６〜１)Ｈの高さ範囲で半導体チップ(3)の角部(3d)を被覆し、側面接着部(8)により、(０〜０.４)Ｈの高さ範囲で半導体チップ(3)の側面(3c)を被覆することにより、半導体素子(3)の角部(3d)の応力が低下することが確認された。 Specifically, when a semiconductor chip (3) formed of a relatively thick silicon substrate having a thickness of about 200 to 600 μm is used, the linear expansion coefficient of the semiconductor chip (3) is about 7 × 10 −6 , epoxy resin The linear expansion coefficient of the adhesive (2) formed by the above method is about 10 × 10 −6 , and the linear expansion coefficient of the resin sealing body (4) formed of epoxy resin is about 30 × 10 −6 . In the conventional semiconductor device, the semiconductor element (3), the adhesive (2), and the resin sealing body (4) are placed on the side surface (3c) and the corner (3d) of the adjacent semiconductor element (3) when the semiconductor device is operated. It was confirmed that stress was generated, and in particular, the stress was concentrated on the corner (3d) of the semiconductor element (3). On the other hand, in the semiconductor device of the present embodiment, the corner portion (3d) of the semiconductor chip (3) is covered with the corner bonding portion (9) in the height range of (0.6 to 1) H, and the side surface. By covering the side surface (3c) of the semiconductor chip (3) in the height range of (0 to 0.4) H by the bonding portion (8), the stress of the corner portion (3d) of the semiconductor element (3) is reduced. It was confirmed that it decreased.
本実施の形態の半導体装置を製造する際に、まず、支持板(1)の上面(1a)に接着剤(2)をディスペンサ等の塗布装置（図示せず）により供給する。図６に示すように、接着剤(2)は、半導体チップ(3)の下面(3b)の中央部(3e)及び各角部(3d)に整合して、支持板(1)の上面(1a)に配置される。次に、コレット（図示せず）により接着剤(2)に整合して半導体チップ(3)を接着剤(2)上に載置し且つ半導体チップ(3)を支持板(1)へ押圧して、接着剤(2)を介して支持板(1)と半導体チップ(3)とを固着する。接着剤(2)に整合して半導体チップ(3)を載置して、半導体チップ(3)を支持板(1)へ押圧すると、半導体チップ(3)の中央部(3e)に配置される接着剤(2)が、半導体チップ(3)の外側に向かって圧延され且つ均一な厚みに偏平化されるので、半導体チップ(3)と支持板(1)との間の空気は、半導体チップ(3)の外側に向かって押圧されて外部に放出される。従って、半導体チップ(3)と支持板(1)との間で接着剤(2)中にボイド（空洞又は未充填部）が形成されず、支持板(1)上での半導体チップ(3)の傾斜固着を防止することができる。 When manufacturing the semiconductor device of the present embodiment, first, the adhesive (2) is supplied to the upper surface (1a) of the support plate (1) by a coating device (not shown) such as a dispenser. As shown in FIG. 6, the adhesive (2) is aligned with the central portion (3e) and each corner portion (3d) of the lower surface (3b) of the semiconductor chip (3), and the upper surface ( Located in 1a). Next, the semiconductor chip (3) is placed on the adhesive (2) in alignment with the adhesive (2) by a collet (not shown), and the semiconductor chip (3) is pressed against the support plate (1). Then, the support plate (1) and the semiconductor chip (3) are fixed via the adhesive (2). When the semiconductor chip (3) is placed in alignment with the adhesive (2) and the semiconductor chip (3) is pressed against the support plate (1), the semiconductor chip (3) is placed at the center (3e). Since the adhesive (2) is rolled toward the outside of the semiconductor chip (3) and flattened to a uniform thickness, the air between the semiconductor chip (3) and the support plate (1) It is pressed toward the outside of (3) and released to the outside. Therefore, no void (void or unfilled portion) is formed in the adhesive (2) between the semiconductor chip (3) and the support plate (1), and the semiconductor chip (3) on the support plate (1) is not formed. Can be prevented.
前述した特許文献１の半導体装置では、フィルムを２分割又は４分割して、半導体チップの下面の中央部に整合するフィルムを有さないため、半導体チップとアイランドとの間の空気が半導体チップの外側に向かって押圧されず、空気が良好に外部に放出されない。また、９分割のフィルムも開示するが、半導体チップの下面の角部に整合するフィルムの間に別のフィルムを有するため、半導体チップとアイランドとの間で空気の移動が阻害されて、空気が良好に外部に放出されない。
In the semiconductor device of
また、半導体チップ(3)の各角部(3d)に配置される接着剤(2)は、半導体チップ(3)を支持板(1)へ押圧すると、角部(3d)に沿って半導体チップ(3)の上面(3a)に向かって延伸して、半導体チップ(3)の角部(3d)を高い位置で被覆する。よって、前述したように、半導体装置の作動時に半導体チップ(3)の角部(3d)に加わる応力が角部(3d)の周辺部に分散し、角部(3d)への応力集中による半導体チップ(3)の破損又は電気的特性の劣化を防止することができる。接着剤(2)により半導体チップ(3)の角部(3d)を高い位置で被覆するには、接着剤(2)の粘性率、支持板(1)の上面(1a)に塗布する接着剤(2)の分量及びコレットにより半導体チップ(3)を接着剤(2)に押圧する力の大きさが重要であるが、これらの値は、実験又はシミュレーションを繰り返すことにより適宜に決定される。 In addition, the adhesive (2) disposed at each corner (3d) of the semiconductor chip (3) is pressed along the corner (3d) when the semiconductor chip (3) is pressed against the support plate (1). Extending toward the upper surface (3a) of (3), the corner (3d) of the semiconductor chip (3) is covered at a high position. Therefore, as described above, the stress applied to the corner portion (3d) of the semiconductor chip (3) during the operation of the semiconductor device is dispersed in the peripheral portion of the corner portion (3d), and the semiconductor is caused by stress concentration on the corner portion (3d). It is possible to prevent damage to the chip (3) or deterioration of electrical characteristics. To cover the corner (3d) of the semiconductor chip (3) at a high position with the adhesive (2), the viscosity of the adhesive (2), the adhesive applied to the upper surface (1a) of the support plate (1) The amount of (2) and the magnitude of the force for pressing the semiconductor chip (3) against the adhesive (2) by the collet are important, but these values are appropriately determined by repeating experiments or simulations.
本実施の形態では、支持板(1)の上面(1a)に接着剤(2)を配置する際に、半導体チップ(3)の下面(3b)の中央部(3e)及び各角部(3d)に整合する位置にそれぞれ円形且つ同分量の複数の接着剤(2)を配置する。また、接着剤(2)を介して支持板(1)と半導体チップ(3)とを固着する際に、複数の接着剤(2)の略中心(O)に半導体チップ(3)の下面(3b)の各角部(3d)を整合して、半導体チップ(3)を載置する。同形状且つ同分量の接着剤(2)の略中心(O)に半導体チップ(3)の下面(3b)の各角部(3d)を整合することにより、接着剤(2)を介して支持板(1)の上面(1a)と半導体チップ(3)とを平行に固着することができる。図６では、半導体チップ(3)の下面(3b)の４つの隅角に対向する４つの接着剤(2)と、半導体チップ(3)の下面(3b)の略中央部(3e)に対向する１つの接着剤(2)とが支持板(1)に塗布され、半球状に形成された各接着剤(2)の頂上部に半導体チップ(3)の隅角及び中央部が当接して固着される。続いて、接着剤(2)を加熱硬化して、接着剤(2)により半導体チップ(3)と支持板(1)とが固着される。 In the present embodiment, when the adhesive (2) is disposed on the upper surface (1a) of the support plate (1), the central portion (3e) and each corner portion (3d) of the lower surface (3b) of the semiconductor chip (3) are arranged. A plurality of adhesives (2) of a circular shape and an equal amount are arranged at positions matching with (). In addition, when fixing the support plate (1) and the semiconductor chip (3) via the adhesive (2), the lower surface of the semiconductor chip (3) (approximately) the center (O) of the plurality of adhesives (2) ( The corners (3d) of 3b) are aligned and the semiconductor chip (3) is placed. Support through the adhesive (2) by aligning each corner (3d) of the lower surface (3b) of the semiconductor chip (3) with the approximate center (O) of the same shape and amount of adhesive (2) The upper surface (1a) of the plate (1) and the semiconductor chip (3) can be fixed in parallel. In FIG. 6, the four adhesives (2) facing the four corners of the lower surface (3b) of the semiconductor chip (3) and the substantially central portion (3e) of the lower surface (3b) of the semiconductor chip (3) are opposed. One adhesive (2) is applied to the support plate (1), and the corners and the center of the semiconductor chip (3) are in contact with the top of each hemispherical adhesive (2). It is fixed. Subsequently, the adhesive (2) is cured by heating, and the semiconductor chip (3) and the support plate (1) are fixed by the adhesive (2).
その後、従来と同様に、リード細線（ボンディングワイヤ）(5)により、半導体チップ(3)の上部電極（ボンディングパッド）(14)を外部リード、配線導体又は他の素子の電極に接続し、樹脂封止体(4)により、支持板(1)、接着剤(2)、半導体チップ(3)、リード細線(5)及び外部リードの一端、支持板(1)の上面(1a)に配置された配線導体又は他の素子を被覆して、図１に示す半導体装置が完成する。角接着部(9)は、側面接着部(8)より高く且つ半導体チップ(3)の上面(3a)より低い位置で形成される。よって、半導体チップ(3)の上面(3a)より上方に角接着部(9)が突出しないため、半導体チップ(3)の上部電極(14)にリード細線(5)の一端を良好にワイヤボンディングすることができる。 After that, as in the conventional case, the upper electrode (bonding pad) (14) of the semiconductor chip (3) is connected to the external lead, the wiring conductor or the electrode of another element by the fine lead wire (bonding wire) (5), and the resin By the sealing body (4), the support plate (1), the adhesive (2), the semiconductor chip (3), the lead wire (5) and one end of the external lead are arranged on the upper surface (1a) of the support plate (1). The semiconductor device shown in FIG. 1 is completed by covering the wiring conductor or other element. The corner bonding portion (9) is formed at a position higher than the side surface bonding portion (8) and lower than the upper surface (3a) of the semiconductor chip (3). Therefore, since the corner bonding portion (9) does not protrude above the upper surface (3a) of the semiconductor chip (3), one end of the lead fine wire (5) is well bonded to the upper electrode (14) of the semiconductor chip (3). can do.
本発明の実施の形態は、図１〜図６に示す実施の形態に限定されず、変更が可能である。例えば、半導体装置を製造する際に、図７に示すように、支持板(1)の上面(1a)に接着剤(2)をＸ形に配置してもよい。Ｘ形の４つの端部に半導体チップ(3)の各角部(3d)を整合し、接着剤(2)が交差するＸ形の中央部に半導体チップ(3)の中央部(3e)を整合して、支持板(1)の上面(1a)に半導体チップ(3)を固着することができる。また、図８に示すように、半導体チップ(3)の各側面(3c)に対向する支持板(1)の上面(1a)に溝(15)を形成し、円形又は角形に形成された単一の接着剤(2)を半導体チップ(3)の中央部(3e)に整合して支持板(1)の上面(1a)に配置してもよい。コレットにより半導体チップ(3)を接着剤(2)に押圧したとき、半導体チップ(3)の側面(3c)に向かって延伸する接着剤(2)は、溝(15)内に充填されて半導体チップ(3)の側面(3c)を殆ど被覆しないが、半導体チップ(3)の角部(3d)に向かって延伸する接着剤(2)は、溝(15)の間を移動して半導体チップ(3)の角部(3d)を十分な厚さで被覆することができる。半導体チップ(3)は、ダイオードチップ又はトランジスタチップに限定されず、モノリシックＩＣ等の他の半導体素子でもよい。また、接着剤(2)は、エポキシ樹脂系接着剤に限定されず、ポリイミド樹脂系接着剤等の他の接着剤でもよい。 The embodiment of the present invention is not limited to the embodiment shown in FIGS. 1 to 6 and can be changed. For example, when manufacturing a semiconductor device, as shown in FIG. 7, the adhesive (2) may be arranged in an X shape on the upper surface (1a) of the support plate (1). The corners (3d) of the semiconductor chip (3) are aligned with the four ends of the X shape, and the central portion (3e) of the semiconductor chip (3) is aligned with the central portion of the X shape where the adhesive (2) intersects. In alignment, the semiconductor chip (3) can be fixed to the upper surface (1a) of the support plate (1). Further, as shown in FIG. 8, a groove (15) is formed on the upper surface (1a) of the support plate (1) facing each side surface (3c) of the semiconductor chip (3), and a single unit formed in a circular or square shape. One adhesive (2) may be arranged on the upper surface (1a) of the support plate (1) in alignment with the central portion (3e) of the semiconductor chip (3). When the semiconductor chip (3) is pressed against the adhesive (2) by the collet, the adhesive (2) extending toward the side surface (3c) of the semiconductor chip (3) is filled in the groove (15) and the semiconductor. The adhesive (2) that hardly covers the side surface (3c) of the chip (3) but extends toward the corner (3d) of the semiconductor chip (3) moves between the grooves (15) and moves to the semiconductor chip. The corner (3d) of (3) can be covered with a sufficient thickness. The semiconductor chip (3) is not limited to a diode chip or a transistor chip, and may be another semiconductor element such as a monolithic IC. The adhesive (2) is not limited to an epoxy resin adhesive, and may be another adhesive such as a polyimide resin adhesive.
本発明は、動作時の熱により半導体装置に発生する応力を緩和できるため、例えば、パワートランジスタ等の大電流により動作する樹脂封止型半導体装置に良好に適用できる。 Since the stress generated in the semiconductor device due to heat during operation can be relieved, the present invention can be favorably applied to, for example, a resin-sealed semiconductor device that operates with a large current such as a power transistor.
(1)・・支持板、 (1a)・・上面、 (2)・・接着剤、 (3)・・半導体チップ（半導体素子）、 (3a)・・上面、 (3b)・・下面、 (3c)・・側面、 (3d)・・角部、 (3e)・・中央部、 (4)・・樹脂封止体、 (5)・・リード細線、 (7)・・介在部、 (8)・・側面接着部、 (9)・・角接着部、 (14)・・上部電極、 (1) ・ ・ Support plate, (1a) ・ ・ Upper surface, (2) ・ ・ Adhesive, (3) ・ Semiconductor chip (semiconductor element), (3a) ・ ・ Upper surface, (3b) ・ ・ Lower surface, ( 3c) ・ ・ Side, (3d) ・ ・ Corner, (3e) ・ ・ Center, (4) ・ ・ Resin encapsulant, (5) ・ ・ Lead thin wire, (7) ・ ・ Intervening part, (8 ) ・ ・ Side adhesive part, (9) ・ ・ Corner adhesive part, (14) ・ ・ Upper electrode,
Claims (5)
前記接着剤は、前記支持板の上面に前記半導体素子の下面を固着する介在部と、前記半導体素子の複数の側面を被覆する側面接着部と、前記半導体素子の複数の角部を被覆する角接着部とを有し、
前記角部に沿って前記介在部から前記半導体素子の上面に向かって前記角接着部を延伸させ、
前記側面に沿って前記介在部から前記半導体素子の上面に向かって前記側面接着部を延伸させて、
前記側面接着部より高い位置まで前記角接着部を形成したことを特徴とする半導体装置。 A support plate, a rectangular semiconductor element fixed to the upper surface of the support plate via an adhesive, and at least a part of the support plate, a resin sealing body that covers the adhesive and the semiconductor element,
The adhesive includes an interposition portion that fixes the lower surface of the semiconductor element to the upper surface of the support plate, a side surface adhesive portion that covers a plurality of side surfaces of the semiconductor element, and a corner that covers a plurality of corner portions of the semiconductor element. Having an adhesive part,
Extending the corner bonding portion from the interposition portion toward the upper surface of the semiconductor element along the corner portion,
Extending the side adhesive portion from the interposition portion toward the upper surface of the semiconductor element along the side surface,
2. The semiconductor device according to claim 1, wherein the corner bonding portion is formed up to a position higher than the side surface bonding portion.
前記側面接着部より高く且つ前記半導体素子の上面より低い位置に前記角接着部を形成した請求項１に記載の半導体装置。 The upper electrode formed on the upper surface of the semiconductor element and an external lead disposed around the support plate, a wiring conductor on the support plate or a lead fine wire that electrically connects the electrode of another element,
The semiconductor device according to claim 1, wherein the corner bonding portion is formed at a position higher than the side surface bonding portion and lower than the upper surface of the semiconductor element.
前記角接着部は、(０.６〜１)Ｈの高さ範囲で前記角部を被覆し、
前記側面接着部は、(０〜０.４)Ｈの高さ範囲で前記側面を被覆する請求項１又は２に記載の半導体装置。 When the height from the lower surface to the upper surface of the semiconductor element is H,
The corner adhesive portion covers the corner portion in a height range of (0.6-1) H,
The semiconductor device according to claim 1, wherein the side surface bonding portion covers the side surface in a height range of (0 to 0.4) H.
前記接着剤に整合して前記半導体素子を前記接着剤に載置し且つ前記半導体素子を前記支持板へ押圧して、前記接着剤を介して前記支持板と前記半導体素子とを固着する工程と、
少なくとも前記支持板の一部、接着剤及び半導体素子を樹脂封止体により被覆する工程とを含むことを特徴とする半導体装置の製法。 A step of arranging an adhesive on the upper surface of the support plate in alignment with the central portion and each corner portion of the lower surface of the semiconductor element;
Placing the semiconductor element on the adhesive in alignment with the adhesive and pressing the semiconductor element against the support plate to fix the support plate and the semiconductor element through the adhesive; ,
And a step of covering at least part of the support plate, an adhesive, and a semiconductor element with a resin sealing body.
前記接着剤を介して前記支持板と前記半導体素子とを固着する工程は、複数の前記接着剤の略中心に前記半導体素子の下面の各角部を整合して、前記半導体素子を載置する工程を含む請求項４に記載の半導体装置の製法。 The step of disposing the adhesive on the upper surface of the support plate includes the step of disposing a plurality of circular and equal amounts of the adhesive at positions matching the central portion and each corner of the lower surface of the semiconductor element,
The step of adhering the support plate and the semiconductor element through the adhesive places the semiconductor element by aligning each corner of the lower surface of the semiconductor element with the approximate center of the plurality of adhesives. The manufacturing method of the semiconductor device of Claim 4 including a process.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2006197276A JP5157098B2 (en) | 2006-07-19 | 2006-07-19 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2006197276A JP5157098B2 (en) | 2006-07-19 | 2006-07-19 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2008028040A true JP2008028040A (en) | 2008-02-07 |
| JP5157098B2 JP5157098B2 (en) | 2013-03-06 |
Family
ID=39118387
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2006197276A Expired - Fee Related JP5157098B2 (en) | 2006-07-19 | 2006-07-19 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP5157098B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013007707A (en) * | 2011-06-27 | 2013-01-10 | Hamamatsu Photonics Kk | Spectroscopic module |
| JP2015053442A (en) * | 2013-09-09 | 2015-03-19 | 三菱電機株式会社 | Semiconductor device |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS604246A (en) * | 1983-06-23 | 1985-01-10 | Toshiba Corp | Lead frame |
| JPH02241040A (en) * | 1989-03-15 | 1990-09-25 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPH03238834A (en) * | 1990-02-15 | 1991-10-24 | Citizen Watch Co Ltd | Method and device for coating of paste |
| JPH09289221A (en) * | 1996-04-22 | 1997-11-04 | Nec Corp | Bare chip mounting structure and manufacturing method thereof |
| JP2003188212A (en) * | 2001-10-11 | 2003-07-04 | Dt Circuit Technology Co Ltd | Semiconductor device and manufacturing method thereof |
| JP2005516399A (en) * | 2002-01-18 | 2005-06-02 | アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド | Method and apparatus for controlling die attach fillet height to reduce die shear stress |
| JP2007165740A (en) * | 2005-12-16 | 2007-06-28 | Hitachi Ulsi Systems Co Ltd | Method of manufacturing semiconductor device |
-
2006
- 2006-07-19 JP JP2006197276A patent/JP5157098B2/en not_active Expired - Fee Related
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS604246A (en) * | 1983-06-23 | 1985-01-10 | Toshiba Corp | Lead frame |
| JPH02241040A (en) * | 1989-03-15 | 1990-09-25 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPH03238834A (en) * | 1990-02-15 | 1991-10-24 | Citizen Watch Co Ltd | Method and device for coating of paste |
| JPH09289221A (en) * | 1996-04-22 | 1997-11-04 | Nec Corp | Bare chip mounting structure and manufacturing method thereof |
| JP2003188212A (en) * | 2001-10-11 | 2003-07-04 | Dt Circuit Technology Co Ltd | Semiconductor device and manufacturing method thereof |
| JP2005516399A (en) * | 2002-01-18 | 2005-06-02 | アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド | Method and apparatus for controlling die attach fillet height to reduce die shear stress |
| JP2007165740A (en) * | 2005-12-16 | 2007-06-28 | Hitachi Ulsi Systems Co Ltd | Method of manufacturing semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013007707A (en) * | 2011-06-27 | 2013-01-10 | Hamamatsu Photonics Kk | Spectroscopic module |
| JP2015053442A (en) * | 2013-09-09 | 2015-03-19 | 三菱電機株式会社 | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP5157098B2 (en) | 2013-03-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4746646B2 (en) | Multilayer electronic components | |
| JP5387685B2 (en) | Manufacturing method of semiconductor device | |
| US6753613B2 (en) | Stacked dice standoffs | |
| JP4785917B2 (en) | Multi-chip module manufacturing method | |
| US20060151206A1 (en) | Semiconductor device and manufacturing method therefor | |
| JP2005311321A (en) | Semiconductor device and its manufacturing method, and liquid crystal module/semiconductor module provided with the semiconductor device | |
| JP2006005333A (en) | Stacked electronic component and manufacturing method of same | |
| JP2010010301A (en) | Semiconductor device and method of manufacturing the same | |
| US20020125564A1 (en) | Semiconductor device reinforced by a highly elastic member made of a synthetic resin | |
| JP2006100752A (en) | Circuit arrangement and its manufacturing method | |
| JP4549171B2 (en) | Hybrid integrated circuit device | |
| JP2000031343A (en) | Semiconductor device | |
| US10964627B2 (en) | Integrated electronic device having a dissipative package, in particular dual side cooling package | |
| JP5157098B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP5621712B2 (en) | Semiconductor chip | |
| JP2004193363A (en) | Semiconductor device and method of manufacturing the same | |
| JP5381175B2 (en) | Semiconductor device and manufacturing method of semiconductor device | |
| JP4647673B2 (en) | Heat dissipation type multi-hole semiconductor package | |
| TW200412659A (en) | Semiconductor package with heat dissipating structure | |
| JP5058144B2 (en) | Resin sealing method for semiconductor element | |
| KR20070080324A (en) | Attaching and stacking method of semiconductor chip using polyimide layer with adhesive strength | |
| US20060108681A1 (en) | Semiconductor component package | |
| KR102365004B1 (en) | Semiconductor package and a method of manufacturing the same | |
| KR20080098797A (en) | Semiconductor package and method for manufacturing the same | |
| JP2005353704A (en) | Multilayered semiconductor device and its manufacturing method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20090629 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20100122 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20120214 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20120404 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20121113 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20121126 |
|
| R150 | Certificate of patent or registration of utility model |
Ref document number: 5157098 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20151221 Year of fee payment: 3 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| LAPS | Cancellation because of no payment of annual fees |