JP2008022597A - Dc power supply for electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To surely restrain a rush current of a power supply input circuit even if there occur the chattering of a power supply switch and a short-circuiting failure of an internal power supply. <P>SOLUTION: In this DC power supply for an electronic apparatus which is constituted in such a manner that, between an external DC power supply and an electronic capacitor C1 arranged at an input stage of an internal power supply, there are arranged a resistor R3 for restraining a rush current, and a switch circuit (DT, T2 or the like) with a delay timer which makes main switches T1 arranged at both ends of the resistor gradually brought into short-circuited states by being delayed from a time point when the external DC power supply is connected by the power-on of the power supply switch S1: the operation of the delay timer is returned to an initial state by using a comparator (CMP or the like) which detects that the power supply switch has been changed to an off-state from an on-state by comparing the level of an input voltage V1 and the level of a voltage V2, and a detection signal of the comparator circuit. The DC power supply device for the electronic apparatus includes countermeasures against the forcible off-control of the other detection circuit and the main switches, and a load-side short-circuiting failure. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a general direct current (DC) power supply for electronic equipment, and more particularly to an inrush current limiting circuit of a power input circuit.

  In many cases, power input specifications of general electronic devices are set to AC100V, DC110V, DC24V, and the like. And when supplying an electric power source to an electronic device, a mechanical switch and MCCB may be provided outside the electronic device in terms of maintenance. In addition, since most electronic devices have a relatively large capacity electrolytic capacitor attached to the power input circuit, an inrush current flows to charge the capacitor when the switch is turned on. Since the peak value of the inrush current needs to be limited due to restrictions such as the capacity of the power supply on the supply side and the switching capacity of the switch, an inrush current limiting circuit is generally provided in the power input circuit (for example, patents) Reference 1).

  8 and 11 show examples of inrush current limiting circuits in the case of DC power input. The DC power supply of FIG. 8 is delayed from the time when the inrush current limiting resistor R3 and the external DC power supply are connected between the external DC power supply (DC24V) and the electrolytic capacitor C1 provided at the input stage of the internal power supply circuit DCC. And a switch circuit for gradually short-circuiting the main switch provided at both ends of the resistor R3. In this switch circuit, a field effect transistor (FET) T1 is a main switch that short-circuits both ends of a resistor R3, a transistor T2 is an on / off control switch for T1, and a delay timer circuit DT is connected to an external DC power source from the point of connection of T2. The on-operation is delayed.

  The circuit operation of FIG. 8 will be described. FIG. 9 shows a timing chart when the switch S1 is turned on in the circuit of FIG. Immediately after the switch S1 is turned on, the transistor T1 is in the off state because the gate-source voltage VGS is 0 V, and the capacitor C1 is charged through the resistor R3. The peak value Iin1 of the inrush current at this time is expressed by the following equation.

Iin1 = V1 / R3 (1)
Further, the final value of the charging voltage V2 by the resistor R3 is as follows.

V2 = (Zi / (Zi + R3)) × V1 (2)
Here, Zi: input impedance of the power supply circuit DCC From the above formula (2), a delay time is given until the operation of the power supply circuit DCC starts, and until that time, the circuit configuration is such that the input impedance Zi of the power supply circuit is high. Thus, the charging voltage V2 by the resistor R3 can be a voltage close to V1.

  The delay timer circuit DT has a circuit configuration in which a base current is supplied to the transistor T2 after a delay time t1 after the level of V2 becomes equal to or higher than Vs (for example, V1 × 0.5). The delay timer circuit DT can be easily configured by using a general voltage detection IC, and the delay time t1 is set by a constant of the capacitor C3. Here, the delay time t1 is set to a value larger than the charging time of C1 by the resistor R3. When T2 is turned on by the delay timer circuit DT, the capacitor C2 is charged through the resistor R1, and the level of V3 gradually decreases from V1, and finally settles to the following level.

V3 = V1 × R1 / (R1 + R2) (3)
Since the difference voltage (V1-V3) is the gate-source voltage VGS of T1, the final voltage V3 level is set to a level at which T1 is completely turned on. Since the on-resistance of T1 is sufficiently smaller than the resistance R3, the voltage of V2 is charged to a level closer to V1. The reason why the change in V3 is inclined by the capacitor C2 is to limit the re-inrush current Iin3 by gradually reducing the ON resistance of the FET.

  Next, the DC power supply of FIG. 11 limits the inrush current by providing a constant current circuit between the external DC power supply (DC 24V) and the electrolytic capacitor C1 provided at the input stage of the internal power supply circuit DCC. The constant current circuit is a transistor T1 through which a main current flows, a resistor R2 interposed in series with the emitter of the transistor T1 as a main current detecting means, and the transistor T2 is used when the detected main current exceeds the current limit value. The inrush current is limited by suppressing the base current of the transistor T1.

  The circuit operation of FIG. 11 will be described. FIG. 12 shows a timing chart when the switch S1 is turned on in the circuit of FIG. When S1 is turned on, a base current flows through the transistor T1 by the resistor R1, and T1 is turned on. When a collector current of a certain value or more flows through T1, T2 is turned on by a voltage drop of R2, and the base current of T1 is reduced to limit the collector current of T1. Here, the value of the constant current is roughly determined by the following equation.

Iin1 = VBE2 / R2 (4)
Here, the base-emitter saturation voltage of VBE2: T2 This constant current value Iin1 is intended to limit the inrush current, and is set larger than the current values Iin2 and Iin3 during normal operation.
JP 2003-189464 A

  Problems of the circuit of FIG. 8 will be described. Since the switch S1 is a mechanical switch, it causes chattering when turned on and off. FIG. 10 shows the effect of chattering when the switch is turned off. When the switch S1 is turned off, the level of V2 decreases with a certain slope due to the discharge of the capacitor C1. The level of V1 is substantially the same level as V3 through the on-resistance while T1 is on. If the switch S1 is turned on again by chattering before the level of V2 falls below Vs, since T1 remains on, an excessive inrush current Iin5 that charges C1 flows through the small on-resistance of T1. become.

  Problems of the circuit of FIG. 11 will be described. Even when a short circuit or an overcurrent mode failure occurs inside, the input current is limited to a certain level or less because it is a constant current circuit. However, since almost the same voltage as V1 is applied between the collector and emitter of T1, large power consumption (about V1 × Iin1) continues in T1. This is shown in FIG. Depending on the specification of T1, a failure may occur beyond the safe operating area. After this, since T1 can also be a failure in the short-circuit mode, a large short-circuit current flows. Even in this case, the external fuse can be cut and protected, but it is not preferable that the internal fuse fails until T1. This problem may be solved by selecting an FET that can withstand the power consumption at this time for T1, but it is disadvantageous in terms of economy and product size.

  An object of the present invention is to provide a DC power supply for electronic equipment that can reliably limit the inrush current of a power input circuit even when chattering of a power switch or a short circuit failure of an internal power supply occurs.

  In order to solve the above-described problems, the present invention detects chattering of a power switch and occurrence of a short circuit failure of an internal power supply, and returns a switch circuit provided in parallel to the inrush current suppression resistor R3 to an initial state or forcibly turns it off. As described above, it has the following configuration.

(1) Between the external DC power supply and the electrolytic capacitor provided at the input stage of the internal power supply circuit, the resistance of the resistor is delayed from the time when the external DC power supply is connected by turning on the power switch and the inrush current limiting resistor. In a DC power supply for electronic equipment provided with a switch circuit with a delay timer that gradually short-circuits the main switch provided at both ends,
A comparator circuit for detecting that the power switch is changed from the on state to the off state by comparing the level of the input voltage V1 from the external DC power source and the level of the voltage V2 of the capacitor;
And a circuit for returning a delay timer operation by the switch circuit to an initial state by a detection signal of the comparator circuit.

  (2) The comparator circuit is provided with a diode in series on a power supply line between the external DC power supply and the main switch, and compares the voltage between the diode and the power switch with the voltage of the capacitor. It is characterized by.

(3) An inrush current limiting resistor is inserted between the external DC power source and the electrolytic capacitor provided in the input stage of the internal power circuit, and the resistance of the resistor is delayed from when the external DC power source is connected by turning on the power switch. In a DC power supply for electronic equipment provided with a switch circuit with a delay timer that gradually short-circuits the main switch provided at both ends,
A detection circuit for detecting that the power switch is changed from the on state to the off state by comparing the level of the input voltage V1 from the external DC power source and the level of the voltage V2 of the capacitor;
And a switch for forcibly turning off the main switch by a detection signal of the detection circuit.

  (4) In the detection circuit, a diode is provided in series on a power supply line between the external DC power supply and the main switch, and a voltage between the diode and the power switch is between the diode and the main switch. The voltage is compared.

(5) In a DC power supply for electronic equipment that limits inrush current by providing a constant current circuit between an external DC power supply and an electrolytic capacitor provided at the input stage of the internal power supply circuit,
A detection circuit for detecting from the voltage of the capacitor that an overcurrent or short-circuit mode failure has occurred on the internal power supply circuit side;
And a circuit for forcibly turning off the main switch by a detection signal of the detection circuit.

  As described above, according to the present invention, chattering of the power switch and occurrence of a short circuit failure of the internal power supply are detected, and the switch circuit provided in parallel with the inrush current suppression resistor R3 is returned to the initial state or forcibly turned off. Therefore, the inrush current of the power input circuit can be surely limited even in these phenomena. Specifically, the following effects are obtained.

  (1) In the case of the first embodiment or the second embodiment, the inrush current can be kept within the design value even if there is a chattering operation at the time of turning on and off peculiar to the external mechanical switch.

  (2) In the case of the third embodiment, even when a short-circuit mode failure occurs, the short-circuit current does not flow, the current is suppressed to a certain level or less, and the failure of the transistor of the inrush current limiting circuit is prevented. it can.

(Embodiment 1)
FIG. 1 shows a first circuit that solves the problems of the circuit of FIG. FIG. 2 shows a time chart when the switch S1 is changed from the on state to the off state in the circuit of FIG.

  In the circuit of FIG. 1, compared with the circuit of FIG. 8, comparator circuits (D1, R4 to R7, CMP for detecting that the power switch S1 is turned off from the on state by comparing the level of V1 with the level of V2). And a circuit for returning the delay timer operation of the delay timer circuit DT to the initial state according to the comparison result.

  When the switch S1 is on, the output of the comparator CMP is in the H state. When the switch S1 is turned off, the level of V2 decreases with a certain slope as in the circuit of FIG. 8, but the level of V1 is disconnected from V2 by the diode D1 in series with the power supply line, so it instantaneously drops to 0V. . In response to this, the output of the comparator CMP changes to L. In response to the change of the comparator output to L, the delay timer circuit DT cuts off the base current flowing through the transistor T2 and turns off T2. When T2 is turned off, the electric charge of the capacitor C2 is discharged through R2, the gate-source voltage VGS of T1 is reduced, and T1 is turned off.

  Here, when the switch S1 is turned on again by chattering, the output of the comparator CMP returns to H, but the delay timer circuit keeps T2 off until the timer t1 elapses. The timer value t1 is set to a value sufficiently larger than the chattering time t2, so that T1 is not turned on again by chattering. During this time, a current flows through the resistor R3, so that it can be suppressed to an inrush current or less when the switch is first turned on.

(Embodiment 2)
FIG. 3 shows a second circuit that solves the problems of the circuit of FIG. FIG. 4 shows a time chart when the switch S1 is turned off from the off state in the circuit of FIG.

  In the circuit of FIG. 3, compared to the circuit of FIG. 8, a circuit (D1, D2, R4) that detects that the power switch S1 is changed from the on state to the off state by comparing the level of the voltage V1 and the level of the capacitor voltage V2. , R5) and a transistor T3 forcing the transistor T1 to an off state by discharging the capacitor C2 when the power switch S1 is turned off.

  When the switch S1 is on, the base and emitter of the transistor T3 are at substantially the same level, and T3 is in the off state. When the switch S1 is turned off, a base current flows to the transistor T3 through the resistor R5, and T3 is turned on. Then, the electric charge of the capacitor C2 is discharged through T3, the gate-source voltage VGS of T1 becomes small, and T1 is turned off.

  When the switch S1 is turned on again by chattering, the capacitor C1 is charged through the resistor R3, and the potential of V2 rises. In addition, since T2 is kept on, the capacitor C2 is charged through the resistor R1. Depending on the time during which the switch S1 is on, T1 is turned on again and C1 is charged through T1. In the case of FIG. 8, when the switch S1 is turned on by chattering, T1 is also immediately turned on with a small on-resistance, but in the circuit of FIG. 3, it delays turning on T1 until the level of V2 rises. In addition, since the on-resistance is gradually reduced, the inrush current is limited.

  When T1 is turned on again, if the level difference between V1 and V2 is large, the peak value of the inrush current also increases. However, by adjusting the charging time of the capacitors C1 and C2, the difference between V1 and V2 when T1 is turned on again. The level difference can be reduced and the peak value of the inrush current can be suppressed.

(Embodiment 3)
FIG. 5 shows a circuit in which the problems of the circuit of FIG. 11 are solved. FIG. 6 shows a time chart when the switch S1 is turned on, and FIG. 7 shows a state when a short-circuit mode failure occurs inside.

  In the circuit of FIG. 5, compared to the circuit of FIG. 11, a voltage detection circuit (R4, R5, DET) for detecting that an overcurrent or short-circuit mode failure has occurred on the internal power supply circuit side from the level change of V2, and this voltage A transistor T3 for forcibly turning off T1 by controlling the base current of the transistor T1 by detection is added. The voltage detection circuit is a circuit that causes a base current to flow through the transistor T3 when the level of V2 becomes equal to or higher than Vs.

  When the switch S1 is turned on, the capacitor C1 is first charged through the resistor R3. When the level of V2 exceeds Vs, the transistors T3 and T1 are turned on, and a constant current flows through T1. When a short-circuit mode failure occurs internally during operation, the level of V2 drops to near 0 V, so that the supply of base current from the voltage detection circuit to T3 does not flow, and T3 and T1 are turned off. Therefore, the same current as when the switch is first turned on only flows through the transistor T1 instantaneously. After T1 is turned off, a short-circuit current (V1 / R3) flows through the resistor R3. Although this short-circuit current continuously flows through R3, since it is a resistor with a built-in fuse, the built-in fuse is melted and protected after a certain period of time.

  In practice, if the operating current of the external fuse F1 is appropriately selected, the external fuse can be blown before the internal fuse is blown.

  Note that the voltage detection circuit and the circuit for suppressing inrush current in each embodiment can be appropriately changed in design.

The circuit block diagram which shows Embodiment 1 of this invention. 3 is a time chart of the first embodiment. The circuit block diagram which shows Embodiment 2 of this invention. 4 is a time chart of the second embodiment. The circuit block diagram which shows Embodiment 3 of this invention. 10 is a time chart of the third embodiment. 10 is a time chart of the third embodiment. The conventional circuit block diagram. The time chart of a conventional circuit. The time chart of a conventional circuit. The conventional circuit block diagram. The time chart of a conventional circuit. The time chart of a conventional circuit.

Explanation of symbols

T1 field transistor (main switch)
T2, T3 Transistor R3 Inrush current limiting resistor S1 Power switch F1 Fuse C1 Electrolytic capacitor DCC Internal power supply circuit DT Delay timer circuit CMP Comparator D1, D2 Diode DET Voltage detection circuit

Claims (5)

Between the external DC power supply and the electrolytic capacitor provided at the input stage of the internal power supply circuit, provided at both ends of the resistor, delayed from the point in time when the external DC power supply is connected by turning on the power switch, and the inrush current limiting resistor In a DC power supply for electronic equipment provided with a switch circuit with a delay timer for gradually short-circuiting the main switch,
A comparator circuit for detecting that the power switch is changed from the on state to the off state by comparing the level of the input voltage V1 from the external DC power source and the level of the voltage V2 of the capacitor;
A DC power supply for electronic equipment, comprising: a circuit for returning a delay timer operation by the switch circuit to an initial state by a detection signal of the comparator circuit.   The comparator circuit is characterized in that a diode is provided in series on a power supply line between the external DC power supply and the main switch, and a voltage between the diode and the power switch is compared with a voltage of the capacitor. The DC power supply for electronic equipment according to claim 1. Between the external DC power supply and the electrolytic capacitor provided at the input stage of the internal power supply circuit, provided at both ends of the resistor, delayed from the point in time when the external DC power supply is connected by turning on the power switch, and the inrush current limiting resistor In a DC power supply for electronic equipment provided with a switch circuit with a delay timer for gradually short-circuiting the main switch,
A detection circuit for detecting that the power switch is changed from the on state to the off state by comparing the level of the input voltage V1 from the external DC power source and the level of the voltage V2 of the capacitor;
A DC power supply for electronic equipment, comprising: a switch for forcibly turning off the main switch by a detection signal of the detection circuit.   The detection circuit includes a diode in series with a power supply line between the external DC power supply and the main switch, and a voltage between the diode and the power switch and a voltage between the diode and the main switch. The DC power supply for electronic equipment according to claim 3, which is compared. In the DC power supply for electronic equipment that limits the inrush current by providing a constant current circuit between the external DC power supply and the electrolytic capacitor provided at the input stage of the internal power supply circuit,
A detection circuit for detecting from the voltage of the capacitor that an overcurrent or short-circuit mode failure has occurred on the internal power supply circuit side;
And a circuit for forcibly turning off the main switch by a detection signal of the detection circuit.

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