JP2008019501A - Method of wafer plating - Google Patents

Method of wafer plating Download PDF

Info

Publication number
JP2008019501A
JP2008019501A JP2006339379A JP2006339379A JP2008019501A JP 2008019501 A JP2008019501 A JP 2008019501A JP 2006339379 A JP2006339379 A JP 2006339379A JP 2006339379 A JP2006339379 A JP 2006339379A JP 2008019501 A JP2008019501 A JP 2008019501A
Authority
JP
Japan
Prior art keywords
plating
wafer
anode electrode
current
peripheral
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2006339379A
Other languages
Japanese (ja)
Other versions
JP4976120B2 (en
Inventor
Yuji Uchiumi
裕二 内海
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
EEJA Ltd
Original Assignee
Electroplating Engineers of Japan Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Electroplating Engineers of Japan Ltd filed Critical Electroplating Engineers of Japan Ltd
Priority to JP2006339379A priority Critical patent/JP4976120B2/en
Priority to TW096118953A priority patent/TWI363107B/en
Priority to US11/809,479 priority patent/US20070289873A1/en
Priority to KR1020070055348A priority patent/KR100900608B1/en
Publication of JP2008019501A publication Critical patent/JP2008019501A/en
Application granted granted Critical
Publication of JP4976120B2 publication Critical patent/JP4976120B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D17/00Constructional parts, or assemblies thereof, of cells for electrolytic coating
    • C25D17/001Apparatus specially adapted for electrolytic coating of wafers, e.g. semiconductors or solar cells
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D17/00Constructional parts, or assemblies thereof, of cells for electrolytic coating
    • C25D17/005Contacting devices
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D17/00Constructional parts, or assemblies thereof, of cells for electrolytic coating
    • C25D17/10Electrodes, e.g. composition, counter electrode
    • C25D17/12Shape or form
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/94Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00Electroplating characterised by the article coated
    • C25D7/12Semiconductors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/1147Manufacturing methods using a lift-off mask
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/741Apparatus for manufacturing means for bonding, e.g. connectors
    • H01L2224/742Apparatus for manufacturing bump connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01018Argon [Ar]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01022Titanium [Ti]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01074Tungsten [W]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01077Iridium [Ir]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3025Electromagnetic shielding

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technique for wafer plating treatment by which plating film thickness can be made uniform on the total area of a plated wafer surface. <P>SOLUTION: This method of wafer plating includes: arranging a wafer in an opening of a plating tank; bringing a peripheral side of the wafer and a cathode electrode into contact with each other; supplying a plating liquid; causing the plating liquid that has reached the wafer to flow in the direction of a periphery of a wafer surface to be plated; and supplying a plating current by an anode electrode arranged within the plating tank so as to be opposed to the wafer and the cathode electrode, whereby the wafer is subjected to plating treatment. In this method, the anode electrode has a shape almost the same as the wafer surface to be plated, a plurality of peripheral-edge current supplying sections are provided in the peripheral edge of the anode electrode, and a central current supplying section is provided in the center of the anode electrode. A peripheral-edge plating current supplied from the peripheral-edge current supplying sections and a central plating current supplied from the central current supplying section can be adjusted. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は半導体用のウェハーのめっき処理に関するものである。   The present invention relates to a plating process for semiconductor wafers.

従来、半導体用のウェハーにめっき処理をする場合、めっき槽の開口部へ、カソード電極に接触したウェハーを配置し、このウェハーに向けてめっき液を供給し、ウェハーに到達しためっき液がウェハーの被めっき表面の外周方向に流動させるようにして、めっき槽内にウェハーと対向させて配置したアノード電極と前記カソード電極とによってめっき電流を供給してめっきを施すウェハーめっき方法が知られている。このウェハーめっき方法は、めっき槽の開口部に対してウェハーを交換することにより、順次めっき処理が行える点から、小ロットの生産やめっき処理工程の自動化に好適なものとして広く用いられているものである。このウェハーのめっき処理では、ウェハーの被めっき面全面で膜厚を均一にすることが重要であり、この膜厚の均一性を向上させるための種々の改善が提案されている。   Conventionally, when a semiconductor wafer is plated, a wafer in contact with the cathode electrode is placed in the opening of the plating tank, a plating solution is supplied toward the wafer, and the plating solution that reaches the wafer is removed from the wafer. A wafer plating method is known in which plating is performed by supplying a plating current between the anode electrode and the cathode electrode, which are arranged to face a wafer in a plating tank so as to flow in the outer peripheral direction of the surface to be plated. This wafer plating method is widely used as suitable for small lot production and automation of the plating process because it can be sequentially plated by replacing the wafer to the opening of the plating tank. It is. In this wafer plating process, it is important to make the film thickness uniform over the entire surface to be plated of the wafer, and various improvements for improving the film thickness uniformity have been proposed.

例えば、めっき電流の局部的な集中によって、ウェハーの被めっき面全面で均一な膜厚を実現できない場合に対して、膜厚のバラツキに合わせた遮蔽板などをめっき槽内に配置することにより、めっき電流の集中を緩和させる対策が知られている(特許文献1)。また、カソード電極側の対策としては、ウェハーの周縁に接触させるカソード電極を分割して、均一な電析を被めっき面全面に行われるように、分割したカソード電極とアノード電極とにより、カレントミラー回路を形成する対策が知られている(特許文献2)。さらに、アノード電極側においては、ウェハーに対向配置させるアノード電極を、相互に絶縁領域を有するように、周辺アノード電極と中央アノード電極とに複数分割し、中央アノード電極へのめっき処理の通電時間を周辺アノード電極へのめっき処理の通電時間よりも小さくして、めっき厚みを制御する方法が知られている(特許文献3)。これらの先行技術によれば、ある程度の均一性がある膜厚で、ウェハーの被めっき面にめっき処理を行うことが可能となる。
特開平8−74088号公報 特開2001−115297号公報 特開平7−197299号公報
For example, when a uniform film thickness cannot be realized over the entire surface to be plated of the wafer due to local concentration of plating current, by arranging a shielding plate or the like in accordance with the film thickness variation in the plating tank, A countermeasure for reducing the concentration of plating current is known (Patent Document 1). As a countermeasure on the cathode electrode side, the cathode electrode to be contacted with the peripheral edge of the wafer is divided, and the divided cathode electrode and the anode electrode are used so that uniform electrodeposition is performed on the entire surface to be plated. A countermeasure for forming a circuit is known (Patent Document 2). Furthermore, on the anode electrode side, the anode electrode arranged opposite to the wafer is divided into a plurality of peripheral anode electrodes and a central anode electrode so as to have an insulating region, and the energization time of the plating process to the central anode electrode is increased. A method of controlling the plating thickness by making it shorter than the energization time of the plating treatment to the peripheral anode electrode is known (Patent Document 3). According to these prior arts, it is possible to perform plating on the surface to be plated of the wafer with a film thickness having a certain degree of uniformity.
JP-A-8-74088 JP 2001-115297 A JP-A-7-197299

しかしながら、めっき槽内に遮蔽板を配置したり、アノード電極を分割するような対策を行うことは、めっき装置構造を複雑にし、ウェハーの口径が変わった場合には、その都度、その口径に合わせた調整、即ち、遮蔽板のサイズ変更や、アノード電極の分割形状など調整をする必要がある。また、アノード電極を分割し個別に制御するためには、整流器を複数準備することなどのコスト面においてもデメリットがある。そのため、ウェハーのめっき処理を行う際には、より簡単なめっき装置構造で、めっき装置のメインテナンスを含め、より簡易な対策で均一な膜厚を実現できるめっき処理技術が要望されている。   However, taking measures such as placing a shielding plate in the plating tank or dividing the anode electrode complicates the structure of the plating apparatus, and if the wafer diameter changes, it is necessary to match the diameter each time. In other words, it is necessary to adjust the size of the shielding plate and the divided shape of the anode electrode. Further, in order to divide the anode electrode and control it separately, there is a demerit in terms of cost such as preparing a plurality of rectifiers. Therefore, when performing the plating process of a wafer, there is a demand for a plating process technique that can realize a uniform film thickness with a simpler measure, including maintenance of the plating apparatus, with a simpler plating apparatus structure.

また、分割したカソード電極により、ウェハーに均一な電析が行えるようにめっき電流を供給する対策では、ウェハーの周辺部分におけるめっき処理の制御は可能なものの、ウェハーの中央部を含めた被めっき面全面においての膜厚制御については十分なものとはいえなかった。   In addition, with the measures to supply plating current so that uniform electrodeposition can be performed on the wafer by the divided cathode electrode, the plating process in the peripheral part of the wafer can be controlled, but the surface to be plated including the central part of the wafer It could not be said that the film thickness control over the entire surface was sufficient.

さらに、最近の半導体業界においては、ウェハーサイズの大口径、例えば12インチ(約300mm)径のものが登場しており、このような大口径のウェハーに対し、被めっき面全面で、より均一な膜厚を容易に実現できるめっき処理技術が強く求められているのが現状である。   Furthermore, in the recent semiconductor industry, a wafer size having a large diameter, for example, 12 inches (about 300 mm) diameter has appeared. For such a large diameter wafer, the entire surface to be plated is more uniform. At present, there is a strong demand for a plating technique that can easily realize the film thickness.

そこで、本発明は、従来のウェハーのめっき処理技術を改善し、大口径のウェハーであっても、被めっき面全面で均一な膜厚のめっきを行えるウェハーのめっき方法を提供せんとするものである。   Therefore, the present invention is to improve the conventional wafer plating process technology, and to provide a wafer plating method capable of plating a uniform film thickness on the entire surface to be plated even for a large-diameter wafer. is there.

上記課題を解決すべく、本発明は、めっき槽の開口部にウェハーを配置し、ウェハー外周側とカソード電極とを接触させ、めっき液を供給し、ウェハーに到達しためっき液がウェハーの被めっき表面の外周方向に流動させるようにして、めっき槽内にウェハーと対向させて配置したアノード電極と前記カソード電極とによってめっき電流を供給して、ウェハーにめっき処理を行うウェハーめっき方法において、前記アノード電極は、ウェハーの被めっき面と略同一形状とし、アノード電極の周縁へ複数の周縁電流供給部を設けるとともに、アノード電極の中央へ中央電流供給部を設け、前記周縁電流供給部から供給する周縁めっき電流と、中央電流供給部から供給する中央めっき電流とを調整するものとした。このめっき方法によれば、めっき槽内に遮蔽板を配置したり、めっき装置を特別な構造に改造する必要もなく、ウェハーの被めっき面全面において均一な膜厚のめっき処理を行うことが可能となる。   In order to solve the above-mentioned problems, the present invention arranges a wafer in the opening of the plating tank, brings the wafer outer peripheral side into contact with the cathode electrode, supplies the plating solution, and the plating solution reaching the wafer is plated on the wafer. In a wafer plating method, in which a plating current is supplied by an anode electrode and a cathode electrode arranged to face a wafer in a plating tank so as to flow in the outer peripheral direction of the surface, and the wafer is plated, The electrode has substantially the same shape as the surface to be plated of the wafer, a plurality of peripheral current supply portions are provided at the periphery of the anode electrode, a central current supply portion is provided at the center of the anode electrode, and the peripheral edge supplied from the peripheral current supply portion The plating current and the central plating current supplied from the central current supply unit were adjusted. According to this plating method, there is no need to arrange a shielding plate in the plating tank or to modify the plating equipment to a special structure, and it is possible to perform plating processing with a uniform film thickness on the entire surface to be plated of the wafer. It becomes.

本発明のウェハーめっき方法における、複数の周縁電流供給部は、少なくとも3カ所以上、より好ましくは4カ所以上設けることが望ましい。また、この周縁電流供給部の数をあまり多く設けても、膜厚の均一性に寄与する効果が減少する傾向となる。めっき処理をする大口径のウェハーなどを考慮すると、周縁電流供給部は10カ所以下にすることが望ましい。実用的には、4カ所から8カ所の周縁電流供給部を設けることが好ましい。   In the wafer plating method of the present invention, it is desirable to provide a plurality of peripheral current supply units at least three or more, more preferably four or more. Further, even if the number of peripheral current supply portions is too large, the effect of contributing to the uniformity of the film thickness tends to decrease. Considering a large-diameter wafer to be plated, it is desirable that the peripheral current supply unit be 10 places or less. Practically, it is preferable to provide 4 to 8 peripheral current supply units.

本発明のウェハーめっき方法における、アノード電極における周縁めっき電流と中央電流供給部から供給する中央めっき電流との調整は、総めっき電流を分配することである。つまり、アノード電極に供給する総めっき電流のうち、所定割合のめっき電流を中央電流供給部に供給し、その残り分に相当するめっき電流を周縁電流供給部に割り当てるのである。例えば、ウェハーの被めっき面中央付近が周辺部分よりも厚めの膜厚でめっき処理される場合、総めっき電流のうち、4割を中央電流供給部に供給し、残りの6割を周縁電流供給部に割り当てて供給するようにする。このめっき電流の調整割合は、不均一となっためっき厚み状態に併せて適宜決定すればよい。供給する電流調整は、中央と周縁とで供給する電流値自体を異なるように設定する方法や、中央と周縁とのめっき処理時間(通電時間)を異なるようにする方法などを採用することができる。   In the wafer plating method of the present invention, the adjustment of the peripheral plating current in the anode electrode and the central plating current supplied from the central current supply unit is to distribute the total plating current. In other words, a predetermined proportion of the total plating current supplied to the anode electrode is supplied to the central current supply unit, and the plating current corresponding to the remainder is assigned to the peripheral current supply unit. For example, if the wafer is plated at a thickness near the center of the surface to be plated with a thickness greater than that of the peripheral portion, 40% of the total plating current is supplied to the central current supply unit, and the remaining 60% is supplied to the peripheral current. Allotted to the department. What is necessary is just to determine suitably the adjustment ratio of this plating current according to the plating thickness state which became non-uniform | heterogenous. As the current adjustment to be supplied, a method of setting the current value itself to be different between the center and the periphery, a method of making the plating treatment time (energization time) between the center and the periphery different, or the like can be adopted. .

また、本発明のウェハーめっき方法では、平板からなるアノード電極を用いて、該平板に複数の穿孔を設け、めっき電流分布を調整することが好ましい。平板のアノード電極に、複数の穿孔をするとその穿孔内をめっき液が通過することになるが、その穿孔の数や形成位置を調整することにより、ウェハーの被めっき面におけるめっき電流分布を調整することが可能となる。アノード電極へのめっき電流の供給を調整するとともに、めっき電流分布を調整することで、より均一性な膜厚のめっき処理が可能となる。   In the wafer plating method of the present invention, it is preferable to use a flat anode plate and provide a plurality of perforations on the flat plate to adjust the plating current distribution. When a plurality of perforations are made in the flat plate anode electrode, the plating solution passes through the perforations. By adjusting the number and positions of the perforations, the plating current distribution on the surface to be plated of the wafer is adjusted. It becomes possible. By adjusting the supply of the plating current to the anode electrode and adjusting the plating current distribution, a plating process with a more uniform film thickness can be performed.

そして、本発明のウェハーめっき方法においては、チタニウム製の電極基材上に、中間層として白金被膜と、その中間層表面に酸化イリジウム被膜とが設けられたアノード電極を採用することが好ましい。このような構造のアノード電極を用いると、電極コストの大幅な増加を抑制しつつ、めっき厚みの均一性の向上を図ることが実現でき、めっき液に対する耐食性も優れているため、めっき液の安定性も維持(電解めっき処理においてめっき液を破壊しない性質)できる。特に、ウェハーに金めっき処理を行う場合、このような構造のアノード電極であると、長時間の金めっき処理を行っても、電極表面に金の析出が生じなく、電極のメンテナンスも容易となる。   And in the wafer plating method of this invention, it is preferable to employ | adopt the anode electrode by which the platinum film and the iridium oxide film were provided in the intermediate | middle layer surface on the electrode base material made from titanium. By using the anode electrode with such a structure, it is possible to improve the uniformity of the plating thickness while suppressing a significant increase in the electrode cost, and the corrosion resistance against the plating solution is also excellent. It is also possible to maintain the property (a property that does not destroy the plating solution in the electrolytic plating process). In particular, when a gold plating process is performed on a wafer, the anode electrode having such a structure does not cause gold deposition on the electrode surface even if the gold plating process is performed for a long time, and the maintenance of the electrode is facilitated. .

以上説明したように、本発明によれば、大口径のウェハーであっても、めっき装置の構造を大幅に変更することもなく、ウェハーの被めっき面全面において均一な膜厚のめっき処理が可能となる。   As described above, according to the present invention, even a large-diameter wafer can be plated with a uniform film thickness over the entire surface to be plated without significantly changing the structure of the plating apparatus. It becomes.

第一実施形態:以下、本発明の一実施形態を説明する。図1は本実施形態におけるカップ型めっき装置のめっき槽断面の概略を表したものである。図1で示すように、本実施形態のカップ型のめっき装置1は、めっき槽2の開口部に沿ってウェハーWを載置できるようになっており、ウェハーWの外周部3と接触するようにリング状のカソード電極Cが配置されている。カソード電極Cの下には、めっき液の漏洩防止用のシールパッキン4が配置されている。 First embodiment: An embodiment of the present invention will be described below. FIG. 1 shows an outline of a cross section of a plating tank of a cup type plating apparatus in the present embodiment. As shown in FIG. 1, the cup-type plating apparatus 1 of the present embodiment is configured so that the wafer W can be placed along the opening of the plating tank 2 so as to come into contact with the outer peripheral portion 3 of the wafer W. A ring-shaped cathode electrode C is disposed on the surface. Under the cathode electrode C, a seal packing 4 for preventing leakage of the plating solution is disposed.

めっき槽2には、底部中央にめっき液供給口5が設けられており、開口部2に載置されたウェハーWに向けて上昇流で供給されためっき液がめっき槽2の外部に流出できるようにしためっき液流出口6とが設けられている。さらに、めっき槽2の底側には、載置されたウェハーWと対向するようにアノード電極Aが設置されている。   The plating tank 2 is provided with a plating solution supply port 5 at the center of the bottom, and the plating solution supplied in an upward flow toward the wafer W placed in the opening 2 can flow out of the plating tank 2. A plating solution outlet 6 is provided. Furthermore, an anode electrode A is installed on the bottom side of the plating tank 2 so as to face the mounted wafer W.

この図1に示すアノード電極Aの平面拡大概略図を図2に示す。アノード電極Aは、複数の穿孔10が設けられており、この穿孔10をめっき液が流通できるようにされている。また、このアノード電極Aは、円板状の電極母材Ti上にPtめっき(厚さ0.5〜2μm)をし、そのPtの上にさらにIr(厚み1〜2μm)をめっきした後、電気炉によって大気雰囲気中で熱処理を行うことにより、酸化イリジウム(IrO)が電極表面を被覆されたものを使用した(特許文献特開2006−22379号公報参考)。 FIG. 2 shows an enlarged schematic plan view of the anode electrode A shown in FIG. The anode electrode A is provided with a plurality of perforations 10 through which a plating solution can flow. In addition, the anode electrode A is obtained by performing Pt plating (thickness 0.5 to 2 μm) on the disk-shaped electrode base material Ti and further plating Ir (thickness 1 to 2 μm) on the Pt. A material in which the electrode surface was coated with iridium oxide (IrO 2 ) by performing heat treatment in an air atmosphere with an electric furnace was used (see Japanese Patent Application Laid-Open No. 2006-22379).

さらに、アノード電極Aについては、その周縁の4カ所に周縁電流供給端子(ar1〜ar4)と、中央部に中央電流供給端子(ac)とが設けられており、これら各端子をめっき電流供給電源(図示せぬ)に接続した。尚、リング状のカソード電極Cについては、電極の周辺4カ所に設けられた接続端子をめっき電流供給電源に接続した。   Further, the anode electrode A is provided with peripheral current supply terminals (ar1 to ar4) at four positions on the peripheral edge and a central current supply terminal (ac) at the center, and these terminals are connected to a plating current supply power source. (Not shown). For the ring-shaped cathode electrode C, connection terminals provided at four locations around the electrode were connected to a plating current supply power source.

次に、上記した本実施形態におけるカップ型めっき装置によるウェハーめっき処理評価試験を行った結果について説明する。この試験では、直径8インチ(約200mm)のウェハーの被めっき面にTiW膜(3000Å)とその表面にAuのシード金属膜(1000Å)が施されたシード金属付きウェハーを使用した。アノード電極Aについては、直径204mm、厚さ1mmのTi製円板に、Ptめっき及びIrめっきを施し、熱処理した後、直径8mmの穿孔を161箇所に電極全面へ均等に形成したものを使用した(特開2006−22379号公報参照)。   Next, the result of performing the wafer plating treatment evaluation test by the cup type plating apparatus in the above-described embodiment will be described. In this test, a wafer with a seed metal having a TiW film (3000 mm) on the surface to be plated of an 8-inch diameter wafer (about 200 mm) and an Au seed metal film (1000 mm) on the surface thereof was used. For the anode electrode A, a Ti disk having a diameter of 204 mm and a thickness of 1 mm was subjected to Pt plating and Ir plating, heat-treated, and then 8 mm diameter perforations were uniformly formed at 161 locations on the entire surface of the electrode. (Refer to Unexamined-Japanese-Patent No. 2006-22379).

めっき処理は、ノンシアン系で、弱アルカリ性の高純度金めっき液を使用した(日本エレクトロプレイティングエンジニヤース製、製品名MICOFAB Au660)。この金めっき液によるめっき条件は、液温60℃、pH7〜8、めっき電流密度0.8A/dmで、膜厚18μmを目標めっき厚として行った。また、ウェハーのシード金属膜表面には、厚み25μmのレジストを被覆し、液晶用の角柱状バンプを複数形成する際に用いるバンプ形成用パターン(開口総面積0.35dm)をレジストに形成したものをめっき処理した。そして、めっき処理の際のアノード電極における周縁めっき電流値(ar1〜ar4の4端子の合計めっき電流値)と中央めっき電流値とが3:7の割合になるように、めっき電流供給量を調節した。この供給量の割合は、予め、中央めっき電流値と周縁めっき電流値との供給量がアノード電極全体で均等になるようにめっき電流の供給量を設定してめっき処理したウェハーを作製し、そのウェハーのめっき厚みを調べ、中央付近と周縁部分のめっき厚みを比較することにより決定した。また、周縁めっき電流値(ar1〜ar4の4端子の合計めっき電流値)と中央めっき電流値とのめっき電流供給量の割合調整は、先に中央めっき電流のみを所定時間供給した後に、中央めっき電流を供給しない状態で、周辺めっき電流を所定時間供給することにより行った。 For the plating treatment, a non-cyan, weakly alkaline high-purity gold plating solution was used (manufactured by Nippon Electroplating Engineers, product name MICOFAB Au660). Plating conditions using this gold plating solution were a solution temperature of 60 ° C., pH 7 to 8, a plating current density of 0.8 A / dm 2 , and a film thickness of 18 μm as a target plating thickness. The surface of the seed metal film of the wafer was coated with a resist having a thickness of 25 μm, and a bump forming pattern (total opening area 0.35 dm 2 ) used when forming a plurality of prismatic bumps for liquid crystal was formed on the resist. The thing was plated. Then, the plating current supply amount is adjusted so that the peripheral plating current value (total plating current value of the four terminals ar1 to ar4) and the central plating current value in the anode electrode during the plating process are in a ratio of 3: 7. did. Proportion of this supply amount is prepared in advance by preparing a plating-processed wafer by setting the supply amount of the plating current so that the supply amount of the central plating current value and the peripheral plating current value is uniform over the entire anode electrode. It was determined by examining the plating thickness of the wafer and comparing the plating thickness near the center and the peripheral portion. Moreover, the ratio adjustment of the plating current supply amount between the peripheral plating current value (the total plating current value of the four terminals ar1 to ar4) and the central plating current value is performed after the central plating current only is supplied for a predetermined time before the central plating. This was performed by supplying a peripheral plating current for a predetermined time without supplying current.

比較のために、図1に示したカップ型めっき装置において、アノード電極として、Ti製のメッシュ形状(直径204mmのエキスパンドメタル、長軸約11mm、短軸約8mm菱形開口)のものに、Ptめっき(厚み4μm)を施したものを使用して、金めっき処理を行った。このメッシュ状のアノード電極については、その周縁の1カ所(図2のar1に相当する位置)にめっき電流供給用端子が設けられており、この1カ所の端子よりアノード電極にめっき電流を供給するようにした。その他のめっき処理条件については、上記と同様にした。   For comparison, in the cup-type plating apparatus shown in FIG. 1, Pt plating is applied to an anode electrode having a Ti mesh shape (expanded metal with a diameter of 204 mm, long axis of about 11 mm, short axis of about 8 mm rhombus opening). A gold plating treatment was performed using a material having a thickness of 4 μm. The mesh-like anode electrode is provided with a plating current supply terminal at one position (a position corresponding to ar1 in FIG. 2) at the periphery thereof, and the plating current is supplied to the anode electrode from the one terminal. I did it. Other plating treatment conditions were the same as described above.

めっき処理試験の評価は、めっき処理後のウェハーのレジストを剥離して、角柱状バンプの高さ(めっき厚み)を測定することにより行った。このバンプ高さ(めっき厚)は、被めっき面側に形成されたバンプを触針式段差測定器(KLA−Tencor P11)を用いて測定した。具体的には、図3に示すようにウェハーの被めっき面中心及びその周辺部分に形成された角柱状バンプについて、合計13カ所のバンプ高さ(W1〜W13)を測定した。表1には、このバンプ高さ測定結果より得られた、平均値(Avg.)、最大値(MAX.)、最小値(MIN.)、バラツキ幅(Range.)、バラツキ幅(Range.)/平均値(Avg.)を示す。尚、表1に示す平均値(Avg.)、最大値(MAX.)、最小値(MIN.)、バラツキ幅(Range.)の単位はμmであり、バラツキ幅(Range.)/平均値(Avg.)の単位は%である。   Evaluation of the plating treatment test was performed by peeling the resist of the wafer after the plating treatment and measuring the height (plating thickness) of the prismatic bumps. The bump height (plating thickness) was measured by using a stylus type step measuring instrument (KLA-Tencor P11) for the bump formed on the surface to be plated. Specifically, as shown in FIG. 3, the bump heights (W1 to W13) at a total of 13 locations were measured for the prismatic bumps formed at the center of the surface to be plated of the wafer and the peripheral portion thereof. Table 1 shows the average value (Avg.), Maximum value (MAX.), Minimum value (MIN.), Variation width (Range.), Variation width (Range.) Obtained from the bump height measurement results. / Indicates an average value (Avg.). The unit of the average value (Avg.), Maximum value (MAX.), Minimum value (MIN.), And variation width (Range.) Shown in Table 1 is μm, and the variation width (Range.) / Average value ( The unit of Avg.) Is%.

Figure 2008019501
Figure 2008019501

表1に示す実施例がアノード電極周縁の4カ所と中央からめっき電流供給を行った結果であり、比較例がメッシュ状アノード電極周縁の1カ所からめっき電流を行った結果を示している。この結果より、実施例の方が比較例に比べ、最大値と最小値との差、即ち、膜厚のバラツキ幅(Range.)が大幅に小さくなっていることが判明した。また、Range./Avg.値(バラツキ幅を平均値で割った値)は、実施例が明らかに小さい値を示しており、めっき厚みの均一性の極めて高いめっき処理であることが確認された。   The example shown in Table 1 is the result of supplying the plating current from four places and the center of the periphery of the anode electrode, and the comparative example shows the result of performing the plating current from one place of the periphery of the mesh-like anode electrode. From this result, it was found that the difference between the maximum value and the minimum value, that is, the variation width (Range) of the film thickness was significantly smaller in the example than in the comparative example. Also, Range. / Avg. The value (the value obtained by dividing the variation width by the average value) clearly shows a small value in the example, and it was confirmed that the plating treatment had extremely high plating thickness uniformity.

また、比較例では、アノード電極の1カ所に設けた電流供給用の端子部分に相当するウェハー被めっき面の部分が、極端に厚くめっき処理されており、このことがめっき厚みのバラツキ幅を大きくしていたことが判った。これに対し、実施例の場合では、ウェハー被めっき面の外周付近のめっき厚みも均一に処理されていることが判明した。また、本実施例では、カソード電極側の電流供給を分割しては行っていないが、このカソード電極側の電流供給を分割すること、具体的には、めっき電流の供給の際に、上記特許文献2のようなカソード電極側の分割供給方法と、本実施例のアノード電極側の分割供給方法とを組み合わせて、めっき電流の供給を制御することで、ウェハー被めっき面全面におけるめっき厚みの均一性の向上、特に被めっき面の外周付近のめっき厚みの均一性を向上させることが可能とである。   Further, in the comparative example, the portion of the wafer plating surface corresponding to the current supply terminal portion provided at one place of the anode electrode is subjected to extremely thick plating treatment, which increases the variation width of the plating thickness. I found out that I was doing. On the other hand, in the case of the example, it was found that the plating thickness near the outer periphery of the surface to be plated was uniformly processed. Further, in this embodiment, the current supply on the cathode electrode side is not divided, but the current supply on the cathode electrode side is divided, specifically, when the plating current is supplied, the above-mentioned patent Uniform plating thickness over the entire surface to be plated by controlling the supply of plating current by combining the divided supply method on the cathode electrode side as in Document 2 and the divided supply method on the anode electrode side in this embodiment. In particular, it is possible to improve the uniformity of the plating thickness in the vicinity of the outer periphery of the surface to be plated.

第二実施形態:続いて、本発明のもう一つの実施形態について説明する。この第二実施形態では、上記第一実施形態と同じ構造のカップ型めっき装置(図1)を使用した。但し、この第二実施形態のめっき装置は、ウェハーサイズが12インチ径(約300mm径)のものを処理できるものである。また、使用したアノード電極Aは、直径294mm、厚さ2mmのTi製円板に、Ptめっき及びIrめっきを施し、熱処理した後、直径10mmの穿孔を361箇所に電極全面へ均等に形成したものを使用した(アノード電極Aの製造方法については上記第一実施形態と同様)。また、このアノード電極Aについては、図4に示すように、周縁の6カ所へ均等な間隔で設けた周縁電流供給端子(ATR、AR、ABR、ATL、AL、ABL)と、中央部に中央電流供給端子(AC)とを設け、これら各端子をめっき電流供給電源(図示せぬ)に接続した。尚、リング状のカソード電極Cについては、上記第一実施形態と同様に、リング状カソード電極Cの周辺7カ所に設けられた接続端子をめっき電流供給電源に接続した。また、アノード電極Aと対向するウェハーとの距離、即ち、極間距離は21mmとした。 Second Embodiment: Next, another embodiment of the present invention will be described. In the second embodiment, a cup type plating apparatus (FIG. 1) having the same structure as that of the first embodiment is used. However, the plating apparatus according to the second embodiment can process a wafer having a 12-inch diameter (about 300 mm diameter). The anode electrode A used was a Ti disk having a diameter of 294 mm and a thickness of 2 mm, which was subjected to Pt plating and Ir plating, heat-treated, and then 10 mm diameter perforations were uniformly formed on the entire surface of the electrode at 361 locations. (The manufacturing method of the anode electrode A is the same as in the first embodiment). Further, as shown in FIG. 4, the anode electrode A has peripheral current supply terminals (ATR, AR, ABR, ATL, AL, ABL) provided at equal intervals at six peripheral positions, and a central portion at the center. A current supply terminal (AC) was provided, and each of these terminals was connected to a plating current supply power source (not shown). For the ring-shaped cathode electrode C, connection terminals provided at seven locations around the ring-shaped cathode electrode C were connected to a plating current supply power source, as in the first embodiment. The distance between the anode electrode A and the facing wafer, that is, the distance between the electrodes was 21 mm.

次に、上記した本実施形態におけるカップ型めっき装置によるウェハーめっき処理評価試験を行った結果について説明する。この試験では、直径12インチ(約300mm)のウェハーの被めっき面にTiW膜(3000Å)とその表面にAuのシード金属膜(1000Å)が施されたシード金属付きウェハーを使用し、その表面に所定形状の金バンプを形成し、形成された金バンプ高さを測定して、めっき処理の均一性を調査した。そして、本試験では、二種類の金バンプを形成して、それぞれ評価した。一つは、角柱状で、目標バンプ高さ23μmのバンプを、ウェハー表面状に複数個形成(ウェハー表面上におけるバンプ形成総面積約0.1dm:バンプ<ア>と称す)するものである。他の一つは、同じく角柱状で、目標バンプ高さ16μmのバンプを、ウェハー表面状に複数個形成(ウェハー表面上におけるバンプ形成総面積約1.0dm:バンプ<イ>と称す)するものである。この二種類のバンプは、目標バンプ高さから2μmの範囲内(バンプ高さを測定した総てのバンプの内の最大値と最小値との差が2μm以内であること)で形成されていることを製品スペックとして要求されているものである。 Next, the result of performing the wafer plating treatment evaluation test by the cup type plating apparatus in the above-described embodiment will be described. In this test, a wafer with a seed metal having a TiW film (3000 mm) on the surface to be plated of a wafer having a diameter of 12 inches (about 300 mm) and an Au seed metal film (1000 mm) on the surface is used. A gold bump having a predetermined shape was formed, and the height of the formed gold bump was measured to investigate the uniformity of the plating process. In this test, two types of gold bumps were formed and evaluated. One is to form a plurality of bumps having a prismatic shape and a target bump height of 23 μm on the surface of the wafer (total bump formation area on the wafer surface is about 0.1 dm 2 : referred to as bump <a>). . The other is the same prismatic shape, and a plurality of bumps with a target bump height of 16 μm are formed on the surface of the wafer (total bump formation area on the wafer surface is about 1.0 dm 2 : referred to as bump <A>). Is. These two types of bumps are formed within a range of 2 μm from the target bump height (the difference between the maximum value and the minimum value of all the bumps whose bump heights are measured is within 2 μm). This is required as product specifications.

バンプ形成を行う金めっき処理は、上記第一実施形態と同じ金めっき液を使用した。めっき条件は、液温60℃、pH7〜8、めっき電流密度0.8A/dmとした。また、ウェハーのシード金属膜表面には、各バンプ高さに合わせた所定厚みのレジストを被覆し、角柱状バンプを複数形成するためのバンプ形成用パターンをレジストに形成し、その後金めっき処理をした。 The same gold plating solution as in the first embodiment was used for the gold plating treatment for forming the bumps. The plating conditions were a liquid temperature of 60 ° C., a pH of 7 to 8, and a plating current density of 0.8 A / dm 2 . Also, the surface of the seed metal film of the wafer is coated with a resist having a predetermined thickness according to each bump height, and a bump forming pattern for forming a plurality of prismatic bumps is formed on the resist, and then gold plating treatment is performed. did.

めっき処理時のアノード電極に対するめっき電流の供給は次のような方法によって行った。具体的には、図4に示すアノード電極の周辺の6カ所すべてからめっき電流を供給する場合(第1方式)、図4に示すATLの1カ所から供給する場合(第2方式)、図4のABR、ABLの2カ所から供給する場合(第3方式)、図4のAC、即ち、アノード電極の中央部の1カ所から供給する場合(第4方式)
、の4種類のめっき電流供給方法によって、金バンプの形成を行った。
The plating current was supplied to the anode electrode during the plating process by the following method. Specifically, when supplying plating current from all six locations around the anode electrode shown in FIG. 4 (first method), supplying from one ATL location shown in FIG. 4 (second method), FIG. When supplying from two locations of ABR and ABL (third method), when supplying from AC in FIG. 4, that is, from one central portion of the anode electrode (fourth method)
Gold bumps were formed by the four plating current supply methods.

めっき処理試験の評価は、上記第一実施形態の場合と同様に、めっき処理後、レジストを剥離して、角柱状バンプの高さ(めっき厚み)を測定することにより行った。バンプ高さ(めっき厚)は、被めっき面側に形成された金バンプを触針式段差測定器(KLA−Tencor P11)を用いて測定した。具体的には、図3に示したようにウェハーの被めっき面中心及びその周辺部分に形成された角柱状バンプについて、合計13カ所のバンプ高さ(W1〜W13)を測定した。表2には、このバンプ高さ測定結果より得られた、平均値(Avg.)、最大値(MAX.)、最小値(MIN.)、バラツキ幅(Range.)を示す。尚、表2に示す平均値(Avg.)、最大値(MAX.)、最小値(MIN.)、バラツキ幅(Range.)の単位はμmである。   Evaluation of the plating treatment test was performed by peeling the resist after the plating treatment and measuring the height (plating thickness) of the prismatic bumps, as in the case of the first embodiment. The bump height (plating thickness) was measured on a gold bump formed on the surface to be plated using a stylus type step measuring instrument (KLA-Tencor P11). Specifically, as shown in FIG. 3, the bump heights (W1 to W13) at a total of 13 locations were measured for the prismatic bumps formed at the center of the surface to be plated of the wafer and the peripheral portion thereof. Table 2 shows the average value (Avg.), Maximum value (MAX.), Minimum value (MIN.), And variation width (Range.) Obtained from the bump height measurement results. The unit of the average value (Avg.), Maximum value (MAX.), Minimum value (MIN.), And variation width (Range.) Shown in Table 2 is μm.

Figure 2008019501
Figure 2008019501

表2に示すように、バンプ<ア>を形成する場合、第1方式或いは第3方式のめっき電流供給によれば、製品スペックとして要求されたバラツキ幅2μmを満足できる金バンプの形成が可能となることが判明した。一方、バンプ<イ>の場合では、第1〜第4方式の総てにおいて、製品スペックとして要求されたバラツキ幅2μmを満足できる金バンプを形成できた。表2に示す結果では、バンプ<ア>の場合とバンプ<イ>の場合とでは、その傾向が異なる結果となっているが、これはバンプ<ア>の形成では、総メッキ面積がバンプ<イ>に比べ、遙かに小さなことによるものと考えられる。   As shown in Table 2, when the bump <A> is formed, it is possible to form a gold bump satisfying the variation width of 2 μm required as a product specification by supplying the plating current of the first method or the third method. Turned out to be. On the other hand, in the case of the bump <A>, the gold bumps that satisfy the variation width of 2 μm required as the product specifications could be formed in all of the first to fourth methods. In the results shown in Table 2, the tendency is different between the case of the bump <A> and the case of the bump <A>. However, in the formation of the bump <A>, the total plating area is less than the bump <A>. This is probably because it is much smaller than i>.

本実施形態におけるカップ型めっき装置の概略断面図。The schematic sectional drawing of the cup type plating apparatus in this embodiment. アノード電極の平面拡大概略図Planar enlarged schematic view of the anode electrode ウェハー被めっき面の膜厚測定部を示す平面図。The top view which shows the film thickness measurement part of a wafer to-be-plated surface. 第二実施形態で使用したアノード電極の平面拡大概略図Planar enlarged schematic view of the anode electrode used in the second embodiment

符号の説明Explanation of symbols

1 めっき装置
2 めっき槽
3 周縁部
4 シールパッキン
5 めっき液供給口
6 めっき液流出口
A アノード電極
C カソード電極
W ウェハー
ar1〜4 周縁電流供給部
ac 中央電流供給部
ATR〜ABL 周縁電流供給部
AC 中央電流供給部
DESCRIPTION OF SYMBOLS 1 Plating apparatus 2 Plating tank 3 Peripheral part 4 Seal packing 5 Plating solution supply port 6 Plating solution outlet A Anode electrode C Cathode electrode W Wafer ar1-4 Peripheral current supply part ac Central current supply part ATR-ABL Peripheral current supply part AC Central current supply

Claims (3)

めっき槽の開口部にウェハーを配置し、ウェハー外周側とカソード電極とを接触させ、めっき液を供給し、ウェハーに到達しためっき液がウェハーの被めっき表面の外周方向に流動させるようにして、めっき槽内にウェハーと対向させて配置したアノード電極と前記カソード電極とによってめっき電流を供給して、ウェハーにめっき処理を行うウェハーめっき方法において、
前記アノード電極は、ウェハーの被めっき面と略同一形状とし、アノード電極の周縁へ複数の周縁電流供給部を設けるとともに、アノード電極の中央へ中央電流供給部を設け、
前記周縁電流供給部から供給する周縁めっき電流と、中央電流供給部から供給する中央めっき電流とを調整することを特徴とするウェハーめっき方法。
Place the wafer in the opening of the plating tank, bring the wafer outer peripheral side into contact with the cathode electrode, supply the plating solution, and let the plating solution that reaches the wafer flow in the outer peripheral direction of the surface to be plated of the wafer, In a wafer plating method in which a plating current is supplied by an anode electrode and a cathode electrode arranged to face a wafer in a plating tank, and the wafer is plated.
The anode electrode has substantially the same shape as the surface to be plated of the wafer, and a plurality of peripheral current supply portions are provided at the periphery of the anode electrode, and a central current supply portion is provided at the center of the anode electrode,
A wafer plating method comprising adjusting a peripheral plating current supplied from the peripheral current supply unit and a central plating current supplied from a central current supply unit.
前記アノード電極は平板からなり、該平板に複数の穿孔を設けることにより、めっき電流分布を調整する請求項1に記載のウェハーメッキ方法。 The wafer plating method according to claim 1, wherein the anode electrode is formed of a flat plate, and the plating current distribution is adjusted by providing a plurality of perforations in the flat plate. 前記アノード電極は、チタニウム製の電極基材上に、中間層として白金被膜と、その中間層表面に酸化イリジウム被膜とが設けられた請求項1又は請求項2に記載のウェハーめっき方法。 3. The wafer plating method according to claim 1, wherein the anode electrode is provided with a platinum film as an intermediate layer and an iridium oxide film on the surface of the intermediate layer on an electrode substrate made of titanium.
JP2006339379A 2006-06-14 2006-12-18 Wafer plating method Active JP4976120B2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2006339379A JP4976120B2 (en) 2006-06-14 2006-12-18 Wafer plating method
TW096118953A TWI363107B (en) 2006-06-14 2007-05-28 Method of wafer plating
US11/809,479 US20070289873A1 (en) 2006-06-14 2007-06-01 Method of wafer plating
KR1020070055348A KR100900608B1 (en) 2006-06-14 2007-06-07 Method of wafer plating

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2006164355 2006-06-14
JP2006164355 2006-06-14
JP2006339379A JP4976120B2 (en) 2006-06-14 2006-12-18 Wafer plating method

Publications (2)

Publication Number Publication Date
JP2008019501A true JP2008019501A (en) 2008-01-31
JP4976120B2 JP4976120B2 (en) 2012-07-18

Family

ID=38860501

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006339379A Active JP4976120B2 (en) 2006-06-14 2006-12-18 Wafer plating method

Country Status (4)

Country Link
US (1) US20070289873A1 (en)
JP (1) JP4976120B2 (en)
KR (1) KR100900608B1 (en)
TW (1) TWI363107B (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010185122A (en) * 2009-02-13 2010-08-26 Ebara Corp Member for passing electric current to anode holder, and anode holder
EP2363748A1 (en) 2010-02-12 2011-09-07 Fujifilm Corporation Lithographic printing plate precursor and plate making method thereof
JP2015161028A (en) * 2014-02-25 2015-09-07 株式会社荏原製作所 Anode unit and plating apparatus including the same
KR20170108317A (en) * 2016-03-17 2017-09-27 삼성전기주식회사 Plating apparatus
US10480094B2 (en) 2016-07-13 2019-11-19 Iontra LLC Electrochemical methods, devices and compositions
WO2023286604A1 (en) * 2021-07-12 2023-01-19 東京エレクトロン株式会社 Substrate liquid treatment device and substrate liquid treatment method

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102009023769A1 (en) * 2009-05-22 2010-11-25 Hübel, Egon, Dipl.-Ing. (FH) Method and device for the controlled electrolytic treatment of thin layers
AT510593B1 (en) * 2010-12-15 2012-05-15 Markus Dipl Ing Dr Hacksteiner DEVICE FOR METALLIZING WAFERS
KR101881861B1 (en) 2011-05-02 2018-07-25 삼성전자주식회사 Electrical pattern structure and method of manufacturing the same

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02200800A (en) * 1989-01-30 1990-08-09 Nec Corp Method for adjusting current distribution for electroplating
JPH04143299A (en) * 1990-10-03 1992-05-18 Fujitsu Ltd Electroplating method
JPH07197299A (en) * 1993-12-29 1995-08-01 Casio Comput Co Ltd Plating method and plating device
JPH11135462A (en) * 1997-10-28 1999-05-21 Shinjiro Suganuma Semiconductor manufacturing device
JPH11293493A (en) * 1984-04-13 1999-10-26 Sony Corp Electroplating device
JP2005133113A (en) * 2003-10-28 2005-05-26 Fujitsu Ltd Plating apparatus

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5393396A (en) * 1990-10-30 1995-02-28 Gould Inc. Apparatus for electrodepositing metal
US6497801B1 (en) * 1998-07-10 2002-12-24 Semitool Inc Electroplating apparatus with segmented anode array
US6375826B1 (en) * 2000-02-14 2002-04-23 Advanced Cardiovascular Systems, Inc. Electro-polishing fixture and electrolyte solution for polishing stents and method
JP2001316887A (en) 2000-05-08 2001-11-16 Tokyo Electron Ltd Plating equipment
US6830673B2 (en) * 2002-01-04 2004-12-14 Applied Materials, Inc. Anode assembly and method of reducing sludge formation during electroplating
JP2006022379A (en) 2004-07-08 2006-01-26 Electroplating Eng Of Japan Co Electrolytic plating apparatus
JP2006057113A (en) 2004-08-17 2006-03-02 Tdk Corp Jet plating device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11293493A (en) * 1984-04-13 1999-10-26 Sony Corp Electroplating device
JPH02200800A (en) * 1989-01-30 1990-08-09 Nec Corp Method for adjusting current distribution for electroplating
JPH04143299A (en) * 1990-10-03 1992-05-18 Fujitsu Ltd Electroplating method
JPH07197299A (en) * 1993-12-29 1995-08-01 Casio Comput Co Ltd Plating method and plating device
JPH11135462A (en) * 1997-10-28 1999-05-21 Shinjiro Suganuma Semiconductor manufacturing device
JP2005133113A (en) * 2003-10-28 2005-05-26 Fujitsu Ltd Plating apparatus

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010185122A (en) * 2009-02-13 2010-08-26 Ebara Corp Member for passing electric current to anode holder, and anode holder
EP2363748A1 (en) 2010-02-12 2011-09-07 Fujifilm Corporation Lithographic printing plate precursor and plate making method thereof
JP2015161028A (en) * 2014-02-25 2015-09-07 株式会社荏原製作所 Anode unit and plating apparatus including the same
KR20170108317A (en) * 2016-03-17 2017-09-27 삼성전기주식회사 Plating apparatus
KR102505435B1 (en) * 2016-03-17 2023-03-03 삼성전기주식회사 Plating apparatus
US10480094B2 (en) 2016-07-13 2019-11-19 Iontra LLC Electrochemical methods, devices and compositions
US10697083B2 (en) 2016-07-13 2020-06-30 Ionta LLC Electrochemical methods, devices and compositions
WO2023286604A1 (en) * 2021-07-12 2023-01-19 東京エレクトロン株式会社 Substrate liquid treatment device and substrate liquid treatment method

Also Published As

Publication number Publication date
US20070289873A1 (en) 2007-12-20
TWI363107B (en) 2012-05-01
KR20070119502A (en) 2007-12-20
TW200817534A (en) 2008-04-16
KR100900608B1 (en) 2009-06-02
JP4976120B2 (en) 2012-07-18

Similar Documents

Publication Publication Date Title
JP4976120B2 (en) Wafer plating method
CN110306224B (en) Apparatus and method for electroplating metals using an ionically resistive ionically permeable element
KR100577662B1 (en) Method and apparatus for controlling local current to achieve uniform plating thickness
TWI700395B (en) Apparatus and method for modulating azimuthal uniformity in electroplating
US8496789B2 (en) Electrochemical processor
JPH1180989A (en) Plating apparatus
US20230193501A1 (en) Plating apparatus and plating method
KR20140035940A (en) Electrochemical processor
US7993462B2 (en) Substrate-supporting device having continuous concavity
US7214297B2 (en) Substrate support element for an electrochemical plating cell
KR102515885B1 (en) Method for determining feed point arrangement in electroplating device and electroplating device for plating a rectangular substrate
TWI638069B (en) Electrical plating equipment
JP2007308783A (en) Apparatus and method for electroplating
WO2019118169A1 (en) Electroplating dynamic edge control
CN1718868A (en) Electrolytic film plating device
US8012319B2 (en) Multi-chambered metal electrodeposition system for semiconductor substrates
US9735017B2 (en) Method of manufacturing semiconductor device
TWI759133B (en) Plating apparatus and plating method
JP2008297586A (en) Electrolytic plating apparatus
CN212357443U (en) Electroplating device and anode assembly thereof
US20240076795A1 (en) Spatially and dimensionally non-uniform channelled plate for tailored hydrodynamics during electroplating
JPH11135462A (en) Semiconductor manufacturing device
JP3053016B2 (en) Copper plating apparatus and plating method
JP2000034599A (en) Electrode for plating, plating device and plating method
JP2012126966A (en) Cup type plating device, and plating method

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20091218

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20100517

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20120302

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20120313

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20120406

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20120412

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20150420

Year of fee payment: 3

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250