JP2008017175A - Data processing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data processing device capable of realizing high-reliability data transfer by utilizing a high-speed serial bus. <P>SOLUTION: In the data process device, a signal transfer means comprises a plurality of lanes in which a transmission serial transfer path, and a reception serial transfer path are formed in pair, and is used for inter-unit communication. When a batch of data is to be transmitted from one unit to the other unit by using the signal transfer means, a plurality of lanes are used, and the other unit compares the data of a plurality of lanes that have been received. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a data processing apparatus using signal transmission means having a plurality of lanes formed by pairing a transmission serial transmission path and a reception serial transmission path for inter-unit communication.

Conventionally, when performing high-speed serial transfer such as PCI-Express in an image processing apparatus that handles various image data, it is scalable by automatically changing the number of lanes of the PCI-Express bus to be used depending on the type and capacity of the data. A data transfer function was provided (see Patent Document 1).
Japanese Patent Laid-Open No. 2005-210653

  However, such a conventional apparatus does not have a function of ensuring the reliability of data transferred using a high-speed serial bus.

  The present invention has been made in view of such a situation, and an object of the present invention is to provide a data processing apparatus capable of realizing highly reliable data transfer using a high-speed serial bus.

  The present invention is a data processing apparatus using signal transmission means having a plurality of lanes formed by pairing a transmission serial transmission path and a reception serial transmission path for inter-unit communication, wherein the signal is transmitted from one unit to the other unit. When a set of data is transmitted using the transmission means, a plurality of lanes are used, and the other unit compares the received data of the plurality of lanes.

  In addition, when the received data of one or more lanes is different for the received data of the plurality of lanes, the other unit determines that it is a reception error and requests retransmission to the one unit. It is a thing.

  In addition, when the received data of one or more lanes is different for the received data of the plurality of lanes, the other unit determines that it is a reception error and requests retransmission to the one unit. One unit sets the combination of the plurality of lanes used at the time of data retransmission different from the previous transmission.

  Also, a data processing device using signal transmission means having a plurality of lanes formed by pairing a transmission serial transmission path and a reception serial transmission path for inter-unit communication, wherein the signal transmission means is transferred from one unit to the other unit. When the group of data is transmitted using the first lane, the group of data is transmitted in the first lane, the parity data formed for the group of data is transmitted in the second lane, and the other lane is transmitted. This unit creates parity data for the data received in the first lane and compares it with the parity data received in the second lane.

  Therefore, according to the present invention, since an error during data transfer is detected and a retransmission request is made, highly reliable data transfer can be realized.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 shows a configuration example of an image forming apparatus according to an embodiment of the present invention.

  In the figure, a controller 1 controls the entire image forming apparatus and realizes an interface with an external apparatus. An operation display unit 2 is a man for a user to operate the image forming apparatus. The magnetic disk device 3 is used to configure a machine interface, stores various file data, and also has a file server function for temporarily storing image data and storing it as electronic data.

  The scanner unit 4 is for reading a document image at a predetermined resolution, the plotter unit 5 is for recording and outputting an image at a predetermined resolution, and the engine control unit 6 includes the scanner unit 4 and the plotter. This is for controlling the operation of the unit 5 and exchanging various data with the controller 1.

  Further, the engine control unit 6 performs various image processing and data compression on the image data obtained by the scanner unit 4 and transfers the image data to the controller 1.

  The digital image data created by the controller 1 is transferred to the engine control unit 6, and the engine control unit 6 sends the received digital image data to the plotter unit 5 in accordance with the writing linear velocity of the plotter unit 5. Forward.

  FIG. 2 shows an example of the internal configuration of the controller 1.

  In the figure, a CPU (central processing unit) 11 is a central control unit that performs overall control of the entire image forming apparatus, and controls each part in accordance with a program.

  The memory 12 is used as a work memory for programs and a frame memory for image data, and the peripheral device 13 controls interface with terminal devices such as personal computer devices and server devices, stores programs, log information, etc. It is for performing control and processing. The digital image processing device 14 is for executing various image processing.

  The memory control unit 15 is for controlling transmission / reception of data among the CPU 11, the memory 12, the peripheral device 13, and the digital image processing device 14.

  Here, the memory control unit 15 and the digital image processing device 14 are connected via a PCI-Express bus 16, and output data of the digital image processing device 14 is connected via a PCI-Express bus 17. And output to the engine control unit 6.

  The arbiter circuit 15a of the memory control unit 15 is a circuit unit that performs determination of data transfer paths, priority order, and time division arbitration in response to requests from the CPU 11, the peripheral device 13, and the digital image processing device 14. is there.

  The transmission buffer 15b is for sending out the output data of the arbiter circuit 15a, and the reception buffer 15c is for receiving the data received by the arbiter circuit 15a and sending it out to the arbiter circuit 15a.

  FIG. 3 is a diagram showing an electrical connection configuration in the case of a 4-lane configuration as an example of the configuration of the PCI-Express buses 16 and 17. Here, a lane is formed by pairing a transmission serial transmission path and a reception serial transmission path.

  In this case, although electrically composed of 4 lanes, the signal line of the path where data is actually transferred by the configuration setting is 1 lane (x1 lane (using one pair of signal lines)), 2 lanes (x2 It is possible to set and select lanes (using two pairs of signal lines) and 4 lanes (x4 lanes (using four pairs of signal lines)).

  With the function that can change the connection form by this configuration setting, for example, when the data transfer amount (bandwidth) request per unit time is large as in the case of image data, the data transfer is performed using the full 4 lanes. In this way, when the data transfer amount is small, the bus configuration is such that the logical connection form can be changed so that the transfer is performed in only one arbitrary lane.

  FIG. 4 shows an example of command data transfer processing between the digital image processing device 14 and the engine control unit 6, for example.

  When command data transfer is requested (process 101), two arbitrary lanes are selected from the PCI-Express bus 17 connected to the digital image processing device 14 and the engine control unit 6 (process 102).

  Next, the configuration setting process of each device (the digital image processing device 14 and the engine control unit 6) is performed to establish the logical connection of the selected two lanes (process 103).

  Then, using the two lanes selected at this time, the transmitting side transmits exactly the same data (process 104).

  The device receiving the data temporarily stores the data of each lane in the memory (process 105), and compares all the bytes of the stored data (process 106).

  Then, it is checked whether or not there is a complete match (decision 107). If the match is complete and the result of determination 107 is YES, the data transfer ends normally.

  On the other hand, as a result of comparing the stored data, even if even one byte does not match, and if the result of determination 107 is NO, a retry request is issued to the transmitting device (process 108).

  As a result, the transmission-side device that has received the retry request selects a lane that is physically different from the lane selected in process 102 (process 109).

  Thereafter, the process returns to the process 103 and the above-described process flow is executed.

  Here, the program of this control flow may be a fixed storage medium stored in a ROM or the like in the peripheral device 13 or may be a method in which the program is downloaded to the memory 12 from a removable storage medium.

  Thus, in this case, since the same data is transferred to a plurality of lanes and the comparison is performed on the receiving side, the reliability of the data transferred by the high-speed serial bus can be improved. .

  Also, as a result of checking, if it is determined that there is an error in the transferred data, it has a function to automatically issue a retry request, improving the reliability of the data transferred via the high-speed serial bus It can be made.

  In addition, when a retry request is received, it has a function to reconfigure and retransmit data in a lane that is physically different from the previously transferred lane, improving the reliability of data transferred via the high-speed serial bus. It can be made.

  FIG. 5 shows another example of command data transfer processing between the digital image processing device 14 and the engine control unit 6, for example.

  When command data transfer is requested (process 201), two arbitrary lanes are selected from the PCI-Express bus 17 connected to the digital image processing device 14 and the engine control unit 6 (process 202).

  Next, the configuration setting process of each device (the digital image processing device 14 and the engine control unit 6) is performed to establish the logical connection of the selected two lanes (process 203).

  Then, command data is transmitted to one of the two selected lanes, and a parity code (for example, in units of bytes) matching the command data is transmitted to the other lane (process 204).

  The device that has received the data temporarily stores the data of each lane in the memory (process 205), calculates the parity code of the command data, and compares it with the received parity code (process 206).

  Next, it is checked whether or not there is a parity error (determination 207). If there is no parity error and the result of determination 207 is YES, the data transfer ends normally.

  On the other hand, if there is even one sum check error and the result of determination 207 is YES, a retry request is issued to the transmitting device (process 208).

  As a result, the transmission-side device that has received the retry request selects a lane physically different from the lane selected in process 202 (process 209).

  Thereafter, the process returns to the process 203 and the above-described process flow is executed.

  Here, the data for checking the data is not limited to the parity code, and other check data may be used.

  Thus, in this case, since the data check data such as the parity code is transferred to the lane different from the lane to which the data is transferred, and has a function of checking on the receiving side, the high-speed serial bus It is possible to improve the reliability of the data transferred by.

  In the above-described embodiment, the case where the PCI-Express bus is used for data transfer of the internal unit of the image forming apparatus is described. However, the case where the PCI-Express bus is used for other data transfer is described. Also, the present invention can be applied in the same manner.

1 is a block diagram illustrating a configuration example of an image forming apparatus according to an embodiment of the present invention. The block diagram which showed an example of the internal structure of the controller 1. FIG. The circuit diagram which showed the electrical connection form at the time of setting it as a 4-lane structure as an example of a PCI-Express bus 16 and 17 structure. For example, a flowchart showing an example of command data transfer processing between the digital image processing device 14 and the engine control unit 6. For example, a flowchart illustrating another example of command data transfer processing between the digital image processing device 14 and the engine control unit 6.

Explanation of symbols

1 Controller 6 Engine control unit

Claims (4)

A data processing device using signal transmission means having a plurality of lanes formed by pairing a transmission serial transmission path and a reception serial transmission path, for inter-unit communication,
When a set of data is transmitted from one unit to the other unit using the signal transmission means, a plurality of lanes are used, and the other unit compares the received data of the plurality of lanes. A data processing apparatus.   If the received data of one or more lanes is different from the received data of the plurality of lanes, the other unit determines that it is a reception error and makes a retransmission request to the one unit. The data processing apparatus according to claim 1. If the received data of one or more lanes is different for the received data of a plurality of lanes, the other unit determines a reception error and requests retransmission to the one unit.
The data processing apparatus according to claim 1, wherein the one unit sets a combination of the plurality of lanes used at the time of data retransmission to a combination different from the previous transmission. A data processing device using signal transmission means having a plurality of lanes formed by pairing a transmission serial transmission path and a reception serial transmission path, for inter-unit communication,
When transmitting a set of data from one unit to the other unit using the signal transmission means, the first lane transmits the set of data, and the second lane transmits the set of data. Send the parity data formed for the data,
The data processing apparatus according to claim 1, wherein the other unit creates parity data for the data received in the first lane and compares it with the parity data received in the second lane.