JP2008017168A - Image signal processing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a means which rapidly reads correction data recorded on a low-speed ROM. <P>SOLUTION: A ROM data transfer circuit 20 writes in control data used for image processing recorded on a ROM 8 by a first record means 7 used for subfield orthogonal conversion processing and frame delay processing of image data. A first ROM data reading control circuit 24 reads the data required by each field to vertical blanking etc. out of the conversion data recorded on the first record means 7, writes them in a second record means 25, and reads them by using a second ROM data reading control circuit 26, thus utilizing them. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a video signal processing apparatus for a plasma display panel (PDP).

  An image display device using a PDP (plasma display panel) or a liquid crystal panel has an advantage that it can be made thin and have a large screen, and is being developed.

A video display device using a PDP or a liquid crystal panel is more suitable for reproducing the non-linear characteristics of the input / output of the display device and the gradation of the video appropriately than the CRT which has been used as a device of the video display device conventionally. Processing for adding correction is performed by a correction circuit or the like. Further, this correction processing needs to dynamically change the table conversion data referred to by the correction circuit according to the level of the video signal or the like.
JP 2001-184016 A

  However, the table conversion data required by the gamma correction circuit or the like is, for example, table conversion data for converting a 10-bit video signal into a 16-bit signal. The table conversion data has a total size of 16384 bits. Furthermore, if this table conversion data is provided for each of the three primary colors red, blue, and green, the table conversion data has a total size of 49152 bits, which is three times that of a single color.

  When reading table conversion data of such a size from a low-speed ROM in accordance with the characteristics of the video signal, the data is temporarily recorded in a relatively high-speed SRAM or the like during the vertical blanking period and the video signal processing. Sometimes data is read from the SRAM at high speed. However, it takes time to read a large amount of table conversion data such as a gamma correction circuit from a low-speed ROM, and it is difficult to complete the reading operation in a vertical blanking period or the like. In addition, the 1080I and 720P video formats used in high-definition broadcasting and the like have an extremely short proportion of the vertical blanking period in one frame as compared with the conventional NTSC format. Reading table conversion data from a low-speed ROM has become very difficult.

  On the other hand, a method of transferring large data such as table conversion data for gamma conversion into a plurality of frames and transferring the data from a low-speed ROM to a high-speed SRAM is considered. It becomes impossible to switch the table conversion data for conversion, and the responsiveness deteriorates.

  An object of the present invention is to provide a video signal processing apparatus that can use table conversion data at high speed even when table conversion data used for gamma conversion or the like is recorded in a low-speed ROM. .

  The video signal processing apparatus according to the present invention includes a data arbitration circuit that receives a plurality of read and write requests and performs control of reading and writing data to the first recording unit, a data arbitration circuit, and the first recording unit. Frame delay control circuit for frame delay control of video signal, subfield orthogonal transform circuit for performing orthogonal transform of subfield data by data arbitration circuit and first recording means, and data required for video signal processing read from ROM A ROM data transfer circuit for recording in the first recording means using the arbitration circuit, and a second data read out from the first recording means for writing only data necessary for video processing for each frame using the data arbitration circuit. 1 ROM data read control circuit, and second read out necessary data sequentially from the second recording means according to the video signal Those comprising a ROM data read control circuit.

  The first recording means operates at a higher speed than the ROM, and the data arbitration circuit sends a write request output from the ROM data read control circuit to the first recording means and a subfield orthogonal transformation circuit. Read and write requests outputted from the frame delay control circuit, read and write requests outputted from the frame delay control circuit, and read requests outputted from the first ROM data read control circuit are inputted and read out from the first recording means. Arbitrate write control.

  According to the present invention, data recorded in a low-speed ROM can be read at high speed. In addition, it is possible to switch data used for correction at high speed for each frame according to the characteristics of the video signal. Furthermore, by using a recording means essential for subfield orthogonal transformation, it can be realized without an increase in cost.

(First embodiment)
Hereinafter, a video signal processing apparatus in a plasma display apparatus will be described as an example of a video signal processing apparatus according to the present invention.

  FIG. 2 is a block diagram showing the overall configuration of the video signal processing apparatus according to the embodiment of the present invention. The video signal processing apparatus of FIG. 2 includes an AD converter 1, a scanning line conversion circuit 2, a gamma correction circuit 3, an image quality correction circuit 4, a subfield conversion circuit 5, a data control circuit 6, a first recording unit 7, and a ROM 8. .

  A video signal VD is input to the AD converter 1. Further, the horizontal synchronizing signal H and the vertical synchronizing signal V are inputted, and the video signal VD is converted into a digital signal. The image is input to the scanning line conversion circuit 2, and scanning line conversion corresponding to the number of scanning lines of the plasma display panel is performed. The video data after the scanning line conversion is input to the gamma correction circuit 3.

  The data control circuit 6 reads all table conversion data recorded in the ROM 8 when the plasma display device is turned on from the ROM 8 that records table conversion data such as a plurality of gamma correction data according to the characteristics of the video signal. The RDI is read and recorded in the first recording means 7. The gamma correction circuit 3 reads the gamma correction data GO from the data control circuit 6 according to the characteristics of the input video data after the scanning line conversion. At this time, the data control circuit 6 reads the table conversion data read from the ROM 8 and recorded in the first recording means 7 as the gamma correction data GO in accordance with the video signal input to the gamma correction circuit 3. At this time, the data control circuit 6 reads out a desired area of the table conversion data recorded in the first recording means 7 as the gamma correction data GO in accordance with the video signal input to the gamma correction circuit 3.

  The gamma correction circuit 3 performs gamma correction of the video signal based on the video data after the scanning line conversion and the gamma correction data GO read from the data control circuit 6, and inputs the video signal after the gamma correction to the image quality correction circuit 4. The image quality correction circuit 4 performs image quality correction processing using the delayed video signal DO delayed by one frame of the video signal DI. In accordance with the horizontal synchronizing signal H and the vertical synchronizing signal V, the video data DI is output to the data control circuit 6 and the delayed video signal DO delayed by one frame is received. Image quality correction processing is performed using the horizontal synchronization signal H, vertical synchronization signal V, video signal DI, and delayed video signal DO, and the corrected video data is input to the subfield conversion circuit 5. In the subfield conversion circuit 5, the horizontal synchronization signal H and the vertical synchronization signal V and the image signal after image quality correction output from the image quality correction circuit 4 are input, the image signal is subjected to subfield conversion processing, and the subfield data SFD is converted. Input to the data control circuit 6. Details of the subfield conversion processing will be described later.

  In the data control circuit 6, the subfield data SFD is recorded in the first recording means 7, and the subfield orthogonal transformation data SFDO is output by the read control from the first recording means 7 started by the subfield data read trigger SFTRG. Is done. Details of the subfield orthogonal transform processing will be described later.

  As the first process, the data control circuit 6 writes all the table conversion data recorded in the ROM 8 to the first recording means 7 when the plasma display device is turned on, and the second process. In response to a request from the gamma correction circuit 3, table conversion data for gamma correction corresponding to the characteristics of the video data is read from the first recording means 7 during the vertical blanking period of the video signal and supplied to the gamma correction circuit 3. Processing, and as third processing, the video data DI input from the image quality correction circuit 4 is written in the first recording means 7 and the delayed video signal DO delayed by one frame is read and supplied to the image quality correction circuit 4; As a fourth process, the subfield data SFD supplied from the subfield conversion circuit 5 is written in the first recording means 7, and the subfield data And it outputs the subfield data orthogonal transformation data SFDO by reading the subfield data from the first recording means 7 in accordance chromatography data read trigger SFTRG. As described above, the data control circuit 6 performs arbitration of four types of independent processes for the first recording unit 7. Details of the arbitration process in the data control circuit 6 will be described later.

  As described above, the video signal VD is input, and the data control circuit 6 performs arbitration processing on the first recording unit 7, thereby performing processing such as gamma conversion processing using table conversion data, and 1 of video data. Video processing using a frame delay signal and orthogonal transformation of subfield data can be performed using the first recording means 7 which is one recording means.

  FIG. 1 is a block diagram of the data control circuit 6 in the video signal processing apparatus shown in FIG. The data control circuit 6, the first recording means 7, and the ROM 8 are the same as those shown in FIG.

  1 includes a ROM data transfer circuit 20, a subfield orthogonal transform circuit 21, a frame delay control circuit 22, a data arbitration circuit 23, a first ROM data read control circuit 24, a second recording means 25, 2 ROM data read control circuit 26.

  The data arbitration circuit 23 requests the first recording means 7 from four types of circuits (request 1), a write request from the ROM data transfer circuit 20, and (request 2) a write from the frame delay control circuit 22. Arbitration of the read request, (request 3) write and read request from the subfield orthogonal transform circuit 21, and (request 4) read request from the first ROM data read control circuit 24 are performed. Details regarding the arbitration processing of the data arbitration circuit 23 will be described later.

  The ROM data transfer circuit 20 reads table conversion data such as gamma correction data recorded in the ROM 8 when the plasma display device is activated, and inputs the read table conversion data to the data arbitration circuit 23. The data arbitration circuit 23 writes the table conversion data input from the ROM data transfer circuit 20 in the first recording means 7. Depending on the recording capacity of the first recording means 7, all the table conversion data recorded in the ROM 8 may be recorded in the first recording means 7, or a part of the table conversion data may be recorded. May be. When all the table conversion data recorded in the ROM 8 is recorded in the first recording means 7, the data transfer from the ROM 8 to the first recording means 7 is performed only once when the plasma display device is activated, etc. There is no need to transfer data while the plasma display device is operating. Further, when a part of the table conversion data recorded in the ROM 8 is recorded in the first recording means 7, for example, the table conversion data not recorded in the first recording means 7 due to a change in user settings. When reference is required, a series of table conversion data including the necessary table conversion data is transferred from the ROM 8 to the first recording means 7 and then newly recorded in the first recording means 7. Gamma conversion processing or the like is performed with reference to desired table conversion data.

  The table conversion data recorded in the first recording means 7 includes the table conversion data required for each frame in the first ROM during a period in which normal video signal processing is not performed in a vertical blanking period of the video signal. A read request is output from the data read control circuit 24 to the data arbitration circuit 23. The data arbitration circuit 23 reads desired table conversion data from the first recording means 7 in accordance with a request from the first ROM data read control circuit 24, and outputs it to the first ROM data read control circuit 24. The first ROM data read control circuit 24 records the table conversion data required for each frame input from the data arbitration circuit 23 in the second recording means 25. The second ROM data read control circuit 26 sequentially reads the table conversion data recorded in the second recording means 25 according to the level of the video signal, and performs processing such as gamma conversion.

  Thus, the table conversion data recorded in the second recording means 25 can be updated every frame, and the recording capacity of the first recording means 7 that records a plurality of table conversion data and other video data. In contrast, the recording capacity of the second recording means 25 may be much smaller, and a relatively expensive SRAM can be used even when high-speed reading processing such as gamma conversion of a video signal is required. . Further, the first recording means 7 needs to operate at high speed and has a large storage capacity, and a DRAM or SDRAM can be used. Further, in the plasma display device, subfield orthogonal transformation described later is an essential process. For subfield orthogonal transform, it is necessary to record at least one frame of subfield data, and the first recording means 7 for recording the subfield data is necessarily required and has a large recording capacity. By recording the table conversion data of the ROM 8 in a part of the recording area of the large-capacity first recording means 7 necessary for the subfield orthogonal transform processing, it is possible to record relatively large data recorded in the ROM. There is no need to prepare a dedicated recording means. In this way, by recording the table conversion data on the low-speed ROM in the first recording means 7 capable of high-speed operation without increasing the cost, every frame is limited in a limited period such as a vertical blanking period. It is possible to read out the table conversion data required for the above at high speed. In this embodiment, the example in which the first ROM data read control circuit 24 records the gamma correction data in the second recording unit 25 has been described. However, it is necessary for image quality correction other than the gamma correction data. Even when a plurality of table conversion data are required, it is possible to cope with this by having a plurality of second recording means 25 and a plurality of second ROM data reading control circuits 26.

  The frame delay control circuit 22 inputs the video signal DI to the data arbitration circuit 23 in accordance with the horizontal synchronization signal H and the vertical synchronization signal V. The data arbitration circuit 23 performs a process of recording the video signal input from the frame delay control circuit 22 in the first recording unit 7 and a process of reading the delayed video signal DO delayed by one frame and outputting it to the frame delay control circuit 22. As a result, a delayed video signal DO delayed by one frame with respect to the video signal DI is obtained. In the present embodiment, the image signal delayed by one frame is used in the image quality correction circuit 4, but may be used in the scanning line conversion circuit 2.

  The subfield orthogonal transform circuit 21 inputs the subfield data SFD, the subfield data read trigger SFTRG, the horizontal synchronization signal H, and the vertical synchronization signal V, and inputs the subfield data SFD to the data arbitration circuit 23. The data arbitration circuit 23 performs a process of writing the subfield data SFD input from the subfield orthogonal transform circuit 21 to the first recording unit 7 in accordance with the horizontal synchronization signal H and the vertical synchronization signal V. Further, in accordance with the subfield data read trigger SFTRG, the subfield data is read from the first recording means 7, and as a result, subfield orthogonal transformation data SFDO obtained by orthogonal transformation of the subfield data is obtained.

  FIG. 3 shows a timing chart of the orthogonal transformation process of the subfield data. In the timing chart of FIG. 3, the video data input is a video signal output from the image quality correction circuit 4 and input to the subfield conversion circuit 5 ((1) in FIG. 3). Subfield data after subfield conversion is input ((2) in FIG. 3), and the primary orthogonal transformation output is obtained by rearranging the subfield data SFD in time series by the subfield orthogonal transformation circuit 21. The next orthogonal transform output ((3) in FIG. 3), SFTRG represents a subfield data read trigger ((4) in FIG. 3), and SFDO represents subfield orthogonal transform data orthogonally transformed according to the subfield data read trigger SFTRG. This is shown ((5) in FIG. 3). In the timing chart of FIG. 3, the video data input is a 4-bit video signal, the number of subfields is 4, and the timing chart when a 16-pixel video data input is input is shown. Even when the resolution of the video data input, the number of pixels, and the number of subfields are different from the example of the timing chart of FIG. 3, subfield data can be orthogonally transformed in the same manner.

  Video data input is input to the subfield conversion circuit 5 in the order of img0, img1, and img2 in time series. Each video data is composed of 4 bits. The pixel-based video data input is subjected to sub-field conversion by the sub-field conversion circuit 5 to obtain pixel-based sub-field data SFD. The subfield data SFD is output in the order of sf0, sf1, and sf2 in a time series as in the case of video data input, and each data is configured as 4-bit subfield data. sf0 [0], sf0 [1], sf0 [2], and sf0 [3] respectively indicate data of subfields 0 to 3 in data SF0 after subfield conversion of video input data img0. The subfield data SFD is subjected to first-order orthogonal transform by the subfield orthogonal transform circuit 21 to obtain a first-order orthogonal transform output. The primary orthogonal transform output is obtained by rearranging the sub-field data SFD in units of pixels for each sub-field with four pixels as one set. That is, as the first output, the data of 0 subfield is collected for 4 pixels (corresponding to SF0 to SF3), and the subsequent data is 4 pixels of data of 1 subfield, 2 subfields, 3 subfields. The collected data continues. Thereafter, data obtained by rearranging the data for four pixels sf4 to sf7 in the order of subfields follows. In the present embodiment, the data of the subfields are arranged in ascending order, but can be arranged in descending order. The primary orthogonal transform output is written in the first recording means 7 and the data for each subfield is continuously read according to the subfield data read trigger SFTRG. When reading data in the 0 subfield, four data (sequential data of 16 pixels in the 0 subfield) from sf0 [0] to sf3 [0] by sf15 [0] are read out three times. Read continuously. Similarly, the data of all subfields are continuously read according to the subfield data read trigger SFTRG. In this way, the video data input is subjected to the read control so that the data of the same subfield continues after being written in the first recording means 7 through the primary orthogonal transformation after the subfield transformation. The orthogonal transformation of the field data is performed. When subfield conversion is performed on the video data input, the subfield conversion table data is recorded in the ROM 8 and converted using the subfield conversion table data recorded in the first recording means in the same manner as the gamma correction data. Good.

  FIG. 4 shows a block diagram of a data arbitration circuit in the data control circuit of FIG. 4 includes a buffer control circuit 30, a first buffer recording unit 31, a second buffer recording unit 32, a third buffer recording unit 33, a fourth buffer recording unit 34, and a fifth buffer recording. Means 35 are included. The first recording means 7, ROM 8, ROM data transfer circuit 20, frame delay control circuit 22, data arbitration circuit 23, subfield orthogonal transformation circuit 21, first ROM data read control circuit 24, and second recording means. Reference numeral 25 denotes the same one as shown in FIGS.

  The ROM data transfer circuit 20 writes the table conversion data RDI read from the ROM 8 in the first buffer recording means 31. The first buffer recording means 31 is used to absorb the difference between the data output speed of the ROM data transfer circuit 20 and the writing speed of the first recording means 7. The writing process to the first recording means after reading the table conversion data from the ROM 8 is performed with the highest priority over the writing or reading to the other first recording means 7.

  For the table conversion data recorded in the first recording means 7, the buffer control circuit 30 performs the first recording of the table conversion data required for each frame during a period in which no video signal exists, such as a vertical blanking period. Read from the means 7 and write to the second buffer recording means 32. In this way, by performing the read operation from the first recording means 7 during a period when there is no video signal such as a vertical blanking period, consideration is given so that processing for writing or reading requests to other first recording means does not overlap. Has been. The first ROM data read control circuit 24 rearranges the data written in the second buffer recording means 32 into a desired data series and then records the data in the second recording means 25, and the gamma which requires table conversion data. The correction circuit or the like uses the data recorded in the second recording means 25 as appropriate. Here, the second buffer recording means 32 is used to absorb the difference between the reading speed of the first recording means and the operating speed of the first ROM data read control circuit 24. In the present embodiment, the operation in the case where there is one set of the first ROM data read control circuit 24 and the second recording means 25 has been described. However, the first ROM data read control circuit 24 and the second ROM data read control circuit 24 It is also possible to read out and use another table conversion data recorded in the first recording means 7 using the common second buffer recording means 32.

  The frame delay control circuit 22 writes the video signal in the third buffer recording means 33 with the video signal DI as an input. The buffer control circuit 30 reads the video data written in the third buffer recording means 33 and writes it in the first recording means 7. Further, the buffer control circuit 30 reads out the video data delayed by one frame from the first recording means 7 and writes it in the fourth buffer recording means 34. The frame delay control circuit 22 reads the video signal delayed by one frame written in the fourth buffer recording means 34 and outputs it as a delayed video signal DO. The third buffer recording means 33 is used to absorb the difference between the writing speed of the frame delay control circuit 22 and the writing speed of the first recording means 7. The fourth buffer recording means 34 is used to absorb the difference between the reading speed of the frame delay control circuit 22 and the reading speed of the first recording means 7.

  The subfield orthogonal transform circuit 21 receives the subfield data SFD and writes the data after the primary orthogonal transform in the fifth buffer recording means 35. The buffer control circuit 30 reads the data after the first orthogonal transformation from the fifth buffer recording means 35 and writes it to the first recording means 7. The subfield orthogonal transform circuit 21 outputs a subfield data read request to the buffer control circuit 30 according to the subfield data read trigger SFTRG, and the buffer control circuit 30 reads the subfield data from the first recording means 7. As a result, the subfield orthogonal transformation data SFDO after the orthogonal transformation is output.

  The buffer control circuit 30 performs an arbitration process in response to a write / read request from the frame delay control circuit 22 and the subfield orthogonal transform circuit 21 to the first recording unit 7, and a write / read process to the first recording unit To control.

  When the subfield data read trigger SFTRG is generated regardless of the video signal synchronization signal, the subfield data read trigger SFTRG may be generated during the vertical blanking period. In this case, although the subfield data read request and the data read request from the first ROM data read control circuit 24 overlap with the first recording means 7, the subfield data read request is not waited. In addition, it is necessary to set a higher priority for subfield data read requests. This is because when a subfield data read request is input, it is necessary to output the subfield orthogonal transform data SFDO to the data driver of the plasma display device during a certain period. Therefore, when the subfield data read trigger SFTRG is input to the subfield orthogonal transform circuit 21 during the period in which the first ROM data read control circuit 24 reads the table conversion data from the first recording means 7. Then, the reading process of the table conversion data by the ROM data reading control circuit 24 is interrupted, and the reading process of the subfield orthogonal transformation data SFDO is started. As soon as the reading of the subfield orthogonal transformation data SFDO is completed, the reading process of the table conversion data by the ROM data reading control circuit 24 is resumed.

  When SDRAM or DRAM is used as the first recording unit, the buffer control circuit 30 uses the period during which writing or reading control is not performed on the first recording unit, and the SDRAM or DRAM. The refresh process is performed.

  As described above, the video signal processing apparatus according to the present invention can read data recorded in a low-speed ROM at high speed. In addition, it is possible to switch data used for correction at high speed for each frame according to the characteristics of the video signal. Furthermore, by using a recording means that is essential for subfield orthogonal transform, it can be realized without an increase in cost. As a result, it is possible to improve the gradation in the low gradation part. For example, the number of gradations can be increased from 2048 gradations to 3072 gradations. Further, by performing the arbitration, it is possible to improve the gradation without causing the display system to fail.

  The present invention is useful in a video signal processing apparatus such as a plasma display panel (PDP).

Data control circuit block diagram The block diagram which shows the structure of the video signal processing apparatus which concerns on one embodiment of this invention Timing chart of orthogonal transformation processing of subfield data Block diagram of data arbitration circuit in data control circuit

Explanation of symbols

6 Data control circuit 7 First recording means 8 ROM
20 ROM Data Transfer Circuit 21 Subfield Orthogonal Transform Circuit 22 Frame Delay Control Circuit 23 Data Arbitration Circuit 24 First ROM Data Read Control Circuit 25 Second Recording Unit 26 Second ROM Data Read Control Circuit H Horizontal Sync Signal V Vertical Sync signal SFTRG Subfield data read trigger

Claims (2)

A data arbitration circuit that performs read and write control of data to the first recording means in response to a plurality of read and write requests;
A frame delay control circuit for controlling a frame delay of a video signal by the data arbitration circuit and the first recording unit;
A subfield orthogonal transform circuit for performing orthogonal transform of subfield data by the data arbitration circuit and the first recording means;
ROM data transfer circuit for reading out data necessary for video signal processing from ROM and storing it in the first recording means using the data arbitration circuit;
A first ROM data read control circuit that reads from the first recording means only data necessary for video processing for each frame using the data arbitration circuit, and writes the data to the second recording means;
A second ROM data read control circuit for sequentially reading necessary data in accordance with a video signal from the second recording means;
The video signal processing apparatus according to claim 1, wherein the first recording means operates at a higher speed than the ROM. The data arbitration circuit, for the first recording means, a write request output from the ROM data read control circuit, a read and write request output from the subfield orthogonal transform circuit, and the frame delay control. A read / write request output from the circuit and a read request output from the first ROM data read control circuit are input to perform arbitration of data read / write control with respect to the first recording means. The video signal processing apparatus according to claim 1.

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