JP2008016540A - Semiconductor package and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To inspect the packaging of a semiconductor package easily and reliably, and to thin a chip size level. <P>SOLUTION: The semiconductor package 1 comprises: a semiconductor element 2 having a plurality of electrode sections 2a on one surface; an insulation base 4 that is joined to one surface of the semiconductor element and has an opening 3 for exposing the plurality of electrode sections each; a metal layer 5 formed on one surface of the base; and an external electrode 6 patterned so that it is routed from one surface of the metal layer onto the side of the metal layer and that of the base while being connected to the plurality of electrode sections each electrically via the opening. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor package having a semiconductor element such as an IC chip and a method for manufacturing the semiconductor package.

  A wide variety of semiconductor packages having semiconductor elements such as IC chips have been conventionally provided, but those utilizing a lead frame are widely used because of their simple structure and low cost manufacturing.

  Here, a general semiconductor package using a lead frame will be briefly described with reference to FIG. FIG. 50 is a cross-sectional view showing an example of a conventional semiconductor package. As shown in FIG. 50, in a semiconductor package 40, a semiconductor element 41 such as an IC chip is bonded to a die pad 43 of a lead frame 42 via a die bonding agent (not shown). The electrode 43 is electrically connected through a bonding wire 44. Further, the semiconductor element 41, the die pad 43 and the bonding wire 44 are sealed inside by a mold resin portion 45 made of epoxy resin or the like. Thereby, the semiconductor element 41, the die pad 43, and the bonding wire 44 are packaged without being exposed to the outside.

Currently, a semiconductor package using such a lead frame is mounted on various electronic devices and widely used. However, with the recent high integration of semiconductors and the miniaturization and thinning of semiconductor-related products, there has been a demand for semiconductor packages that are smaller and thinner. In this regard, it has been difficult to further reduce the package size and thickness in a semiconductor package using a lead frame.
Therefore, recently, in order to meet the above-described needs, a semiconductor package that is packaged in substantially the same size as a semiconductor element to reduce the thickness has been provided (for example, see Patent Document 1).

  This thinned semiconductor package is also called wafer level packaging, and an example of a manufacturing method thereof will be described with reference to FIGS. FIG. 51 is a process diagram for manufacturing a conventional semiconductor package, in which metal posts are provided on a wafer on which a plurality of semiconductor elements are fabricated. FIG. 52 is a diagram showing a state in which the metal post is sealed inside with resin after the state shown in FIG. FIG. 53 is a view showing a state in which the front surface of the metal post is exposed by polishing the surface of the resin after the state shown in FIG. FIG. 54 is a view showing a state in which eutectic solder balls are provided at the tips of exposed metal posts after the state shown in FIG. FIG. 55 is a view showing a state where a plurality of semiconductor packages are manufactured by dicing the wafer into pieces by dicing after the state shown in FIG.

First, as shown in FIG. 51, a metal post 52 is provided on the surface of a wafer 50 on which a plurality of semiconductor elements 51 are manufactured. At this time, the metal post 52 is provided so as to be electrically connected to an electrode portion (not shown) of each semiconductor element 51. In this case, a case where two metal posts 52 are provided for each semiconductor element 51 is taken as an example.
Next, as shown in FIG. 52, a liquid or solid resin 53 is provided so as to cover a plurality of metal posts 52 provided on the wafer 50, and the metal posts 52 are sealed inside. Next, as shown in FIG. 53, the surface of the resin 53 is polished until the tip of the metal post 52 is exposed.

Next, as shown in FIG. 54, eutectic solder balls (solder bumps) 54 are provided at the tips of the exposed metal posts. Finally, as shown in FIG. 55, by dicing the wafer 50 into pieces, a plurality of semiconductor packages 55 with reduced thickness can be manufactured at a time.
The semiconductor package 55 manufactured in this way is placed, for example, so that the solder bumps 54 face the circuit board side, and then bonded to the circuit board using the solder bumps 54. That is, flip chip mounting is performed.
JP 2001-267455 A

However, the conventional semiconductor package described above still has the following problems.
That is, the semiconductor package 55 is manufactured in a state close to the thickness of the wafer 50 and is very thin. However, since the metal post 52 is formed only on one side by an external electrode, it is flip-chip mounted. It was difficult to inspect the mounting later. That is, because of the flip chip mounting, when the semiconductor package 55 is placed on a circuit board or the like, the solder bumps 54 are hidden behind the semiconductor package 55 and cannot be confirmed. For this reason, it is difficult to perform a mounting inspection such as the degree of melting of the solder after the semiconductor package 55 and the circuit board are joined by solder.

  The present invention has been made in view of such circumstances, and an object of the present invention is to provide a chip size level semiconductor package capable of easily and reliably performing mounting inspection, and to efficiently manufacture the semiconductor package. And a method for manufacturing a semiconductor package.

The present invention provides the following means in order to solve the above problems.
A semiconductor package of the present invention includes a semiconductor element having a plurality of electrode portions on one surface, and an insulating substrate having openings that are bonded to one surface of the semiconductor element and expose the plurality of electrode portions, respectively. An external electrode patterned so as to wrap around from one surface of the base material to the side surface in a state of being electrically connected to the plurality of electrode portions through the openings. It is a feature.

  According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor package, comprising: a semiconductor element having a plurality of electrode portions on one surface; and an insulation having openings that are bonded to one surface of the semiconductor element and expose the plurality of electrode portions. And an external electrode patterned so as to wrap around from one surface of the substrate to the side surface in a state of being electrically connected to the plurality of electrode portions through the openings, respectively. A method of manufacturing a plurality of semiconductor packages using a wafer in which a plurality of the semiconductor elements are provided in advance, wherein the openings are formed in the base material, and the plurality of semiconductors are in the vicinity of the openings. A marking step for forming a through-hole in a position surrounding each of the periphery of the element; and after the marking step, the opening and the electrode portion are positioned so as to face each other while positioning the base Bonding the wafer to the other surface of the substrate, and after the bonding step, patterning a conductive material at a predetermined position on one surface of the substrate including the opening and the through hole, An electrode forming step to be formed; and a cutting step of cutting the wafer along at least the through-hole so as to separate each of the plurality of semiconductor elements after the electrode forming step. is there.

In the semiconductor package and the manufacturing method of the semiconductor package according to the present invention, a marking process, a bonding process, an electrode forming process, and a cutting process are sequentially performed using a wafer on which a plurality of semiconductor elements are provided in advance. A plurality of semiconductor packages can be manufactured simultaneously.
First, an insulating base material having the same or larger size as the wafer is prepared, and a marking process is performed in which openings and through holes are formed in the base material. This opening exposes the electrode portion of each semiconductor element. A through hole is formed in the vicinity of the opening and surrounding the periphery of the semiconductor element so as to penetrate the substrate. That is, this through hole is formed between adjacent semiconductor elements.

  After the marking process is completed, a plurality of semiconductor elements are bonded to the base material using the openings and the through holes as marks. That is, the wafer is bonded to the other surface of the base material by fusion or the like while positioning so that the opening formed in the base material and the electrode portion face each other. In particular, since the position of the electrode portion can be confirmed from the one surface side of the substrate through the opening, the semiconductor elements provided on the wafer can be accurately aligned.

  After the joining step is completed, an electrode forming step is performed in which the conductive material is patterned at a predetermined position on one surface of the base material to form an external electrode. At this time, the conductive material is patterned so as to include both the opening and the through hole. As a result, the conductive material enters the opening and the through hole. Therefore, the external electrode is in contact with and electrically connected to the electrode portion of the semiconductor element through the opening.

  After the electrode forming process is completed, a cutting process for cutting the wafer with a dicing blade or the like is performed so as to separate the plurality of semiconductor elements. At this time, cutting is performed with a width smaller than the size of the through-hole while at least along the through-hole formed in the base material. Thereby, a plurality of semiconductor elements can be solidified, and a plurality of semiconductor packages can be manufactured at a time.

Particularly, since the through hole into which the external electrode has entered is cut with a width smaller than the size of the through hole, a part of the external electrode remains on the inner peripheral surface of the through hole. As a result, a semiconductor package in which external electrodes are formed not only on one side of the substrate but also on the side surface, that is, a semiconductor package having external electrodes patterned so as to wrap around from one side of the substrate to the side surface. Can be manufactured.
Accordingly, when this semiconductor package is turned over and flip chip mounted on an external component such as a circuit board, the external electrode formed on one surface side of the base material is hidden as in the conventional case. Is also formed on the side surface side, so the state after mounting (soldering condition etc.) can be confirmed through this part. Therefore, inspection after mounting can be performed easily and reliably.
Further, since only a base material such as a polyimide film is used, the thickness can be minimized, and the chip size level can be reduced.

As described above, according to the semiconductor package of the present invention, it is possible to easily and surely perform the mounting inspection while reducing the thickness.
In addition, according to the method for manufacturing a semiconductor package according to the present invention, a semiconductor package capable of exhibiting such an effect can be efficiently manufactured at a time. In particular, since it can be manufactured using a wafer on which a plurality of semiconductor elements are provided in advance, a large number of semiconductor packages can be manufactured at one time, and the productivity is excellent.

  Further, in the method for manufacturing a semiconductor package according to the present embodiment, in the method for manufacturing a semiconductor package according to the present invention, the electrode forming step forms the conductive material on the entire surface of the substrate by plating. Then, the external electrode is formed by patterning the deposited plating layer by etching using a mask.

  In the method for manufacturing a semiconductor package according to the present invention, when performing the electrode forming step, first, a conductive material is formed on the entire one surface of the substrate by plating. At this time, the plating enters the opening and the through hole. Next, the formed plating layer is patterned by etching using a mask, and external electrodes are formed only at predetermined positions on one surface of the substrate including the openings and the through holes. That is, an unnecessary portion of the plating layer formed on one surface side of the substrate is removed. Thus, even if the through-hole has already been formed on the base material, the external electrode can be easily and reliably formed at a predetermined position on one surface of the base material by a simple method of plating and etching. It is easy to manufacture and can improve productivity.

  The method for manufacturing a semiconductor package according to the present invention is the method for manufacturing a semiconductor package according to the present invention, wherein the electrode forming step applies the conductive material in paste form to the predetermined position and applies the applied conductive material. And the external electrode is formed by curing.

  In the method of manufacturing a semiconductor package according to the present invention, when performing the electrode forming process, a paste-like conductive material is applied to a predetermined position on one surface of the base material including the opening and the through hole by screen printing or the like. The external electrode is formed by applying and curing the applied conductive material. As described above, the external electrode can be directly formed at a predetermined position on one surface of the base material without performing etching or the like, so that it can be manufactured more efficiently and productivity can be improved.

  In addition, the semiconductor package of the present embodiment includes a semiconductor element having a plurality of electrode portions on one surface and an insulating material having openings that are bonded to one surface of the semiconductor element and expose the plurality of electrode portions. A base material, a metal layer formed on one surface of the base material, and electrically connected to the plurality of electrode portions through the openings, respectively, from one surface of the metal layer And an external electrode patterned to wrap around the side surface of the metal layer and the side surface of the base material.

  According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor package, comprising: a semiconductor element having a plurality of electrode portions on one surface; and an insulation having openings that are bonded to one surface of the semiconductor element and expose the plurality of electrode portions. One of the metal layers in a state of being electrically connected to the plurality of electrode portions through the openings, and a metal layer formed on one surface of the base material, respectively. A method of manufacturing a plurality of semiconductor packages having external electrodes patterned so as to wrap around from the surface to the side surface of the metal layer and the side surface of the substrate using a wafer on which a plurality of the semiconductor elements are provided in advance A metal layer forming step of forming the metal layer on one surface of the substrate, and after the metal layer forming step, forming the opening in the metal layer, and in the vicinity of the opening, Circumference of multiple semiconductor elements A marking step for forming a through-hole at a position surrounding each of the substrate, and after the marking step, with the substrate interposed therebetween, while positioning so that the opening and the electrode portion face each other, the other of the substrate A bonding step of bonding the wafer to the surface of the substrate, and after the bonding step, the base material is processed according to the opening and the through hole formed in the metal layer to form the opening and the through hole in the base material. A base material processing step, and after the base material processing step, a conductive material is patterned at a predetermined position on one surface of the metal layer including the opening and the through hole formed in the base material and the metal layer. An electrode forming step for forming the external electrode, and a cutting step for cutting the wafer along at least the through-hole so as to separate each of the plurality of semiconductor elements after the electrode forming step. It is characterized in.

In the semiconductor package and the semiconductor package manufacturing method according to the present invention, a metal layer forming step, a marking step, a bonding step, a base material processing step, an electrode forming step, and a wafer using a wafer on which a plurality of semiconductor elements are provided in advance. A plurality of semiconductor packages can be manufactured simultaneously by sequentially performing each step of the cutting step.
First, an insulating base material having the same size as or larger than that of the wafer is prepared, and a metal layer forming step is performed in which a metal layer such as copper is formed on one surface of the base material by fusion or the like.

  After this metal layer forming step is completed, a marking step for forming openings and through holes in the metal layer is performed. This opening is for exposing the electrode portion of each semiconductor element later. In addition, a through hole is formed in the vicinity of the opening and surrounding the periphery of the semiconductor element so as to penetrate only the metal layer. That is, this through hole is formed between adjacent semiconductor elements. At this point, openings and through holes are formed only in the metal layer.

  After the marking process is completed, a wafer provided with a plurality of semiconductor elements is bonded to the base material with the openings and the through holes as marks. That is, a bonding process is performed in which the wafer is bonded to the other surface of the substrate by fusion or the like while the substrate is positioned so that the opening formed in the metal layer and the electrode portion face each other. .

  After the joining step is completed, the base material is processed in accordance with the openings and through holes formed in the metal layer, and the base material processing step for forming the same openings and through holes in the base material is performed. As a result, the electrode portion of the semiconductor element is exposed to the metal layer side through the through hole.

  After this substrate processing step, an electrode forming step is performed in which an external electrode is formed by patterning a conductive material at a predetermined position on one surface of the metal layer including the opening and the through hole. As a result, the conductive material enters the opening and the through hole. Therefore, the external electrode is in contact with and electrically connected to the electrode portion of the semiconductor element through the opening.

  Then, after the electrode forming process, a cutting process for cutting the wafer with a dicing blade or the like is performed so as to separate the plurality of semiconductor elements. At this time, cutting is performed with a width smaller than the size of the through-hole while at least along the through-hole formed in the base material. Thereby, a plurality of semiconductor elements can be solidified, and a plurality of semiconductor packages can be manufactured at a time.

Particularly, since the through hole into which the external electrode has entered is cut with a width smaller than the size of the through hole, a part of the external electrode remains on the inner peripheral surface of the through hole. As a result, a semiconductor package in which external electrodes are formed not only on one side of the metal layer but also on the side surface of the metal layer and the substrate, that is, from one side of the metal layer to the side surface of the metal layer and the substrate. A semiconductor package having external electrodes patterned so as to wrap around can be manufactured.
Therefore, when the semiconductor package is turned over and flip chip mounted on an external component such as a circuit board, the external electrode formed on one surface side of the metal layer is hidden as in the conventional case. Is also formed on the side surface side, so the state after mounting (soldering condition etc.) can be confirmed through this part. Therefore, inspection after mounting can be performed easily and reliably.

In addition, since the external electrode is formed on the metal layer, the “conductive” of the conductive material is good and the adhesion can be increased. Therefore, the external electrode can be formed more stably, and the reliability can be improved also in this respect.
Further, since only a base material such as a polyimide film is used, the thickness can be minimized, and the chip size level can be reduced.

As described above, according to the semiconductor package of the present invention, it is possible to easily and surely perform the mounting inspection while reducing the thickness.
In addition, according to the method for manufacturing a semiconductor package according to the present invention, a semiconductor package capable of exhibiting such an effect can be efficiently manufactured at a time. In particular, since it can be manufactured using a wafer on which a plurality of semiconductor elements are provided in advance, a large number of semiconductor packages can be manufactured at one time, and the productivity is excellent.

  According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor package, comprising: a semiconductor element having a plurality of electrode portions on one surface; and an insulation having openings that are bonded to one surface of the semiconductor element and expose the plurality of electrode portions. One of the metal layers in a state of being electrically connected to the plurality of electrode portions through the openings, and a metal layer formed on one surface of the base material, respectively. A method of manufacturing a plurality of semiconductor packages having external electrodes patterned so as to wrap around from the surface to the side surface of the metal layer and the side surface of the substrate using a wafer on which a plurality of the semiconductor elements are provided in advance A metal layer forming step for forming the metal layer on one surface of the base material, and after the metal layer forming step, the opening is formed in the base material and the metal layer, and in the vicinity of the opening. The plurality of half A marking step for forming a through-hole at a position surrounding each of the surroundings of the body element; and after the marking step, the wafer is placed on the other surface of the substrate while aligning so that the opening and the electrode portion face each other. A bonding step for bonding the electrodes, and an electrode forming step for forming the external electrode by patterning a conductive material at a predetermined position on one surface of the metal layer including the opening and the through hole after the bonding step; And a cutting step of cutting the wafer along at least the through-hole so as to separate the plurality of semiconductor elements after the electrode forming step.

In the semiconductor package manufacturing method according to the present invention, a metal layer forming process, a marking process, a bonding process, an electrode forming process, and a cutting process are sequentially performed using a wafer on which a plurality of semiconductor elements are provided in advance. Thus, a plurality of semiconductor packages can be manufactured simultaneously.
First, an insulating base material having the same size as or larger than that of the wafer is prepared, and a metal layer forming step is performed in which a metal layer such as copper is formed on one surface of the base material by fusion or the like.

  After this metal layer forming step is completed, a marking step for forming openings and through holes is performed on both the base material and the metal layer. This opening exposes the electrode portion of each semiconductor element. A through hole is formed in the vicinity of the opening and surrounding the periphery of the semiconductor element so as to penetrate both the base material and the metal layer. That is, this through hole is formed between adjacent semiconductor elements.

  After the marking process is completed, a wafer provided with a plurality of semiconductor elements is bonded to the base material with the openings and the through holes as marks. That is, a bonding process is performed in which the wafer is bonded to the other surface of the base material by fusion or the like while positioning the opening and the electrode portion so as to face each other. In particular, since the position of the electrode portion can be confirmed from the metal layer side through the opening, the semiconductor element can be accurately aligned.

  After the joining process is completed, an electrode forming process is performed in which an external electrode is formed by patterning a conductive material at a predetermined position on one surface of the metal layer including the opening and the through hole. As a result, the conductive material enters the opening and the through hole. Therefore, the external electrode is in contact with and electrically connected to the electrode portion of the semiconductor element through the opening.

After the electrode forming process is completed, a cutting process for cutting the wafer with a dicing blade or the like is performed so as to separate the plurality of semiconductor elements. At this time, cutting is performed with a width smaller than the size of the through-hole while at least along the through-hole formed in the base material.
Thereby, a plurality of semiconductor elements can be solidified, and a plurality of semiconductor packages can be manufactured at a time.

Particularly, since the through hole into which the external electrode has entered is cut with a width smaller than the size of the through hole, a part of the external electrode remains on the inner peripheral surface of the through hole. As a result, a semiconductor package in which external electrodes are formed not only on one side of the metal layer but also on the side surface of the metal layer and the substrate, that is, from one side of the metal layer to the side surface of the metal layer and the substrate. A semiconductor package having external electrodes patterned so as to wrap around can be manufactured.
Therefore, when the semiconductor package is turned over and flip chip mounted on an external component such as a circuit board, the external electrode formed on one surface side of the metal layer is hidden as in the conventional case. Is also formed on the side surface side, so the state after mounting (soldering condition etc.) can be confirmed through this part. Therefore, inspection after mounting can be performed easily and reliably.

In addition, since the external electrode is formed on the metal layer, the “conductive” of the conductive material is good and the adhesion can be increased. Therefore, the external electrode can be formed more stably, and the reliability can be improved also in this respect.
Further, since only a base material such as a polyimide film is used, the thickness can be minimized, and the chip size level can be reduced.

As described above, according to the semiconductor package of the present invention, it is possible to easily and surely perform the mounting inspection while reducing the thickness.
In addition, according to the method for manufacturing a semiconductor package according to the present invention, a semiconductor package capable of exhibiting such an effect can be efficiently manufactured at a time. In particular, since it can be manufactured using a wafer on which a plurality of semiconductor elements are provided in advance, a large number of semiconductor packages can be manufactured at one time, and the productivity is excellent.

  The method for manufacturing a semiconductor package according to the present invention is the method for manufacturing a semiconductor package according to the present invention, wherein the electrode forming step is performed by depositing the conductive material on one whole surface of the metal layer by plating. The external electrode is formed by patterning the deposited plating layer by etching using a mask.

  In the method of manufacturing a semiconductor package according to the present invention, when performing the electrode forming step, first, a conductive material is formed on the entire one surface of the metal layer by plating. At this time, the plating enters the opening and the through hole. Next, the formed plating layer is patterned by etching using a mask to form external electrodes only at predetermined positions on one surface of the metal layer including the opening and the through hole. That is, an unnecessary portion of the plating layer formed on one surface side of the metal layer is removed. Thus, even if through holes have already been formed in both the metal layer and the base material, the external electrode can be easily and reliably placed at a predetermined position on one surface of the metal layer by a simple method of plating and etching. Since it can form, it is easy to manufacture and productivity can be improved.

  The method for manufacturing a semiconductor package according to the present invention is the method for manufacturing a semiconductor package according to the present invention, wherein the electrode forming step applies the conductive material in paste form to the predetermined position and applies the applied conductive material. And the external electrode is formed by curing.

  In the method of manufacturing a semiconductor package according to the present invention, when performing the electrode formation step, a paste-like conductive material is applied to a predetermined position on one surface of the metal layer including the opening and the through hole by screen printing or the like. The external electrode is formed by applying and curing the applied conductive material. As described above, the external electrode can be directly formed at a predetermined position on one surface of the metal layer without performing an etching process or the like, so that it can be manufactured more efficiently and productivity can be improved.

  According to another aspect of the present invention, there is provided a semiconductor package having an insulating photosensitive element having a semiconductor element having a plurality of electrode portions on one surface and an opening formed on one surface of the semiconductor element and exposing the plurality of electrode portions. And an external electrode patterned so as to wrap around from one surface of the photosensitive resin to the side surface while being electrically connected to the plurality of electrode portions through the openings. It is characterized by that.

  According to another aspect of the present invention, there is provided a semiconductor package manufacturing method comprising: a semiconductor element having a plurality of electrode portions on one surface; and an insulation having openings formed on one surface of the semiconductor element and exposing the plurality of electrode portions. And an external electrode patterned so as to wrap around from one surface of the photosensitive resin to the side surface in a state of being electrically connected to the plurality of electrode portions through the openings. A semiconductor package including a plurality of the semiconductor elements, and a resin forming step of forming the photosensitive resin on one surface of the wafer; and After the resin forming step, the photosensitive resin is exposed to form the opening in the photosensitive resin, and penetrates to a position in the vicinity of the openings and surrounding each of the plurality of semiconductor elements. Marking step for forming a hole, and electrode forming step for patterning a conductive material at a predetermined position on one surface of the photosensitive resin including the opening and the through hole after the marking step. And a cutting step of cutting the wafer along at least the through-hole so as to separate the plurality of semiconductor elements after the electrode forming step.

In the semiconductor package and the semiconductor package manufacturing method according to the present invention, each step of the resin forming step, the marking step, the bonding step, the electrode forming step, and the cutting step is performed using a wafer on which a plurality of semiconductor elements are provided in advance. By performing in order, a plurality of semiconductor packages can be manufactured simultaneously.
First, a resin forming process is performed in which a photosensitive resin is formed on one whole surface of a wafer provided with a plurality of semiconductor elements by coating or the like. Thereby, the electrode part of each semiconductor element will be in the state covered with photosensitive resin.

  After this resin formation process is completed, a photosensitive resin is exposed using a mask or the like, and a marking process is performed to form openings and through holes in the photosensitive resin. This opening exposes the electrode portion of each semiconductor element. A through hole is formed in the vicinity of the opening and surrounding the periphery of the semiconductor element so as to penetrate both the base material and the metal layer. That is, this through hole is formed between adjacent semiconductor elements. Thereby, the electrode part of the some semiconductor element provided in the wafer will be in the state exposed to the photosensitive resin side.

  After this marking process is completed, an electrode forming process is performed in which an external electrode is formed by patterning a conductive material at a predetermined position on one surface of the photosensitive resin including the opening and the through hole. As a result, the conductive material enters the opening and the through hole. Therefore, the external electrode is in contact with and electrically connected to the electrode portion of the semiconductor element through the opening.

After the electrode forming process is completed, a cutting process for cutting the wafer with a dicing blade or the like is performed so as to separate the plurality of semiconductor elements. At this time, cutting is performed with a width smaller than the size of the through-hole while at least along the through-hole formed in the base material.
Thereby, a plurality of semiconductor elements can be solidified, and a plurality of semiconductor packages can be manufactured at a time.

Particularly, since the through hole into which the external electrode has entered is cut with a width smaller than the size of the through hole, a part of the external electrode remains on the inner peripheral surface of the through hole. As a result, a semiconductor package in which external electrodes are formed not only on one side of the photosensitive resin but also on the side surface, that is, a semiconductor having an external electrode patterned so as to wrap around from one side of the photosensitive resin to the side surface A package can be manufactured.
Therefore, when the semiconductor package is turned over and flip chip mounted on an external component such as a circuit board, the external electrode formed on one surface side of the metal layer is hidden as in the conventional case. Is also formed on the side surface side, so the state after mounting (soldering condition etc.) can be confirmed through this part. Therefore, inspection after mounting can be performed easily and reliably.

  Further, since the semiconductor package can be easily manufactured only by forming the photosensitive resin on one surface of the wafer, the manufacturing is simple. Further, the thickness can be reduced as much as possible, and the chip size level can be reduced.

As described above, according to the semiconductor package of the present invention, it is possible to easily and surely perform the mounting inspection while reducing the thickness.
In addition, according to the method for manufacturing a semiconductor package according to the present invention, a semiconductor package capable of exhibiting such an effect can be efficiently manufactured at a time. In particular, since it can be manufactured using a wafer on which a plurality of semiconductor elements are provided in advance, a large number of semiconductor packages can be manufactured at one time, and the productivity is excellent.

  Moreover, the manufacturing method of the semiconductor package of this invention is the manufacturing method of the semiconductor package of the said invention WHEREIN: The said electrode formation process formed the said conductive material into the film by plating on one whole surface of the said photosensitive resin. Then, the external electrode is formed by patterning the deposited plating layer by etching using a mask.

  In the method for manufacturing a semiconductor package according to the present invention, when performing the electrode forming step, first, a conductive material is formed on the entire surface of the photosensitive resin by plating. At this time, the plating enters the opening and the through hole. Next, the formed plating layer is patterned by etching using a mask to form external electrodes only at predetermined positions on one surface of the metal layer including the opening and the through hole. That is, an unnecessary portion of the plating layer formed on one surface of the photosensitive resin is removed. Thus, since the external electrode can be easily and reliably formed at a predetermined position on one surface of the photosensitive resin by a simple method of plating and etching, it is easy to manufacture and the productivity can be improved.

  Further, the semiconductor package manufacturing method of the present invention is the method of manufacturing a semiconductor package of the present invention, wherein the electrode forming step applies the paste-like conductive material to the predetermined position and the applied conductive material. And the external electrode is formed by curing.

  In the method for manufacturing a semiconductor package according to the present invention, when performing the electrode forming step, a paste-like conductive material is screen-printed or the like on a predetermined position on one surface of the photosensitive resin including the opening and the through hole. In addition, the external electrode is formed by curing the applied conductive material. As described above, the external electrode can be directly formed at a predetermined position on one surface of the photosensitive resin without performing etching or the like, so that it can be manufactured more efficiently and productivity can be improved.

  The semiconductor package manufacturing method of the present invention is the semiconductor package manufacturing method according to any one of the above-described present invention, wherein the width of the through hole is set to be larger than twice the thickness of the external electrode during the marking step. It is characterized by being formed with a large width.

  In the method for manufacturing a semiconductor package according to the present invention, when the through hole is formed in the marking process, the through hole is formed with a width larger than twice the film thickness of the external electrode to be formed later. Accordingly, when the external electrode enters the through hole and is formed on the inner peripheral surface, it is possible to prevent the through hole from being completely blocked by the external electrode. That is, the external electrode is in a state where a change such as a dent is provided at the position of the through hole. Therefore, the position of the through hole can be confirmed even after the external electrode is formed. Therefore, when performing the cutting process, the wafer can be accurately cut even from the external electrode side, and the cutting operation is facilitated.

  The semiconductor package manufacturing method of the present invention is the semiconductor package manufacturing method of any one of the above-described present invention, wherein the wafer is cut with a width larger than the width of the through hole during the cutting step, The external electrode is cut with a width smaller than the width of the hole.

  In the method of manufacturing a semiconductor package according to the present invention, when performing the cutting process, the width for cutting the wafer is distinguished from the width for cutting the external electrode that has entered the through hole. First, by cutting the external electrode with a width smaller than the width of the through hole, the portion that becomes the side electrode can be left as much as possible. Therefore, a more reliable semiconductor package can be manufactured. Further, by cutting the wafer side with a width larger than the width of the through hole, the external electrode and the wafer are separated. Therefore, even when the external electrode is melted by solder during flip-chip mounting, it does not wrap around and come into contact with the wafer, thereby preventing electrical contact. Therefore, malfunction can be prevented and quality can be improved.

  The semiconductor package manufacturing method of the present invention is characterized in that, in the semiconductor package manufacturing method of the present invention, the wafer side is cut first in the cutting step.

  In the method of manufacturing a semiconductor package according to the present invention, when the cutting process is performed, the wafer side having a large width to be cut is cut first, so that the cutting from the wafer side to the external electrode side can be continued. That is, the wafer can be cut from the same direction without turning the wafer over. Therefore, the time taken for the cutting process can be shortened, and productivity can be further increased.

  Further, the semiconductor package manufacturing method of the present invention is the semiconductor package manufacturing method according to any one of the above-mentioned present invention, wherein a mark is formed on the other surface of the wafer facing the through hole before performing the cutting step. And a mark forming step for forming the mark.

  In the method for manufacturing a semiconductor package according to the present invention, the position where the through hole is formed can be confirmed from the other surface side of the wafer by performing the mark forming step before the cutting step. Therefore, even from the wafer side, the wafer can be accurately cut by using this mark as a guide.

According to the semiconductor package of the present invention, it is possible to easily and surely perform mounting inspection while reducing the thickness.
In addition, according to the method for manufacturing a semiconductor package according to the present invention, a semiconductor package capable of exhibiting such an effect can be efficiently manufactured at a time. In particular, since it can be manufactured using a wafer on which a plurality of semiconductor elements are provided in advance, a large number of semiconductor packages can be manufactured at one time, and the productivity is excellent.

(First embodiment)
A semiconductor package and a semiconductor package manufacturing method according to a first embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a cross-sectional view showing a first embodiment of a semiconductor package according to the present invention.
As shown in FIG. 1, the semiconductor package 1 of the present embodiment includes an IC chip (semiconductor element) 2 having two (plurality) of electrode portions 2 a on one surface, and is bonded to one surface of the IC chip 2. And an insulating base material 4 having openings 3 through which the electrode portions 2a are exposed. In the semiconductor package 1, a metal layer 5 is provided on the upper surface, which is one surface 4 a of the substrate 4, and an external electrode 6 is formed on the surface of the metal layer 5. The external electrode 6 wraps around the side surface of the metal layer 5 and the side surface of the base material 4 from one surface of the metal layer 5 in a state of being electrically connected to the electrode portion 2 a through the opening 3. It is patterned.

  Although the polyimide film was used for the said base material 4 in this embodiment, another material may be sufficient if it is an electrically insulating material. For example, a PEN (polyethylene naphthalate) film or the like is also suitable from the viewpoint of strength, heat resistance, and availability. The metal layer 5 is made of copper (Cu) in this embodiment, but may be made of other materials as long as it is made of a conductive metal material.

  Further, two external electrodes 6 of the present embodiment are formed in accordance with the number of electrode portions 2a, and are formed so as to be electrically insulated from each other. That is, the external electrodes 6 are formed so as to wrap around the side surfaces of the base material 4 only in the vicinity of the electrode portions 2 a, and the external electrodes 6 are not connected to each other through the side surface portions of the base material 4.

  The semiconductor package 1 configured as described above is turned upside down and placed so that one surface of the external electrode 6 is in surface contact with an external component (not shown) such as a circuit board, and using solder. Used by joining to external parts. That is, it is used by flip chip mounting.

Next, a semiconductor package manufacturing method for manufacturing a plurality of the semiconductor packages 1 at the same time will be described. FIG. 2 is a plan view showing a wafer used when the semiconductor package shown in FIG. 1 is manufactured. As shown in FIG. 2, this manufacturing method is a method of manufacturing using a wafer 10 in which a plurality of IC chips 2 are provided in advance. In FIG. 2, a wafer 10 provided with 92 IC chips 2 is shown.
The manufacturing method of the semiconductor package of this embodiment performs the metal layer forming process, the marking process, the joining process, the base material processing process, the electrode forming process, and the cutting process in order using the wafer 10. It is a manufacturing method. Hereinafter, these steps will be described in detail with reference to FIGS. 3 to 14. FIG. 3 is a flowchart showing an example of a process when manufacturing the semiconductor package shown in FIG. 4 to 14 are partial cross-sectional views showing the state of the semiconductor package in each step shown in the flowchart of FIG.

First, a metal layer forming process is performed. FIG. 4 is a partial cross-sectional view showing a state immediately after finishing the metal layer forming process in the semiconductor package manufacturing process. In the metal layer forming step, a base 4 having the same size as the wafer 10 or larger than the wafer 10 is prepared, and the metal layer 5 is fused to one surface 4a of the base 4 as shown in FIG. (S1).
In the present embodiment, a case where the base material 4 is a long polyimide film and a size larger than the wafer 10 is used as shown in FIG. 2 will be described as an example. For example, the base material 4 is formed in a square shape when viewed from above, and marks M are provided at the four corners for accurate positioning and setting in a cutting device (not shown) having a dicing blade.

FIG. 5 is a diagram illustrating a state in which openings and through holes are formed in the metal layer after the state illustrated in FIG. 4.
After the above-described metal layer forming step is completed, as shown in FIG. 5, the opening 3 is formed in the metal layer 5, and the through holes are positioned in the vicinity of the openings 3 and surrounding the plurality of IC chips 2. The marking process for forming 11 is performed (S2).
Specifically, a mask (not shown) is provided at a predetermined position of the metal layer 5 by photolithography, and the metal layer 5 is etched within a range excluding the mask. By carrying out like this, the opening 3 and the through-hole 11 can each be formed. The openings 3 are for exposing the electrode portions 2a of the IC chip 2 later, and are formed according to the number of IC chips 2 and the number of electrode portions 2a. Further, the through hole 11 is formed between the adjacent IC chips 2 and serves as a guide when solidifying later. At this time, the opening 3 and the through hole 11 are formed only in the metal layer 5.
In this embodiment, when performing this marking process, the width (W1) of the through hole 11 and the width (W2) of the opening 3 are formed to be larger than twice the film thickness (h) of the external electrode 6. ing.

FIG. 6 is a diagram illustrating a state in which the wafer is bonded to the base material after the state illustrated in FIG. 5.
Next, after the marking process is finished, as shown in FIG. 6, the base material 4 is positioned while the base material 4 is sandwiched between the openings 3 and the electrode portions 2a of the IC chips 2 so as to face each other. A bonding step of bonding the plurality of wafers 10 to the lower surface, which is the other surface 4b, is performed (S3). That is, using the opening 3 and the through hole 11 as a mark, the wafer 10 provided with the IC chip 2 on the other surface 4b of the substrate 4 is fused while being aligned so that the opening 3 and the electrode portion 2a face each other. Join by etc.

FIG. 7 is a diagram illustrating a state in which openings and through holes are formed in the base material after the state illustrated in FIG. 6.
Next, after the joining process is completed, as shown in FIG. 7, the base material 4 is processed in accordance with the opening 3 and the through hole 11 formed in the metal layer 5, and the opening 3 and the through hole 11 are formed in the base material 4. A base material processing step to be formed is performed (S4). Specifically, etching is performed using the metal layer 5 as a mask, and the opening 3 and the through hole 11 similar to the opening 3 and the through hole 11 formed in the metal layer 5 are formed in the substrate 4. As a result, the electrode portion 2 a of the IC chip 2 is exposed to the metal layer 5 side through the opening 3. In addition, since the process at this time reduces the influence with respect to the base material 4 and the wafer 10 as much as possible, an etching process is preferable.

FIG. 8 is a diagram showing a state in which a metal layer is formed by plating a conductive material after the state shown in FIG.
Next, after the base material processing step is finished, the conductive material is patterned at a predetermined position on one surface of the metal layer 5 including the opening 3 and the through hole 11 formed in the metal layer 5 and the base material 4 to form the external electrode. The electrode formation process which forms 6 is performed.
Specifically, as shown in FIG. 8, first, a metal layer 12 is formed by depositing a conductive material on one whole surface of the metal layer 5 by plating (S5). This plating may be performed by combining electroless plating and electroplating, by combining direct plating and electroplating, or by only electroless plating. Thereby, the metal layer 12 by plating enters the opening 3 and the through hole 11.

  At this time, as described above, the width (W1) of the through hole 11 and the width (W2) of the opening 3 are larger than the film thickness of the external electrode 6, that is, the film thickness (h) of the metal layer 12. Therefore, the opening 3 and the through hole 11 after plating are not completely closed, and some dents 3a and 11a are generated. Therefore, the positions of the through holes 11 and the openings 3 can be confirmed even after plating.

FIG. 9 is a diagram showing a state in which a mask is patterned on the plated metal layer after the state shown in FIG.
Subsequently, as shown in FIG. 9, a mask (resist film) 13 is formed on the plated metal layer by photolithography (S6). This mask 13 is for forming the external electrode 6 from the metal layer 12, and is formed so as to connect the adjacent electrode portions 2a with the through hole 11 interposed therebetween.

FIG. 10 is a diagram illustrating a state in which external electrodes are formed after the state illustrated in FIG. 9.
Next, by etching the metal layer 12 in a range excluding the mask 13 and peeling the mask 13, the external electrode 6 can be formed at a predetermined position including the opening 3 and the through hole 11 as shown in FIG. Yes (S7). Since the external electrode 6 is in contact with the electrode portion 2a of the IC chip 2 through the opening 3, it is in an electrically connected state.

Next, after the electrode forming step is completed, a cutting step of cutting the wafer 10 along at least the through-holes 11 is performed so as to separate the plurality of IC chips 2 (S8). FIG. 11 is a diagram showing a state where adjacent external electrodes are cut after the state shown in FIG.
Specifically, first, the wafer 10 is set using the mark M of the base material 4 shown in FIG. Next, as shown in FIG. 11, the external electrode 6 side is cut first with a width smaller than the width (W1) of the through hole 11 along the through hole 11 by a dicing blade (not shown).
Thereby, an insulation state is ensured between the adjacent IC chips 2. At this time, in addition to the accurate positioning by the mark M provided on the base material 4, as described above, a slight dent 11 a is generated in the plated through-hole 11. Even from the bottom, the dent 11a can be used as a guide for accurate cutting. Further, since the external electrode 6 is cut with a width smaller than that of the through hole 11, a portion that becomes a side electrode can be left as much as possible.

FIG. 12 is a diagram illustrating a state in which a dicing tape is attached to one surface of the external electrode after the state illustrated in FIG. 11.
After the cutting on the external electrode 6 side is completed, a dicing tape 14 is attached to one surface of each external electrode 6 as shown in FIG. After pasting, the wafer 10 is turned over and set in the processing apparatus again. At this time, similarly, the mark M provided on the substrate 4 is set while being accurately positioned.

FIG. 13 is a diagram illustrating a state in which the wafer is cut after turning the wafer upside down after the state illustrated in FIG. 12. Moreover, FIG. 14 is a figure which shows the state which peeled the dicing tape after the state shown in FIG.
Then, as shown in FIG. 13, the wafer 10 is cut with a dicing blade having a width larger than the width (W1) of the through hole 11. After cutting, the dicing tape 14 is peeled off, whereby a plurality of IC chips 2 can be separated from the same wafer 10 as shown in FIG. 14, and a plurality of semiconductor packages 1 can be manufactured at a time. it can.

In particular, as shown in FIG. 11, the through hole 11 into which the external electrode 6 has entered is cut with a width smaller than the width (W1) of the through hole 11, so that not only one surface of the metal layer 5 but also the metal layer 5 and the semiconductor package 1 in which the external electrode 6 is also formed on the side surface of the base material 4, that is, the external pattern patterned so as to wrap around the side surface of the metal layer 5 and the base material 4 from one side of the metal layer 5. The semiconductor package 1 having the electrodes 6 can be manufactured.
Therefore, when the semiconductor package 1 is turned over and flip chip mounted on an external component (not shown) such as a circuit board, the external electrode 6 formed on one surface side of the metal layer 5 is hidden as in the conventional case. However, since the external electrode 6 is also formed on the side surface side, it is possible to confirm the state after mounting (such as the degree of melting of solder) through this portion. Therefore, inspection after mounting can be performed easily and reliably.

  Further, since the wafer 10 is cut with a width larger than the width (W1) of the through hole 11 during the cutting process, the external electrode 6 and the wafer 10, that is, the IC chip 2 are separated from each other to be in a non-contact state. It has become. Therefore, even when the external electrode 6 is melted by solder during flip chip mounting, it does not wrap around and contact the IC chip 2 and can be prevented from making electrical contact. Therefore, malfunction can be prevented, quality can be improved, and reliability can be improved.

Further, since the external electrode 6 is formed on the metal layer 5, the “sticking” of the conductive material is good and the adhesion can be increased. Therefore, the external electrode 6 can be formed more stably, and the reliability can be improved also in this respect. Moreover, since only the base material 4 such as a polyimide film is used, the thickness can be reduced as much as possible, and the chip size level can be reduced.
Moreover, since the external electrode 6 can be reliably formed by a simple method such as plating and etching during the electrode forming step, it is easy to manufacture and the productivity can be increased. Further, since the external electrode 6 side is cut first in the cutting step, the strong wafer 10 remains without being cut when turned over. Therefore, it can be turned over in a stable state, and stable production can be performed.

  As described above, according to the semiconductor package 1 of the present embodiment, mounting inspection can be easily and reliably performed while reducing the thickness. Further, according to the semiconductor package manufacturing method of the present embodiment, the semiconductor package 1 that exhibits the above-described effects can be efficiently manufactured at a time. In particular, since it can be manufactured using the wafer 10 on which a plurality of IC chips 2 are provided in advance, a large number of semiconductor packages 1 can be manufactured at a time, and the productivity is excellent.

(Second Embodiment)
Next, a semiconductor package and a semiconductor package manufacturing method according to a second embodiment of the present invention will be described with reference to FIGS. In the second embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted. The difference between the second embodiment and the first embodiment is that in the first embodiment, the wafer 10 is bonded after the opening 3 and the through hole 11 are formed only in the metal layer 5, whereas in the second embodiment, the second embodiment is different. The wafer 10 is bonded after the opening 3 and the through hole 11 are formed in both the metal layer 5 and the substrate 4.

The manufacturing method of the semiconductor package of this embodiment is a method for manufacturing by sequentially performing a metal layer forming step, a marking step, a joining step, an electrode forming step, and a cutting step. Each of these steps will be described below.
First, as in the first embodiment, a base material 4 having a size larger than that of the wafer 10 is prepared, and a metal layer forming step for forming the metal layer 5 on one surface 4a of the base material 4 is performed.

FIG. 15 is a process diagram for explaining a second embodiment of a method for manufacturing a semiconductor package according to the present invention, wherein a metal layer is formed on a substrate, and then an opening and a penetration are formed in the substrate and the metal layer. It is a figure which shows the state which formed the hole.
After the metal layer forming step is completed, as shown in FIG. 15, a marking step for forming the opening 3 and the through hole 11 in both the base material 4 and the metal layer 5 is performed. Specifically, the opening 3 and the through hole 11 are formed by processing using a laser, a punch / drill, or the like.

FIG. 16 is a diagram illustrating a state in which the wafer is bonded to the base material after the state illustrated in FIG. 15.
Next, after the marking process is completed, as shown in FIG. 16, a plurality of IC chips 2 are provided on the other surface 4b of the base material 4 while aligning the openings 3 and the electrode portions 2a so as to face each other. A bonding process for bonding the wafer 10 is performed. At this time, unlike the first embodiment, since the position of the electrode portion 2a can be confirmed from the metal layers 5 and 12 side through the opening 3, the IC chip 2 can be more accurately aligned.

  Next, after the bonding process is completed, the external electrode 6 is formed by patterning a conductive material at a predetermined position on one surface of the metal layer 5 including the opening 3 and the through hole 11 as in the first embodiment. An electrode formation process is performed.

  FIG. 17 is a diagram showing a state in which a metal layer is formed by plating a conductive material after the state shown in FIG. FIG. 18 is a view showing a state in which a mask is patterned on the plated metal layer after the state shown in FIG. FIG. 19 is a diagram showing a state in which external electrodes are formed after the state shown in FIG.

  That is, as shown in FIG. 17, a conductive layer is formed on one surface of the metal layer 5 by plating to form a metal layer (plating layer) 12, and then the plated metal layer as shown in FIG. A mask 13 is formed on 12 by photolithography. Then, the metal layer 12 is etched in a range excluding the mask 13 and the mask 13 is peeled off. Thereby, as shown in FIG. 19, the external electrode 6 can be formed at a predetermined position including the opening 3 and the through hole 11.

FIG. 20 is a diagram showing a state in which the wafer is cut after the state shown in FIG.
Finally, by performing the cutting process in the same manner as in the first embodiment, a plurality of semiconductor packages 1 can be simultaneously manufactured as shown in FIG. The semiconductor package 1 manufactured in this way can exhibit the same effects as the first embodiment.
In particular, according to the manufacturing method of the present embodiment, since the through-hole 11 is formed in both the base material 4 and the metal layer 5 before performing the bonding step, the IC chip 2 can be easily bonded.

(Third embodiment)
Next, a semiconductor package and a semiconductor package manufacturing method according to a third embodiment of the present invention will be described with reference to FIGS. In the third embodiment, the same components as those in the second embodiment are denoted by the same reference numerals, and the description thereof is omitted. The difference between the third embodiment and the second embodiment is that, in the second embodiment, the metal layer 5 is formed between the substrate 4 and the external electrode 6, but in the third embodiment, this metal The point is that the layer 5 is not formed.

FIG. 21 is a cross-sectional view showing a third embodiment of a semiconductor package according to the present invention.
As shown in FIG. 21, the semiconductor package 20 of the present embodiment is bonded to the IC chip 2 and one surface of the IC chip 2, and has an insulating base 4 having openings 3 that expose the electrode portions 2 a. And an external electrode 6 patterned so as to wrap around from one surface 4a of the base material 4 to the side surface in a state of being electrically connected to the electrode portion 2a through the opening 3 respectively.

Next, a method for manufacturing the semiconductor package 20 configured as described above will be described.
The manufacturing method of this embodiment is a method of manufacturing by sequentially performing a marking process, a joining process, an electrode forming process, and a cutting process. Each of these steps will be described below. The manufacturing method of the present embodiment is basically the same process sequence as that of the manufacturing method of the second embodiment, except that the metal layer 5 is not formed on the one surface 4a of the substrate 4.

FIG. 22 is a process diagram showing the method of manufacturing the semiconductor package shown in FIG. 21, and is a diagram showing a state in which openings and through holes are formed in the base material.
First, as shown in FIG. 22, a marking process for forming the opening 3 and the through hole 11 in the base material 4 is performed. Specifically, as in the second embodiment, the opening 3 and the through hole 11 are formed by a mask (not shown) provided by a photolithography technique and an etching process using the mask.

FIG. 23 is a diagram illustrating a state in which the wafer is bonded to the base material after the state illustrated in FIG. 22.
Next, after the marking process is completed, as shown in FIG. 23, a plurality of IC chips 2 are provided on the other surface 4b of the base material 4 while aligning the openings 3 and the electrode portions 2a so as to face each other. A bonding process for bonding the wafer 10 is performed. At this time, since the position of the electrode portion 2a can be confirmed from the one surface 4a side of the substrate 4 through the opening 3, the IC chip 2 can be aligned more accurately.

Next, after the joining process is completed, an electrode forming process is performed in which a conductive material is patterned to form the external electrode 6 at a predetermined position on the one surface 4a of the substrate 4 including the opening 3 and the through hole 11.
FIG. 24 is a diagram showing a state in which a metal layer is formed by plating a conductive material after the state shown in FIG. FIG. 25 is a view showing a state in which a mask is patterned on the plated metal layer after the state shown in FIG. FIG. 26 is a diagram showing a state in which external electrodes are formed after the state shown in FIG.

  That is, as shown in FIG. 24, after a metal layer 12 is formed by depositing a conductive material on one whole surface 4a of the substrate 4 by plating, the metal layer 12 is formed on the plated metal layer 12 as shown in FIG. A mask 13 is formed by photolithography. Then, the metal layer 12 is etched in a range excluding the mask 13 and the mask 13 is peeled off. As a result, the external electrode 6 can be formed at a predetermined position including the opening 3 and the through hole 11 as shown in FIG.

FIG. 27 is a diagram showing a state in which the wafer is cut after the state shown in FIG.
Finally, by performing the cutting process in the same manner as in the second embodiment, a plurality of semiconductor packages 20 can be simultaneously manufactured as shown in FIG.

As in the second embodiment, the semiconductor package 20 manufactured in this way can be easily and reliably inspected for mounting while reducing the thickness. In particular, since the metal layer 5 is not formed between the substrate 4 and the external electrode 6, further reduction in thickness can be achieved.
Moreover, according to the manufacturing method of this embodiment, since the process of forming the metal layer 5 on the one surface 4a of the base material 4 can be omitted, the productivity can be further increased.

(Fourth embodiment)
Next, a semiconductor package and a semiconductor package manufacturing method according to a fourth embodiment of the present invention will be described with reference to FIGS. In the fourth embodiment, the same components as those in the third embodiment are denoted by the same reference numerals, and the description thereof is omitted. The difference between the fourth embodiment and the third embodiment is that, in the third embodiment, the external electrode 6 is formed by plating or the like when performing the electrode forming step, but in the fourth embodiment, the paste-like conductive material is formed. The external electrode 6 is formed using a conductive material.

That is, in the manufacturing method of the present embodiment, when performing the electrode forming step, first, a paste-like conductive material is applied to a predetermined position where the external electrode 6 is formed, and the applied conductive material is heated and cured. The external electrode 6 is formed.
FIG. 28 is a process diagram for explaining the fourth embodiment of the semiconductor package manufacturing method according to the present invention, and shows a state in which the wafer is bonded after the opening and the through hole are formed in the base material. It is. FIG. 29 is a diagram showing a state in which external electrodes are formed after the state shown in FIG.

Specifically, as shown in FIG. 28, after bonding the wafer 10 to the other surface 4 b of the base material 4, as shown in FIG. 29, one surface of the base material 4 including the opening 3 and the through hole 11. A paste-like conductive material such as a silver paste is applied to the predetermined position 4a by screen printing or the like, and then cured by heating. Thereby, the external electrode 6 can be formed.
In particular, according to the manufacturing method of the present embodiment, the external electrode 6 can be formed directly on a predetermined position of the one surface 4a of the base material 4 without performing etching or the like. Can increase productivity.

(Fifth embodiment)
Next, a semiconductor package and a semiconductor package manufacturing method according to a fifth embodiment of the invention will be described with reference to FIGS. In the fifth embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted. The difference between the fifth embodiment and the first embodiment is that the substrate 4 is used in the first embodiment, whereas the photosensitive resin 31 is used instead of the substrate 4 in the fourth embodiment. Is a point.

FIG. 30 is a cross-sectional view showing a fifth embodiment of a semiconductor package according to the present invention.
As shown in FIG. 30, the semiconductor package 30 of the present embodiment is formed of an IC chip 2 and an insulating photosensitive film formed on one surface of the IC chip 2 and having openings 3 through which a plurality of electrode portions 2 a are exposed. The external electrode 6 patterned so as to wrap around the side surface from one surface 31a of the photosensitive resin 31 while being electrically connected to the plurality of electrode portions 2a through the opening 3 and the photosensitive resin 31, respectively. And.

Next, a method for manufacturing the semiconductor package 30 configured as described above will be described.
The manufacturing method according to the present embodiment is a method in which a resin forming step, a marking step, an electrode forming step, and a cutting step are sequentially performed, and the mark forming step is performed before the cutting step for manufacturing. Here, the case where the mark forming process is performed in the first stage before the resin forming process is described. Each of these steps will be described in detail below.

FIG. 31 is a process diagram showing a method of manufacturing the semiconductor package shown in FIG. 30 and shows a state in which marks are formed on the wafer.
First, as shown in FIG. 31, a mark forming process is performed for forming a mark 10 </ b> M serving as a guideline for the cutting process on the other surface of the wafer 10 so as to face the through hole 11 to be formed later. . Specifically, the mark 10M is formed on the other surface of the wafer 10 by performing etching using a mask (not shown).

FIG. 32 is a view showing a state in which a photosensitive resin is formed on the wafer after the state shown in FIG.
After the mark formation process is completed, as shown in FIG. 32, a resin formation process is performed in which a photosensitive resin 31 (for example, a photosensitive polyimide resin) is formed on the entire one surface of the wafer 10 by coating or the like. As a result, the electrode portions 2 a of the plurality of IC chips 2 provided on the wafer 10 are covered with the photosensitive resin 31. The photosensitive resin 31 preferably has resistance so as not to be affected by the etching process performed in the subsequent electrode forming step.

After this resin formation process is completed, the photosensitive resin 31 is exposed to perform a marking process for forming the openings 3 and the through holes 11 in the photosensitive resin 31. FIG. 33 is a view showing a state in which openings and through holes are formed in the photosensitive resin after the state shown in FIG. 32.
Specifically, the region other than the region where the opening 3 and the through hole 11 are formed is covered with a mask (not shown) provided by a photolithography technique, and then exposed to expose the photosensitive resin 31 as shown in FIG. 3 and the through-hole 11 can be formed. Thereby, the electrode parts 2a of the plurality of IC chips 2 provided on the wafer 10 are exposed to the photosensitive resin 31 side.

After the marking process is completed, an electrode forming process is performed in which the external electrode 6 is formed by patterning a conductive material at a predetermined position on one surface 31a of the photosensitive resin 31 including the opening 3 and the through hole 11.
FIG. 34 is a diagram showing a state in which a metal layer is formed by plating a conductive material after the state shown in FIG. FIG. 35 is a view showing a state in which a mask is patterned on the plated metal layer after the state shown in FIG. FIG. 36 is a diagram showing a state in which external electrodes are formed after the state shown in FIG.

  That is, as shown in FIG. 34, a conductive material is deposited on the entire surface 31a of the photosensitive resin 31 by plating to form the metal layer 12, and then the plated metal layer 12 as shown in FIG. A mask 13 is formed by photolithography. Then, the metal layer 12 is etched in a range excluding the mask 13 and the mask 13 is peeled off. Thereby, the external electrode 6 can be formed as shown in FIG.

FIG. 37 is a view showing a state in which the wafer is cut after the state shown in FIG.
Finally, by performing a cutting process as in the first embodiment, a plurality of semiconductor packages 30 can be manufactured simultaneously as shown in FIG. At this time, in the present embodiment, the base material 4 is not used, but the mark 10M is formed on the other surface side of the wafer 10 by the mark forming process, so that the through hole 11 is formed even from the wafer 10 side. Can be confirmed. Therefore, the wafer 10 can be accurately cut by using the mark 10M as a guide. That is, accurate cutting can be performed without using the base material 4 provided with the alignment marks M at the four corners as in the first embodiment.

As in the first embodiment, the semiconductor package 30 manufactured in this way can be easily and reliably inspected for mounting while reducing the thickness. In particular, since there is no substrate 4, further thinning can be achieved.
Further, according to the manufacturing method of the present embodiment, the base material 4 is not necessary, and the semiconductor package 30 can be manufactured simply by forming the photosensitive resin 31 on one surface of the wafer 10, so that the manufacturing is simple.

  In this embodiment, the case where the mark forming process is performed first has been described. However, the mark forming process is not necessarily performed first, and may be performed at any stage before the cutting process is performed.

(Sixth embodiment)
Next, a semiconductor package and a semiconductor package manufacturing method according to a sixth embodiment of the present invention will be described with reference to FIGS.
In addition, in this 6th Embodiment, the same code | symbol is attached | subjected about the part same as the component in 5th Embodiment, and the description is abbreviate | omitted. The difference between the sixth embodiment and the fifth embodiment is that, in the fifth embodiment, the external electrode 6 is formed by plating or the like when performing the electrode forming step, but in the sixth embodiment, the paste-like conductivity is formed. The external electrode 6 is formed using a material.

  That is, in the manufacturing method of the present embodiment, when performing the electrode forming step, first, a paste-like conductive material is applied to a predetermined position where the external electrode 6 is formed, and the applied conductive material is heated and cured. The external electrode 6 is formed.

  FIG. 38 is a process diagram for explaining the sixth embodiment of the semiconductor package manufacturing method according to the present invention, and shows a state in which the wafer is bonded after the opening and the through hole are formed in the photosensitive resin. FIG. FIG. 39 is a diagram showing a state in which external electrodes are formed after the state shown in FIG.

Specifically, as shown in FIG. 38, after the opening 3 and the through hole 11 are formed in the photosensitive resin 31, as shown in FIG. 39, one of the photosensitive resins 31 including the opening 3 and the through hole 11 is formed. A paste-like conductive material such as silver paste is applied to a predetermined position of the surface 31a by screen printing or the like, and then heated and cured. Thereby, the external electrode 6 can be formed.
In particular, according to the manufacturing method of the present embodiment, the external electrode 6 can be directly formed at a predetermined position on the one surface 31a of the photosensitive resin 31 without performing an etching process or the like. Can increase productivity.

  The technical scope of the present invention is not limited to the above embodiment, and various modifications can be made without departing from the spirit of the present invention.

  For example, in the first embodiment and the second embodiment, the external electrode 6 is formed by etching using the plating and the mask 13, but the present invention is not limited to this, and the paste-like conductive resin is used as in the fourth embodiment. The external electrode 6 may be formed using the above.

In the first embodiment, when the cutting process is performed, the wafer 10 is cut with a width larger than the width (W1) of the through hole 11 and the outer width is smaller than the width (W1) of the through hole 11. Although the electrode 6 is cut, the present invention is not limited to this case, and the wafer 10 side may be cut with a width obtained by cutting the external electrode 6. In this case, cutting can be performed at a time from the external electrode 6 side without turning the wafer 10 upside down.
However, as in the first embodiment, by changing the cutting width between the external electrode 6 side and the wafer 10 side, it is possible to prevent both from being electrically contacted by solder when flip chip mounting is performed. More preferred.

Further, when the cutting width is changed in this way, in the first embodiment, the cutting is performed first from the external electrode 6 side. However, the cutting may be performed first from the wafer 10 side having a large cutting width.
FIG. 40 is a diagram for explaining another example when the cutting step is performed, and is a diagram illustrating a state in which an external electrode is formed on a base material. FIG. 41 is a diagram showing a state in which the wafer side is cut first after the state shown in FIG. FIG. 42 is a diagram showing a state in which the external electrodes are cut from the wafer side after the state shown in FIG.

  That is, after the external electrode 6 is formed as shown in FIG. 40, the wafer 10 side is first cut as shown in FIG. And as shown in FIG. 42, you may cut | disconnect the external electrode 6 side from the same direction continuously. By doing so, the wafer 10 can be cut at a time from the wafer 10 side without turning the wafer 10 upside down. Therefore, the time taken for the cutting process can be shortened, and productivity can be further increased.

Furthermore, in the first embodiment, as in the fifth and sixth embodiments, it is preferable to perform a mark forming step to form the mark 10M on the other surface side of the wafer 10. By doing so, the wafer 10 can be cut more accurately. Moreover, even if the size of the base material 4 is substantially the same as that of the wafer 10 and there are no alignment marks M at the four corners, accurate cutting can be performed.
The cutting sequence and the mark forming process described above are not limited to the first embodiment, and can be applied to all the embodiments.

In each of the above embodiments, when the opening 3 and the through hole 11 are formed, both are formed to have a width larger than twice the film thickness (h) of the external electrode 6, but at least the through hole 11. It is only necessary to form with this width.
FIG. 43 is a diagram for explaining another example when performing the cutting step, and shows a state in which openings and through holes are formed in the metal layer on the base material. FIG. 44 is a view showing a state in which the wafer is bonded to the base material after the state shown in FIG. FIG. 45 is a view showing a state in which openings and through holes are formed in the base material after the state shown in FIG. FIG. 46 is a diagram showing a state in which a metal layer is formed by plating a conductive material after the state shown in FIG. FIG. 47 is a diagram showing a state in which a mask is patterned on the plated metal layer after the state shown in FIG. FIG. 48 is a diagram showing a state in which external electrodes are formed after the state shown in FIG. FIG. 49 is a diagram showing a state in which the external electrodes and the wafer are cut after the state shown in FIG.

  That is, as shown in FIG. 43, when performing the marking process, the width (W1) of the through hole 11 is set to the same width as the first embodiment (a width larger than twice the film thickness h), and the opening 3 The width (W2) may be smaller (a width smaller than twice the film thickness h). In this state, after the joining step shown in FIG. 44 and the base material processing step shown in FIG. 45, the metal layer 12 is formed by performing plating in the electrode forming step as shown in FIG. Unlike the form, the inside of the opening 3 is completely filled. After that, a mask 13 is formed as shown in FIG. 47, and etching is performed using the mask 13, so that the external electrode 6 in which the recess 11a is formed only in the through hole 11 as shown in FIG. Can be formed.

  As a result, as shown in FIG. 49, the semiconductor package 1 manufactured through the cutting process can be provided with the external electrode 6 which is a flat one surface having no dent or the like. Therefore, when placed on the external part upside down, there is no gap between the external part and the surface is in surface contact. Therefore, there is no possibility that air (void) is mixed in the external electrode 6 when the external electrode 6 is melted and joined with solder. Therefore, it is possible to increase the adhesion force and bond more firmly, and to improve the mounting reliability.

1 is a cross-sectional view showing a first embodiment of a semiconductor package according to the present invention. It is a figure which shows the wafer used when manufacturing the semiconductor package shown in FIG. It is a flowchart at the time of manufacturing the semiconductor package shown in FIG. It is process drawing which showed the manufacturing method of the semiconductor package shown in FIG. 1, Comprising: It is a figure which shows the state which formed the metal layer on the base material. It is a figure which shows the state which formed the opening and the through-hole in the metal layer after the state shown in FIG. It is a figure which shows the state which joined the wafer in which the several IC chip was provided in the other surface of the base material after the state shown in FIG. It is a figure which shows the state which formed the opening and the through-hole in the base material after the state shown in FIG. It is a figure which shows the state which plated on one surface of the metal layer after the state shown in FIG. 7, and formed the metal layer into a film. It is a figure which shows the state which formed the mask on the metal layer by plating after the state shown in FIG. FIG. 10 is a diagram showing a state in which an external electrode is formed by etching a metal layer by plating using a mask after the state shown in FIG. 9. It is a figure which shows the state which cut | disconnected the external electrode with the width | variety smaller than the width | variety of a through-hole after the state shown in FIG. It is a figure which shows the state which affixed the dicing tape on the one surface of an external electrode after the state shown in FIG. FIG. 13 is a diagram illustrating a state where the wafer is turned over after the state illustrated in FIG. 12 and then cut with a width larger than the width of the through hole. It is a figure which shows the state which peeled the dicing tape and solidified after the state shown in FIG. 13, and manufactured the several semiconductor package. FIG. 5 is a view showing a second embodiment of a method for producing a semiconductor package according to the present invention, and a process diagram showing a method for producing the semiconductor package shown in FIG. 1, and after forming a metal layer on a substrate, It is a figure which shows the state which formed the opening and the through-hole in the base material and the metal layer. FIG. 16 is a diagram illustrating a state in which a wafer having a plurality of IC chips provided on the other surface of the substrate is bonded after the state illustrated in FIG. 15. It is a figure which shows the state which formed the metal layer by plating on one surface of a metal layer after the state shown in FIG. It is a figure which shows the state which formed the mask on the metal layer by plating after the state shown in FIG. It is a figure which shows the state which formed the external electrode by etching the metal layer by plating using the mask after the state shown in FIG. It is a figure which shows the state which cut | disconnected and solidified the base material and the external electrode after the state shown in FIG. 19, and manufactured the several semiconductor package. It is sectional drawing which shows 3rd Embodiment of the semiconductor package which concerns on this invention. It is process drawing which showed the manufacturing method of the semiconductor package shown in FIG. 21, Comprising: It is a figure which shows the state which formed the opening and the through-hole in the base material. It is a figure which shows the state which joined the wafer in which the several IC chip was provided in the other surface of the base material after the state shown in FIG. It is a figure which shows the state which plated on one side of the base material after the state shown in FIG. 23, and formed the metal layer into a film. It is a figure which shows the state which formed the mask on the metal layer by plating after the state shown in FIG. FIG. 26 is a view showing a state in which an external electrode is formed by etching a metal layer by plating using a mask after the state shown in FIG. 25. It is a figure which shows the state which cut | disconnected and solidified the base material and the external electrode after the state shown in FIG. 26, and manufactured the several semiconductor package. FIG. 22 is a view showing the fourth embodiment of the method for manufacturing a semiconductor package according to the present invention, and is a process drawing showing the method for manufacturing the semiconductor package shown in FIG. 21, after forming an opening and a through hole in the base material FIG. 3 is a view showing a state in which a wafer provided with a plurality of IC chips is bonded to the other surface of the substrate. It is a figure which shows the state which applied the paste-form electroconductive material after the state shown in FIG. 28, and was hardened by heating, and formed the external electrode. It is sectional drawing which shows 5th Embodiment of the semiconductor package which concerns on this invention. FIG. 31 is a process diagram showing the method of manufacturing the semiconductor package shown in FIG. 30, and is a diagram showing a state in which a mark serving as a guide for cutting is formed on the other surface of the wafer. FIG. 32 is a view showing a state in which a photosensitive resin is formed on one surface of the wafer after the state shown in FIG. 31. It is a figure which shows the state which formed the opening and the through-hole in the photosensitive resin after the state shown in FIG. It is a figure which shows the state which plated on one side of the photosensitive resin after the state shown in FIG. 33, and formed the metal layer. It is a figure which shows the state which formed the mask on the metal layer by plating after the state shown in FIG. It is a figure which shows the state which formed the external electrode by etching the metal layer by plating using the mask after the state shown in FIG. FIG. 37 is a diagram showing a state in which a plurality of semiconductor packages are manufactured by cutting and solidifying the wafer and external electrodes after the state shown in FIG. 36. FIG. 30 is a view showing a semiconductor package manufacturing method according to a sixth embodiment of the present invention and a process diagram showing the semiconductor package manufacturing method shown in FIG. 30, in which a photosensitive resin is formed on one surface of the wafer. It is a figure which shows the state which formed the opening and the through-hole in photosensitive resin after doing. It is a figure which shows the state which applied the paste-form electroconductive material after the state shown in FIG. 38, and was heat-hardened, and formed the external electrode. In the manufacturing method of the semiconductor package which concerns on this invention, it is a figure which shows an example at the time of changing a cutting order, Comprising: It is a figure which shows the state which formed the external electrode in one surface of a base material. It is a figure which shows the state which cut | disconnected the wafer by the width | variety larger than the width | variety of a through-hole after the state shown in FIG. FIG. 42 is a diagram showing a state in which the external electrode is continuously cut from the wafer side with a width smaller than the width of the through hole after the state shown in FIG. 41. It is process drawing which shows the modification of the manufacturing method of the semiconductor package which concerns on this invention, Comprising: While forming a through-hole with a width | variety larger than twice the film thickness of an external electrode in a base material, it is more than twice film thickness. It is a figure which shows the state which formed the opening with small width. FIG. 44 is a diagram showing a state in which a wafer provided with a plurality of IC chips is bonded to the other surface of the base material after the state shown in FIG. 43. It is a figure which shows the state which formed the opening and the through-hole in the base material after the state shown in FIG. FIG. 46 is a diagram illustrating a state where a metal layer is formed by plating on one surface of the metal layer after the state illustrated in FIG. 45. It is a figure which shows the state which formed the mask on the metal layer by plating after the state shown in FIG. FIG. 48 is a diagram showing a state in which an external electrode is formed by etching a metal layer by plating using a mask after the state shown in FIG. 47. FIG. 49 is a diagram illustrating a state in which a plurality of semiconductor packages are manufactured by cutting and solidifying a wafer and external electrodes after the state illustrated in FIG. 48. It is sectional drawing which shows an example of the conventional semiconductor package using a lead frame. It is process drawing in the case of manufacturing the other conventional semiconductor package, Comprising: It is sectional drawing which shows the state which provided the metal post in the wafer in which the several semiconductor element was produced. FIG. 52 is a cross-sectional view showing a state where a metal post is sealed with a resin after the state shown in FIG. 51. FIG. 53 is a cross-sectional view showing a state in which the surface of the resin is polished to expose the surface of the metal post after the state shown in FIG. 52. FIG. 54 is a cross-sectional view showing a state in which solder bumps are provided on exposed metal posts after the state shown in FIG. 53; FIG. 55 is a cross-sectional view showing a state where a plurality of semiconductor packages are manufactured by cutting and solidifying the wafer after the state shown in FIG. 54.

Explanation of symbols

h Film thickness of external electrode M Mark formed on the other surface of the wafer W1 Width of the through hole W2 Width of the opening 1, 20, 30 Semiconductor package 2 IC chip (semiconductor element)
2a Electrode part 3 Opening 4 Base material 4a One side of the base material 4b The other side of the base material 5 Metal layer 6 External electrode 10 Wafer 11 Through-hole 12 Metal layer (plating layer)
13 Mask 31 Photosensitive resin 31a One side of photosensitive resin 31b The other side of photosensitive resin

Claims (17)

A semiconductor element having a plurality of electrode portions on one surface;
An insulating base material bonded to one surface of the semiconductor element and having an opening exposing each of the plurality of electrode portions;
An external electrode patterned to wrap around from one surface of the base material to the side surface in a state of being electrically connected to the plurality of electrode portions through the openings. A semiconductor package. A semiconductor element having a plurality of electrode portions on one surface;
An insulating base material bonded to one surface of the semiconductor element and having an opening exposing each of the plurality of electrode portions;
A metal layer formed on one side of the substrate;
Patterned so as to wrap around from one surface of the metal layer to the side surface of the metal layer and the side surface of the base material while being electrically connected to the plurality of electrode portions through the openings. A semiconductor package comprising an external electrode. A semiconductor element having a plurality of electrode portions on one surface;
An insulating photosensitive resin formed on one surface of the semiconductor element and having an opening exposing each of the plurality of electrode portions;
An external electrode patterned to wrap around from one surface of the photosensitive resin to the side surface in a state of being electrically connected to the plurality of electrode portions through the openings. A characteristic semiconductor package. A semiconductor element having a plurality of electrode portions on one surface, an insulating base material bonded to one surface of the semiconductor element and having an opening exposing each of the plurality of electrode portions; A plurality of the semiconductor elements are preliminarily provided with a semiconductor package including an external electrode patterned so as to wrap around from one surface of the base material to a side surface in a state of being electrically connected to each of a plurality of electrode portions. A method of manufacturing a plurality of wafers using a provided wafer,
A marking step of forming the opening in the base material and forming a through hole at a position in the vicinity of the opening and surrounding each of the plurality of semiconductor elements,
After the marking step, a bonding step of bonding the wafer to the other surface of the substrate while aligning the opening and the electrode portion so as to face each other,
After the joining step, an electrode forming step of forming the external electrode by patterning a conductive material at a predetermined position on one surface of the base material including the opening and the through hole;
A method of manufacturing a semiconductor package, comprising: a step of cutting the wafer along at least the through hole so as to separate the plurality of semiconductor elements after the electrode forming step.   In the electrode forming step, the conductive material is formed on the entire surface of the substrate by plating, and then the formed plating layer is patterned by etching using a mask to form the external electrode. The method of manufacturing a semiconductor package according to claim 4, wherein the semiconductor package is formed.   5. The semiconductor package according to claim 4, wherein in the electrode forming step, the external electrode is formed by applying the paste-like conductive material at the predetermined position and curing the applied conductive material. Manufacturing method. A semiconductor element having a plurality of electrode portions on one surface, an insulating base material bonded to one surface of the semiconductor element and having an opening exposing each of the plurality of electrode portions, and one of the base materials A metal layer formed on a surface, and a side surface of the metal layer and the base material from one surface of the metal layer in a state of being electrically connected to the plurality of electrode portions through the openings, respectively. A plurality of semiconductor packages each including an external electrode patterned so as to wrap around the side surface of the semiconductor device using a wafer in which a plurality of the semiconductor elements are provided in advance.
A metal layer forming step of forming the metal layer on one surface of the substrate;
After the metal layer formation step, the marking step of forming the opening in the metal layer and forming a through hole at a position in the vicinity of the opening and surrounding each of the plurality of semiconductor elements,
After the marking step, the bonding step of bonding the wafer to the other surface of the substrate while positioning the opening and the electrode portion so as to face each other with the substrate interposed therebetween,
After the joining step, the base material processing step of processing the base material according to the opening and the through hole formed in the metal layer, and forming the opening and the through hole in the base material;
After the base material processing step, the external electrode is formed by patterning a conductive material at a predetermined position on one surface of the metal layer including the opening and the through hole formed in the base material and the metal layer. An electrode forming step,
A method of manufacturing a semiconductor package, comprising: a step of cutting the wafer along at least the through hole so as to separate the plurality of semiconductor elements after the electrode forming step. A semiconductor element having a plurality of electrode portions on one surface, an insulating base material bonded to one surface of the semiconductor element and having an opening exposing each of the plurality of electrode portions, and one of the base materials A metal layer formed on a surface, and a side surface of the metal layer and the base material from one surface of the metal layer in a state of being electrically connected to the plurality of electrode portions through the openings, respectively. A plurality of semiconductor packages each including an external electrode patterned so as to wrap around the side surface of the semiconductor device using a wafer in which a plurality of the semiconductor elements are provided in advance.
A metal layer forming step of forming the metal layer on one surface of the substrate;
After the metal layer forming step, the marking step for forming the opening in the base material and the metal layer, and forming a through hole at a position in the vicinity of the opening and surrounding each of the plurality of semiconductor elements,
After the marking step, a bonding step of bonding the wafer to the other surface of the substrate while aligning the opening and the electrode portion so as to face each other,
After the bonding step, an electrode forming step of patterning a conductive material at a predetermined position on one surface of the metal layer including the opening and the through hole to form the external electrode;
A method of manufacturing a semiconductor package, comprising: a step of cutting the wafer along at least the through hole so as to separate the plurality of semiconductor elements after the electrode forming step.   In the electrode formation step, the conductive material is formed on the entire surface of the metal layer by plating, and then the formed plating layer is patterned by etching using a mask to form the external electrode. 9. The method of manufacturing a semiconductor package according to claim 7, wherein the semiconductor package is formed.   9. The electrode forming step according to claim 7 or 8, wherein the external electrode is formed by applying the paste-like conductive material to the predetermined position and curing the applied conductive material. A method for manufacturing a semiconductor package. A semiconductor element having a plurality of electrode portions on one surface, an insulating photosensitive resin formed on one surface of the semiconductor element and having an opening exposing each of the plurality of electrode portions; and A semiconductor package including an external electrode patterned so as to wrap around from one surface of the photosensitive resin to a side surface in a state of being electrically connected to each of the plurality of electrode portions; A method of manufacturing a plurality of wafers using a plurality of wafers provided in advance,
A resin forming step of forming the photosensitive resin on one surface of the wafer;
After the resin forming step, the photosensitive resin is exposed to form the opening in the photosensitive resin, and through holes are formed in the vicinity of the plurality of semiconductor elements in the vicinity of the opening. Marking process to
After the marking step, an electrode forming step of forming the external electrode by patterning a conductive material at a predetermined position on one surface of the photosensitive resin including the opening and the through hole;
A method of manufacturing a semiconductor package, comprising: a step of cutting the wafer along at least the through hole so as to separate the plurality of semiconductor elements after the electrode forming step.   In the electrode forming step, the conductive material is formed on the entire surface of the photosensitive resin by plating, and then the formed plating layer is patterned by etching using a mask to form the external electrode. The method of manufacturing a semiconductor package according to claim 11, wherein:   12. The semiconductor package according to claim 11, wherein in the electrode forming step, the external electrode is formed by applying the paste-like conductive material to the predetermined position and curing the applied conductive material. Manufacturing method.   14. The semiconductor package according to claim 4, wherein, in the marking step, the through hole is formed to have a width larger than twice the thickness of the external electrode. Production method.   15. In the cutting step, the wafer is cut with a width larger than the width of the through hole, and the external electrode is cut with a width smaller than the width of the through hole. A method for manufacturing a semiconductor package according to claim 1.   16. The method of manufacturing a semiconductor package according to claim 15, wherein the wafer is cut first from the wafer side in the cutting step. The mark forming step of forming a mark on the other surface of the wafer facing the through hole before the cutting step is provided. The manufacturing method of the semiconductor package of description.

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