JP2008010849A5 - - Google Patents
Download PDFInfo
- Publication number
- JP2008010849A5 JP2008010849A5 JP2007141450A JP2007141450A JP2008010849A5 JP 2008010849 A5 JP2008010849 A5 JP 2008010849A5 JP 2007141450 A JP2007141450 A JP 2007141450A JP 2007141450 A JP2007141450 A JP 2007141450A JP 2008010849 A5 JP2008010849 A5 JP 2008010849A5
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- impurity region
- impurity
- film
- semiconductor films
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000004065 semiconductor Substances 0.000 claims 36
- 239000012535 impurity Substances 0.000 claims 34
- 239000003990 capacitor Substances 0.000 claims 6
- 238000004519 manufacturing process Methods 0.000 claims 4
- 238000000034 method Methods 0.000 claims 3
- 239000000463 material Substances 0.000 claims 2
- 239000000758 substrate Substances 0.000 claims 2
- 238000005530 etching Methods 0.000 claims 1
- 230000001678 irradiating effect Effects 0.000 claims 1
Claims (12)
前記アナログ回路部は、それぞれ複数の容量素子から構成される複数のブロックを具備する容量部を有し、The analog circuit unit includes a capacitor unit including a plurality of blocks each composed of a plurality of capacitor elements,
前記複数の容量素子の各々は、第1の不純物領域、及び前記第1の不純物領域を挟んで設けられた複数の第2の不純物領域を有する半導体膜と、前記第1の不純物領域の上方に絶縁膜を介して設けられた導電膜とを有し、Each of the plurality of capacitor elements includes a first impurity region, a semiconductor film having a plurality of second impurity regions provided across the first impurity region, and a first impurity region above the first impurity region. A conductive film provided through an insulating film,
前記複数の容量素子は、互いに並列に接続され、The plurality of capacitive elements are connected in parallel to each other,
前記複数のブロックにおいて、互いに隣接するブロックに設けられた半導体膜同士の最短の間隔は、20μm以上200μm以下であることを特徴とする半導体装置。In the plurality of blocks, the shortest distance between semiconductor films provided in blocks adjacent to each other is 20 μm or more and 200 μm or less.
前記複数の容量素子の各々は、第1の不純物領域、及び前記第1の不純物領域を挟んで設けられた複数の第2の不純物領域を有する半導体膜と、前記第1の不純物領域の上方に絶縁膜を介して設けられた導電膜とを有し、
前記複数の容量素子は、互いに並列に接続されていることを特徴とする半導体装置。 Each have a capacitance portion comprising a plurality of blocks including a plurality of capacitive elements,
Each of said plurality of capacitive elements, a first impurity region, and a semiconductor film having a second impurity area plurality of which are provided across the first impurity region, above the first impurity region And a conductive film provided via an insulating film,
Before SL plurality of capacitive elements is a semiconductor device characterized by being connected in parallel with each other.
前記複数の容量素子の各々は、第1の不純物領域、及び前記第1の不純物領域を挟んで設けられた複数の第2の不純物領域を有する半導体膜と、前記第1の不純物領域の上方に絶縁膜を介して設けられた導電膜とを有し、
前記複数の容量素子の各々に設けられた前記導電膜は、前記第1の配線を介して互いに電気的に接続され、
前記複数の容量素子の各々に設けられた前記複数の第2の不純物領域は、前記第2の配線を介して互いに電気的に接続されていることを特徴とする半導体装置。 Includes a plurality of blocks including a plurality of capacitive elements respectively, a first wiring, a capacitor portion having a second wiring,
Each of said plurality of capacitive elements, a first impurity region, and a semiconductor film having a second impurity area plurality of which are provided across the first impurity region, above the first impurity region And a conductive film provided via an insulating film,
The conductive layer provided on each of front Symbol plurality of capacitor elements are electrically connected to each other through the first wiring,
The semiconductor device, wherein the plurality of second impurity regions provided in each of the plurality of capacitors are electrically connected to each other through the second wiring.
前記第1の配線は、前記導電膜より抵抗が低い材料で設けられていることを特徴とする半導体装置。 In claim 3 ,
The semiconductor device is characterized in that the first wiring is provided with a material whose resistance is lower than that of the conductive film.
前記第1の配線と前記第2の配線は、同一面上に設けられていることを特徴とする半導体装置。 In claim 3 or 4 ,
The semiconductor device, wherein the first wiring and the second wiring are provided on the same surface.
前記複数のブロックにおいて、互いに隣接するブロックに設けられた半導体膜同士の最短の間隔は、20μm以上200μm以下であることを特徴とする半導体装置。 In any one of claims 2 to 5,
In the plurality of blocks, the shortest distance between semiconductor films provided in blocks adjacent to each other is 20 μm or more and 200 μm or less.
前記第1の不純物領域及び前記第2の不純物領域は、それぞれn型を示す不純物元素またはp型を示す不純物元素を含み、
前記第1の不純物領域に含まれる前記不純物元素の濃度は、前記第2の不純物領域に含まれる前記不純物元素の濃度より小さいことを特徴とする半導体装置。 In any one of Claims 1 thru | or 6 ,
Each of the first impurity region and the second impurity region includes an n-type impurity element or a p-type impurity element,
The concentration of the impurity element contained in the first impurity region, wherein a smaller than the concentration of the impurity element contained in the second impurity regions.
前記複数のブロックに設けられた前記複数の容量素子は、互いに並列に接続されていることを特徴とする半導体装置。 In any one of claims 1 to 7,
It said plurality of said plurality of capacitive elements provided in the block, wherein a are connected in parallel to each other.
前記複数の半導体膜に第1の不純物元素を導入して第1の不純物領域を形成し、
前記複数の半導体膜を覆うように第1の絶縁膜を形成し、
前記半導体膜の一部を覆うように前記第1の絶縁膜を介して前記複数の半導体膜上にそれぞれ導電膜を選択的に形成し、
前記導電膜をマスクとして前記複数の半導体膜に第2の不純物元素を導入して、前記導電膜と重ならない領域に第2の不純物領域を形成し、
前記複数の半導体膜及び前記導電膜を覆うように第2の絶縁膜を形成し、
前記第2の絶縁膜上に、前記導電膜と電気的に接続する第1の配線及び前記第2の不純物領域と電気的に接続する第2の配線とを形成し、
前記第1の配線は、前記複数の半導体膜の上方にそれぞれ形成された前記導電膜が互いに電気的に接続されるように設け、
前記第2の配線は、前記複数の半導体膜にそれぞれ形成された前記第2の不純物領域が互いに電気的に接続されるように設けることを特徴とする半導体装置の作製方法。 Forming a plurality of blocks having a plurality of semiconductor films on a substrate;
Introducing a first impurity element into the plurality of semiconductor films to form a first impurity region;
Forming a first insulating film so as to cover the plurality of semiconductor films;
A conductive film is selectively formed on each of the plurality of semiconductor films through the first insulating film so as to cover a part of the semiconductor film,
A second impurity region is formed in a region that does not overlap the conductive film by introducing a second impurity element into the plurality of semiconductor films using the conductive film as a mask;
Forming a second insulating film so as to cover the plurality of semiconductor films and the conductive film;
Forming a first wiring electrically connected to the conductive film and a second wiring electrically connected to the second impurity region on the second insulating film;
The first wiring is provided so that the conductive films respectively formed above the plurality of semiconductor films are electrically connected to each other,
The method for manufacturing a semiconductor device, wherein the second wiring is provided so that the second impurity regions formed in the plurality of semiconductor films are electrically connected to each other.
前記半導体膜にレーザー光を照射して結晶質半導体膜を形成し、
前記結晶質半導体膜を選択的にエッチングして、複数の結晶質半導体膜を有するブロックを複数形成し、
前記複数の結晶質半導体膜に第1の不純物元素を導入して第1の不純物領域を形成し、
前記複数の結晶質半導体膜を覆うように第1の絶縁膜を形成し、
前記結晶質半導体膜の一部を覆うように前記第1の絶縁膜を介して前記複数の結晶質半導体膜上にそれぞれ導電膜を選択的に形成し、
前記導電膜をマスクとして前記複数の結晶質半導体膜に第2の不純物元素を導入して、前記導電膜と重ならない領域に第2の不純物領域を形成し、
前記複数の結晶質半導体膜及び前記導電膜を覆うように第2の絶縁膜を形成し、
前記第2の絶縁膜上に、前記導電膜と電気的に接続する第1の配線及び前記第2の不純物領域と電気的に接続する第2の配線とを形成し、
前記第1の配線は、前記複数の結晶質半導体膜の上方にそれぞれ形成された前記導電膜が互いに電気的に接続されるように設け、
前記第2の配線は、前記複数の結晶質半導体膜にそれぞれ形成された前記第2の不純物領域が互いに電気的に接続されるように設けることを特徴とする半導体装置の作製方法。 Forming a semiconductor film on the substrate;
Irradiating the semiconductor film with a laser beam to form a crystalline semiconductor film,
Selectively etching the crystalline semiconductor film to form a plurality of blocks having a plurality of crystalline semiconductor films ;
Introducing a first impurity element into the plurality of crystalline semiconductor films to form a first impurity region;
Forming a first insulating film so as to cover the plurality of crystalline semiconductor films;
A conductive film is selectively formed on each of the plurality of crystalline semiconductor films via the first insulating film so as to cover a part of the crystalline semiconductor film,
Introducing a second impurity element into the plurality of crystalline semiconductor films using the conductive film as a mask to form a second impurity region in a region not overlapping the conductive film;
Forming a second insulating film so as to cover the plurality of crystalline semiconductor films and the conductive film;
Forming a first wiring electrically connected to the conductive film and a second wiring electrically connected to the second impurity region on the second insulating film;
The first wiring is provided so that the conductive films respectively formed above the plurality of crystalline semiconductor films are electrically connected to each other.
The method for manufacturing a semiconductor device, wherein the second wiring is provided so that the second impurity regions respectively formed in the plurality of crystalline semiconductor films are electrically connected to each other.
前記第1の配線を、前記導電膜より抵抗が低い材料で形成することを特徴とする半導体装置の作製方法。 In claim 9 or 10 ,
The method for manufacturing a semiconductor device, wherein the first wiring is formed using a material having lower resistance than the conductive film.
前記複数のブロックにおいて、互いに隣接するブロックに設けられた半導体膜同士の最短の間隔を20μm以上200μm以下とすることを特徴とする半導体装置の作製方法。 In any one of claims 9 to 11,
A manufacturing method of a semiconductor device, wherein, in the plurality of blocks, a shortest distance between semiconductor films provided in blocks adjacent to each other is set to 20 μm to 200 μm.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007141450A JP2008010849A (en) | 2006-06-01 | 2007-05-29 | Semiconductor device and method of manufacturing the same |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006153548 | 2006-06-01 | ||
JP2007141450A JP2008010849A (en) | 2006-06-01 | 2007-05-29 | Semiconductor device and method of manufacturing the same |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008010849A JP2008010849A (en) | 2008-01-17 |
JP2008010849A5 true JP2008010849A5 (en) | 2010-06-17 |
Family
ID=39068726
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007141450A Withdrawn JP2008010849A (en) | 2006-06-01 | 2007-05-29 | Semiconductor device and method of manufacturing the same |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2008010849A (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101617013B1 (en) | 2008-09-30 | 2016-04-29 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor device |
JP5349945B2 (en) | 2008-12-25 | 2013-11-20 | 株式会社半導体エネルギー研究所 | Semiconductor device |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4332244B2 (en) * | 1998-10-30 | 2009-09-16 | シャープ株式会社 | MOS type capacitive element |
JP2001007292A (en) * | 1999-06-24 | 2001-01-12 | Sanyo Electric Co Ltd | Semiconductor integrated circuit and arrangement method therefor |
JP4916658B2 (en) * | 2003-12-19 | 2012-04-18 | 株式会社半導体エネルギー研究所 | Semiconductor device |
-
2007
- 2007-05-29 JP JP2007141450A patent/JP2008010849A/en not_active Withdrawn
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR101547326B1 (en) | Transistor and method of manufacturing the same | |
JP4985477B2 (en) | Transistor circuit forming substrate and transistor manufacturing method | |
JP2009157354A5 (en) | ||
JP2009003434A5 (en) | ||
JP2011524091A5 (en) | ||
JP2014215485A5 (en) | ||
JP2009032673A5 (en) | ||
JP2012256847A5 (en) | ||
JP2009033145A5 (en) | ||
JP2005294814A5 (en) | ||
TW200515586A (en) | Semiconductor device and method for fabricating the same | |
JP2013168419A5 (en) | ||
JP2008244460A5 (en) | ||
JP2011129165A5 (en) | ||
JP2009124121A5 (en) | ||
JP2008118142A5 (en) | ||
JP2013168617A5 (en) | ||
JP2010278040A5 (en) | Semiconductor device manufacturing method | |
WO2009075073A1 (en) | Nonvolatile memory device and fabrication method therefor | |
JP2009124124A5 (en) | ||
JP2014075377A5 (en) | ||
JP2008124266A5 (en) | ||
JP2010244808A5 (en) | ||
JP2006352098A5 (en) | ||
JP2004165559A5 (en) |