JP2001007292A - Semiconductor integrated circuit and arrangement method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress generation of coupling capacity between wiring and to prevent input/output of noise by arranging an island-shaped upper electrode on a non-selected capacitor as a dummy in a semiconductor integrated circuit. SOLUTION: An N-type epitaxial layer is laminated on a P-type semiconductor substrate. An isolation region reaching the substrate from the surface is formed at the epitaxial layer. Then, a transistor, a diffused resistor, and a capacitor are produced in an island. Capacitors 45, 46, 47,... are provided at one region of a semiconductor chip in a row, which are N-type diffused regions formed at each island and become a lower electrode EL of the capacitors. The capacitors 46 and 47 are selected capacitors, and dummy electrodes 70 and 71 are provided at the non-selected capacitor 45. When no dummy electrodes 70 and 71 are provided, a computer arranges first-layer L1 as in a dotted line on the non-selected capacitor 45, thus forming a bypass circuit and performing automatic arrangement, as in the wiring L1 indicated by a solid line.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit and a method of arranging the same, and more particularly to preventing capacitive coupling in automatic wiring.

[0002]

2. Description of the Related Art Conventionally, an ASIC is mainly composed of a MOS, and a gate array, a master slice and the like have been realized. MOS is a digital circuit mainly composed of digital circuits. A circuit is formed by turning on and off transistors, and transistors, resistors, and the like have almost the same size. Therefore, transistors, resistors, and the like are repeated, and these are selected by wiring to form one circuit.
C has been realized.

[0003] However, a linear circuit, particularly a BIP linear circuit, has a plurality of electronic circuit blocks, and elements constituting the electronic circuit blocks have various characteristics and various sizes.
Therefore, it is difficult to mount all of these types, but the semiconductor elements such as transistors, diodes, resistors and capacitors are divided into several types and arranged repeatedly like a gate array or master slice, and selected. Then, what constitutes a circuit came out.

FIG. 4 shows capacitors arranged in one area in this analog master slice. For example, a MIS type capacitor 1 is formed. 2
Is an N-type or P-type diffusion region formed in the semiconductor layer, 3 is a dielectric layer formed on the diffusion region 2, and 4 is a dielectric layer formed on the dielectric layer 3. The formed upper electrodes 5 are first metal wirings in contact with the upper electrodes. The diffusion region 2 is in contact with a second metal wiring 7 serving as a lower electrode through a contact hole 6 from an insulating film formed on the surface thereof. In addition, 8 is P
It is an isolation region that reaches from the semiconductor substrate of the type to the surface of the N-type semiconductor layer.

[0005]

The capacitance value of the capacitor is selected from a plurality of capacitors 1 to achieve a predetermined value. However, when accuracy is required, the dielectric layer 3 is trimmed (change in size). Then, the size of the upper electrode 4 and the size of the first metal wiring 5 are reduced according to the size of the dielectric layer 3.

The size of the dielectric layer 3 is not changed,
The upper electrode 4 was trimmed to reduce its size, and the size of the first metal wiring 5 was reduced to match this size.

In either case, the first metal wiring 5
A portion where the diffusion region 2 shows a face occurs in a region (a non-overlapping portion) where the size is smaller than the size of the diffusion region 2 and the first metal wiring 5 is not formed.

On the other hand, since the automatic wiring is arranged by recognizing the presence or absence of the electrodes 5 and 7, the wirings 9 and 10 are sometimes arranged in the non-overlapping part. In this case, the wirings 9, 10
Is capacitively coupled to the diffusion region 2 and furthermore is capacitively coupled between the two wirings 9 and 10, so that noise intrusion occurs between the wirings 9 and 10 and the capacitor and between the wirings 9 and 10. There was a problem that occurred.

[0009]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and is solved by disposing an upper electrode as a dummy even in a non-selected capacitor.

[0010] By arranging electrodes as dummy on the non-selected capacitors, the computer recognizes that no wiring is provided on the non-selected capacitors, and the wiring is bypassed.

In the case where the capacitors are arranged in a group in a row, if a dummy electrode is provided for a non-selected capacitor, the wiring is not provided in the region arranged in the row. to decide. Therefore, it is possible to trim the dielectric layer or the upper electrode at some points in the column of the capacitors, so that the capacitance value with high accuracy can be determined.

[0012]

Embodiments of the present invention will be described below. The present invention particularly relates to a semiconductor integrated circuit employing a master slice of a linear circuit, and will be described here with a BIP-IC, but can also be applied to a MOS type linear circuit.

The master slice of the present invention has a base as shown in FIG. 5 mounted on a wafer and relates to a master slice for trimming elements.

The master slice to be trimmed is
A wafer before the formation of the contact holes is prepared. Then, based on the desired circuit, the elements in the IC are selected, and the wiring is provided together with the formation of the contact (the trimming position is determined here), thereby selecting the elements and realizing the circuit, and designing in a short time. is there.

A description will now be given with reference to FIGS.
First, an MIS type capacitor will be described. Generally, an N-type epitaxial layer 42 is laminated on a P-type semiconductor substrate 40, and an isolation region 43 reaching the substrate from the surface is formed in the epitaxial layer 42. A plurality of N-type islands 44 are formed as a region surrounded by the separation region 43.

In the island 44, a transistor, a diffusion resistor, and a capacitor are formed.

Since the present invention is an analog master slice semiconductor integrated circuit device, as shown in FIG.
6, 47... Are provided.

Reference numerals 48, 49, and 50 denote N-type diffusion regions formed in the respective islands, which are portions serving as lower electrodes EL of the capacitors. Here, a P-type diffusion region may be used instead of the N-type diffusion region.

An insulating film 51 is formed on the entire surface of the semiconductor chip, and a region 53 where a dielectric layer 52 of the capacitor is formed.
Is open. In the region 53, a film such as a Si oxide film or a Si nitride film is formed as the dielectric layer 52 of the capacitor. Further, on the entire surface, a second insulating film 54 is formed.
Is formed. Then, the second insulating film 5 on the dielectric layer 52
On 4, a contact hole 58 for the upper electrode 57 is formed, and a contact hole 59 for the lower electrode is also formed. A first metal wiring 57 as an upper electrode is provided in the contact hole 58, and a second metal wiring 57 serving as a lower electrode is provided in the contact hole 59.
Metal wiring 60 is provided.

The capacitors are provided in groups in a row, and a plurality of capacitors are selected according to the capacitance value of each capacitor used in the electronic circuit and connected in series.
A desired value is realized by connecting in parallel or by combining series connection and parallel connection.

In FIG. 1, capacitors 46 and 47 are the selected capacitors, and capacitor 45 is a non-selected capacitor.

The present invention resides in that dummy electrodes 70 and 71 are provided on the non-selected capacitors. If the dummy electrodes 70 and 71 are not provided, the computer arranges the first-layer wiring L1 as shown by a dotted line on the non-selection capacitor 45. This is performed, and automatic arrangement is performed as shown by a wiring L1 shown by a solid line.

Naturally, the first-layer wiring L arranged in the horizontal direction
No. 2 is not superimposed on the capacitor because the dummy electrode is formed on the selected or non-selected capacitor.

The dummy electrodes 70 and 71 are formed in the same step as the upper electrodes 57 and 60 in consideration of sharing of the process steps. However, it may be performed in another step or may be formed of another metal material. Further, a material such as poly-Si may be formed between the dielectric layer 52 and the upper electrode, or a plurality of dielectric layers may be stacked.

Next, FIG. 3 will be described as a second embodiment.

In both embodiments, a group of capacitors is formed,
This is selected, and a predetermined capacitance value is realized by series connection and / or parallel connection. However, a desired capacitance value may not be realized due to the processing capability, accuracy, and processing time of the computer.

However, in the present invention, the left capacitor 80 is provided with the upper electrode 83 which completely covers the diffusion region.
Since the capacitor 82 covered with the dummy electrode 84 is on the right, the wiring L3 bypasses this capacitor row. Therefore, the capacitor 81 can be trimmed, and by connecting it in series and / or in parallel, a highly accurate capacitance value is realized.

Here, the lower electrode EL may be a poly-Si film formed on the insulating film 51. In this case, impurities are introduced to reduce the resistance value. Also, the second insulating film 5
4 may be omitted.

The upper electrode 57, the electrode 60, and the dummy electrodes 70 and 71 may be integrally formed in the same layer as the wiring, or the wiring may be formed in the second layer and contacted.

Next, FIGS. 5 and 6 will be described. For example, the semiconductor chip 20 is divided into a plurality of block columns (here, three columns BL1, BL2, BL3 on the left and right), and each block column is divided into a plurality of blocks. For example, the first block BL1 is a block 1
In the block 10, the second block column BL2 in the second column is the block block B in the third column in the blocks 11 to 20.
L3 is composed of blocks 21 to 30.

Each of the blocks 1 to 30 comprises a basic unit cell UC as shown in an enlarged view (lower view in FIG. 5) indicated by an arrow. The unit cells UC are formed in groups so that a circuit diagram can be selected.

That is, a plurality of types of resistors having different values are selected, and each is arranged in a group. The same applies to a transistor (hereinafter referred to as Tr) and a capacitor. In particular, Tr is a vertical and horizontal PNP-T in the figure.
r and vertical NPN-Tr are arranged in groups. The method of arranging the block strings and the number of arrangements are merely examples, and the present invention is not limited thereto. A diode or the like may be provided in addition to the resistors, Trs, and capacitors, which are the elements in the block. Further, each of these elements is a group of elements having different sizes (meaning that the resistance has a different resistance value, the Tr has a different current capacity, and the capacitor has a different capacitance value). It is arranged as.

In FIG. 5, a rectangle formed by the outermost solid line is shown as a semiconductor IC (semiconductor chip) 20.
Bonding pads 21 are formed. A substantially rectangular area surrounded by the formation area of the bonding pads 21 is an area where the block row BL and the blocks 1 to 30 are arranged, and is an element formation area. However, a protection diode or the like may be formed under the bonding pad in some cases, but is ignored here because it is extremely small in view of the ratio of the number of elements. At least one power supply pad and one ground pad are formed in the bonding pads 21.

First, a plurality of electronic circuit blocks are formed on the semiconductor chip 20 of FIG. 5, and these are electrically connected to each other to realize one IC circuit. Each electronic circuit block is configured by selecting an element in a block according to the circuit diagram, and is configured by at least one block.

On the other hand, the region where the capacitor of the present invention is formed is formed at the uppermost portion of the unit cell UL, and a plurality of types are formed in rows as shown in FIG.

In FIG. 6, as an example, three capacitors C1 having a large size and 12 capacitors C2 smaller than the capacitor C1 extend in a row on the left and right. Although it is shown in a few states due to the restrictions on the figure, there may be cases where it is actually formed more.

Since the present IC is used in the master slice, the wafer is stored in advance before the first-layer metal wiring is formed, that is, in a state where the insulating film in which the contact hole is formed is coated. I have. Alternatively, a wafer is prepared in which all contacts are opened and a wiring material is applied on the entire surface.

When an order is received, this wafer is prepared, and the elements of the unit cell UL are selected according to the circuit diagram.

Of course, a capacitor is also selected. This choice,
FIG. 6 shows non-selection. Naturally, the selected capacitors are connected as a circuit by wiring, but the non-selected capacitors are not connected as wiring. However, similar to the previous embodiment, the dummy electrodes are provided on the non-selected capacitors, so that the wiring can be prevented from extending over the non-selected capacitors. This is because the computer recognizes the dummy wiring and arranges it around the dummy wiring.

In this state, the capacitor can be trimmed as shown in FIG. That is, since the capacitors on both sides have an upper electrode and / or a dummy electrode, even if there is a non-selective capacitor in the middle, the capacitors are arranged substantially straight, and no wiring extends to the non-top portion.

[0041]

According to the present invention, by providing a dummy electrode for a non-selected capacitor, the wiring provided close to the capacitor is arranged so as to be bypassed without overlapping with the diffusion region EL. Therefore, no coupling capacitance is generated between the wiring and the diffusion region and between the wiring and the wiring, so that noise can be prevented from entering and exiting.

Conventionally, when the wiring is superimposed on the diffusion region, the automatic wiring mode is canceled and the wiring is manually detoured. Can be.

[Brief description of the drawings]

FIG. 1 is a plan view of a semiconductor integrated circuit according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along line AA of FIG.

FIG. 3 is a plan view of the semiconductor integrated circuit of the present invention.

FIG. 4 is a plan view of a conventional semiconductor integrated circuit.

FIG. 5 is a diagram illustrating a semiconductor chip formed by a master slice.

FIG. 6 is a diagram illustrating the capacitor arrangement of FIG. 5;

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F038 AC05 BH03 BH19 CA04 CA17 CA18 CD05 DF11 EZ09 EZ20 5F064 AA03 BB21 BB35 CC23 DD10 DD19 EE06 EE17 EE22 EE26 EE27 EE36 EE46

Claims (6)

[Claims] 1. A capacitor which is selected by an electronic circuit formed on a semiconductor chip and a capacitor which is not selected are arranged in groups, and a wiring electrically connected to an upper electrode of the selected capacitor is provided. In the semiconductor integrated circuit to be provided, the non-selected capacitor is provided with an island-shaped upper electrode that is not electrically connected to the wiring. 2. A plurality of rectangular blocks are provided as an arrangement region of a semiconductor element. In the blocks, capacitors that are selected and capacitors that are not selected are arranged in a matrix by an electronic circuit. A semiconductor integrated circuit, wherein the upper electrode is provided with a wiring electrically connected thereto, and the non-selected capacitor is provided with an island-shaped upper electrode not electrically connected to the wiring. 3. The capacitor according to claim 1, wherein the upper electrode is made of poly-Si, and the lower electrode disposed opposite to the upper electrode via a dielectric film of the capacitor is made of a diffusion region or poly-Si. 3. The semiconductor integrated circuit according to claim 1. 4. A plurality of the blocks are arranged in a row in a row, and a plurality of types of capacitors having different capacitance values are arranged in a row, extending in parallel with an arrangement direction of the blocks. 4. The semiconductor integrated circuit according to claim 1, 2 or 3. 5. The capacitor according to claim 1, wherein at least one of the selected capacitors is formed by trimming a dielectric layer and / or an upper electrode constituting the capacitor. Item 5. A semiconductor integrated circuit according to item 4. 6. A capacitor is formed in a group so that capacitors required to constitute an electronic circuit can be selected or deselected. The capacitor is selected from the group of capacitors based on the electronic circuit, and wiring is connected to the selected capacitor. In the method of arranging a semiconductor integrated circuit to be provided, the selected capacitor is provided with an upper electrode constituting the capacitor and a wiring electrically connected to the upper electrode, and other capacitors except the selected capacitor include:
An island-shaped upper electrode which is not electrically connected to the wiring is provided.