JP2008010777A - Semiconductor device, and semiconductor relay using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high withstand voltage and reliable semiconductor device for a semiconductor relay. <P>SOLUTION: The semiconductor device comprises an SOI substrate 11 having active layers 14, 15 isolated by an insulation film 13; a photo-receiving array 6 which is formed on the surface of the active layer 15, and to which anode and cathode of a plurality of photo-receiving elements that are isolated by an insulation film 18 are connected by a wiring layer 31; and a gate electrode 26 which is formed on the surface of the active layer 14, isolated by the insulation film 18, disposed on a source region 24, a drain region 20, and between both regions 20, 24. The semiconductor device further comprises MOS elements 5 in which the anode and cathode of the photo-receiving element 6 are connected to a gate electrode 26 and a source region 24, respectively, via a wiring layer 32 that straddles the insulation film 18; in which the source regions 24 are connected to each other; and in which drain regions 20 are connected to external connection terminals 8. In addition, an resistance element 27 is disposed in an insulating film 29 between the source region 24 and drain region 20 of the MOS element 5. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a semiconductor relay using the semiconductor device.

  Semiconductor relays are non-contact and can have a long life, and are used in various devices. Although it is often used for FA equipment, measuring equipment, communication equipment, etc., recently, the demand for semiconductor relays that support high voltage resistance, including in-vehicle equipment, has increased, and withstand voltage characteristics have been improved and costs have been reduced. It is desired.

  However, it is difficult to improve the breakdown voltage of a power MOS (Metal Oxide Semiconductor) transistor (MOS element) for output. In addition, the semiconductor relay is a light emitting element such as an LED, a light receiving element array in which a light receiving element as a photovoltaic element is connected in series, a control circuit for discharging the residual charge of the gate of the MOS element and turning it off at high speed, The two MOS elements for ensuring the bidirectionality are the main components. A semiconductor relay combines these components and is mounted in a single package. However, if there are many parts, it takes time to assemble, and it is difficult to ensure assembly accuracy and connection strength, resulting in a decrease in assembly yield. It is done.

  Therefore, in the light receiving element array, the control circuit, and the MOS element excluding the light emitting element (LED, Light Emitting Diode), four MOS elements (double diffusion electric field) formed in the peripheral portion of the substrate separated by dielectrics. Effect type transistors) are connected in series, and the same number of light receiving element arrays (voltage output type photodiode arrays) as the MOS elements that receive the output light of the light emitting elements are formed in the central portion of the substrate, and the light receiving element arrays adjacent to the MOS elements In addition, a dielectric isolation semiconductor device (chip) in which a control circuit (shunt resistor) is connected in parallel between the source and gate of a MOS element is disclosed (for example, see Patent Document 1). More specifically, this semiconductor device is made into one chip using a wafer formed by bonding (the thermal oxide film thickness is about 3 μm and the specific resistance on the MOS element forming side is 100 Ω · cm). The individual MOS elements are connected by bonding wires.

The disclosed semiconductor device attempts to obtain a withstand voltage when the insulating film (thermal oxide film) has a thickness of about 3 μm and the active layer has a specific resistance of 100 Ω · cm. There is a problem that can not be. Further, since individual MOS elements are connected by bonding wires, there is a problem that the assembly process is troublesome and the reliability is poor.
Japanese Patent Laid-Open No. 2005-252909

  An object of the present invention is to provide a semiconductor device with high withstand voltage and high reliability, and a semiconductor relay using the semiconductor device.

  A semiconductor device of one embodiment of the present invention includes an SOI substrate having an active layer separated by a first insulating film, and a second substrate formed on the surface of the active layer and extending in a vertical direction from the surface of the active layer. A light receiving element array formed by connecting anodes and cathodes of a plurality of adjacent light receiving elements separated by an insulating film by a first wiring layer, and the active layer separated by the second insulating film A source region and a drain region formed therein, and a gate electrode formed above a surface of the active layer between the source region and the drain region via a third insulating film, The anode of the light receiving element array is connected to the gate electrode, the cathode of the light receiving element array is connected to the source region, and the drain region is interposed through a second wiring layer straddling the two insulating films. Comprising: a MOS element connected to an external connection terminal; and a resistor formed in the third insulating film between the source region and the drain region of the MOS element. To do.

  The semiconductor relay according to another aspect of the present invention includes a light emitting element, an SOI substrate having an active layer separated by a first insulating film, a surface of the active layer, and a vertical direction from the surface of the active layer. A light receiving element array formed by connecting anodes and cathodes of a plurality of adjacent light receiving elements separated by a second insulating film extending to the first wiring layer, and the second insulating film. A source region and a drain region formed in the isolated active layer, and a gate electrode formed above the surface of the active layer between the source region and the drain region via a third insulating film The anode of the light receiving element array is connected to the gate electrode and the cathode of the light receiving element array is connected to the source region via a second wiring layer straddling the second insulating film A MOS element having the drain region connected to an external connection terminal; and a resistor formed in the third insulating film between the source region and the drain region of the MOS element. And a semiconductor device.

  According to the present invention, it is possible to provide a semiconductor device with high withstand voltage and high reliability, and a semiconductor relay using the semiconductor device.

  Embodiments of the present invention will be described below with reference to the drawings. In each figure, the same components are denoted by the same reference numerals.

In a semiconductor device according to an embodiment of the present invention and a semiconductor relay using the semiconductor device, a MOS element and a light receiving element array include an SOI (Silicon on Insulator) in which a support substrate and a device formation layer (referred to as an active layer) are separated by an insulating film. ) When monolithically formed on the substrate, the relationship between the breakdown voltage and the active layer thickness when the insulating film thickness is 3.0 μm or more and the impurity concentration is about 10 ¹⁴ to 10 ¹⁵ cm ⁻³ , and sufficient light is It is formed based on the knowledge about the thickness of the active layer to be absorbed.

As shown in FIG. 5, when the horizontal axis represents the thickness of the active layer and the vertical axis represents the breakdown voltage, and the impurity concentration of the active layer is about 10 ¹⁴ to 10 ¹⁵ cm ⁻³ , the breakdown voltage is about 600 V with a thickness of 15 μm. When the thickness is 30 μm, the breakdown voltage is about 800 V, and when extrapolated, it can be seen that the thickness is about 10 μm and the breakdown voltage is about 500 V.

  Further, as shown in FIG. 6, when the active layer thickness (μm) is taken on the horizontal axis and the ratio of the absorbed light to the incident light, that is, the light absorption rate (%) is taken on the vertical axis, the emission wavelength λ of the light emitting element. At 850 nm, the absorptance of the light receiving element is calculated to be about 63% when the film thickness is 15 μm. The light absorptance with respect to the thickness of the active layer has the same tendency even in the emission wavelength from visible light to near infrared.

  An embodiment of the present invention will be described with reference to FIGS. FIG. 1 is an equivalent circuit diagram showing electrical connection of a semiconductor relay. FIG. 2 schematically shows the arrangement of the components of the semiconductor device used in the semiconductor relay and the electrical connection thereof by a thick solid line. FIG. 2 (a) is a plan view, and FIG. 2 (b) is FIG. It is sectional drawing along the XX line of a). FIG. 3 schematically shows the structure of a MOS element, which is a component of the semiconductor device. FIG. 3A is a plan view, and FIG. 3B is a cross-sectional view taken along line YY in FIG. is there. FIG. 4 is a cross-sectional view schematically showing the structure of the semiconductor relay.

  As shown in FIG. 1, the semiconductor relay 1 includes a semiconductor device 2 including two MOS elements 5, a light receiving element array 6, a control circuit 7, and the like, and a light emitting device 3 having a light emitting element 10 such as an LED. The semiconductor device 2 and the light emitting device 3 are electrically separated and connected via light from the light emitting element 10.

  The light emitting element 10 is, for example, an LED that emits infrared light having a wavelength of about 850 μm. The anode A and the cathode C of the light emitting element 10 are connected to the light emitting element terminal 43, respectively.

  The semiconductor device 2 includes a light receiving element array 6 in which a plurality of, for example, twelve light receiving elements that are photovoltaic elements are connected in series. The light receiving element array 6 is formed with a control circuit 7 for discharging the residual charge of the gate of the MOS element 5 and turning it off at high speed, and is connected to the anode A and the cathode C of the light receiving element array 6, respectively. . The anode A of the light receiving element array 6 is connected to the respective gates G of the MOS elements 5, and the cathode C of the light receiving element array 6 is connected to the respective sources S of the MOS elements 5 via the control circuit 7. Each drain D of the MOS element 5 is connected to a signal terminal 41.

  As shown in FIG. 2, the semiconductor device 2 includes an SOI substrate 11 having an SOI structure in which a support substrate 12 and active layers 14 and 15 are separated by an insulating film 13 as a first insulating film, and active layers 14 and 15. On the surface of the semiconductor device, the two high-breakdown-voltage MOS elements 5 separated by the insulating film 18 as the second insulating film, the light-receiving element array 6 separated by the insulating film 18, and the control circuit 7 are provided. ing. The MOS element 5 is a lateral power MOS transistor.

In the SOI substrate 11, for example, the support substrate 12 is made of silicon crystal, the insulating film 13 is made of an oxide film having a thickness of about 3 μm or more, and the active layers 14 and 15 are made of silicon crystal. The MOS element 5 and the light receiving element array 6 are separated by an insulating film 18 in a groove 17 provided between the active layers 14 and 15, and the MOS element 5 and the light receiving element array 6 and the support substrate 12 are SOI substrates. 11 insulating films 13. The breakdown voltage of the high breakdown voltage MOS element 5 is 600 V, for example, and the active layer 14 is formed to be n-type with an impurity concentration of about 10 ¹⁴ to 10 ¹⁵ cm ⁻³ and a film thickness of about 16 μm. The insulating film 18 is formed by, for example, RIE (Reactive Ion Etching) method, anisotropically etching the active layer 14 substantially perpendicularly to the surface to form a groove 17, and then CVD (Chemical Vapor Deposition) method. It is formed by depositing a silicon oxide film.

  As shown in FIG. 2A, each MOS element 5 is disposed on both sides in one direction of the semiconductor device 2 with the light receiving element array 6 interposed therebetween and the periphery of the plane is separated by an insulating film 18. ing. As shown in FIG. 3, the MOS element 5 has a p + type well region 22 having a certain width with a track shape formed by connecting semicircles with straight lines as boundaries between the inside and the outside, and closer to the inside of the well region 22. The n + type source region 24 having the same shape is formed, and the n + type drain region 20 having the same outer boundary at the center of the track shape is formed. The gate electrode 26 of the MOS element 5 is disposed above the well region 22 via an insulating film 29 which is a third insulating film functioning as a gate insulating film. The inner boundary line of the line and source region 22 is formed in a track shape having substantially both boundary lines.

  As shown in FIGS. 2 and 3, an electric field relaxation resistor having a spiral shape with a constant width along the track shape in the insulating film 29 inside the gate electrode 26 and outside the upper portion of the drain region 20. 27 is arranged. The resistor 27 is for suppressing the influence of the electric field distribution on the active layer 14 and the like from the outside. The outer end of the resistor 27 is connected to the source region 24 and the well region 22 via a contact portion (broken line portion in FIG. 3), and the inner end is connected to the drain region 20. Note that the resistor 27 has approximately four turns between the source region 24 and the drain region 20, but a more suitable number of turns depending on the distance between the source region 24 and the drain region 20, the width of the resistor 27, and the like. Can be selected. The resistor 27 is made of, for example, polycrystalline silicon, and has a resistance value that is so large that the current between the source region 24 and the drain region 20 can be ignored.

  As shown in FIG. 2, the light receiving element array 6 is separated from the periphery of the plane by an insulating film 18 at a position close to a central portion in one direction on the surface of the semiconductor substrate 11 and a side portion in a direction perpendicular to one direction. Yes. In the light receiving element array 6, for example, anodes and cathodes of 12 light receiving elements separated by the insulating film 18 are sequentially connected in series via a wiring layer 31 that is a first wiring layer. The anode at the end of the light receiving element array 6 is connected to the gate electrode 26 of the MOS element 5 and the control circuit 7 via the wiring layer 32 which is the second wiring layer, and the cathode at the end is connected to the wiring layer 32. The control circuit 7 is connected to each source region 24 of the MOS element 5.

The active layer 15 of the light receiving element array 6 is formed with an n-layer having an impurity concentration of about 10 ¹⁴ to 10 ¹⁵ cm ⁻³ and a film thickness of about 16 μm. For example, a p-type diffusion layer 23 is formed on a part of the n-type active layer 15 and is connected to the wiring layers 31 and 32 from a cathode contact and an anode contact (not shown) on the surface, respectively. The wiring layers 31 and 32 are formed across the insulating film 18 that separates the individual light receiving elements of the light receiving element array 6.

  As shown in FIGS. 2 and 3, the wiring layer 32 connected to the drain region 20 is connected to the external connection terminal 8 beyond the upper part of the spiral resistor 27. The wiring layer 31 and the wiring layer 32 that connect the MOS element 5, the light receiving element array 6, the control circuit 7, the external connection terminal 8, and the like may be the same wiring layer.

As described above, the semiconductor device 2 is separated by the insulating film 13 having a thickness of about 3 μm, the SOI substrate 11 having the active layers 14 and 15 having an impurity concentration of about 10 ¹⁴ to 10 ¹⁵ cm ⁻³ and a thickness of about 16 μm. The anode and cathode of a plurality of light receiving elements formed on the surface of the active layer 15 and separated from the insulating film 18 are formed on the surface of the light receiving element array 6 connected by the wiring layer 31 and the active layer 14, and the insulating film 18, the source region 24, the drain region 20, the gate electrode 26 between the both regions 20, 24, and the anode and cathode of the light receiving element array 6 are respectively connected via the wiring layer 32 straddling the insulating film 18. The MOS element 5 connected to the gate electrode 26 and the source region 24, the source region 24 connected to each other, and the drain region 20 connected to the external connection terminal 8, and the MOS element 5 And a resistor 27 in an insulating film 29 between the wiring layer 32 and the active layer 14 to pass over areas with different potential.

  As a result, the light receiving element array 6 has an electromotive force necessary and sufficient to drive the MOS element 5. In the MOS element 5, the potential gradient generated by the wiring layer 32 is gradually lowered stepwise by the resistor 27, so that the influence of the high-voltage wiring layer 32 connecting the drain region 20 and the bonding pad 8 is suppressed. Thus, the MOS element 5 can secure a withstand voltage of 600 V between the drain and the source.

  In the semiconductor device 2, the high breakdown voltage MOS elements 5, the light receiving element array 6, and the control circuit 7 that are monolithically connected are connected by the wiring layer 32, so that the MOS elements 5 are connected to each other by bonding wires. do not have to.

  Next, the semiconductor relay 1 on which the semiconductor device 2 described above is mounted will be described. As shown in FIG. 4, the semiconductor relay 1 is disposed at a position where the semiconductor device 2 and the light emitting element 10 in which the high breakdown voltage MOS element 5, the light receiving element array 6, and the control circuit 7 are monolithically formed face each other. ing. The light emitting element 10 is fixed to a bed 52 made of, for example, a lead frame so as to emit light toward the bottom surface (mounting surface) of the semiconductor relay 1. One of the anode and the cathode of the light emitting element 10 is connected to the light emitting element terminal 43 through the bed 52, and the other of the anode and the cathode is connected to the light emitting element terminal 43 through the bonding wire 55. . The back surface of the semiconductor device 2 is fixed to a bed 51 made of, for example, a lead frame so that the light receiving element array 6 faces the light emitting element 10. Each external connection terminal 8 of the MOS element 5 is connected to the signal terminal 41 via a bonding wire 55.

  The semiconductor relay 1 is a transparent resin 57 that transmits the emission wavelength of the light emitting element 10 and has high electrical insulation between the semiconductor device 2 and the light emitting element 10 that are arranged opposite to each other, such as a silicone resin or an epoxy. The resin is filled to ensure optical coupling between the light emitting element 10 and the light receiving element array 6 and electrical insulation between the light emitting element 10 and the semiconductor device 2. A part of the signal terminal 41 and the light emitting element terminal 43, the bed 51, the bonding wire 55, the transparent resin 57, and the like are sealed with an opaque mold resin 59 and fixed to each other. The signal terminal 41 and the light emitting element terminal 43 are exposed by being bent into a gull wing shape from the mold resin 59, but in other shapes, for example, an insertion type shape such as DIP (Dual In-line package), etc. There is no problem.

  The semiconductor relay 1 is assembled by a method similar to the known semiconductor relay assembly to form the semiconductor relay 1. In the semiconductor device 2, the MOS element 5, the light receiving element array 6, and the control circuit 7 are connected by the wiring layer 32, so that a process of connecting the MOS elements 5 with bonding wires is not necessary. As a result, the bonding wire does not protrude on the surface of the semiconductor device, and handling during assembly is easy.

  The semiconductor relay 1 has the characteristics of the above-described semiconductor device 2 in terms of characteristics. That is, the semiconductor relay 1 receives light emitted from the light emitting element 10, and the light receiving element array 6 can drive the MOS element 5 with a sufficient electromotive force, and the MOS element 5 can handle a signal of 600V. . In addition, since the number of parts and the number of bonding wires are suppressed, the semiconductor relay 1 is less affected by the temperature and humidity generated around the bonding wires after assembly, and has a more reliable product. It becomes possible to do.

  As mentioned above, although the Example of this invention was described, this invention is not limited to the said Example, It can implement in various deformation | transformation within the range which does not deviate from the summary of this invention.

  For example, in the embodiments, an example in which the active layer is an n-type is shown. However, even if the active layer is a p-type, reverse-conductivity type MOS elements and light receiving elements can be formed, and a similar high breakdown voltage semiconductor device is obtained. It is possible.

  In the embodiment, an example of a semiconductor device in which the withstand voltage of 600 V is obtained and the active layer thickness of the SOI substrate is set to about 16 μm is shown. However, if the withstand voltage is 500 V, for example, the active layer thickness is Is about 10 μm and withstand voltage of 800 V, the active layer thickness can be about 30 μm. In the embodiment, the insulating film thickness under the active layer of the SOI substrate is fixed. However, it is possible to make the active layer withstand voltage more suitable by using the insulating film thickness as a parameter.

  Further, in the embodiment, the example in which one end of the electric field relaxation resistor of the MOS element is connected to the source region and the other end is connected to the drain region is shown. It is possible to have a floating potential placed inside. The shape of the resistor may be one plate or a plurality of strips in addition to the spiral shape.

  In the embodiment, the MOS element has a source region outside the track shape and a drain region at the center, but the drain region outside the track shape and the source region at the center are not. Is possible.

  In the embodiment, the light receiving element array is configured by twelve light receiving elements connected in series. However, the number of light receiving elements connected to obtain a desired voltage can be increased or decreased. It is.

  Further, in the embodiment, the light coupling is achieved by making the light emitting element and the light receiving element array face each other. However, the reflection type light coupling in which the light from the light emitting element is reflected and is incident on the light receiving element array is also possible. Even optical coupling is acceptable.

  In the embodiment, an example in which an LED that emits infrared light is used has been described. However, red light or other light having a relatively short wavelength may be used, and the light source is not limited to an LED, but an LD (Laser Diode). Or other light sources.

The present invention can be configured as described in the following supplementary notes.
(Supplementary Note 1) An SOI substrate having an active layer separated by a first insulating film and a second insulating film formed on the surface of the active layer and extending in a vertical direction from the surface of the active layer A light receiving element array formed by connecting anodes and cathodes of a plurality of adjacent light receiving elements by a first wiring layer, and a source formed in the active layer separated by the second insulating film A gate electrode formed through a third insulating film above the surface of the active layer between the source region and the drain region, and straddling the second insulating film Via the second wiring layer, the anode of the light receiving element array is connected to the gate electrode, the cathode of the light receiving element array is connected to the source region, and the drain region is connected to an external connection terminal. A semiconductor device comprising: a connected MOS element; and a resistor formed in the third insulating film between the source region and the drain region of the MOS element.

(Supplementary note 2) The semiconductor device according to supplementary note 1, wherein the resistor is polycrystalline silicon.

(Supplementary note 3) The semiconductor device according to supplementary note 1, wherein one end of the resistor is connected to the source region and the other end is connected to the drain region.

The equivalent circuit schematic which shows the electrical connection of the semiconductor relay which concerns on the Example of this invention. FIG. 2 (a) is a plan view and FIG. 2 (b) schematically shows the arrangement of the components of the semiconductor device used in the semiconductor relay according to the embodiment of the present invention and the electrical connection thereof by a thick solid line. FIG. 3 is a cross-sectional view taken along line XX in FIG. FIG. 3A schematically shows a configuration of a MOS element that is a component of a semiconductor device according to an embodiment of the present invention. FIG. 3A is a plan view, and FIG. 3B is a YY line in FIG. FIG. Sectional drawing which shows typically the structure of the semiconductor relay which concerns on the Example of this invention. The figure which shows the relationship between the active layer thickness of the semiconductor device based on the Example of this invention, and a proof pressure. The figure which shows the relationship between the active layer thickness of the semiconductor device which concerns on the Example of this invention, and the light absorption rate by an active layer.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor relay 2 Semiconductor device 3 Light emitting device 5 MOS element 6 Light receiving element array 7 Control circuit 8 External connection terminal 10 Light emitting element 11 SOI substrate 12 Support substrate 13, 18, 29 Insulating film 14, 15 Active layer 17 Groove 20 Drain region 22 Well region 23 P-type diffusion layer 24 Source region 26 Gate electrode 27 Resistors 31, 32 Wiring layer 41 Signal terminal 43 Light emitting element terminal 45 Light 51, 52 Bed 55 Bonding wire 57 Transparent resin 59 Mold resin

Claims (5)

An SOI substrate having an active layer separated by a first insulating film;
Anodes and cathodes of a plurality of adjacent light receiving elements formed on the surface of the active layer and separated by a second insulating film extending in the vertical direction from the surface of the active layer are connected by a first wiring layer, respectively. A light receiving element array formed,
A source region and a drain region formed in the active layer separated by the second insulating film, and a third insulating film above the surface of the active layer between the source region and the drain region The anode of the light receiving element array is connected to the gate electrode via a second wiring layer straddling the second insulating film, and the cathode of the light receiving element array Is connected to the source region, and the drain region is connected to an external connection terminal, a MOS element,
A resistor formed in the third insulating film between the source region and the drain region of the MOS element;
A semiconductor device comprising:   The MOS element has one of the source region and the drain region having a width with a track shape formed by connecting semicircles with straight lines as an inner boundary, and the source region and the drain region at the center of the track shape. The semiconductor device according to claim 1, comprising the other.   The semiconductor device according to claim 2, wherein the resistor is formed in a spiral shape and is disposed closer to the active layer than the second wiring layer. The first insulating film has a film thickness of 3 μm or more, and the active layer has an impurity concentration of about 10 ¹⁴ to 10 ¹⁵ cm ⁻³ or less and a film thickness of 15 μm or more. The semiconductor device according to claim 1, wherein: A light emitting element;
An SOI substrate having an active layer separated by a first insulating film, and a plurality of adjacent ones formed on the surface of the active layer and separated by a second insulating film extending in a vertical direction from the surface of the active layer A light receiving element array formed by connecting an anode and a cathode of a light receiving element by a first wiring layer, and a source region and a drain region formed in the active layer separated by the second insulating film And a second wiring having a gate electrode formed through a third insulating film above the surface of the active layer between the source region and the drain region and straddling the second insulating film The anode of the light receiving element array is connected to the gate electrode, the cathode of the light receiving element array is connected to the source region, and the drain region is connected to an external connection terminal through a layer. And S element, and a semiconductor device comprising the a third resistor formed in the insulating film between the source region and the drain region of the MOS device,
A semiconductor relay comprising:

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