JP2008010000A5 - - Google Patents

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JP2008010000A5
JP2008010000A5 JP2007199925A JP2007199925A JP2008010000A5 JP 2008010000 A5 JP2008010000 A5 JP 2008010000A5 JP 2007199925 A JP2007199925 A JP 2007199925A JP 2007199925 A JP2007199925 A JP 2007199925A JP 2008010000 A5 JP2008010000 A5 JP 2008010000A5
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Japan
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states
processor
instructions
information
sample
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JP2007199925A
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JP4847408B2 (ja
JP2008010000A (ja
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Priority claimed from US10/434,515 external-priority patent/US7240223B2/en
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Publication of JP2008010000A5 publication Critical patent/JP2008010000A5/ja
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Publication of JP4847408B2 publication Critical patent/JP4847408B2/ja
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Claims (6)

  1. プロセッサと、
    命令とデータのうち少なくとも1つを格納するシステムメモリと、
    から構成され、
    前記命令とデータのうち少なくとも1つは、プロセッサ情報の1つまたは複数のサンプルを含むサンプル履歴の関数として複数の状態から選択された状態で前記プロセッサを動作させ、前記複数の状態の各状態はそれぞれ異なる性能レベルを有し、前記命令とデータのうち少なくとも1つは前記プロセッサ情報の1つまたは複数の未来サンプルを予測することを特徴とするコンピュータシステム。
  2. プロセッサの動作に関連するプロセッサ情報のサンプルを受信するステップと、
    命令とデータのうち少なくとも1つを、前記プロセッサが前記プロセッサ情報の1つまたは複数のサンプルを含むサンプル履歴の関数として複数の状態から選択された状態で動作し、前記プロセッサ情報の1つまたは複数の未来サンプルを予測するように構成するステップと、
    から成り、前記複数の状態の各状態はそれぞれ異なる性能レベルを有することを特徴とする方法。
  3. プロセッサの動作に関連するプロセッサ情報のサンプルを受信する手段と、
    前記情報の1つまたは複数のサンプルを含むサンプル履歴の関数として複数の状態から選択された状態で前記プロセッサが動作し、前記プロセッサ情報の1つまたは複数の未来サンプルを予測するように前記プロセッサを構成する手段と、
    から構成され、
    前記複数の状態の各状態はそれぞれ異なる性能レベルを有することを特徴とするデータ処理システム。
  4. 実行されたときに、
    プロセッサの動作に関連する情報のサンプルを受信するステップと、
    前記情報の1つまたは複数のサンプルを含むサンプル履歴の関数として複数の状態から選択された状態で前記プロセッサが動作し、前記プロセッサ情報の1つまたは複数の未来サンプルを予測するするように、命令とデータのうち少なくとも1つを構成させるステップと、
    から成る動作を前記データ処理システムに実行させる命令を有し、
    前記複数の状態の各状態がそれぞれ異なる性能レベルを有することを特徴とするマシン可読媒体。
  5. サブシステムと、
    命令とデータのうち少なくとも1つを格納するメモリと、
    から構成され、前記命令とデータのうち少なくとも1つは、前記サブシステムに、サブシステム情報の1つまたは複数のサンプルを含むサンプル履歴の関数として複数の状態から選択された状態で動作させ、前記サブシステムの1つまたは複数の未来の状態を予測させ、前記複数の状態の各状態はそれぞれ異なる性能レベルを有することを特徴とするデータ処理システム。
  6. 実行されたときに、
    データ処理システムの動作に関連する情報のサンプルを受信するステップと、
    前記データ処理システムが前記情報のサンプルを含むサンプル履歴の関数として複数の状態から選択された状態で動作し、1つまたは複数の未来の状態を予測するように構成するステップと、
    から構成される方法を前記データ処理システムに実行させる命令を有し、
    前記複数の状態の各状態はそれぞれ異なる性能レベルを有することを特徴とするマシン可読媒体。
JP2007199925A 2003-05-07 2007-07-31 プロセッサシステムにおける動的電力管理の方法および装置 Expired - Lifetime JP4847408B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/434,515 US7240223B2 (en) 2003-05-07 2003-05-07 Method and apparatus for dynamic power management in a processor system
US10/434,515 2003-05-07

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP2006501289A Division JP4065458B2 (ja) 2003-05-07 2004-04-21 プロセッサシステムにおける動的電力管理の方法および装置

Publications (3)

Publication Number Publication Date
JP2008010000A JP2008010000A (ja) 2008-01-17
JP2008010000A5 true JP2008010000A5 (ja) 2008-06-26
JP4847408B2 JP4847408B2 (ja) 2011-12-28

Family

ID=33416706

Family Applications (2)

Application Number Title Priority Date Filing Date
JP2006501289A Expired - Lifetime JP4065458B2 (ja) 2003-05-07 2004-04-21 プロセッサシステムにおける動的電力管理の方法および装置
JP2007199925A Expired - Lifetime JP4847408B2 (ja) 2003-05-07 2007-07-31 プロセッサシステムにおける動的電力管理の方法および装置

Family Applications Before (1)

Application Number Title Priority Date Filing Date
JP2006501289A Expired - Lifetime JP4065458B2 (ja) 2003-05-07 2004-04-21 プロセッサシステムにおける動的電力管理の方法および装置

Country Status (8)

Country Link
US (2) US7240223B2 (ja)
EP (1) EP1620783B1 (ja)
JP (2) JP4065458B2 (ja)
KR (1) KR100858766B1 (ja)
CN (1) CN1784646B (ja)
AU (1) AU2004239644B2 (ja)
CA (1) CA2515855C (ja)
WO (1) WO2004102363A2 (ja)

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