JP2008005217A - Analog circuit using arithmetic amplifier - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To highly accurately and easily adjust a resistance value for adjusting the offset and gain of the output signal of an arithmetic amplifier, without the reliability of a circuit element deteriorate, or increase the manufacturing cost. <P>SOLUTION: The potential of the positive input terminal of an operating amplifier 73 is set to half, and the same number of resistors R13, R13A to R13C and R16A to R16C for offset adjustment are connected in parallel between the negative input terminal and power source of the operating amplifier 73 and between the negative input terminal and ground of the operating amplifier 73. Also, a plurality of resistors R15A to R15C are connected in parallel between the negative input terminal and output terminal of the operating amplifier 73 as resistors for determining the numerator of an amplification rate between the negative input terminal and output terminal of the operating amplifier 73, and a plurality of resistors R14A to R14C are connected in parallel as resistors for determining the denominator of the amplification rate between the negative input terminal and the output terminal of a buffer circuit 71 connected to this terminal, and the resistors which become unnecessary by adjustment, among those resistors are detached from the parallel connection. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an analog circuit using an operational amplifier incorporated in a voltage converter device for a vehicle, and more particularly to an operational amplifier capable of easily correcting the influence on offset and gain on an output signal due to variations in circuit elements. The present invention relates to an analog circuit using.

  In recent years, in vehicle equipment, as a measure for improving efficiency and saving energy, the vehicle drive system 10 having the electric motor 11 that generates the driving force shown in FIG. 4 includes a power source 12, a step-up / down converter 13, and an inverter 14. It is. However, the electric motor 11 is a three-phase motor when the vehicle is driven, but becomes a generator when the vehicle is braked. An arrow Y1 indicates the direction of energy that flows when the vehicle is driven, and an arrow Y2 indicates the direction of energy that flows when the vehicle is braked.

The power source 12 includes a power supply voltage from an overhead wire or a battery connected in series.
The step-up / down converter 13 boosts the voltage V _L (eg, 280 V) of the power source 12 to a voltage V _H (eg, 750 V) suitable for driving the motor 11 when the vehicle is driven, and a motor that serves as a generator when the vehicle is braked. The voltage V _H (eg, 750 V) generated from the voltage 11 is stepped down to the voltage V _L (eg, 280 V) of the power supply circuit to perform a power regeneration operation.

The inverter 14 performs ON / OFF control of the switching element in the inverter 14 so that a current flows to each phase of the three-phase motor 11 from the voltage V _H boosted by the step-up / down converter 13 when the vehicle is driven. The speed of the vehicle is changed according to the frequency. Further, at the time of vehicle braking, the switching element is ON / OFF controlled in synchronism with the voltage generated in each phase of the motor 11, so-called rectification operation is performed, and the DC voltage is regenerated.

  Next, a detailed configuration of the step-up / down converter 13 is shown in FIG. 5 and will be described. The step-up / down converter 13 is roughly configured to include a reactor 16, a capacitor 17, two switching elements 21 and 22, and control circuits 23 a and 23 b that control the switching elements 21 and 22. As shown in FIG. 5, the switching elements 21 and 22 of the drive system of recent vehicle equipment include a diode 27 (or 28) in parallel between the IGBT 25 (or 26) and the emitter / collector of the IGBT 25 (or 26). Is connected. That is, the diode 27 (or 28) is connected so that a current flows in a direction opposite to the current flowing through the IGBT 25 (or 26).

The principle of the step-up / step-down operation of the step-up / down converter 13 will be described. Further, FIG. 6 shows a waveform of a current flowing through the reactor 16 at the time of boosting.
First, the boosting operation will be described. When the IGBT 25 of the switching element 21 is turned on (conducted) between the times t0 to t1, between the times t2 and t3, and between the times t4 and t5 in FIG. 6, the current I flows through the reactor 16 and the reactor 16 (inductance L ) energy LI ^2/2 is stored in the.

On the other hand, when the IGBT 25 of the switching element 21 is turned off (non-conducting) between the times t1 and t2, between the times t3 and t4, and after the time t5, the current I flows through the diode 28 of the switching element 22 and the reactor 16 Is stored in the capacitor 17.
Next, the step-down operation will be described. IGBT26 is ON of the switching element 22 (conductive), the current I flows in the reactor 16, the energy of the LI ^2/2 is stored in the reactor 16.

On the other hand, when the IGBT 26 of the switching element 22 is turned off (non-conducting), a current flows through the diode 27 of the switching element 21, and the energy stored in the reactor 16 is regenerated to the power supply 12.
Thus, by changing the ON time (ON duty) of the switching element 21 or 22, the voltage of the step-up / step-down can be adjusted, and an approximate value can be obtained by the following equation.
V _L / V _H = ON duty (%)
V _L : power supply voltage V _H : voltage after boosting ON duty: ratio of conduction period to switching cycle of switching element 21 or 22.
However, since there are actually fluctuations in the load, fluctuations in the power supply voltage, etc., the voltage V _H after the step-up / step-down is monitored, and the ON time (ON duty) of the switching elements 21 and 22 is controlled so as to become the target value. I do.

  FIG. 7 is a block diagram of the step-up / down converter IPM 30. The IPM 30 is broadly divided into an upper arm switching unit 31, a lower arm switching unit 32, and a control unit 23. The IPM 30 includes the switching units 31 and 32 on the high voltage circuit side, and the low voltage circuit side. It is necessary to electrically insulate from the control unit 23, and for this reason, signals are exchanged using photocouplers 34, 35, 36, 37, 38, a pulse transformer (not shown), and the like.

  The switching unit 31 of the upper arm includes a temperature detecting diode 40 embedded in the same chip as the switching element 22 described above, and a temperature between two resistors 41 and 42 connected in series between the emitter of the IGBT 26 and the ground. An IGBT protection circuit 43 connected to the anode side of the detection diode 40, a gate driver 44 connected between the output side of the IGBT protection circuit 43 and the gate side of the IGBT 26, and the anode of the temperature detection diode 40 And an IGBT chip temperature detection unit 45 connected to the side.

The switching unit 32 of the lower arm includes a temperature detection diode 50 embedded in the same chip as the switching element 21 described above, and between two resistors 51 and 52 connected in series between the emitter of the IGBT 25 and the ground. An IGBT protection circuit 53 connected to the anode side of the temperature detection diode 50, a gate driver 54 connected between the output side of the IGBT protection circuit 53 and the gate side of the IGBT 25, and the temperature detection diode 50 An IGBT chip temperature detection unit 55 connected to the anode side and a VH detection circuit 56 that detects the boosted voltage V _H are provided.

The VH detection circuit 56 includes a voltage dividing circuit 57 that divides the input voltage V _H , a level adjustment circuit 58 that adjusts the level of the voltage divided by the voltage dividing circuit 57, and a triangular wave generator that generates a triangular wave 59 and a comparator 60 that compares the triangular wave with the voltage after level adjustment, and outputs a voltage of “L” or “H” level obtained as a result of the comparison to the photocoupler 38.

The control unit 23 smoothes a signal “1” corresponding to “0” or “H” corresponding to “L” from the photocoupler 38 and converts it to a DC level, and this LPF (Low Pass Filter) 62 The VH comparator 63 that compares the DC level from the LPF 62 with the step-up / step-down command value, and the boosted voltage V _H is a predetermined voltage value corresponding to the step-up / step-down command value according to the comparison result of the VH comparator 63. A gate signal generator 64 for outputting a gate signal to the photocouplers 34 and 36 is provided.

In the IPM 30 having such a configuration, the target portion of the present invention is that the temperature detection diodes 40 and 50 embedded in the same chip as the switching elements 22 and 21 are used to control the operating state of the IPM 30 as a system. The IGBT chip temperature detectors 45 and 55 measure the chip temperature of the IGBTs 26 and 25 using the VF voltage.
The IGBT chip temperature detectors 45 and 55 are represented by an internal block diagram in FIG. 8 as a representative of the IGBT chip temperature detector 45 of the switching unit 31 of the upper arm and will be described.

  The IGBT chip temperature detection unit 45 has a constant current source 70 connected to the anode side of the temperature detection diode 40 on the high voltage circuit side, and a + input connected between the constant current source 70 and the temperature detection diode 40. The operational amplifier buffer circuit 71, the level converter 77, the triangular wave generator 78, the operational amplifier connected to the output side of the triangular wave generator 78 and the level converter 77, and the output side of the comparator 79 A FET (Field Effect Transistor) 81 having a gate connected via a resistor 80 and a source connected to the photocoupler 35 of the digital / analog converter 90 via a resistor 82 is provided.

The level converter 77 includes an operational amplifier 73 having a negative input connected to the output of the buffer circuit 71 via a resistor 72, a resistor 74 connected between the input and output of the operational amplifier 73, a first power supply Vcc1, and the like. Resistors 75 and 76 connected between the ground and between the + and − inputs of the operational amplifier 73 are provided.
The digital / analog converter 90 includes a photocoupler 35, a binarization circuit 91, a buffer circuit 92, and an LPF circuit (low-pass filter) 93.

  The photocoupler 35 includes a light emitting diode 85 connected between the first power supply Vcc1 and the FET 81 and a resistor 84 connected in parallel, and a light receiving diode 87 that receives light emitted from the light emitting diode 85. A light receiving diode 87 is connected between the base of the transistor 88 and the second power supply Vcc2, and a resistor 89 is connected between the cathode of the light receiving diode 87 and the collector of the transistor 88.

The binarization circuit 91 is connected to the emitter of the transistor 88 of the photocoupler 35. The buffer circuit 92 is an operational amplifier in which the + input is connected to the output side of the binarization circuit 91 and the -input and the output are connected. And an LPF circuit 93 is connected to the output of the buffer circuit 92.
When the temperature of the IGBT 26 is measured by the IGBT chip temperature detecting unit 45 as described above, a constant current is supplied from the constant current source 70 to the temperature detecting diode 40 embedded in the same chip as the IGBT 26. As a result, both voltages VF (also referred to as VF voltage signals) of the temperature detection diode 40 have voltage values proportional to the temperature as shown in FIG. That is, when the chip temperature of the temperature detecting diode 40 is 165 ° C., VF = 1.5V, and at 25 ° C., VF = 2.0 V is obtained. In practice, the VF change amount 500 mV is the full span of the temperature signal.

FIG. 10 shows details of the VF / PWM conversion circuit 100 including the buffer circuit 71, the level converter 77, the triangular wave generator 78, and the comparator 79.
The triangular wave generator 78 includes resistors R21, R22, R23, which are connected as illustrated between the comparator 101 and the operational amplifier 102, and the-, + input terminals and output terminals of these 101, 102, the power supply Vcc1, and the ground. R24, R25, R26 and a capacitor C11 are provided. The same components as those in FIG. 8 will be described using the same reference numerals.

A triangular wave signal is generated from a triangular wave generator 78 between a predetermined upper limit value and a lower limit value.
Both voltages VF of the temperature detection diode 40 are impedance-converted by the buffer circuit 71, and then the level converter 77 matches the upper limit value of the triangular wave signal with the high-temperature (eg, 165 ° C.) side VF. Amplification and level addition / subtraction are performed so that the lower limit value matches the low temperature (eg, 25 ° C.) side VF.

That is, the level converter 77 expands the width of the VF voltage signal (gain adjustment) so that the width level of the VF voltage signal matches the level (amplitude) of the upper and lower limits of the triangular wave signal. The upper and lower levels of the level of the expanded VF voltage signal coincide with the upper and lower positions of the triangular wave (offset adjustment). The gain and offset are adjusted as follows.
In FIG. 10, the voltage of the power supply Vcc1 is divided by resistors R11 and R12 to make a + input of the operational amplifier 73, and the offset amount is determined by the resistor R13 connected between the power supply Vcc1 and the -input of the operational amplifier 73. The gain of the operational amplifier 73 is determined by the resistor R14 connected between the output of the buffer circuit 71 and the negative input of the operational amplifier 73 and the resistor R15 connected between the negative input and the output of the operational amplifier 73.

After this level adjustment, the comparator 79 at the subsequent stage compares the output voltage Vlev of the level converter 77 with the output voltage Vtri of the triangular wave generator. If Vlev> Vtri, the output of the comparator 79 is “L”. When Vlev <Vtri, “H” is set.
The duty of the output pulse of the comparator 79 generated by this operation is proportional to the VF voltage signal. For example, the duty 0% is a low temperature (eg, 25 ° C.) side VF, and 100% is a high temperature (eg, 165 ° C.) side VF. Are transmitted from the switching units 31 and 32 to the binarization circuit 91 of the control unit 23 as a PWM signal.

  In the binarization circuit 91, the PWM signal is generated with a voltage (binarization signal V 1 / V 2) of V 1 when the duty of the PWM signal is 0% and V 2 when the duty of the PWM signal is 100%. When this binarized signal V1 / V2 is impedance-converted by the buffer circuit 92 and then smoothed by the LPF circuit 93 and converted to a direct current level, it is insulated from each arm corresponding to the voltage VF across the temperature detection diode 40. An output voltage (IGBT chip temperature voltage signal) Vout can be obtained.

  The voltage signal Vout proportional to the IGBT chip temperature obtained in this way is transmitted to a higher system (not shown) of the buck-boost converter 13, and the system constantly detects the temperature of the IGBTs 25 and 26, for example, When the IGBT chip temperature exceeds the predetermined temperature T1, the switching frequency is halved, and when the IGBT chip temperature exceeds the predetermined temperature T2, the protection function for stopping the switching (step-up / step-down operation) is activated.

  Since the operation of this protection function affects the driving of the vehicle, the chip temperatures of the IGBTs 25 and 26 must be accurately measured, and an accuracy of approximately ± 5% is required. The error factors at the time of measuring the chip temperature can be broadly classified as follows: variation in both voltage VF values and temperature coefficients of the temperature detection diodes 40 and 50 embedded in the IGBT chip, the buffer circuit 71, the level converter 77, and generation of a triangular wave. There are two types of circuit system variations, including a circuit 78, a photocoupler (PWM signal isolation transmission circuit) 35, a binarization circuit 91, a buffer circuit 92, and an LPF circuit 93.

The variations in the VF values of the temperature detection diodes 40 and 50 are mainly caused by the semiconductor process. Therefore, for example, ± 3% of 60% of the total allowable error of ± 5% is a variation in the VF value. In the circuit system, it is necessary to suppress the error to ± 2%. Therefore, each circuit is required to have a performance with an error of ± 0.5%.
For this reason, it is necessary to use highly accurate circuit elements such as resistance elements, constant voltage elements, operational amplifiers, etc., but the environmental temperature of the vehicle is assured to operate in a wide range of −40 to + 105 ° C., and high reliability for vehicles. From the point that prompt response in the case of a complaint is required, there is no choice but to select from an in-vehicle IC such as a major domestic semiconductor manufacturer.

In the VF / PWM conversion circuit 100 shown in FIG. 10, a forward direction proportional to the temperature generated in the temperature detection diode 40 by a constant current IF supplied from a constant current source 70 (not shown in FIG. 10, see FIG. 8). The drop voltage (VF = 1.5 V when the chip temperature is 165 ° C., VF = 2.0 V when the chip temperature is 25 ° C.) is impedance-converted by the buffer circuit 71 and supplied to the level converter 77.
Since the potential of the power supply Vcc1 is fixed to the potential Vcc11 obtained by dividing the potential of the power supply Vcc1 by the resistors R11 and R12 at the + input terminal of the operational amplifier 73 of the level converter 77, the output voltage of the operational amplifier 73 is expressed by the following equation (1). Is done.

  On the other hand, the upper limit value Vsu and the lower limit value Vsd of the triangular wave signal from the triangular wave generator 78 are expressed by the following equations (2) and (3). The power source Vcc1 is fixed to the potential Vcc12 obtained by dividing the power supply Vcc1 by the resistors R21 and R22 at the negative input terminal of the comparator 101.

However, V _{723 LOW} is an “L” level output of the comparator 101. “//” is a simplified notation of the combined value when the resistors shown before and after are connected in parallel. For example, “R ₂₄ // R ₂₅ ” in the equation (3) is R ₂₄ and R ₂₅ . The combined resistance value when is connected in parallel. The same applies to the following.
Such a triangular wave of the upper limit value Vsu and lower limit value Vsd of the output signal of the triangular wave generator 78 and the output of the level converter 77 are compared by the comparator 79 and expressed by the following equations (4) to (6). A PWM signal having a pulse width proportional to the temperature is generated.

  This PWM signal is insulated by the photocoupler 35 of the digital / analog converter 90 whose detailed configuration is shown in FIG. 11, and then transmitted to the binarization circuit 91, the buffer circuit 92, and the LPF circuit 93. The relationship between the duty of the PWM signal and the output of the LPF circuit 93 (IGBT chip temperature voltage signal Vout) is expressed by the following equation (7).

However, V _ce is the voltage between the collector and emitter of the saturation TR61, is generally 0.15V. V _LPF is an output of the LPF circuit 93.
In these formulas (1) to (7), if a high-precision resistor of ± 0.1% is used, the error in the output of the LPF circuit 93 depends on variations in the power supplies Vcc1 and Vcc2.

In particular, since Vcc1 is used in a circuit that handles a signal having a full span of 500 mV, a highly stable and highly accurate voltage source is required, and a highly accurate shunt regulator must be used. Further, since Vcc2 handles a signal having a full span of 4V, higher accuracy than Vcc1 is not required.
Variations in the potential Vcc1 when the shunt regulator is used as the power supply Vcc1 and the potential Vcc2 when the shunt regulator is used as the power supply Vcc2 can be treated as a normal distribution.

In the voltage variation of these reference voltage source is above formula (1) ~ (7), V cc1, the value of V _cc2 is changed, the output of the LPF circuit 93 in proportion to the temperature, the temperature range is the output voltage at 130 ° C. The span assigned to the width of 4V and the offset assigned to the output of 4.5V at a temperature of 25 ° C. will be affected.
12 and 13 the effect on the output of the LPF circuit 93 in the case of varying the aforementioned V _cc1, shown in FIGS. 14 and 15 the effect on the output of the LPF circuit 93 in the case of varying the V _cc2 .

If V _cc1, variations in the distribution of the output voltage of the V _cc2 is a normal distribution, in the range from the center value of the distribution to the 3 [sigma], the error and interval in cumulative distribution ratio caused IGBT chip temperature voltage signal (LPF output) Vout Statistical calculations were made. As a result, at 1.2σ or less (77% of the population), the temperature measurement by the circuit can be suppressed to a maximum of ± 2.88% or less, but the remaining 23% exceeds ± 2.88%. In the level converter 77 shown in FIG. 10, the resistance value must be changed by using the resistor R13 for offset adjustment and R15 for gain adjustment.

For this reason, with regard to the resistors R13 and R15, an element having a low resistance value is mounted in advance so that it can be adjusted within ± 5σ, and this is performed by partially cutting the resistance pattern with a laser trimming device. Match the target adjustment value.
In order to obtain this target value, for example, a voltage of 1.607V corresponding to a chip temperature of 135 ° C. and 1.946V corresponding to 40 ° C. are connected to terminals connected to temperature detection diodes 40 and 50 built in the IGBT on the circuit board. Is input as a simulated VF signal and calculated from two LPF output signal levels obtained at that time, or a method of feeding back an error with respect to a target value of the LPF output signal while trimming a resistance value with a laser trimming device . Apart from this, there is also a technique in which the resistors R13 and R15 are not mounted and are mounted after the adjustment resistance value is determined by a test.

As an analog circuit (level converter 77) using this type of conventional operational amplifier, for example, there is one described in Patent Document 1.
JP 2005-2909 A

  By the way, in the level converter 77 corresponding to an analog circuit using a conventional operational amplifier, as described above, the resistors R13 and R15 have a low resistance value in advance so that they can be adjusted within ± 5σ. The element is mounted in advance, and the resistance pattern is partially cut by a laser trimming apparatus so as to match the target adjustment value. However, this trimming process has the following problems.

First, since the adjustment resistance value is lower than the original value, it is necessary to trim the resistance value for the total number of products. For 1.2σ or less (77% of the population), the adjustment of the resistance value is not possible. Although it is unnecessary, trimming man-hours are inevitably generated, which increases the circuit manufacturing cost.
In the case of cutting with a thin laser beam, the resistance pattern is partially cut, and after this trimming, a protective film is coated on the resistance element, but this deteriorates due to the heat cycle during use, and moisture in the air adheres. Since the resistance value may change, the reliability is low accordingly.

Further, there is a method of performing post-mounting when the adjustment resistance value is determined. However, for post-mounting, the circuit board and the initial mounted circuit element are subjected to high-temperature heating twice, which decreases the reliability of the circuit element.
The present invention has been made in view of such problems, and the resistance value for adjusting the offset and gain of the output signal of the operational amplifier can be accurately manufactured without reducing the reliability of the circuit element. An object of the present invention is to provide an analog circuit using an operational amplifier which can be easily adjusted without reducing the cost.

  To achieve the above object, an analog circuit using an operational amplifier according to claim 1 of the present invention is the analog circuit using an operational amplifier, wherein the potential of the positive input terminal of the operational amplifier is set to half of the power supply voltage. A first parallel circuit formed by connecting a plurality of resistors in parallel between the negative input terminal of the operational amplifier and the power supply, and the first parallel circuit between the negative input terminal of the operational amplifier and the ground. A second parallel circuit in which resistors having the same number and the same resistance as that of the first parallel circuit are connected in parallel is connected so that the offset amount of the operational amplifier becomes a desired value. The predetermined resistors of the first and second parallel circuits are separated from the parallel circuit.

  According to this configuration, the adjustment step is not necessary for 1.2σ or less (77% of the population) that originally does not require adjustment. Even when adjustment is necessary, the resistance value of the parallel circuit is changed by disconnecting the resistor constituting the parallel circuit. Unlike the conventional partial removal of the resistance pattern, the unnecessary resistor is completely separated from the parallel circuit, so that the resistance value does not change depending on the atmosphere during use. Further, it is desirable that the power supply voltage has a small fluctuation. Furthermore, the offset of the output signal of the operational amplifier can be adjusted to a predetermined value. According to this method, the adjustment resistance value is lower than the original value even though the adjustment is not necessary for 1.2 σ or less (77% of the population) as in the conventional case, so that the trimming of the resistance value of 100% is performed. Need not be performed. Since this trimming process is not required, the reliability of the circuit elements of the analog circuit can be easily adjusted with high accuracy and without reducing the manufacturing cost.

An analog circuit using an operational amplifier according to a second aspect of the present invention is the analog circuit according to the first aspect, wherein the resistance values of the plurality of resistors constituting the first parallel circuit are different from each other, and the resistance of the reference resistor The resistance value is a power of 2 with respect to the value.
According to this configuration, the value of the offset current can be effectively changed by weighting to a power of 2.
An analog circuit using an operational amplifier according to claim 3 of the present invention is the setting resistor according to claim 1 or 2, wherein an offset amount of the operational amplifier is set between the negative input terminal and the power source. Are further connected.
According to this configuration, the offset of the output signal of the operational amplifier can be adjusted to a predetermined value by the setting resistor.

  An analog circuit using an operational amplifier according to claim 4 of the present invention is an analog circuit using an operational amplifier for determining a numerator of an amplification factor between a negative input terminal and an output terminal of the operational amplifier. A third parallel circuit formed by connecting a plurality of resistors in parallel is connected as a resistor, and the same amplifier is connected between the negative input terminal of the operational amplifier and the output terminal of the preceding circuit connected to the negative input terminal. A fourth parallel circuit formed by connecting a plurality of resistors in parallel as a resistor for determining a denominator of the rate, and a third parallel circuit and a fourth parallel circuit so that the amplification factor of the operational amplifier becomes a desired value; A part of the resistors is disconnected from the parallel circuit.

  According to this configuration, before disconnecting the resistor, the resistance value of the parallel circuit of the resistor that determines the numerator and the resistance value of the parallel circuit of the resistor that determines the denominator are respectively set so that the amplification factor of the operational amplifier is a predetermined value. It is set to become. However, in reality, the amplification factor does not become the target value due to factors such as resistance error, so one or both of the parallel circuit of the resistor that determines the numerator and the parallel circuit of the resistor that determines the denominator The gain is finely adjusted by disconnecting the resistor of the part, and a desired gain is obtained.

In this case, a resistor that determines the numerator and a resistor that determines the denominator are necessary, so one of the numerator side and the denominator side of the resistors constituting the parallel circuit is not separated for coarse adjustment. The remaining resistors may be mounted so as to be separable for fine adjustment.
Also in this case, the adjustment process is not necessary for 1.2σ or less (77% of the population) which originally does not require adjustment.

Even when adjustment is necessary, the resistance value of the parallel circuit is changed by disconnecting the resistor constituting the parallel circuit. Unlike the conventional partial removal of the resistance pattern, the unnecessary resistor is completely separated from the parallel circuit, so that the resistance value does not change depending on the atmosphere during use.
According to this method, the adjustment resistance value is lower than the original value even though the adjustment is not necessary for 1.2 σ or less (77% of the population) as in the conventional case, so that the trimming of the resistance value of 100% is performed. Need not be performed. Since this trimming process is not required, the reliability of the circuit elements of the analog circuit can be easily adjusted with high accuracy and without reducing the manufacturing cost.

An analog circuit using an operational amplifier according to claim 5 of the present invention is the analog circuit according to claim 1 or 4, wherein the resistor is a thick film resistor mounted on a resistor mounting pad. The resistor to be separated for adjustment is characterized in that the thick film resistor is cut and removed with a predetermined width while the thick film resistor is mounted.
According to this configuration, the gain of the operational amplifier includes the parallel resistance value of the plurality of resistors for determining the numerator of the amplification factor, and the parallel resistance value of the plurality of resistors for determining the denominator of the amplification factor. It is determined by the ratio of For this reason, when the gain is adjusted, the resistance film of the required number of resistors among these resistors may be removed by using a laser beam or the like to change the resistance value to a required value.

An analog circuit using an operational amplifier according to a sixth aspect of the present invention is the analog circuit according to the first or fourth aspect, wherein the resistor includes a chip resistor portion mounted on a resistor mounting pad, and the offset amount is adjusted. For the resistor to be separated for the purpose, the chip resistor portion is removed from the resistor mounting pad.
According to this configuration, the gain of the operational amplifier includes the parallel resistance value of the plurality of resistors for determining the numerator of the amplification factor, and the parallel resistance value of the plurality of resistors for determining the denominator of the amplification factor. It is determined by the ratio of For this reason, when adjusting the gain, it is only necessary to remove the necessary number of resistors among these resistors with a laser beam or the like and change the combined resistance value to a necessary value. In this method, the same effect as that of the fifth aspect can be obtained.

An analog circuit using the operational amplifier according to claim 7 of the present invention is a combination of the analog circuit using the operational amplifier according to claim 1 and the analog circuit using the operational amplifier according to claim 4. It is characterized by that.
According to this configuration, the offset and gain can be adjusted as described in the first or fourth aspect.

  An analog circuit using an operational amplifier according to claim 8 of the present invention is an analog circuit using an operational amplifier, wherein a plurality of resistors are connected in parallel between a negative input terminal of the operational amplifier and a power source, A plurality of resistors are connected in parallel between the first current flowing into the operational amplifier via the resistor and the negative input terminal of the operational amplifier and the ground, and flow out of the operational amplifier via the resistor The resistor values of the plurality of resistors are selected so as to be equal to the second current, and the resistors are separated from the parallel circuit so that the offset amount of the operational amplifier becomes a desired value.

According to this configuration, it is possible to obtain substantially the same effect as described in the first aspect.
An analog circuit using an operational amplifier according to a ninth aspect of the present invention is the analog circuit according to the eighth aspect, wherein in each of the parallel circuits, resistance values of a plurality of resistors constituting the parallel circuit are different from each other and serve as a reference resistance. The resistance value is a power of 2 with respect to the resistance value of the vessel.
According to this configuration, it is possible to obtain substantially the same effect as described in the second aspect.

  As described above, according to the present invention, the resistance value for adjusting the offset and gain of the output signal of the operational amplifier can be easily adjusted without reducing the reliability of the circuit elements and without reducing the manufacturing cost. There is an effect that can be adjusted to.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, parts corresponding to each other in all the drawings in this specification are denoted by the same reference numerals, and description of the overlapping parts will be omitted as appropriate.
FIG. 1 is a circuit diagram showing a configuration of a VF / PWM conversion circuit to which a level converter, which is an analog circuit using an operational amplifier according to an embodiment of the present invention, is applied.

  The VF / PWM conversion circuit 110 shown in FIG. 1 is different from the conventional VF / PWM conversion circuit 100 in that a level converter 120, one offset setting resistor R13, and a set of three as a first parallel circuit. Offset fine adjustment resistors R13A, R13B, R13C and a set of three offset fine adjustment resistors R16A, R16B, R16C as a second parallel circuit, and a set of three gain adjustments as a third parallel circuit A resistor R14A, R14B, R14C and a set of three gain adjusting resistors R15A, R15B, R15C as a fourth parallel circuit, and the output signal of the operational amplifier 73 by separating the desired resistor R from the parallel circuit This is because the offset and gain are adjusted.

The offset setting resistor R13 is a conventional resistor R13 for offset setting.
More specifically, the potential of the positive input terminal of the operational amplifier 73 is set to ½ of the voltage of the power supply Vcc1 by setting the resistance value of the resistor R11 = the resistance value of the resistor R12. One set of offset fine adjustment resistors R13A, R13B, R13C between the input terminals and another set of offset fine adjustment resistors R16A, R16B, R16C between the ground and the negative input terminal of the operational amplifier 73. Are connected in parallel.

In this circuit configuration, one offset fine adjustment resistor R13A, R13B, R13C changes the output potential of 71 in the negative direction, and the other offset fine adjustment resistors R16A, R16B, R16C positively adjusts the output potential of 73. Change the direction and play a role of fine adjustment of the offset.
Here, the combined resistance value of the first parallel circuit (resistors R13A, 13B, and 13C) and the combined resistance value of the second parallel circuit (resistors 16A, 16B, and 16C) are made the same, that is, the resistor R13A = R16A. , R13B = R16B, and R13C = R16C, offset adjustments cancel each other in the state where all of the resistors R13A, R13B, R13C, R16A, R16B, and R16C are mounted. Therefore, an adjustment step is not necessary for 1.2σ or less (77% of the population) that originally does not require adjustment, and the initial level adjustment can be performed only by the offset setting resistor R13.

If the resistance values are R13B = 1/2 × R13A and R13C = 1/4 × R13A, 1 to 3 resistors R are removed from R13A, R13B, R13C and R16A, R16B, R16C. With the combination of the resistors R, offset adjustment at equal intervals can be performed in 14 steps of total positive and negative.
On the other hand, as a gain adjustment, a fourth parallel circuit in which a plurality of resistors R15A, R15B, and R15C are connected in parallel as a resistor that is connected between the negative input terminal and the output terminal of the operational amplifier 73 and determines the numerator of the amplification factor. Using a circuit, this is a set of gain adjusting resistors. In addition, a plurality of resistors R14A, R14B, and R14C are connected in parallel as resistors that are connected between the negative input terminal of the operational amplifier 73 and the output terminal of the buffer circuit 71 in the preceding stage to determine the denominator of the amplification factor. Three parallel circuits are used, and this is another set of gain adjusting resistors.

  The resistance value of each resistor is selected so that the combined resistance value of the gain adjusting resistors R14A, R14B, and R14C and the combined resistance value of R15A, R15B, and R15C become initial values for obtaining a desired gain. For setting the gain (gain) of the operational amplifier, resistors are respectively connected between the −input terminal and the output terminal of the operational amplifier 73 and between the −input terminal of the operational amplifier 73 and the output terminal of the buffer circuit 71. It is essential to connect. For this reason, one (for example, R15A and R16A) of resistors constituting the third parallel circuit and the fourth parallel circuit is not disconnected.

Actually, the gain is the parallel resistance value that determines the numerator of the amplification factor by the combination of the resistors R15A, R15B, and R15 connected in parallel between the negative input terminal and the output terminal of the operational amplifier 73, and the negative input of the operational amplifier 73. 96 series resistance values because it is determined by the ratio to the parallel resistance value that determines the denominator of the amplification factor by the combination of resistors R13A, R13B, and R13C connected in parallel between the terminal and the output terminal of the buffer circuit 71. The resistance value of each parallel circuit may be selected so that adjustment can be made at approximately equal intervals by the combination.
The output of the operational amplifier 73 provided with these offset adjustment resistors R13, R13A to R13C and R16A to R16C, and gain adjustment resistors R14A to R14C and R15A to R15C is expressed by the following equation (8).

In this equation (1), in order to perform offset and gain adjustment, the output voltage V _lev of the operational amplifier 73 is obtained by substituting ∞ into the resistance value of the resistor R to be removed or the resistance film removed.
However, since the offset amount also changes due to the gain adjustment, depending on the offset change amount, the offset amount needs to be corrected by the adjustment.

Next, an offset and gain adjustment method will be described with reference to FIG. FIG. 2 shows the configuration of each offset adjustment resistor R13, R13A to R13C and R16A to R16C, and the gain adjustment resistors R14A to R14C and R15A to R15C, where (a) is the configuration before the resistance value adjustment, (B) is a figure which shows the structure after resistance value adjustment.
As shown in FIG. 2A, the resistor R is fixed to a resistor mounting pad, in which a copper wiring pattern 202 is welded and fixed to a land portion 201, and a chip resistor portion 203 is fixed by solder 204 by a surface mounting means (not shown). Has been. The surface of the chip resistor portion 203 is coated with a protective film after a thick film resistor is applied or baked on the ceramic substrate or a metal foil film is formed by sputtering or the like.

  As shown in FIG. 2B, the protective film in the chip resistor unit 203 and the resistor R which is unnecessary and disconnected from the parallel circuit for offset or gain adjustment with respect to the resistor R The resistance film removal region 203a in the desired range of the thick film resistor or metal foil film is cut and removed with a laser beam (not shown). By this adjustment, the unnecessary resistor is disconnected from the parallel circuit, and the offset value or gain can be set to a predetermined value by changing the resistance value of the parallel circuit.

In addition, as shown in FIG. 3B, when the resistor R that is no longer needed is separated from the parallel circuit, the soldering region of the chip resistor 203 is heated with a laser beam and the solder 204 is dissolved. The chip resistor unit 203 may be removed. In this case, the chip resistor 203 may be removed while the solder 204 is melted by pressing a solder iron against both ends of the chip resistor 203. Even if it does in this way, the resistor which became unnecessary from the parallel circuit can be disconnected, and the resistance value of a parallel circuit can be changed and offset or gain can be made into a predetermined value.
In the present embodiment, the description is limited to the voltage variation of the power supplies Vcc1 and Vcc2. However, for example, the variation due to the temperature characteristics of the VF of the temperature detection diodes 40 and 50, and the temperature detection diodes 40 and 50 are applied. It is also possible to compensate for variations in the constant current IF.

  As described above, according to the level converter 120 of the present embodiment, the potential of the positive input terminal of the operational amplifier 73 is set to half, the negative input terminal of the operational amplifier 73 and the power source, and the negative input terminal. The same number of offset adjusting resistors R13A to R13C and R16A to R16C are connected in parallel between the resistor and ground, and the resistors that are no longer necessary for offset adjustment are disconnected from the parallel circuit.

  By disconnecting the resistor that is no longer necessary for the offset adjustment from the parallel circuit, the combined resistance value of the parallel circuit can be changed to a required value, and the offset of the output signal of the operational amplifier 73 can be adjusted to a predetermined value. . As a result, the resistor trimming process is not required for products having a circuit element variation of 1.2σ or less (77% of the population) among all products, and the product cost can be reduced. Also, if adjustment is necessary, the resistance element of the target value is disconnected from the parallel circuit. Specifically, the resistor is removed from the circuit board, or the resistor coating of the resistor is widened with a laser beam or the like. Can be completely cut and removed. In addition, since the resistor that is no longer needed is disconnected from the parallel circuit, it is excellent in terms of deterioration resistance against the use environment of the product, and it is possible to maintain high reliability even when used for in-vehicle use.

Further, one more resistor R13 is connected in parallel between the negative input terminal of the operational amplifier 73 and the power source Vcc1 than between the negative input terminal and the ground, and the single resistor R13 connected in large numbers is excluded. The parallel resistance values of the resistors R13A to R13C between the input terminal and the power source Vcc1 and the resistors R16A to R16C between the input terminal and the ground are made equal.
Thus, since the resistance values of the same number of positive and negative resistors are made equal, the offset adjustment is canceled out. In this case, the initial output level (offset amount) of the operational amplifier 73 can be set only by one extra resistor R13 connected in parallel between the negative input terminal and the power supply Vcc1.

  Further, the resistance values of a plurality of resistors R13A to R13C except for the resistor R13, which is one more connected in parallel between the input terminal and the power source Vcc1, and the input terminal connected in parallel to the ground. The ratio of the resistance values of the plurality of resistors R16A to R16C is a value that is a power of 2. By such weighting to a power of 2, the value of the offset current can be effectively changed.

  Further, a plurality of resistors R15A to R15C are connected in parallel as resistors for determining the numerator of the amplification factor between the −input terminal and the output terminal of the operational amplifier 73, and the −input terminal and the −input terminal are connected in parallel. A plurality of resistors R14A to R14C are connected in parallel as resistors for determining the denominator of the same amplification factor between the output terminal of the buffer circuit 71, which is a preceding circuit to be connected, and these resistors R14A to R14C are connected. And resistors R15A to R15C that are no longer necessary due to gain adjustment are disconnected from the parallel circuit. For disconnection from the parallel circuit, the resistance film of the resistor may be cut and removed, or the resistor itself may be removed. Thus, gain adjustment can be easily performed.

Further, the parallel resistance values of the plurality of resistors R15A to R15C for determining the numerator of the amplification factor are made equal to the parallel resistance values of the plurality of resistors R14A to R14C for determining the denominator of the amplification factor. This facilitates gain adjustment by disconnecting the resistor from the parallel circuit.
In the above example, the voltage of the power supply Vcc1 is divided in half by the resistors R11 and R12. However, the present invention is not limited to this.

That is, in addition to the resistor R13, a plurality of resistors are connected in parallel between the negative input terminal of the operational amplifier 73 and the power source Vcc1, and the first current flowing into the operational amplifier 73 through the resistor and the negative A plurality of resistors are connected in parallel between the input terminal and the ground, and the voltage dividing ratio of the power supply voltage and the plurality of resistors are set so that the second current flowing out from the operational amplifier 73 through the resistors becomes equal. If the resistance value is selected, the offset adjustment is canceled out, and the adjustment process is not required for 1.2σ or less (77% of the population), which originally does not require adjustment, and only the initial value is set by the offset setting resistor R13. Level adjustment can be performed.
Further, in each of the parallel circuits, the resistance values of the plurality of resistors constituting the parallel circuit are different from each other, and can be adjusted by selecting a resistance value that is a power of 2 with respect to the resistance value of the reference resistor. Is easy. Needless to say, the resistance value of the parallel circuit can be adjusted by disconnecting the resistor as in the above example.

It is a circuit diagram which shows the structure of the VF / PWM conversion circuit to which the level converter which is an analog circuit using the operational amplifier which concerns on embodiment of this invention is applied. The structure of each offset adjustment resistor and the gain adjustment resistor in the level converter is shown, (a) is a configuration before resistance value adjustment, (b) is a diagram showing a configuration after resistance value adjustment. The other structure of each offset adjustment resistor and the gain adjustment resistor in the level converter is shown, (a) is a configuration before resistance value adjustment, (b) is a diagram showing a configuration after resistance value adjustment. is there. It is a block diagram which shows the structure of a vehicle drive system. It is a block diagram which shows the structure of the buck-boost converter in a vehicle drive system. It is a current waveform figure which flows into a reactor at the time of voltage boosting operation of a buck-boost converter. It is a block diagram which shows the structure of IPM for step-up / down converters. It is a block diagram which shows the structure of the IGBT chip | tip temperature detection part in IPM for buck-boost converters. It is a temperature characteristic figure of the forward voltage of the IGBT chip temperature detection diode by the constant current circuit in an IGBT chip temperature detection part. It is a circuit diagram which shows the structure of the VF / PWM conversion circuit using the conventional level converter. It is a circuit diagram which shows the structure of the digital-analog converter in IPM for buck-boost converters. It is a figure which shows the span change of the IGBT chip | tip temperature voltage signal at the time of fluctuating the voltage of said 1st power supply. It is a figure which shows the offset change of the IGBT chip | tip temperature voltage signal at the time of fluctuating the voltage of said 1st power supply. It is a figure which shows the span change of the IGBT chip | tip temperature voltage signal at the time of fluctuating the voltage of said 2nd power supply. It is a figure which shows the offset change of IGBT chip | tip temperature voltage signal at the time of fluctuating the voltage of said 2nd power supply.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Vehicle drive system 11 Electric motor 12 Power supply 13 Buck-boost converter 14 Inverter 16 Reactor 17, C42 Capacitor 21, 22 Switching element 23a, 23b Control circuit 25, 26 IGBT
27, 28, 84 Diode 30 IPM for buck-boost converter
31 Upper Arm Switching Unit 32 Lower Arm Switching Unit 34, 35, 36, 37, 38 Photocoupler 40, 50 Temperature Detection Diode 41, 42, 51, 52, 80, 82, 89, R11, R12, R14, R15, R51, R52 Resistor 43, 53 IGBT protection circuit 44 Gate driver 45, 55 IGBT chip temperature detection unit 40, 50 Temperature detection diode 56 VH detection circuit 57 Voltage divider circuit 58 Level adjustment circuit 59 Triangular wave generator 60 Comparator 62 LPF
63 VH comparator 64 Gate signal generator 70 Constant current source 77 Level converter 78 Triangle wave generator 85 Light emitting diode 87 Light receiving diode 88, TR61 Transistor 90 Digital / analog converter 91 Binary circuit 92 Buffer circuit 93 LPF circuit 71, 92 Buffer circuit 73, 102 Operational amplifier 79, 101 Comparator R13 Offset setting resistor R13A, R13B, R13C, R16A, R16B, R16C Offset fine adjustment resistor R14A, R14B, R14C, R15A, R15B, R15C Gain adjustment resistor Vcc1 first power supply (or power supply voltage)
Vcc2 Second power supply (or power supply voltage)
Vout IGBT chip temperature voltage signal (LPF output)

Claims (9)

In an analog circuit using an operational amplifier,
A potential of the positive input terminal of the operational amplifier is set to half of a power supply voltage, and a first parallel circuit formed by connecting a plurality of resistors in parallel between the negative input terminal of the operational amplifier and the power supply is connected, Between the negative input terminal of the operational amplifier and the ground, a second parallel circuit is formed by connecting in parallel the same number of resistors as the first parallel circuit and resistors having substantially the same resistance value as the first parallel circuit. An analog circuit using an operational amplifier, wherein a circuit is connected and a predetermined resistor of the first and second parallel circuits is disconnected from the parallel circuit so that an offset amount of the operational amplifier becomes a desired value.   2. The resistance value of the plurality of resistors constituting the first parallel circuit is a resistance value that is different from each other and is a power of 2 with respect to a resistance value of a reference resistor. An analog circuit using an operational amplifier.   3. An analog using an operational amplifier according to claim 1 or 2, further comprising a setting resistor for setting an offset amount of the operational amplifier between the negative input terminal and the power source. circuit. In an analog circuit using an operational amplifier,
A third parallel circuit in which a plurality of resistors are connected in parallel as a resistor for determining the numerator of the amplification factor is connected between the negative input terminal and the output terminal of the operational amplifier, A fourth parallel circuit in which a plurality of resistors are connected in parallel as a resistor for determining the denominator of the same amplification factor is connected between the input terminal and the output terminal of the preceding circuit connected to the negative input terminal. An analog circuit using an operational amplifier, wherein a part of the resistors of the third and fourth parallel circuits is separated from the parallel circuit so that an amplification factor of the operational amplifier becomes a desired value. The resistor is a thick film resistor mounted on a resistor mounting pad,
5. The resistor according to claim 1, wherein the thick-film resistor is cut and removed with a predetermined width while the thick-film resistor is mounted on the resistor to be separated for adjusting the offset amount. Analog circuit using operational amplifier. The resistor is a chip resistor portion mounted on a resistor mounting pad,
5. The analog circuit using an operational amplifier according to claim 1, wherein the chip resistor is removed from the resistor mounting pad for a resistor to be separated for adjusting the offset amount. 6.   An analog circuit using an operational amplifier, wherein the analog circuit using the operational amplifier according to claim 1 is combined with the analog circuit using the operational amplifier according to claim 4. In an analog circuit using an operational amplifier,
A plurality of resistors are connected in parallel between a negative input terminal of the operational amplifier and a power source, a first current flowing into the operational amplifier through the resistor, a negative input terminal of the operational amplifier, and a ground A plurality of resistors are connected in parallel, and the resistance values of the plurality of resistors are selected so that the second current flowing out from the operational amplifier via the resistors becomes equal, and the offset of the operational amplifier An analog circuit using an operational amplifier, wherein the resistor is separated from the parallel circuit so that the amount becomes a desired value.   In each of the parallel circuits, the resistance values of the plurality of resistors constituting the parallel circuit are different from each other, and are resistance values that are powers of 2 with respect to the resistance value of the reference resistor. An analog circuit using the operational amplifier according to 8.

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